CN1967515A - Host access interface and implement method thereof - Google Patents
Host access interface and implement method thereof Download PDFInfo
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- CN1967515A CN1967515A CN 200610066689 CN200610066689A CN1967515A CN 1967515 A CN1967515 A CN 1967515A CN 200610066689 CN200610066689 CN 200610066689 CN 200610066689 A CN200610066689 A CN 200610066689A CN 1967515 A CN1967515 A CN 1967515A
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Abstract
The invention discloses a host access interface and its implementation, in which the host access interface includes the judge module, signal conversion module and advanced bus master module. The signal conversion module generates the needed interface signals according to the interface timing sequence specification of the said advanced bus master module, and implements the conversion between the interface signals of data registers and the interface signals of the advanced bus master module. The advanced bus master module drives the advanced bus to read/write data, and implements the conversion between the interface signals of the advanced bus master module and the signals of the advanced bus. The host access interface in the invention can provides access interface to the advanced bus, facilitates the integration in System on Chip architecture, and it can flexible configure the data width of the interface, and provides the address self-decrease mode.
Description
Technical field
The present invention relates to a kind of chip configuration interface and its implementation, be particularly related to a kind of can the flexible configuration bit wide, supporting the address when increasing the reading and writing data pattern, to support the address from size reduction mode and chip configuration interface---host access interface (Host Access Interface, HAI) and its implementation of standard advanced EBI can be provided.
Background technology
What at present, chip market had wide range of applications is that company of Texas Instrument (TI) is at the HPI (Host Port Interface, HPI) of high-performance digital signal processor (DSP) configuration. This HPI is a kind of standard interface parts, is used for digital signal processor and other buses or CPU and communicates. According to the difference of data/address bus figure place, HPI can be divided into 8 (HPI-8), 16 (HPI-16) or 32 three classes such as (HPI-32).
Fig. 1 is the structural representation of existing HPI. As shown in Figure 1, HPI 1 ' comprising: judge module 11 '. Judge module 11 ' comprising: data register (Host Data Register, HPID) 111 ', address register (Host Address Register, HPIA) 112 ', control register (HPI Control, HPIC) 113 ' and control logic (Control Logic) 114 '. Wherein, the data that to be main frame write to the memory space of this digital signal processor of data register 111 ' deposit, the perhaps data that read from the memory space of this digital signal processor of main frame; Address register 112 ' what deposit is the address of the memory space of this digital signal processor of host access, and this address register comprises the next time address of data access; Control register 113 ' what deposit is the control parameter of host configuration; Control logic 114 ', be used for HPI under its control, finish communicating by letter between main frame and the digital signal processor by above-mentioned three registers. And, judge module 11 ' can be by communicating such as other unit (such as CPU nuclear, DMALogic or Internal memory etc.) in CBA (Common Bus Architecture) bus etc. and the digital signal processor.
Main frame at first initializes control register and address register, then reads or data writing from data register, to finish the access to HPI.
The data-transmission mode of HPI has following 4 kinds: the read operation that does not certainly increase with the address; The read operation that oneself increases with the address; The write operation that does not certainly increase with the address; The write operation that oneself increases with the address. These patterns have been described 4 kinds of data-transmission modes under this host computer control signal controlling by host computer control signal (HCNTL[1:0]) control in the table 1. Wherein, as host computer control signal HCNTL[1:0] when being 01, the data-transmission mode of HPI increases pattern, at first main frame initializes host interface IP address register certainly for the band address, then use the address certainly to increase the continuous data storage area of mode access, thereby realize data throughout at a high speed. Its address makes main frame can access easily a linear memory zone from increasing function, and need not repeatedly write the address that needs to address register.
Table 1 is at HCNTL[1:0] data-transmission mode under the signal controlling
| HCNTL1 | HCNTL0 | The |
| 0 | 0 | Main frame can be read and write HPI control register (HPIC) |
| 0 | 1 | Main frame can be read and write HPI data register (HPID), HPI of every access, HPI address register (HPIA) automatic torque-increasing 1 |
| 1 | 0 | Main frame can be read and write HPI address register (HPIA) |
| 1 | 1 | Main frame can be read and write HPI data register (HPID), and the HPIA register value is not modified |
Digital signal processor and main frame notify the other side's data to be ready to by sending interrupt signal to the other side, and the state that arranges by detecting the other side judges whether the other side is ready to receive data. By HPI, main frame can directly be accessed the memory space of this digital signal processor.
But existing HPI has the following disadvantages:
1. fixing data bit width (8/16/32) can only be provided, can't be according to actual needs, the data bit width of flexible configuration interface.
2. only support the address from increasing pattern, do not support the address from size reduction mode, the addressing system underaction.
3. present advanced microcontroller bus structures (Advanced Microcontroller Bus Architecture, AMBA) (the Advanced High-performance Bus of the advanced bus in, AHB) become SOC(system on a chip) (System On Chip, SOC) main flow bus, but existing HPI does not provide advanced EBI.
Summary of the invention
The object of the invention is to, a kind of host access interface is provided.
Another object of the present invention is to, a kind of implementation method of host access interface is provided.
Host access interface of the present invention, comprise judge module, signal conversion module and advanced bus master module, wherein: described judge module, an end links to each other with main frame, the other end links to each other with described signal conversion module, is used for sampling main frame input signal and drives the main frame output signal; Described signal conversion module, one end links to each other with described judge module, the other end links to each other with described advanced bus master module, be used for according to described advanced bus master module interface timing sequence specification, produce the interface signal that needs, realize the interface signal of described judge module and the conversion between the advanced bus master module interface signal; Described advanced bus master module, an end links to each other with described signal conversion module, and the other end links to each other with advanced bus, is used for driving advanced bus and reads and writes data, and realize conversion between advanced bus master module interface signal and the advanced bus signals.
Described judge module comprises control register, address register, data register and control logic.
Described control register is provided with the data bit width configuration bit, is used for reading and writing data according to the data bit width that arranges for main frame by described data bit width configuration bit is arranged.
Described control register comprises that the address is from increasing/from the size reduction mode position, for by described address is certainly increased/arranges from the size reduction mode position, reading and writing data according to the data access patterns that arranges for main frame.
Described advanced bus master module interface signal can be standard advanced bus master module I P interface signal.
The implementation method of host access interface of the present invention may further comprise the steps:
Steps A) control register and the address register in the main frame initializes host access interface judge module;
Step B) main frame is described the configuration parameter of selecting control register according to the signal description of host access interface and the position of control register, and configuration parameter is placed on the data/address bus of judge module;
Step C) control logic is obtained described configuration parameter from described data/address bus, and according to described configuration parameter configuration control register;
Step D) described judge module and advanced bus communicate.
Described configuration parameter can comprise data bit width configuration parameter and address from increase/from the size reduction mode parameter.
Wherein, described step D) can comprise the following steps:
Step D1) judge module and advanced bus master module are carried out the signal conversion by signal conversion module;
Step D2) advanced bus master module and advanced bus are carried out the signal conversion, and drive advanced bus read/write data.
Described step D) can also comprise the following steps:
When reading the first in first out unit and allow to read for empty and advanced bus in the data register in the described judge module, need to initiate the read operation of advanced bus burst mode;
When the reading the first in first out unit and be non-NULL of described data register, main frame can directly read its remaining data from the described first in first out unit of reading, and does not need to initiate advanced bus read operation.
Wherein, described step D), can may further comprise the steps:
When Selection of chiller with the address when increasing pattern and carry out reading and writing data, main frame reads and writes data from data register, and after the current data read-write was complete, control logic control address register added 1;
When Selection of chiller with the address when size reduction mode carries out reading and writing data, main frame reads and writes data from data register, and after current data read-write was complete, control logic control address register subtracted 1.
The implementation method of described host access interface can comprise the following steps:
When described data register carries out the read operation process, when its 1st read operation, the bus read operation that 1 advanced bus burst mode of advanced bus master module drive is INCR4 is from the destination address of appointment, take out successively 4 data that the address links up, buffer memory is to described data register.
The implementation method of described host access interface comprises the following steps:
When described data register carries out the read operation process, whenever its carry out the 2nd time, the 3rd time, during the 4th read operation, do not need to initiate advanced bus read operation, main frame is reading out data from described data register directly.
The implementation method of described host access interface can comprise the following steps:
When described data register with the address when size reduction mode or individual address pattern are carried out read operation, initiate the bus read operation that 1 time advanced bus burst mode is single-mode by advanced bus master module.
The invention has the beneficial effects as follows: according to host access interface of the present invention and its implementation, by increasing signal conversion module and advanced bus master module, for advanced bus provides access interface, conveniently be integrated in the architecture of SOC(system on a chip); Can be according to actual needs, by host access interface control register configuration parameter, the data bit width of flexible configuration interface, and realize 8/16/32 reading and writing data by half-word indicating bit pin and byte indicating bit pin co-controlling; Can provide the address to provide the address from subtracting access module when increasing access module, the extended addressing mode improves access efficiency.
Description of drawings
Fig. 1 is the structural representation of existing a kind of HPI;
Fig. 2 is the structural representation of host access interface of the present invention;
Fig. 3 is the structural representation of host access interface judge module.
The specific embodiment
Describe host access interface of the present invention and its implementation in detail below with reference to accompanying drawing 2 and accompanying drawing 3.
Fig. 2 is the structural representation of host access interface of the present invention. As shown in Figure 2, host access interface 2 comprises: judge module 21, signal conversion (CONVERT) module 22 and advanced bus master (AHB MASTER) module 23.
(1) judge module 21, be used for sampling main frame input signal and drive the main frame output signal, comprising: data register (HAID) 211, address register (HAIA) 212, control register (HAIC) 213 and control logic (Control Logic) 214. Difference is, data register 211 of the present invention is used for depositing the data that main frame writes to the memory space of SOC(system on a chip), perhaps the data that read from the memory space of SOC(system on a chip) of main frame; Address register 212, for the address of the memory space of depositing the host access SOC(system on a chip), this address register comprises the next time address of data access; Control register 213 for the control parameter of depositing host configuration, has position as shown in table 2 and describes; Control logic 214 is used for controlling above-mentioned three registers, finishes communicating by letter between host access interface and the advanced bus.
In addition, data register 211 comprises read/write first in first out unit, and its function is identical with the 26S Proteasome Structure and Function cardinal principle of read/write first in first out unit in the existing HPI data register, no longer repeats at this.
(2) signal conversion module 22, according to advanced bus master module interface timing sequence specification (for example be used for, standard advanced bus master module I P interface sequence standard), produce the interface signal that needs, realize the conversion between judge module interface signal and the advanced bus master module interface signal. The interface signal of signal conversion module 22 comprises: control register read/write control signals, advanced bus read/write control signals and advanced bus read/write address signal.
(3) advanced bus master module 23 is used for driving advanced bus read-write, and realizes the conversion between advanced bus master module interface signal and the advanced bus signals.
Concrete, main frame is write data procedures: at first, main frame initializes control register 213 and address register 212, and control register 213 is carried out bit wide dispose, then in data register 211, write first in first out unit data writing, when advanced bus allows read-write, then initiate advanced total line write transactions by advanced bus master module 23, and from the reading out data the first in first out unit of writing of data register 211, then to the destination address data writing of main frame appointment.
Main frame reading data course: at first, advanced bus master module 23 drives advanced bus and carries out the read data operation, from the destination address reading out data of main frame appointment, then buffer memory to data register 211 read the first in first out unit, last main frame is read the first in first out unit reads data from this.
Host access interface of the present invention is by increasing signal conversion module and advanced bus master module, so that host access interface of the present invention provides interface, convenient integrated SOC(system on a chip) for the main flow bus AHB of SOC(system on a chip).
The data-transmission mode of host access interface of the present invention has 4 kinds, comprising: with the address from the read operation that do not increase/certainly subtract, with the address from the read operation that increases/certainly subtract, not with the address from the write operation that increases/certainly subtract and with the address from the write operation that increases/certainly subtract.
Below, will the course of work (with reference to figure 2) of host access interface of the present invention be described, may further comprise the steps:
Steps A ': main frame initializes control register 213 and the address register 212 in the judge module 21;
Step B ': main frame is according to the signal description (referring to table 3) of host access interface, at first drive control signal is selected control register 213, and according to the position of control register 213 (referring to table 2) configuration control register 213 is described, then configuration parameter is placed on data/address bus (hai_data[31～0]) upper (with reference to figure 3);
Step C ': control logic 214 will be chosen described configuration parameter, and it is write in the control register 213, to realize the configuration of bit wide configuration and the pattern that reads and writes data, then main frame sends read/write control signals by the control logic 214 of judge module 21 to advanced bus, data register 211 correspondingly from/to the destination address read/write data of main frame appointment, and address register correspondingly receives/sends the read/write address signal.
Wherein step C ' comprises step:
Step C ' 1: signal conversion module 22 will be finished the conversion between judge module interface signal and the advanced bus master module I P interface signal;
Step C ' 2: advanced bus master module 23 will be finished the conversion between advanced bus master module I P interface signal and the advanced bus signals, and drive advanced bus read/write data.
It is to be noted, corresponding each pin signal and the function of each pin of host access interface 2 of the present invention and existing HPI 1 ' is substantially identical, difference is, the present invention is by the signal of host computer control half-word indicating bit pin (hai_hwil) and byte indicating bit pin (hai_byte), to realize that main frame to the reading and writing data of different pieces of information bit wide (for example, if configuration is 8 bit data bit wides, reference table 3, then make hai_hwil=0 and hai_byte=0, expression is only to the 0th to 7 read-write of control register), the signal of other pins and function are substantially identical, no longer describe at this.
Table 2HAIC describes the position
| The position | Bit | Access | Describe | |
| | Chip | |||
| 0～1 | Bit wide (BitWitdth) | Write | Read | Data bit width operator scheme: `B00 is 32; `B01 is 16; `B1x is 8; Acquiescence=` |
| 2 | Interrupt (ABORT) | Read | Write | ABORT=0 represents the chip normal operation; ABORT=1 represents that the chip extension is dead; Main frame can regularly be inquired about, automatic clear after reading; The host access interface judge module receives response signal at designated time Duan Liwei, can arrange 1 |
| 3 | From increasing from subtracting (IncrDecr) | Write | Read | The address from increase/location is from size reduction mode: 0 for the address from increasing; 1 is that the address is from subtracting. Acquiescence=0 |
| 4 | Auto-alarming (AutoRdError) | Read | Write | Detect from increasing/out of order operation under size reduction mode alarm report |
Table 3HAI interface signal is described
| Signal name | I/O | Bit wide | Signal description |
| The HOST-IO interface signal | |||
| hai_data[31:0] | Input/Output | 32 | The HOST data/address bus |
| hai_cntl[1:0] | Input | 2 | HOST address or control line hai_cntl=' B00～access HAIC hai_cntl=' B01～access HAIA hai_cntl=' B11～access HAID (single read-write) hai_cntl=' B10～access HAID (address from increase/address is from subtracting) |
| hai_hwil | Input | 1 | HOST half-word indicating bit (32Bit scope) (low level～1st a 16Bit/ high level～the 2nd 16Bit) |
| hai_byte | Input | 1 | HOST byte indicating bit (16Bit scope) (low level～1st a 8Bit/ high level～the 2nd 8Bit) |
| hai_cs_n | Input | 1 | The HOST sheet selects control line |
| hai_re_n | Input | 1 | HOST reads enable line (Intel) HOST read-write index line ds-1 (Motorola) |
| hai_ds_n | Input | 1 | Often meet high level (Intel) HOST read-write index line ds-2 (Motorola) |
| hai_we_n | Input | 1 | HOST writes enable line (Intel) HOST read-write control line (Motorola), and is high for reading |
| hai_rdy_n | Output | 1 | The asynchronous READY signal of HOST HOST=MPC860 (Low level effective) HOST=TIC6XX (high level is effective) |
| hai_int | Output | 1 | HOST interrupts reporting signal |
| hai_mode[1～0] | Input | 1 | HOST HAI mode select signal hai_mode[0]=' B0～HOST=MPC860 hai_mode[0]=' B1～HOST=TI C6XX hai_mode[1]=' B0～Intel Mode hai_mode[1]=' B1～Motorola Mode |
| AHB-Master standard interface signal | |||
| AHB-Master standard interface signal. Address, the bit wide that reads and writes data 32Bit; Lack bus request signal hbusreq and bus arbitration signal hgrant | |||
| Universal | |||
| hclk | Input | ||
| 1 | The ahb bus | ||
| hreset_n | Input | ||
| 1 | The ahb bus reset signal, Low level effective | ||
Particularly, the course of work of host access interface comprises that main frame writes process and main frame read procedure (with reference to figure 3).
The I main frame is write process, may further comprise the steps:
Step 101) main frame initializes control register 213 and the address register 212 in the judge module 21;
Step 102) main frame is according to the signal description (referring to table 3) of host access interface, at first drive control signal is selected control register 213, and according to the position of control register 213 (referring to table 2) configuration control register 213 is described, then configuration parameter is placed on the data/address bus;
Step 103) control logic 214 will be chosen described configuration parameter, and it is write in the control register 213, to realize the configuration of bit wide configuration and the pattern that reads and writes data, then the read/write first in first out unit caches data of main frame in the data register 211, and send write control signal by control logic 214 to advanced bus;
Step 104) signal conversion module 22 will be finished the judge module interface signal to the conversion of advanced bus master module I P interface signal;
Step 105) advanced bus master module 23 will be finished described advanced bus master module I P interface signal to the conversion of advanced bus signals, and drive advanced bus and initiate data writing operation;
Step 106) control logic 214 will be controlled data register 211 to the destination address data writing of main frame appointment.
Wherein, step 102) comprise the following steps:
Step 21) describe according to the position of control register as required, the 0th～1 (that is, the data bit width configuration bit) of host configuration control register, wherein: 00 expression configuration, 32 bit data bit wides; 01 expression configuration, 16 bit data bit wides; 1x represents to dispose 8 bit data bit wides, is defaulted as 00;
Step 22) signal of host computer control half-word indicating bit pin (hai_hwil) and byte indicating bit pin (hai_byte), to realize that main frame to the reading and writing data of different pieces of information bit wide (for example, if configuration is 8 bit data bit wides, reference table 3, then make hai_hwil=0 and hai_byte=0, expression is only to the 0th to 7 read-write of control register);
Step 23) according to the needs of main frame certainly to increase or to read and write data from size reduction mode, the 3rd of configuration control register (that is, and the address from increase/from the size reduction mode position), wherein: 0 is expressed as the address from increasing pattern, 1 is expressed as the address from size reduction mode, is defaulted as 0).
In addition, step 103) comprise the following steps:
Step 31) when control logic 214 detects writing the first in first out unit and being non-full sign of data registers 211, main frame is write the first in first out unit with data buffer storage to this, simultaneously control logic 214 drivings are prepared pin (hai_rdy_n) and are dragged down effectively, then notify this write operation of main frame to finish;
Step 32) detect when writing the first in first out unit and being overflow indicator when control logic 214, then keep preparing the pin invalidating signal, and the notice host waits.
Wherein, step 106) comprise the following steps:
Step 61) writing the first in first out unit when advanced bus master module 23 identifications is that non-NULL sign and advanced bus indicate for allowing to read and write, then the first in first out unit of writing from data register 211 takes out data, concurrent advanced bus data writing operation write data to the destination address of main frame appointment;
Step 62) when the first in first out unit is write in advanced bus master module 23 identifications for empty sign, then suspends advanced bus data writing operation.
II main frame read procedure
The process that main frame is write data from the process of host access interface read data and main frame to host access interface is substantially identical, and something in common is no longer repeated. Below, specifically describe main frame and initiate the address from increasing/certainly subtract the reading data course of two kinds of patterns, and main frame is initiated the fixed address pattern (namely, with the address from do not increase/from size reduction mode) reading data course and the fixed address pattern of existing HPI (namely, with the address from not increasing pattern) reading data course substantially identical, no longer repeat at this.
II1) main frame is initiated the address when increasing the mode reads data manipulation, may further comprise the steps:
Step I) main frame is initiated the address when increasing the mode reads data manipulation, the control logic of host access interface is judged the flag bit of reading the first in first out unit in the data register 211, advanced bus master module is judged advanced bus read-write sign, drive advanced bus read operation according to judged result, comprise the following steps:
Step I 1) when reading the first in first out unit for empty sign in the data register 211, write first in first out unit air sign effectively and judge that advanced bus allows the read-write sign effectively, then needs to initiate advanced bus burst mode (AHB BURST) read operation if control logic 214 is judged.
Step I 2) when reading the first in first out unit and is the non-NULL sign, if host access interface control logic 214 judges that this sky sign of writing the first in first out unit is effective, can directly read first in first out unit read step i1 from this this moment) burst mode remain in this after reading and read data in the first in first out unit, do not need to initiate advanced bus read operation.
Here, need to judge whether be empty sign, be because data writing operation has precedence over the read data operation if writing the first in first out unit, only have when writing the first in first out unit to be empty sign, namely when not having data to be written to advanced bus, advanced bus is just carried out the read data operation. Be understandable that the present invention only has precedence over read data with data writing operation and is operating as example and is described, to write data higher than read data priority but the present invention is not limited to.
Below, specifically describe the course of work that main frame is initiated address host access interface when increasing the mode reads data manipulation, may further comprise the steps:
Step 201) the host driven control signal is selected control register 213 read-writes (namely, hai_cntl=00), the configuration parameter with control register 213 is placed on the data/address bus, wherein, the 3rd of host configuration control register 213 is 0 (that is, selecting the address from increasing pattern);
Step 202) the host driven control signal is selected address register 212 read-writes (that is, hai_cntl=01), the initial address of address register is placed on the data/address bus, the address is initial address in the configuration address register 212;
Step 203) the host driven control signal selects data register 211 to read and write (namely from increasing pattern with the address, hai_cntl=10, and the 3rd of host configuration control register 213 is 0), main frame is from the reading out data the first in first out unit of reading of data register 211, after the current data read-write was complete, control logic 214 control address registers 212 added 1;
Step 204) repeating step 203) until the total data read-write is complete.
Wherein, step 203) comprise following situation:
203a) when reading the first in first out unit in the data register 211 and carry out the 1st read operation, advanced bus master module 23 drives 1 bus read operation that advanced bus burst mode is INCR4, destination address from the main frame appointment, take out successively 4 data that the address links up, buffer memory is read the first in first out unit to data register 211, after this was read the first in first out unit and exports the 1st read data to main frame, control logic 214 drives to be prepared the pin signals and drags down effectively;
203b) when in the data register 211 read the first in first out unit carry out respectively the 2nd time, the 3rd time, during the 4th read operation, do not need to initiate advanced bus read operation, main frame can directly be read reading out data the first in first out unit from this, export successively the 2nd, 3,4 data, control logic 214 drives the preparation pin and drags down effectively;
203c) after this reads the 4th read operation end of first in first out unit, read first in first out unit air sign in the control logic 214 set data registers 211, when control logic 214 detects main frame scheduler register 212 (or initiating the host access interface write operation), then resetting, this reads the read-write pointer of first in first out unit, and its empty sign of set.
II2) main frame initiation address operates from the size reduction mode read data:
Main frame is initiated the address when the size reduction mode read data operates, and host access interface may further comprise the steps when driving advanced bus read operation:
Step I i) control logic of host access interface is judged the flag bit of reading the first in first out unit in the data register 211, and advanced bus master module is judged advanced bus read-write sign, drives advanced bus read operation according to judged result, comprises the following steps:
Step I i1) when writing first in first out unit air sign effectively and judging that advanced bus allows the read-write sign effectively, then need to initiate the bus read operation that 1 time advanced bus burst mode is single (SIGNLE) pattern by advanced bus master module.
Below, specifically describing main frame and initiate the address when size reduction mode or the operation of individual address read data, the course of work of host access interface may further comprise the steps:
Step 301) the host driven control signal is selected control register 213 read-writes (namely, hai_cntl=00), the configuration parameter of control register 213 is placed on the data/address bus, and wherein, the 3rd of host configuration control register 213 is 1 (address is from size reduction mode).
Step 302) the host driven control signal is selected address register 212 read-writes (that is, hai_cntl=01), the initial address of address register is placed on the data/address bus, the address is initial address in the configuration address register 212.
Step 303) the host driven control signal selects data register 211 with the address from the size reduction mode read-write (namely, hai_cntl=10, and the 3rd of host configuration control register 213 is 1), main frame is read reading out data in the first in first out unit from data register 211, after the current data read-write was complete, control logic 214 these address registers of control subtracted 1;
Step 304) repeating step 303) until the total data read-write is complete.
After read operation finished, control logic 214 drove preparation pin signal and drags down effectively, reads first in first out unit air sign in the simultaneously set data register 211; When control logic 214 discovery main frame scheduler registers (or initiating host access interface data writing operation), the read-write pointer that then resets and read the first in first out unit, and its empty sign of set.
Here it is to be noted, in known advanced microcontroller bus structures protocol specification, only support the address from increasing and the individual address operation that reads and writes data, therefore, in the present invention, main frame is initiated the address from the reading and writing data during operation of size reduction mode, adopts and the individual address similar operation that reads and writes data, and namely needs to initiate advanced bus burst mode the bus read-write operation that is single-mode.
The implementation method of HPI of the present invention is configured by the bit wide configuration bit to control register, to realize the host access interface of different pieces of information bit wide; And by increasing byte indicating bit pin, come reading and writing data for realizing 8/16/32 by half-word indicating bit pin and byte indicating bit pin co-controlling; By certainly increasing from the size reduction mode position of control register is configured, to realize the reading and writing data of different mode.
In sum, according to host access interface of the present invention and its implementation, by increasing signal conversion module and advanced bus master module, realize the access interface of advanced bus, can be integrated in the architecture of SOC(system on a chip); Can be according to actual needs, by host access interface control register configuration parameter, the data bit width of flexible configuration interface, and realize 8/16/32 reading and writing data by half-word indicating bit pin and byte indicating bit pin co-controlling; Can provide the address to provide the address from subtracting access module when increasing access module, the extended addressing mode improves access efficiency.
More than describing is to make things convenient for those of ordinary skills to understand the present invention; the detailed description that the present invention is carried out; but can expect; within not breaking away from the scope that claim of the present invention contains, can also make other changes and modifications, these variations and revising all in protection scope of the present invention.
Claims (14)
1. a host access interface is characterized in that, comprises judge module, signal conversion module and advanced bus master module, wherein:
Described judge module, an end links to each other with main frame, and the other end links to each other with described signal conversion module, is used for sampling main frame input signal and drives the main frame output signal;
Described signal conversion module, one end links to each other with described judge module, the other end links to each other with described advanced bus master module, be used for according to described advanced bus master module interface timing sequence specification, produce the interface signal that needs, realize the interface signal of described judge module and the conversion between the advanced bus master module interface signal;
Described advanced bus master module, an end links to each other with described signal conversion module, and the other end links to each other with advanced bus, is used for driving advanced bus and reads and writes data, and realize conversion between advanced bus master module interface signal and the advanced bus signals.
2. access interface as claimed in claim 1 is characterized in that, described judge module comprises control register, address register, data register and control logic.
3. access interface as claimed in claim 2 is characterized in that, described control register is provided with the data bit width configuration bit, is used for reading and writing data according to the data bit width that arranges for main frame by described data bit width configuration bit is arranged.
4. access interface as claimed in claim 2 or claim 3, it is characterized in that, described control register comprises that the address is from increasing/from the size reduction mode position, for by described address is certainly increased/arranges from the size reduction mode position, reading and writing data according to the data access patterns that arranges for main frame.
5. access interface as claimed in claim 1 or 2 is characterized in that, described advanced bus master module interface signal is standard advanced bus master module I P interface signal.
6. the implementation method of a host access interface is characterized in that, may further comprise the steps:
Steps A) control register and the address register in the main frame initializes host access interface judge module;
Step B) main frame is described the configuration parameter of selecting control register according to the signal description of host access interface and the position of control register, and configuration parameter is placed on the data/address bus of judge module;
Step C) control logic is obtained described configuration parameter from described data/address bus, and disposes described control register according to described configuration parameter;
Step D) described judge module and advanced bus communicate.
7. the implementation method of host access interface as claimed in claim 6 is characterized in that, described configuration parameter comprise data bit width configuration parameter and address from increase/from the size reduction mode parameter.
8. the implementation method of host access interface as claimed in claim 6 is characterized in that described step D) comprise the following steps:
Step D1) judge module and advanced bus master module are carried out the signal conversion by signal conversion module;
Step D2) advanced bus master module and advanced bus are carried out the signal conversion, and drive advanced bus read/write data.
9. the implementation method of host access interface as claimed in claim 6 is characterized in that described step D) also comprise the following steps:
When reading the first in first out unit and allow to read for empty and advanced bus in the data register in the described judge module, initiate the read operation of advanced bus burst mode;
When the reading the first in first out unit and be non-NULL of described data register, main frame directly reads its remaining data from the described first in first out unit of reading, and does not initiate advanced bus read operation.
10. the implementation method of host access interface as claimed in claim 7 is characterized in that described step D) may further comprise the steps:
When Selection of chiller with the address when increasing pattern and carry out reading and writing data, main frame reads and writes data from data register, and after the current data read-write was complete, control logic control address register added 1.
11. the implementation method of host access interface is characterized in that as claimed in claim 7, described step D) may further comprise the steps:
When Selection of chiller with the address when size reduction mode carries out reading and writing data, main frame reads and writes data from data register, and after current data read-write was complete, control logic control address register subtracted 1.
12. the implementation method of host access interface is characterized in that as claimed in claim 10, also comprises the following steps:
When described data register carries out the read operation process, when its 1st read operation, the bus read operation that 1 advanced bus burst mode of advanced bus master module drive is INCR4 is from the destination address of appointment, take out successively 4 data that the address links up, buffer memory is to described data register.
13. the implementation method of host access interface is characterized in that as claimed in claim 10, also comprises the following steps:
When described data register carries out the read operation process, whenever its carry out the 2nd time, the 3rd time, during the 4th read operation, do not initiate advanced bus read operation, main frame is reading out data from described data register directly.
14. the implementation method of host access interface is characterized in that as claimed in claim 11, also comprises the following steps:
When described data register with the address when size reduction mode or individual address pattern are carried out read operation, initiate the bus read operation that 1 time advanced bus burst mode is single-mode by advanced bus master module.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101227689B (en) * | 2007-12-27 | 2011-01-19 | 华为技术有限公司 | Method and apparatus for reporting information |
| CN102103565A (en) * | 2009-12-21 | 2011-06-22 | 上海奇码数字信息有限公司 | Advanced high-performance system bus connecting device and method |
| CN103827841A (en) * | 2011-09-30 | 2014-05-28 | 英特尔公司 | Bandwidth configurable io connector |
| CN115328846A (en) * | 2022-10-12 | 2022-11-11 | 中科声龙科技发展（北京）有限公司 | Method and device for realizing data operation |
-
2006
- 2006-04-19 CN CNB2006100666893A patent/CN100541469C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101227689B (en) * | 2007-12-27 | 2011-01-19 | 华为技术有限公司 | Method and apparatus for reporting information |
| CN102103565A (en) * | 2009-12-21 | 2011-06-22 | 上海奇码数字信息有限公司 | Advanced high-performance system bus connecting device and method |
| CN103827841A (en) * | 2011-09-30 | 2014-05-28 | 英特尔公司 | Bandwidth configurable io connector |
| CN103827841B (en) * | 2011-09-30 | 2017-03-29 | 英特尔公司 | The I/O connector of configurable bandwidth |
| US9654342B2 (en) | 2011-09-30 | 2017-05-16 | Intel Corporation | Bandwidth configurable IO connector |
| CN115328846A (en) * | 2022-10-12 | 2022-11-11 | 中科声龙科技发展（北京）有限公司 | Method and device for realizing data operation |
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| CN100541469C (en) | 2009-09-16 |
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