CN1292360C - Device and method for implementing automatically reading and writing internal integrated circuit equipment - Google Patents
Device and method for implementing automatically reading and writing internal integrated circuit equipment Download PDFInfo
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- CN1292360C CN1292360C CN 200410000775 CN200410000775A CN1292360C CN 1292360 C CN1292360 C CN 1292360C CN 200410000775 CN200410000775 CN 200410000775 CN 200410000775 A CN200410000775 A CN 200410000775A CN 1292360 C CN1292360 C CN 1292360C
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Abstract
The present invention discloses a device and a method for implementing automatically reading and writing I2C equipment. The device is composed of a command generation module implemented by hardware, and an execution module of reading and writing operation, wherein the command generation module is respectively connected with drive equipment and the execution module of reading and writing operation by asynchronous access buses; the execution module of reading and writing operation is connected with I2C equipment by an I2C bus; in the processes of reading and writing, the drive equipment provides a starting signal, a reading/writing signal, the equipment address of the I2C equipment, a register address and data to be written in a register; the command generation module automatically generates a needed command for accessing the I2C equipment; the components are orderly transmitted to the execution module of reading and writing operation; the execution module of reading and writing operation generates a needed signal sequence for accessing the I2C equipment according to an I2C bus protocol for executing reading and writing operation to the I2C equipment. The device of the present invention also returns a command execution condition to the drive equipment. The present invention simplifies software operation when the I2C equipment is accessed, and saves CPU time.
Description
Technical field
The present invention relates to a kind of read-write equipment and method of integrated device electronics, relate in particular to and realize in the data communication field I2C (inter-integrated circuit internal integrated circuit, a kind of standard interface circuit proposes invention by PHILIPS company) apparatus and method that read or write automatically of equipment.
Background technology
Electronic apparatus system or CPU application system have low speed asynchronous access bus interface under a lot of situations, but there is not the I2C bus (to comprise two signal wires of SDA and SCL, expression is the data signal line and the clock cable of I2C bus respectively, following I2C bus all is meant this two signal wires) interface, and need carry out the reading and writing visit this moment to I2C equipment.This just need carry out the conversion of low speed asynchronous access bus and I2C interface bus.
The general more complicated of method of existing realization low speed asynchronous access bus and the conversion of I2C interface bus, on the WWW.FPGA.COM.CN website, the total line traffic control IP CORE of a up-to-date I2C (integrated circuit (IC) logic kernel) that XILINX (U.S. fpga chip production firm) provides, adopt this complicated method exactly, if active devices (such as CPU) will be visited an I2C equipment, CPU to press the I2C bus protocol step by step and carry out.
For example, CPU will carry out and read an I2C equipment, and the step that carry out is:
1) CPU writes data register to the device address of I2C (DEVICE ADDRESS), and sign is write in setting;
2) CPU read states register judges that whether the I2C bus is busy, do not carry out next step if be in a hurry;
3) CPU write control register sends " beginning " (START) and transmission I2C device address (DEVICE ADDRESS);
4) CPU read states register is judged to send the response (ACK) that whether finishes and receive slave unit, if receive response, then carries out next step operation;
5) CPU writes data register to the register address (WORD ADDRESS) that will visit I2C equipment;
6) CPU write control register is sent the register address of I2C equipment;
7) CPU read states register is judged to send the response (ACK) that whether finishes and receive slave unit.If receive response, then carry out next step operation;
8) CPU write control register sends " end " (STOP);
9) CPU time-delay (, requiring between last " end " and next " beginning " 10 milliseconds time-delay to be arranged) such as AT24C04 because of some I2C equipment needs additional delay;
10) CPU writes data register to the device address of I2C (DEVICE ADDRESS), and sign is read in setting;
11) CPU write control register sends " beginning " (START) and transmission I2C device address (DEVICE ADDRESS);
12) CPU read states register is judged to send the response (ACK) that whether finishes and receive slave unit, if receive response, then carries out next step operation;
13) CPU is provided with control register, makes logic be in accepting state;
14) judge status register, whether data finish receiving.Finish and then carry out next step
15) CPU read data register obtains the data that will read.
As can be seen, each step all be unable to do without operation and the judgement of CPU, and a large amount of time of not only program complexity, and CPU is spent in the response of waiting for slow devices.
Because I2C equipment is equipment more at a slow speed, visits the time that such slow devices consumes CPU; If operate step by step with software, comprise sending the START signal, send data, detect the response signal of SLAVE equipment (slave unit), send the STOP signal again.Each step operation all requires ppu to participate in sending instruction or judgement etc., will waste a large amount of operating cycles of CPU, and for the system that the CPU handling property is had relatively high expectations, this is not calculate very much, also is worthless.In addition, if realize guiding operation visit I2C equipment with software, require the user to understand very much the I2C bus protocol, the agreement that must press the I2C bus is complete operation step by step, comprises how long time-delay waits all to want accurate Calculation.
Summary of the invention
The technical problem to be solved in the present invention is a complex operation when overcoming the visit internal integrated circuit equipment that prior art exists, and the defective of waste CPU time provides a kind of device and method of realizing that automatic reading and writing internal integrated circuit is equipped with.
The device of the automatic reading and writing internal integrated device electronics of realization of the present invention, comprise with hard-wired command generation module and read-write operation execution module, described command generation module links to each other with active devices and described read-write operation execution module respectively by the asynchronous access bus, described read-write operation execution module links to each other with internal integrated circuit equipment by internal integrate circuit bus, wherein:
Described command generation module, be used to receive device address, the register address of enabling signal, read/write signal and internal integrated circuit equipment that described active devices provides and will write the data of register, automatically produce the required instruction of visit internal integrated circuit equipment, deliver to described read-write operation execution module in regular turn, and to described active devices link order implementation status and integrated device electronics data of reading internally;
Described read-write operation execution module, be used for instruction according to described command generation module, abide by the internal integrate circuit bus agreement and produce the signal sequence that visit internal integrated circuit equipment needs, execution is to the read-write operation of inner integrated device electronics, and to described command generation module link order implementation status.
Said apparatus can have following characteristics: described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, data command and halt instruction when detecting active devices and will write an internal integrated circuit equipment.
Said apparatus can have following characteristics: described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, halt instruction, sign on, device address instruction and read indication, reception data command and halt instruction when detecting active devices and will read an internal integrated circuit equipment.
Said apparatus can have following characteristics: described command generation module further comprises:
The order control register by the value that the enabling signal and the read/write signal of described active devices is provided with corresponding control bit, starts inner integrated device electronics is read or write, and when carrying out failure error flag is set;
Device address register, the device address that is used to store the internal integrated circuit equipment that will visit;
The register address register, the address that is used to store the register of the internal integrated circuit equipment that will visit;
Write data register, be used to store the data that to write;
Read data register is used to store the data that will read;
Frequency division is provided with register, is used to be provided with the multiple relation between the CLK frequency of the frequency of the SDA/SCL signal of sending and input;
Described active devices is selected above-mentioned register by the address signal of asynchronous bus.
Said apparatus can have following characteristics: described command generation module is after finishing a read or write look-at-me to be set to described active devices link order implementation status, perhaps after the order control register executes operation with corresponding bit automatic clear, perhaps the combination by above dual mode realizes.
Said apparatus can have following characteristics: described read-write operation execution module comprises command register, receive data register, transmitting data register, clock generating unit, START generation unit, STOP generation unit, data transmission unit and Data Receiving unit, wherein:
Described command register, the value of corresponding control bit is set by the instruction of described command generation module, control the startup of described START generation unit, STOP generation unit, data transmission unit and Data Receiving unit, and the operation complete after with the corresponding positions zero clearing;
Described receive data register is used for the data that data cached receiving element receives;
Described transmitting data register is used for the data that data cached transmitting element will send;
Clock generating unit is used for producing the required clock of each module of read-write operation execution module;
Described START generation unit is used for producing the START sequential that the internal integrate circuit bus agreement is stipulated;
Described STOP generation unit is used for producing the STOP sequential that the internal integrate circuit bus agreement is stipulated;
Described data transmission unit is used for according to the SDA of internal integrate circuit bus agreement regulation, the sequential of SCL the data in the described transmitting data register being sent on the internal integrate circuit bus;
Described Data Receiving unit is used for receiving the data on the internal integrate circuit bus according to the SDA of internal integrate circuit bus agreement regulation, the sequential of SCL.
Said apparatus can have following characteristics: the asynchronous bus between described command generation module and the read-write operation execution module comprises reset signal, clock signal, writes enable signal, transmitting data register is selected signal, command register is selected signal, data bus input and output signal, and the circuit of error indication signal, described error indication signal is produced by the control bit of described command register, is used for to described command generation module link order implementation status.
The method of internal integrated circuit equipment is write in realization of the present invention automatically, is applied to active devices by in hard-wired command generation module and write operation execution module and the system that internal integrate circuit bus links to each other, and this method may further comprise the steps:
(a) address of the internal integrated circuit equipment that will visit of described active devices writes the device address register of described command generation module;
(b) address of the internal integrated circuit device register that will visit of described active devices writes the register address register of described command generation module;
(c) the described active devices data that will write write the data register that writes of described command generation module;
(d) described active devices is provided with the corresponding BIT position startup write operation of order control register in the described command generation module;
(e) described command generation module produces automatically and writes the required instruction of internal integrated circuit equipment, delivers to described write operation execution module in regular turn;
(f) described write operation execution module is abideed by the generation of internal integrate circuit bus agreement and is write the signal sequence of internal integrated circuit equipment and finish write operation, the link order implementation status according to the instruction of described command generation module;
(g) described command generation module is to described active devices link order implementation status;
(h) after described active devices decision operation is correctly finished, finish one time write operation.
In the said method, after the described step (h), if next operation and last operational access is same internal integrated circuit equipment, then directly return step (b), otherwise return step (a).
In the said method, in the described step (e), described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, data command and halt instruction.
In the said method, in the described step (h), described active devices is quoted by the interruption of described command generation module, perhaps detects the value of the corresponding control bit of described command generation module and confirms whether operation is correctly finished; The value of the error indication bit by detecting described command generation module judges whether to carry out the fault processing operation.
Automatically the method for reading internal integrated circuit equipment of the present invention is applied to active devices by in hard-wired command generation module and read operation execution module and the system that internal integrate circuit bus links to each other, and this method may further comprise the steps:
(a) address of the internal integrated circuit equipment that will visit of described active devices writes the device address register of described command generation module;
(b) address of the internal integrated circuit device register that will visit of described active devices writes the register address register of described command generation module;
(c) described active devices is provided with the corresponding BIT position startup read operation of order control register in the described command generation module;
(d) described command generation module produces automatically and reads the required instruction of internal integrated circuit equipment, delivers to described read operation execution module in regular turn;
(e) described read operation execution module is abideed by the generation of internal integrate circuit bus agreement and is read the signal sequence of internal integrated circuit equipment and finish read operation according to the instruction of described command generation module, and the link order implementation status;
(f) described command generation module is returned data and the condition execution instruction of reading to described active devices;
(g) after described active devices decision operation is correctly finished,, finish a read operation from described command generation module sense data.
In the said method, after the described step (g), if next operation and last operational access is same internal integrated circuit equipment, then directly return step (b), otherwise return step (a).
In the said method, in the described step (d), described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, halt instruction, sign on, device address instruction and read indication, reception data command and halt instruction.
In the said method, in the described step (g), described active devices is quoted by the interruption of described command generation module, perhaps detects the value of the corresponding control bit of described command generation module and confirms whether operation is correctly finished; The value of the error indication bit by detecting described command generation module judges whether to carry out the fault processing operation.
As from the foregoing, the present invention produces some instructions that visit internal integrated circuit equipment needs by hard-wired command generation module, replaces a few thing of software, simplifies the loaded down with trivial details operation of software thereby finish; By of the instruction of read-write operation execution module, and abide by the internal integrate circuit bus agreement, finish the concrete operations of visit internal integrated circuit equipment according to command generation module, thereby by the automatic compatible internal integrate circuit bus agreement of device of the present invention.Visit this phenomenon that internal integrated circuit equipment too relies on CPU thereby changed, vacate the CPU more time and do other prior work.Simultaneously, allow the user not need to understand loaded down with trivial details internal integrate circuit bus agreement, simplified the workload of software.
Description of drawings
Fig. 1 is the structured flowchart that the embodiment of the invention is read and write the device of I2C equipment automatically;
Fig. 2 and Fig. 3 are respectively that the asynchronous access bus between embodiment of the invention active devices and the command generation module is write sequential and read sequential chart;
Fig. 4 A and Fig. 4 B are the process flow diagrams of embodiment of the invention active devices visit apparatus of the present invention;
Fig. 5 is the process flow diagram of the generation instruction of embodiment of the invention command generation module;
Fig. 6 is the synoptic diagram that embodiment of the invention command generation module is write sequential;
Fig. 7 is the synoptic diagram that embodiment of the invention command generation module is read sequential;
Fig. 8 is the transmission time sequence figure of I2C bus.
Embodiment
The device that the embodiment of the invention is read and write I2C equipment automatically as shown in Figure 1, this device is made up of command generation module 1 and read-write operation execution module 2, adopts FPGA or CPLD to realize.Command generation module 1 links to each other with read-write operation execution module 2 with active devices 4 respectively by the asynchronous access bus, and read-write operation execution module 2 links to each other with I2C equipment 3 by the I2C bus.Wherein:
1. command generation module 1, realize by hardware, be used to receive device address, the register address of enabling signal, read/write signal and I2C equipment that described active devices provides and will write the data of register, automatically produce the required instruction of visit I2C equipment, give the read-write operation execution module by certain condition and sequencing, to the described active devices link order implementation status and the data of reading, and can judge from I2C equipment and have or not response from I2C equipment.
This module comprises order control register 11, device address register 12, register address register 13, write data register 14, read data register 15 and frequency division is provided with register 16, wherein:
Order control register 11 is used to start I2C equipment is read or write, and is 3 W/R registers, and the function of each bit is as follows:
BIT0=1 writes the I2C devices enable, after executing write operation, and this bit automatic clear;
BIT1=1 reads the I2C devices enable, after executing read operation, and this bit automatic clear;
BIT2=1 is in the operation that execution reads or writes, and wrong appearance, expression correctly do not execute the reading and writing operation;
BIT2=0 is normal.
Register address register 13, the address that is used to store the register that will visit I2C equipment is 8 W/R registers, the WORD ADDRESS in the corresponding diagram 6;
Writing data register 14, be used to store the data that will write, is 8 W/R registers;
Read data register 15 is used to store the data of reading, and is 8 R registers;
Frequency division is provided with register 16, is used to be provided with the multiple relation between the CLK frequency of the frequency of the SDA/SCL signal of sending and input, is 8 W/R registers, and the minimum value of CLK can not be lower than 10MHz.
Computing formula is:
The address of these 6 registers is respectively: 0,1,2,3,4,5.
This module is the interface module of apparatus of the present invention and active devices (such as CPU).Active devices is joined by a general asynchronous access bus and this module, and the signal of asynchronous access bus can be referring to Fig. 1, and table 1 has provided the explanation of asynchronous interface signal.
Table 1
| Signal name | Explain |
| Data bus | Data bus.(I/O) |
| CLK | Clock, the clock signal that operate as normal of the present invention is essential.In |
| CS | Chip selection signal, low level is effective.In |
| WR | Read-write, low representative is write, and the Gao representative is read.In |
| Reset | Reset signal, low level is effective.Be necessary for height during operate as normal.In |
| INT | Interrupt output, 0 expression reading and writing operation is finished, and 1 does not finish or do not have the reading and writing operation, and the register E of reader invention can should interrupt clearly.Out |
| A[2:0] | Address bus wants certain register of access instruction generation module, this bus that correct address indication must be arranged.In |
Fig. 2, Fig. 3 show the transmission time sequence of above-mentioned partial asynchronous interface signal when write and read is operated, and active devices 4 among the figure and the bus between the command generation module can be local bus (local device bus, the BOOT of CPU; The access bus of FLASH etc.), Power PC (the Power PCCPU series of motorola), single-chip microcomputer (51 series), the ISA of interl CPU (Industry Standard Architecture industrial standard architectures) bus, the device bus of MIPS CPU etc., anyly satisfy Fig. 2, the asynchronous access bus of Fig. 3 sequential all can be docked with the present invention, directly uses the present invention.Among the figure:
The time span of Tw-we can be indefinite, as long as in effective write cycle time (CS=0 and wr=0, data bus and A[2:0] effectively), have the rising edge of a CLK to get final product;
The time span of Tw-rd can be indefinite, can be greater than 10 nanoseconds;
Twr-w and Tcs-w can equate, also can not wait;
The relation of Twr-r and Tcs-r will satisfy Twr-r 〉=Tcs-r.
Wherein the character field implication is as follows:
Time access cycle of Tw-we active devices visit write operation of the present invention.
Write signal effective time in the access cycle of Twr-w active devices visit write operation of the present invention.
Chip selection signal effective time in the access cycle of Tcs-w active devices visit write operation of the present invention.
Time access cycle of Tw-rd active devices visit read operation of the present invention.
Write signal ineffective time in the access cycle of Twr-r active devices visit read operation of the present invention.
Chip selection signal effective time in the access cycle of Tcs-r active devices visit read operation of the present invention.
2. the read-write operation execution module 2, are used for the instruction according to described command generation module 1, abide by the I2C bus protocol and produce the signal sequence that visit I2C equipment needs, and carry out the read-write operation to I2C equipment, and to described command generation module link order implementation status.Comprise following a few part in this module:
Command register 21 is used to control the startup of START generation module 25, STOP generation unit 26, data transmission unit 27 and Data Receiving unit 28.It is controlled by command generation module 1, command generation module 1 is by being provided with the different bits of this register, thereby reach the purpose of control read-write operation execution module work, START generation module 25, STOP generation unit 26,28 4 modules of data transmission unit 27 and Data Receiving unit can not be worked simultaneously.In the present embodiment:
25 work of BIT0=1 START generation unit enable, and the START generation unit sends to the beginning sequential among Fig. 8 (start condition) on the I2C bus, after operation is finished, with this BIT position clear 0;
BIT1=1 sends data module 27 work and enables, when sending data module the data of 23 li of transmitting data registers all sent out, and after receiving the response signal of slave unit, with this BIT position clear 0;
BIT2=1 receives data module 28 work and enables, and 8 bit data of the I2C slave unit being sent here when the reception data module all receive, and after sending response signal ACK, automatically with this BIT position clear 0;
26 work of BIT3=1STOP generation unit enable, and the STOP generation module sends to the end sequential among Fig. 8 (stop condition) on the I2C bus, after operation is finished, with this BIT position clear 0.
Receive data register 22 is used for the data that data cached receiving element 28 receives;
Transmitting data register 23, the data that data cached transmitting element 27 will send;
Clock generating unit 24 is used for producing the required clock of each module of read-write operation execution module;
START generation unit 25 is used for producing the START sequential that the I2C bus protocol is stipulated; (the start condition among Fig. 8 begins condition)
STOP generation unit 26 is used for producing the STOP sequential that the I2C bus protocol is stipulated; (the stop condition termination condition among Fig. 8)
Data transmission unit 27 is used for, sending on the I2C bus the data in the transmitting data register 23 according to the SDA of I2C bus protocol regulation, the sequential of SCL;
Data Receiving unit 28 is used for receiving the data on the I2C bus according to the SDA of I2C bus protocol regulation, the sequential of SCL.
Based on above device, shown in Fig. 4 A and Fig. 4 B process flow diagram of the active devices access instruction generation module equipment of the embodiment of the invention, wherein the flow process of write operation may further comprise the steps shown in Fig. 4 A:
If next operation, with last operational access be same I2C equipment, then directly turn back to step 110; If not same I2C equipment, then to turn back to step 100.
As can be seen from the above, for single I2C equipment, active devices only needed for 4 steps operated a write operation can finishing I2C equipment, and wherein step 100,110 and 130 is startup to be set once visit the essential step of I2C equipment.
The flow process of read operation may further comprise the steps shown in Fig. 4 B:
If next operation, with last operational access be same I2C equipment, then directly turn back to step 210; If not same I2C equipment, then to turn back to step 200.
As can be seen from the above, for single I2C equipment, active devices only needed for 3 steps operated the read operation that can finish I2C equipment.Do not resemble existing technology, active devices needs the operation and the judgement in 15 steps, just can finish the read operation to an I2C equipment.
Fig. 7 is the process flow diagram of instruction generation module work, may further comprise the steps:
Step 310 sends START instruction (opening flag of I2C bus, the start condition in the corresponding diagram 8) to the read-write operation execution module;
Step 320 sends DEVICE ADDRESS (I2C device address) and writes indication to the read-write operation execution module;
Step 330 sends WORD ADDRESS instruction (register address of I2C equipment) to the read-write operation execution module;
Step 340 sends data (DATA) to the read-write operation execution module;
Step 350 sends STOP instruction (end mark of I2C bus, the stop condition in the corresponding diagram 8) to the read-write operation execution module;
Step 360 after all instructions are correctly finished, is ordered the BIT0=0 of control register clearly, forfeits the INT signal in producing simultaneously, informs that the active devices write operation finishes, and finishes one time write operation;
Step 400 sends the START instruction to the read-write operation execution module;
Step 410 sends DEVICE ADDRESS and writes indication to the read-write operation execution module;
Step 420 sends WORD ADDRESS instruction to the read-write operation execution module;
Step 430 sends the STOP instruction to the read-write operation execution module;
Step 440 starts the 10ms time-delay;
Step 450 sends the START instruction to the read-write operation execution module;
Step 460 sends DEVICE ADDRESS and reads indication to the read-write operation execution module;
Step 470 sends instruction to the read-write operation execution module, and putting SDA is high resistant, and prepares to receive the data from I2C equipment;
Step 480 after Data Receiving finishes, sends the STOP instruction to the read-write operation execution module;
Step 490 after all instructions are correctly finished, is ordered the BIT1=0 of control register clearly, produces the interrupt INT signal simultaneously, informs that the active devices read operation finishes, and finishes a read operation.
In the above-mentioned steps, command generation module is after the read-write operation execution module sends an instruction, timing start-up time simultaneously, each instruction of this module all designs a fault warning maximum time value, when the time of timing reaches this value and also do not detect this operation correct execution and finish, then think and break down, stop this reading and writing operation, put indicating fault position (will order control register BIT2 to put 1), step 500, mistake appears in indication, informs that the active devices write operation is unsuccessful; Can not correctly finish as this read-write operation, will stop this reading and writing operation, and inform this operation failure of active devices, how carry out next step operation again by the active devices decision with the indicating fault position.
The determination methods whether correct execution is finished is: because the every complete instruction of read-write operation execution module, all corresponding BIT position of clear this module command register.And give command generation module the several Control BIT position of command register by error signal (referring to Fig. 1), concrete enforcement is: error[3:0]=BIT[3:0], BIT[3:0] and be the BIT position of command register.Thereby command generation module is by detecting error[x] value, can learn that this instructs whether proper operation is finished.
The sequential of above-mentioned command generation module when write operation and read operation respectively as shown in Figure 6 and Figure 7, when detecting active devices and will write an I2C equipment, command generation module will send START-successively according to the order of Fig. 6〉send DEVICE ADDRESS and write indication-transmission WORDADDRESS-transmission data-transmission STOP; When detecting active devices and will read an I2C equipment, send START-successively according to the order of Fig. 7〉send DEVICE ADDRESS and write indication-transmissions WORD ADDRESS-send STOP-transmission START-transmission DEVICEADDRESS and read indication-reception data-transmission STOP.
Among Fig. 7, except that DATA partly be send and receive by I2C slave unit (being the I2C equipment among Fig. 1) by the present invention, it all is to be sent by the present invention that other parts all (are removed ACK).MSB represents the high-order BIT of byte among the figure, and LSB represents the low level BIT of byte, and W/R is read-write indication, indicates this cycle to read I2C equipment or writes I2C equipment, and 0 writes, and 1 reads.Place that need to judge the slave unit response is arranged (such as read-write operation execution module of the present invention, after sending DEVICE ADDRESS and read-write indication R/W, will judge the ack signal that I2C equipment is sent back to, (correct ack signal should be the low level 0 of 1 clock period) is if be checked through this ack signal, the read-write operation execution module thinks that then this instruction correct execution finishes) the read-write operation execution module is by detecting Fig. 6, ack signal among Fig. 7 is finished automatically, ACK is that 0 expression slave unit has response, ACK is that 1 expression slave unit does not have response, is equal to the ACK cycle among Fig. 8.
The read-write operation execution module is described below according to the instruction of command generation module, presses the I2C bus protocol and produce the signal sequence that visit I2C equipment needs, carry out situation the read-write operation of I2C equipment.
Fig. 8 has described the transmission time sequence of I2C bus.The I2C bus comprises two signal wires, article one, be data-signal SDA, another is clock signal SCL, corresponding 1 cycle of complete clock of each data bit, clock signal SCL is 1 o'clock, and data SDA can not change, and then is interpreted as beginning (START if change, start condition among Fig. 8) or finish (STOP, the stopcondition among Fig. 8) sign.Work as SCL=1, it is " beginning " that SDA has negative edge; Work as SCL=1, it is " end " that SDA has rising edge.The equipment that takies the I2C bus is main equipment, and accessed equipment is slave unit.A main equipment byte of every transmission (8BIT), slave unit just should have a low level response (slave unit drags down a clock period to SDA) (ACK among Fig. 8) at the 9th CLOCK of SCL, if main equipment detects less than this " response ", then data transmission is unsuccessful.Data transfer sequence is that low level (LSB) finishes with high-order (MSB) beginning.
The read-write operation execution module of present embodiment need produce the transmission time sequence of required I2C bus according to the instruction of command generation module.As shown in Figure 1, connect by asynchronous bus between command generation module 1 and the read-write operation execution module 2.The implication of each signal is as shown in table 2:
Table 2
| Reset | Reset signal. |
| Clock | The clock signal that read-write operation execution module operate as normal is essential. |
| WE | Write enable signal, low level is effective.When this signal hanged down, the data on the Data_i bus were effective. |
| Data_i | The data bus input, command generation module is sent to the read-write operation execution module. |
| Data_o | Data bus output, the read-write operation execution module is sent to command generation module. |
| Txreg_cs | Transmitting data register is selected signal. |
| Comd_cs | Command register is selected signal. |
| Error[3:0] | Error indication signal, whether correct execution is finished to be used to indicate a certain operation. |
Can finish the access control of two intermodules by above signal, for example, when command generation module sends DEVICE ADDRESS instruction, WE and Txreg_cs signal are effective, transmitting data register in the read-write operation execution module is write by Data_i in device address in the command generation module device address register, then, command generation module is provided with the BIT1=1 of the command register of read-write operation execution module again by the Comd_cs signal, the read-write operation execution module detects the BIT1=1 of command register, start the work of transmission data module, the value of transmitting data register is delivered on the I2C bus.After finishing this operation, fall the BIT1 of command register clearly, the BIT1 that command generation module detects the command register of reading and writing operation executing module reverts to 0, learns that last action finishes, begins next operation.The concrete operations of other instruction are not similarly just carefully stated one by one at this.
In sum, because command generation module and read-write operation execution module all are to be realized by hardware, so the access process of entire I 2C equipment does not have CPU to participate in substantially, two modules that just offer that CPU did are finished the necessary condition of visit I2C equipment.So this method has solved and has visited the undue dependence of I2C equipment to software in the prior art.
Claims (15)
1, a kind of device of realizing automatic reading and writing internal integrated device electronics, it is characterized in that, comprise with hard-wired command generation module and read-write operation execution module, described command generation module links to each other with active devices and described read-write operation execution module respectively by the asynchronous access bus, described read-write operation execution module links to each other with internal integrated circuit equipment by internal integrate circuit bus, wherein:
Described command generation module, be used to receive device address, the register address of enabling signal, read/write signal and internal integrated circuit equipment that described active devices provides and will write the data of register, automatically produce the required instruction of visit internal integrated circuit equipment, deliver to described read-write operation execution module in regular turn, and to described active devices link order implementation status and integrated device electronics data of reading internally;
Described read-write operation execution module, be used for instruction according to described command generation module, abide by the internal integrate circuit bus agreement and produce the signal sequence that visit internal integrated circuit equipment needs, execution is to the read-write operation of inner integrated device electronics, and to described command generation module link order implementation status.
2, device as claimed in claim 1, it is characterized in that, described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, data command and halt instruction when detecting active devices and will write an internal integrated circuit equipment.
3, device as claimed in claim 1, it is characterized in that, described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, halt instruction, sign on, device address instruction and read indication, reception data command and halt instruction when detecting active devices and will read an internal integrated circuit equipment.
4, device as claimed in claim 1 is characterized in that, described command generation module comprises:
The order control register by the value that the enabling signal and the read/write signal of described active devices is provided with corresponding control bit, starts inner integrated device electronics is read or write, and when carrying out failure error flag is set;
Device address register, the device address that is used to store the internal integrated circuit equipment that will visit;
The register address register, the address that is used to store the register of the internal integrated circuit equipment that will visit:
Write data register, be used to store the data that to write;
Read data register is used to store the data that will read;
Frequency division is provided with register, is used to be provided with the multiple relation between the CLK frequency of the frequency of the SDA/SCL signal of sending and input;
Described active devices is selected above-mentioned register by the address signal of asynchronous access bus.
5, device as claimed in claim 4, it is characterized in that, described command generation module is after finishing a read or write look-at-me to be set to described active devices link order implementation status, perhaps after the order control register executes operation with corresponding bit automatic clear, perhaps the combination by above dual mode realizes.
6, device as claimed in claim 1, it is characterized in that, described read-write operation execution module comprises command register, receive data register, transmitting data register, clock generating unit, START generation unit, STOP generation unit, data transmission unit and Data Receiving unit, wherein:
Described command register, the value of corresponding control bit is set by the instruction of described command generation module, control the startup of described START generation unit, STOP generation unit, data transmission unit and Data Receiving unit, and the operation complete after with the corresponding positions zero clearing;
Described receive data register is used for the data that data cached receiving element receives;
Described transmitting data register is used for the data that data cached transmitting element will send;
Clock generating unit is used for producing the required clock of each module of read-write operation execution module;
Described START generation unit is used for producing the START sequential that the internal integrate circuit bus agreement is stipulated;
Described STOP generation unit is used for producing the STOP sequential that the internal integrate circuit bus agreement is stipulated;
Described data transmission unit is used for according to the SDA of internal integrate circuit bus agreement regulation, the sequential of SCL the data in the described transmitting data register being sent on the internal integrate circuit bus;
Described Data Receiving unit is used for receiving the data on the internal integrate circuit bus according to the SDA of internal integrate circuit bus agreement regulation, the sequential of SCL.
7, device as claimed in claim 6, it is characterized in that, asynchronous access bus between described command generation module and the read-write operation execution module comprises reset signal, clock signal, writes enable signal, transmitting data register is selected signal, command register is selected signal, data bus input and output signal, and the circuit of error indication signal, described error indication signal is produced by the control bit of described command register, is used for to described command generation module link order implementation status.
8, a kind of method that realizes writing automatically internal integrated circuit equipment is applied to active devices by in hard-wired command generation module and write operation execution module and the system that internal integrate circuit bus links to each other, and this method may further comprise the steps:
(a) address of the internal integrated circuit equipment that will visit of described active devices writes the device address register of described command generation module;
(b) address of the internal integrated circuit device register that will visit of described active devices writes the register address register of described command generation module;
(c) the described active devices data that will write write the data register that writes of described command generation module;
(d) described active devices is provided with the corresponding BIT position startup write operation of order control register in the described command generation module;
(e) described command generation module produces automatically and writes the required instruction of internal integrated circuit equipment, delivers to described write operation execution module in regular turn;
(f) described write operation execution module is abideed by the generation of internal integrate circuit bus agreement and is write the signal sequence of internal integrated circuit equipment and finish write operation, the link order implementation status according to the instruction of described command generation module;
(g) described command generation module is to described active devices link order implementation status;
(h) after described active devices decision operation is correctly finished, finish one time write operation.
9, method as claimed in claim 8 is characterized in that, after the described step (h), if next operation and last operational access is same internal integrated circuit equipment, then directly returns step (b), otherwise returns step (a).
10, method as claimed in claim 8 is characterized in that, in the described step (e), described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, data command and halt instruction.
11, method as claimed in claim 8 is characterized in that, in the described step (h), described active devices is quoted by the interruption of described command generation module, perhaps detects the value of the corresponding control bit of described command generation module and confirms whether operation is correctly finished; The value of the error indication bit by detecting described command generation module judges whether to carry out the fault processing operation.
12, a kind of method that realizes reading automatically internal integrated circuit equipment is applied to active devices by in hard-wired command generation module and read operation execution module and the system that internal integrate circuit bus links to each other, and this method may further comprise the steps:
(a) address of the internal integrated circuit equipment that will visit of described active devices writes the device address register of described command generation module;
(b) address of the internal integrated circuit device register that will visit of described active devices writes the register address register of described command generation module;
(c) described active devices is provided with the corresponding BIT position startup read operation of order control register in the described command generation module;
(d) described command generation module produces automatically and reads the required instruction of internal integrated circuit equipment, delivers to described read operation execution module in regular turn;
(e) described read operation execution module is abideed by the generation of internal integrate circuit bus agreement and is read the signal sequence of internal integrated circuit equipment and finish read operation according to the instruction of described command generation module, and the link order implementation status;
(f) described command generation module is returned data and the condition execution instruction of reading to described active devices;
(g) after described active devices decision operation is correctly finished,, finish a read operation from described command generation module sense data.
13, method as claimed in claim 12 is characterized in that, after the described step (g), if next operation and last operational access is same internal integrated circuit equipment, then directly returns step (b), otherwise returns step (a).
14, method as claimed in claim 12, it is characterized in that, in the described step (d), described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, halt instruction, sign on, device address instruction and read indication, reception data command and halt instruction.
15, method as claimed in claim 12 is characterized in that, in the described step (g), described active devices is quoted by the interruption of described command generation module, perhaps detects the value of the corresponding control bit of described command generation module and confirms whether operation is correctly finished; The value of the error indication bit by detecting described command generation module judges whether to carry out the fault processing operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410000775 CN1292360C (en) | 2004-01-18 | 2004-01-18 | Device and method for implementing automatically reading and writing internal integrated circuit equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200410000775 CN1292360C (en) | 2004-01-18 | 2004-01-18 | Device and method for implementing automatically reading and writing internal integrated circuit equipment |
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| CN1558332A CN1558332A (en) | 2004-12-29 |
| CN1292360C true CN1292360C (en) | 2006-12-27 |
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| CN 200410000775 Expired - Fee Related CN1292360C (en) | 2004-01-18 | 2004-01-18 | Device and method for implementing automatically reading and writing internal integrated circuit equipment |
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| KR100687923B1 (en) * | 2005-04-29 | 2007-02-27 | 삼성전자주식회사 | Master device, control method thereof and electronic apparatus having master device |
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| CN116680230B (en) * | 2023-05-22 | 2024-04-09 | 无锡麟聚半导体科技有限公司 | Hardware acceleration circuit and chip |
| CN116450552B (en) * | 2023-06-09 | 2023-08-29 | 江苏润石科技有限公司 | Asynchronous batch register reading and writing method and system based on I2C bus |
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