CN200972508Y - Communication device between radar main control PC machine and receiver based on USB - Google Patents

Abstract

The utility model discloses an USB-based communications device for radar main control PC and receiver, which relates to a communications device for radar main control PC and receiver. The device comprises a radar receiver (1) and a radar main control PC (5), a data storage (2), a USB interface chip (3) and a USB connection cable (4); the radar receiver (1), the data storage (2), the USB interface chip (3) and a USB connection cable (4) and the radar main control PC (5) are connected in turn; the USB interface chip (3) adopts EZ-USB FX2 chip; the data storage (2) adopts the first in first out memory FIFO. The utility model features in convenient use and is easy to expand. The device has compact size, low cost and reliable transmission, so the device is suitable for the application of communications between the radar main control OC and receiver.

Description

Communication device between radar master control PC and receiver based on USB

Technical Field

The utility model relates to a communication device between radar master control PC and receiver especially relates to a communication device between radar master control PC and receiver based on USB.

Background

1. The high-frequency surface wave radar developed by the Wuhan university radio wave propagation laboratory is an advanced radar system for detecting marine environmental factors such as marine surface wind, wave, flow field, low-speed moving target and the like. The system adopts the linear frequency modulation pulse compression and software radio technology, and the receiver adopts the multi-channel receiving technology and the array signal processing technology, thereby obtaining abundant ocean information.

The working process of the radar system receiver is as follows: the echo signals entering each receiving channel are filtered and mixed, and then sent to a 14-bit analog-to-digital converter (ADC) for band-pass sampling. The sampled digital signals are sent to a Digital Signal Processor (DSP) or a field programmable logic device (FPGA) for processing, such as digital quadrature mixing, filtering, data rate extraction, Fast Fourier Transform (FFT), and the like. The processed signal is required to be transmitted to a PC for further signal processing and result characterization.

In a practical high-frequency radar system, in one working cycle, the data sequence output by the receiver comprises 12288 points, each point is 16-bit data, so that the total data output is 12288 × 16 bit-196608 bit-192 kbit. The time available for data transmission between the receiver and the PC in one working cycle is 0.016s at most. It can thus be calculated that the minimum data transfer speed that needs to be achieved is:

192kb/0.016s＝12000kb/s≈11.7Mb/s

therefore, in order to ensure accurate and timely transmission of data output from the receiver to the PC, a communication method having a data transmission rate much greater than 11.7Mb/s must be selected, and the communication method must have high reliability.

2. The current popular interfaces between peripheral devices and PCs are generally as follows:

(1) RS232 serial interface

The RS232 serial interface is a common interface for PCs. Its data and control information are serially transferred bit by bit. The highest data transmission rate is not more than 115Kbps, the transmission distance is not more than 15 meters, and the number of serial ports on the PC is limited, so that the expansion of peripheral equipment is limited.

(2) Parallel interface

Currently, the parallel interface in a PC is mainly used as a printer port. The parallel port transmits information on a plurality of data lines in units of bytes, so that the data transmission speed is greatly improved, and the information transmitted in parallel does not require a fixed format. However, the parallel signals have crosstalk problems, which is particularly serious in high-speed communication.

(3) ISA bus interface

The ISA bus is an industrial standard structure bus, also called AT bus, and has the data width of 16 bits, the working frequency of 8MHz and the data transmission rate of 6 MB/s. With the development of computer technology, the ISA bus is gradually eliminated, and most PC mainboards on the market do not have ISA slots.

(4) PCI bus interface

The PCI bus is a peripheral device interconnect bus by Intel corporation. The PCI bus has strict specification, ensures that the PCI bus has good compatibility, and the expansion card conforming to the PCI specification can be inserted into any PCI system to reliably work. PCI is independent of CPU, clock frequency is 33MHz, data transmission rate is as high as 132-264 MBps, and the equipment can be Plug and Play. However, the operation of frequently opening the chassis by adopting the PCI expansion card is inconvenient, the PCI slot on the host is limited, and in addition, signals directly enter the computer, various field signals cause great threat to the safety of the computer, and meanwhile, strong electromagnetic interference inside the computer also causes great influence on the signals.

(5) USB interface

USB is known as "universal serial bus" and is an emerging standard for computer peripheral serial communication interfaces. In recent years, there have been increasing numbers of PCs and peripheral devices that support USB. It has the following characteristics:

supporting hot plug. The USB can automatically detect the connection of the equipment, and the software can automatically complete the configuration without the intervention of a user.

And secondly, the expansion is convenient. Ports may be added to peripheral connections through the USB hub.

And thirdly, the USB2.0 protocol supports three rates of 1.5Mb/s, 12Mb/s and 480Mb/s, and is suitable for low-speed, medium-speed and high-speed equipment.

The USB device does not relate to the problems of IRQ conflict and the like, and the USB device independently uses the reserved interrupt of the USB device and does not contend for the limited resources of the PC machine with other devices.

The peripheral equipment can be powered up through a USB connecting cable, and the cable provides 5V direct current voltage.

And sixthly, an error detection mechanism is included to ensure the reliability of data transmission.

And supporting four transmission modes of block transmission (Bulk Transfer), Interrupt transmission (Interrupt Transfer), Isochronous Transfer (Isochronous Transfer) and Control Transfer (Control Transfer).

And has low cost.

From the above description, it can be seen that the USB can meet the speed and reliability requirements of high frequency radar data transmission, and is suitable for being used as a communication bus between a radar receiver and a master PC.

Disclosure of Invention

An object of the utility model is to provide a communication device between radar master control PC and receiver based on USB realizes sending the data of radar receiver output to master control PC accurately, in time.

The purpose of the utility model is realized like this:

the USB is used as a communication bus between the radar master control PC and the receiver, and a high-speed data transmission mode provided by the USB2.0 is adopted. Specifically, the method comprises the following steps:

as shown in fig. 1, the utility model comprises a radar receiver 1, a radar master control PC 5, a data memory 2, a USB interface chip 3 and a USB connecting cable 4;

the radar receiver 1, the data memory 2, the USB interface chip 3, the USB connecting cable 4 and the radar master control PC 5 are connected in sequence.

The utility model discloses a theory of operation is:

firstly, in each working period, after the radar receiver 1 collects and processes signals, the data memory 2 is emptied, and then the processed data is temporarily stored in the data memory 2;

the USB interface chip 3 reads data from the data memory 2;

establishing a block Transfer (Bulk Transfer) channel between the USB interface chip 3 and the radar master control PC 5;

and fourthly, the radar master control PC 5 reads data from the USB interface chip 3 through the block transmission channel.

The utility model has the advantages of it is following and positive effect:

1. is convenient to use. Because USB has the characteristics of hot plug and play, the user can connect and disconnect the receiver under the condition that the PC is started. When the receiver is connected to the system, the operating system will automatically detect the device and automatically load its associated device driver and configure it with its default configuration parameters, without the user having to reboot the system to complete the initialization and configuration work for it by the operating system.

2. Is convenient for expansion. The USB port supports the connection of a plurality of peripheral devices, and a USB host controller can be connected with a maximum of 126 peripheral devices through the USB hub. This feature facilitates the extension of the radar receiver data path.

3. And (4) miniaturization. Compared with other old PC interfaces, the USB interface is small and thin, and is suitable for miniaturization of the receiver volume.

4. The cost is low. The USB does not need a special external case, and the USB interface chip and the cable are low in price, so that the cost of the radar system is reduced.

5. The transmission is reliable. Compared with the prior serial interface, the data transmission of the USB bus has better fault tolerance. Such as adding CRC (cyclic redundancy check) checks to the data packets, including packet error handling and error recovery mechanisms in the protocol, and having the ability to identify defective devices and handle errors differently depending on the type of transmission. By adopting the USB communication bus, the correct transmission of radar data can be well guaranteed.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a circuit diagram of an EZ-USB FX2 chip and a first-in-first-out memory (FIFO);

FIG. 3 is a circuit diagram of the EZ-USB FX2 chip and PC.

Wherein,

1-a radar receiver;

2-a data memory for buffering receiver output data;

3-USB interface chip;

4-a USB connection cable;

5-radar master control PC;

A-EZ-USB FX2 chip;

b-first-in first-out memory (FIFO);

c-a read clock signal line, wherein the read clock signal is provided by A and is used as a clock signal for A and B to carry out synchronous data transmission;

d-read strobe signal line, the read clock signal is provided by A, when the read strobe signal is valid, B loads the data signal to E;

e-data signal lines;

f-interrupt signal line, interrupt signal is offered by B, in order to notify A data storage finish, can read;

6-USB downlink port of PC;

the 7-USB connecting cable internally comprises a power line, a ground line, a D + data line and a D-data line;

8-EZ-USB FX2 chip;

9-D + data lines;

10-D-data lines.

Detailed Description

The following detailed description is made with reference to the accompanying drawings and examples:

1. general of

The method is implemented according to the figure 1, namely, a data memory 2, a USB interface chip 3 and a USB connecting cable 4 are sequentially connected between a radar receiver 1 and a radar master control PC 5.

2. Parts of

1) USB interface chip 3

The USB interface chip 3 is an EZ-USB FX2 chip provided by Cypress company.

The EZ-USB FX2 chip supports full-speed transmission of 12Mb/s and high-speed transmission of 480Mb/s, and 4 USB transmission modes can be used: control transfer, interrupt transfer, block transfer, and isochronous transfer. The chip mainly comprises a USB2.0 transceiver, a Serial Interface Engine (SIE), an enhanced 8051, an 8.5KB Random Access Memory (RAM), a 4KB first-in first-out (FIFO) memory, an I/O port, a data bus, an address bus, a general purpose programmable interface (GPIF) and the like. The Serial Interface Engine (SIE) is responsible for performing functions related to the USB protocol, such as encoding and decoding of serial data, error control, and bit stuffing. Enhanced 8051, as the internal processor (CPU) of EZ-USB FX2, is primarily responsible for controlling the peripheral connections of the chip. A 4KB FIFO memory is used as a configurable buffer for the endpoints 2, 4, 6, 8. Endpoints 2, 4, 6, 8 are high capacity, high bandwidth data transfer endpoints that do not require 8051 firmware intervention to accomplish high speed data transfers with peripheral circuits. In addition, EZ-USB FX2 chip contains 3 fixed 64-byte endpoint buffers inside, which are used to control endpoint 0, input endpoint 1 and output endpoint 1, respectively.

EZ-USB FX2 provides two high-speed transmission modes of Slave first-in first-out (Slave FIFO) and general purpose programmable interface (GPIF): when EZ-USB FX2 operates in Slave FIFO mode, peripheral circuitry may read and write endpoint data buffers in EZ-USB FX2 as normal FIFO; EZ-USB FX2 may be programmed by software to output read and write control waveforms when EZ-USB FX2 operates in GPIF mode. At this point it can access almost any general purpose bus interface. In practical application, different data transmission modes can be flexibly selected.

2) Data storage

The data memory 2 is a first-in first-out memory (FIFO).

3. Hardware connection

1) The radar receiver is connected to a first-in-first-out memory (FIFO).

2) A first-in-first-out memory (FIFO) is connected to the USB interface chip EZ-USB FX2 as shown in FIG. 2. The read clock signal and the read strobe signal are provided from the EZ-USB FX2 to a first-in-first-out buffer (FIFO), and the data signal and the interrupt signal are provided from a first-in-first-out memory (FIFO) to the EZ-USB FX2 chip.

3) The EZ-USB FX2 chip is connected with the USB downlink port of the radar master PC according to the diagram in FIG. 3. Two data output pins of the EZ-USB FX2 are respectively connected with data lines D + and D-of a USB connecting cable, and two data pins in a USB downlink port of the radar master control PC are also respectively connected with data lines D + and D-of the other end of the USB connecting cable.

4. Software design

The software design mainly comprises the design of software such as USB interface chip firmware, device drivers, client application programs and the like.

The firmware of the USB interface chip is the program code which is solidified in the USB interface chip and executed by a chip internal processor (CPU), and for the EZ-USB FX2 chip, the program code is executed by an 8051 singlechip. The USB device driver is kernel level software of the PC operating system and is responsible for interfacing with USB system software, such as a USB bus driver, to complete data communication with USB peripheral devices. The client application program is responsible for interfacing with the USB device driver to operate the USB device and provide visual operations to the user.

The writing of each part of software is described in turn below.

1) Designing USB interface chip firmware

The Cypress corporation, the manufacturer of EZ-USB series chips, provides a firmware library and firmware development framework. The framework performs some of the basic functions of USB communication. Adding code in the framework simplifies the development of firmware.

The firmware of the EZ-USB FX2 of the present example mainly comprises the following parts:

(1) in the initialization function, the transmission mode of the endpoint 2 of the EZ-USB FX2 is configured to be block transmission (bulk transfer), the transmission direction is input, the maximum data packet length is 512 bytes, and the size of an endpoint buffer area is 4096 bytes; enabling input endpoint 1 and endpoint 2; enable interrupt of input endpoint 1; and configures the GPIF output waveform register.

(2) In an interrupt service function corresponding to an interrupt signal sent from a first-in-first-out memory (FIFO), 1 byte of data is written into an endpoint buffer of an input endpoint 1, and 1 is written into an endpoint byte counter of the input endpoint 1 to mark that 1 byte of data is available for reading in the endpoint buffer of the input endpoint 1.

(3) In the interrupt service function corresponding to the input terminal 1, a GPIF output waveform is started, a read strobe signal is enabled, data is read into a buffer area of a terminal 2 of a chip from a first-in first-out memory (FIFO), and the data is sequentially sent to a PC (personal computer) by taking 512 bytes as 1 data packet length.

2) Designing USB device driver

The USB device driver sends an I/O Request by sending an IRP (I/O Request Packet) containing a URB (USB command block) to the USB bus driver, and provides one or empty or full memory buffer according to the data transfer direction (input or output); then the USB bus driver manages the data transmission; after the transmission is finished, the USB device driver can be informed that the IRP is finished.

The USB device driver of this example employs a generic driver EZ-USB GENERAL PURPOSE DEVICE DRIVER (GPD) provided by Cypress corporation for EZ-USB series chips. It provides some standard user mode interfaces for device requests and data transfers and designs its own I/O control operations (IOCTL) for them. The application program can talk with the driver program through the IOCTL operations, and the driver program sends IRP with a USB Request Block (URB) to the bus driver program according to the I/O control operation code, so that the read-write operation of the USB peripheral is completed.

3) Designing client applications

The client application gets a handle to access the device driver by calling Win32 function CreateFile (), and performs I/O control on the device by calling Win32 function DeviceIoControl () to perform IOCTL operation. The client application of this example essentially comprises the following steps:

(1) calling Win32 function CreateFile () to get the handle of the access device driver;

(2) calling a Win32 function DeviceIoControl () to send a read request to an input endpoint 1 of an EZ-USB FX2, entering the next step when 1 byte of data is read and the data is judged to be correct, and otherwise, circularly executing the step;

(3) calling a Win32 function DeviceIoControl () to send a read request to an endpoint 2 of an EZ-USB FX2, and reading radar receiver data from a first-in first-out memory (FIFO);

(4) calling Win32 function CloseHandle () deletes the device handle that accesses the device driver.

5. The detailed workflow of this example is as follows:

1) in a radar system working period, after the receiver processes the signal, the FIFO is emptied first, and then the output data is stored in the FIFO. After the storage is finished, the first-in first-out memory (FIFO) sends an interrupt signal to the USB interface chip.

2) After receiving the interrupt signal, the USB interface chip writes 1 byte of data into the endpoint buffer of the input endpoint 1, and writes 1 into the endpoint byte counter of the input endpoint 1, so as to indicate that 1 byte of data is available for reading in the endpoint buffer of the input endpoint 1.

3) The PC application program calls a Win32 function DeviceIoControl () to send a read request to an input endpoint 1 of an EZ-USB FX2, and when 1 byte of data is read and the data is judged to be correct, the read request is sent to an endpoint 2;

4) after the PC reads 1 byte of data from the input endpoint 1, the USB interface chip will generate the interrupt of the input endpoint 1, and mark that the host computer is allowed to receive radar data; at the moment, the USB interface chip starts GPIF to output a waveform, outputs a read strobe signal, and reads data into a buffer area of an endpoint 2 from a first-in first-out memory (FIFO);

5) the PC reads data from the buffer of endpoint 2 of the USB interface chip.

Claims (3)

1. The utility model provides a communication device between radar master control PC and receiver based on USB, includes radar receiver (1) and radar master control PC (5), its characterized in that:

the USB interface chip also comprises a data memory (2), a USB interface chip (3) and a USB connecting cable (4);

the radar receiver (1), the data memory (2), the USB interface chip (3), the USB connecting cable (4) and the radar master control PC (5) are connected in sequence.

2. The apparatus of claim 1, wherein the apparatus further comprises:

the USB interface chip (3) adopts an EZ-USB FX2 chip.

3. The apparatus of claim 1, wherein the apparatus further comprises:

the data memory (2) is a first-in first-out memory FIFO.

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