CN1960242B - Method, device, system for implementing clock synchronization, and distribution system - Google Patents

Method, device, system for implementing clock synchronization, and distribution system Download PDF

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Publication number
CN1960242B
CN1960242B CN2006101409425A CN200610140942A CN1960242B CN 1960242 B CN1960242 B CN 1960242B CN 2006101409425 A CN2006101409425 A CN 2006101409425A CN 200610140942 A CN200610140942 A CN 200610140942A CN 1960242 B CN1960242 B CN 1960242B
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sync
slave
main frame
delay
local
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CN1960242A (en
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黄文君
遇彬
靳旭哲
胡斌
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ZHONGKONG SCIENCE AND TECHNOLOGY GROUP Co Ltd
Zhejiang University ZJU
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ZHONGKONG SCIENCE AND TECHNOLOGY GROUP Co Ltd
Zhejiang University ZJU
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node

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Abstract

The invention provides a method for implementing clock synchronization including: obtaining a local sending timestamp when a host computer sends SYNC first data packet and a local receiving timestamp when a slave computer receives SYNC between a media access control controller and a physical layer device transceiver, and obtaining the local sending timestamp when the slave computer sends DELAY_REQ and the local receiving timestamp when the host computer receives the DELAY_REQ, using the obtained the local sending timestamp when the host computer sends the SYNC, the local receiving timestamp when the slave computer receives the SYNC, the local sending timestamp when the slave computer sends the DELAY_REQ and the local receiving timestamp when the host computer receives the DELAY_REQ to calculate the network transmission delay of the SYNC from the host computer and the slave computer; according to the local sending timestamp when the host computer sends the SYNC, the local receiving timestamp when the slave computer receives the SYNC and the network transmission delay of the SYNC from the host computer to the slave computer, calculating the counting value deviation between clock counters; correcting the deviation. The invention also provides a device, a system and a distributed system for implementing clock synchronization.

Description

Realize method, device, system and the distributed system of clock synchronization
Technical field
The present invention relates to distributed control technology, relate in particular to Clock Synchronization Technology.
Background technology
In industrial automation, motion control, electric power or telecommunications distributed system, the simultaneous techniques of real-time clock has a wide range of applications.
Fig. 1 is the structural representation of present a kind of clock system.As shown in Figure 1, CPU12 writes the data packet MAC (Media Access Control, medium access control) after the buffer memory of Controller (controller) 13, order MAC Controller13 to send packet again, after MAC Controller13 receives order, according to the data mobility status in the network, select the suitable time that packet is sent to PHY (Physical Layer Device, physical layer equipment) Transceiver (transceiver) 14, after PHYTransceiver14 finishes conversion of signals, packet is sent in the network.
For the clock synchronization that realizes that precision is higher, after MAC Controller13 receives the transmission order that CPU12 sends, should send packet immediately, with the Network Transmission delay fluctuation minimum that guarantees to be introduced by MAC Controller13, this is further requirement just, when MAC Controller13 sends packet, network is an idle condition, that is, do not have other packet to send, and other node on the network can not send packet within a certain period of time yet, in order to avoid cause collision.So CPU12 needs the dispatch network communication to satisfy above-mentioned requirements.In addition, when MAC Controller13 receives a packet and when CPU12 sent interrupt request singal, CPU12 must make an immediate response from network, make the Network Transmission delay fluctuation minimum of introducing by CPU12 response interrupt requests.
In addition, between CPU12 and MAC Controller13, obtain the timestamp of the transmission and the reception of packet, re-use adjustable source oscillation signal and regulate the counting rate of clock counter, make every effort to reach the synchronous of clock, promptly the counting rate of principal and subordinate's clock counter is identical, count value equal.In this process, record CPU12 sends the moment that sends order to MAC Controller13 and stabs as transmitting time, the moment of the interrupt requests of record CPU12 response MAC Controller13 stabs as time of reception, the purpose that acquisition time stabs is exactly in order to calculate the deviation of count value between the clock counter, so, the precision of timestamp directly influences the deviation result who calculates, thus the effect that remote-effects are proofreaied and correct.But, after MACController13 receives the order that CPU12 sends, in the time of generally can being chosen in the network proper state packet is sent, so, the moment that CPU12 gives an order is MAC Controller13 moment of sending packet not necessarily, and in addition, MAC Controller13 is after CPU12 sends interrupt requests, CPU12 might not make an immediate response, and the current running status of the true moment that CPU12 responds this interrupt requests and CPU12 is relevant.Therefore, the precision of the timestamp that obtains between CPU12 and MAC Controller13 is not high, thereby causes the precision of the clock synchronization of this method realization can't reach the submicrosecond level.
Therefore, present Clock Synchronization Technology does not realize that also high accuracy clock is synchronous.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method, device, system and distributed system that realizes clock synchronization, to improve the precision of clock synchronization.
For addressing the above problem, the invention provides a kind of method that realizes clock synchronization, comprise: between media access controller and physical layer equipment transceiver, obtain main frame and send the local transmitting time stamp of SYNC and the local reception timestamp that slave receives SYNC, and obtain slave and send the local transmitting time stamp of DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, the main frame that utilization is obtained sends the local transmitting time of SYNC and stabs, slave receives the local reception timestamp of SYNC, the local transmitting time that slave sends DELAY_REQ is stabbed and main frame receives the local reception timestamp of DELAY_REQ, calculates the Network Transmission delay of SYNC when main frame propagates into slave; Send the local reception timestamp that local transmitting time is stabbed, slave receives SYNC of SYNC and the SYNC Network Transmission when main frame propagates into slave according to main frame and postpone, calculate the deviation of count value between the clock counter; Described deviation is proofreaied and correct.
Obtain that local transmitting time that main frame sends SYNC is stabbed and process that slave receives the local reception timestamp of SYNC is realized by following step: after receiving SYNC, write down the sequence number of described SYNC and the local reception timestamp of slave reception SYNC; After receiving the FOLLOW_UP that carries timestamp, write down sequence number and the described timestamp of described FOLLOW_UP, if the sequence number of described FOLLOW_UP is identical with the sequence number of described SYNC, then described timestamp is the local transmitting time stamp that described main frame sends SYNC.
Calculate the deviation of count value between the clock counter according to following formula:
Offset＝TxSyncTime-RxSyncTime+OneWayDelay，
Wherein, Offset is the deviation of count value between the clock counter, TxSyncTime is the local transmitting time stamp that described main frame sends SYNC, RxSyncTime is the local reception timestamp that described slave receives SYNC, and the Network Transmission that OneWayDelay is described SYNC when main frame propagates into slave postpones.
Obtain that local transmitting time that slave sends DELAY_REQ is stabbed and the process of the local reception timestamp of main frame reception DELAY_REQ is realized by following step: send DELAY_REQ; Write down the sequence number of described DELAY_REQ and the local transmitting time stamp that slave sends DELAY_REQ; The DELAY_RESP of timestamp is carried in reception; Write down sequence number and the described timestamp of described DELAY_RESP, if the sequence number of described DELAY_RESP is identical with the sequence number of described DELAY_REQ, then described timestamp is the local reception timestamp that described main frame receives DELAY_REQ.
The Network Transmission of being calculated described first packet by following formula postpones OneWayDelay:
OneWayDelay＝(RxReqTime-TxReqTime)/2-(TxSyncTime?-RxSyncTime)/2，
Wherein, RxReqTime is the local reception timestamp that described main frame receives DELAY_REQ, and TxReqTime is the local transmitting time stamp that described slave sends DELAY_REQ.
The Network Transmission of the described SYNC that continuous several times is calculated when main frame propagates into slave postpones OneWayDelay averages, with described mean value as calculating the employed OneWayDelay of Offset.
The process that described deviation is proofreaied and correct is realized by following step: according to described deviation calculation frequency compensation value; Regulate described frequency compensation value, so that the deviation of count value is zero between the clock counter.
The present invention also provides a kind of device of realizing clock synchronization, comprise: receive grabber, be used between media access controller and physical layer equipment transceiver, obtaining that local transmitting time that local reception timestamp, main frame that slave receives SYNC send SYNC is stabbed and the local reception timestamp of main frame reception DELAY_REQ; Send grabber, be used between media access controller and physical layer equipment transceiver, obtaining the local transmitting time stamp that slave sends DELAY_REQ; Controller, the local transmitting time that is used to utilize main frame to send SYNC is stabbed, slave receives the local reception timestamp of SYNC, slave sends the local transmitting time stamp of DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, calculating the Network Transmission of SYNC when main frame propagates into slave postpones, and receive the local reception timestamp of SYNC according to described slave, the local transmitting time that main frame sends SYNC is stabbed and the Network Transmission of SYNC when main frame propagates into slave postpones, the deviation of count value and according to described deviation calculation frequency compensation value between the calculating clock counter; The frequency compensation clock is used for according to crystal oscillator frequency and described frequency compensation value, adjusts counting rate.
Described clock counter is the frequency compensation clock.
The present invention also provides a kind of system that realizes clock synchronization, comprising: CPU is used for handle packet; Media access controller is used for data cached bag; The physical layer equipment transceiver is used for packet is carried out conversion of signals; Wherein, described media access controller sends to described physical layer equipment transceiver according to the order of described CPU with described cached data packet, and/or, described cached data packet is sent to described CPU; Described system also comprises: clock synchronizer, be used between described media access controller and described physical layer equipment transceiver, obtaining main frame and send the local transmitting time stamp of SYNC and the local reception timestamp that slave receives SYNC, and obtain slave and send the local transmitting time stamp of DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, the main frame that utilization is obtained sends the local transmitting time of SYNC and stabs, slave receives the local reception timestamp of SYNC, slave sends the local transmitting time stamp of DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, calculating the Network Transmission of SYNC when main frame propagates into slave postpones, send the local transmitting time of SYNC stabs according to main frame, slave receives the local reception timestamp of SYNC and the SYNC Network Transmission when main frame propagates into slave to postpone, calculate the deviation of count value between the clock counter, and described deviation is proofreaied and correct.
Described clock synchronizer is an on-site programmable gate array FPGA.
The present invention also provides a kind of distributed system, comprises at least one main frame and at least one slave, and described main frame and slave comprise respectively: CPU is used for handle packet; Media access controller is used for data cached bag; The physical layer equipment transceiver is used for packet is carried out conversion of signals; Described slave also comprises: clock synchronizer, be used between described media access controller and described physical layer equipment transceiver, obtaining main frame and send the local transmitting time stamp of SYNC and the local reception timestamp that slave receives SYNC, and obtain slave and send the local transmitting time stamp of DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, the main frame that utilization is obtained sends the local transmitting time of SYNC and stabs, slave receives the local reception timestamp of SYNC, slave sends the local transmitting time stamp of DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, calculating the Network Transmission of SYNC when main frame propagates into slave postpones, send the local transmitting time of SYNC stabs according to main frame, slave receives the local reception timestamp of SYNC and the SYNC Network Transmission when main frame propagates into slave to postpone, calculate the deviation of count value between the clock counter, and described deviation is proofreaied and correct.
Described main frame also comprises: clock synchronizer is used to monitor all signals between media access controller and the physical layer equipment transceiver.
Compared with prior art, the present invention has the following advantages:
In the present invention, the acquisition point of timestamp is between media access controller and physical layer equipment transceiver, because packets need is passed through CPU successively, media access controller and physical layer equipment transceiver just can send in the network, generally speaking, media access controller can not send packet after receiving CPU transmission order immediately, so, if acquisition time stabs between CPU and media access controller, then the deviation that goes out of subsequent calculations is not very accurate, therefore, the timestamp that the present invention obtains can provide foundation more accurately for subsequent treatment, thereby correcting action more suitably improves the precision of clock synchronization.
In the present invention, can frequency of utilization compensating clock regulating frequency offset, the frequency compensation clock is a kind of hard-wired high-resolution, high accuracy clock counter, its existence makes, even use common non-adjustable active or passive crystal oscillator to make signal source of clock, still can realize the accurate adjusting of clock, owing to use non-adjustable crystal oscillator cost lower, so the frequency of utilization compensating clock can reduce cost.
In the present invention, Network Transmission is postponed and can average,, reduced the influence of the fluctuation of Network Transmission delay synchronization accuracy with the data of mean value as calculation deviation.
Description of drawings
Fig. 1 is the structural representation of present a kind of clock system;
Fig. 2 is a kind of flow chart of the inventive method;
Fig. 3 is a kind of structural representation of apparatus of the present invention;
Fig. 4 is the structural representation of frequency compensation clock;
Fig. 5 is a kind of structural representation of clock system of the present invention.
Embodiment
Below we will be in conjunction with the accompanying drawings, optimum implementation of the present invention is described in detail.At first it is to be noted, the implication of the term of using among the present invention, words and claim can not only only limit to its literal and common implication and go to understand, the implication and the notion that also comprise and then conform to technology of the present invention, this is because we are as the inventor, to suitably provide the definition of term, so that the most appropriate description is carried out in our invention.Therefore, the configuration that provides in this explanation and the accompanying drawing is first-selected embodiment of the present invention, rather than will enumerates all technical characteristics of the present invention.We will recognize to also have the various equivalent scheme or the modifications that can replace our scheme.
At first, the overall technical architecture to method provided by the invention describes.Method of the present invention comprises: the local transmitting time of obtaining first packet between media access controller and physical layer equipment transceiver is stabbed and the local reception timestamp; Stab and the local reception timestamp calculates the deviation of count value between the clock counter according to the local transmitting time of described first packet; Described deviation is proofreaied and correct.
Method provided by the invention can be applied in the distributed system, further, is applied in main frame in the distributed system and/or the clock system in the slave, and clock system should comprise a clock synchronization apparatus.
Now method of the present invention is elaborated.
Fig. 2 is a kind of flow chart of implementing the inventive method.As shown in Figure 2:
Step S201: main frame sends SYNC (first packet) at regular intervals, and the sequence number TxSyncSeq of record SYNC and local transmitting time stamp TxSyncTime.
Main frame sends time interval of SYNC at every turn should be identical, for example, can be fixed as 1 second, but this time interval allows ± 10% error.
SYNC encapsulates with the form of PTP (Precision Time Protocol, Precision Time Protocol), sends as the broadcast frame or the multicast frame of media access control sublayer, and all slaves in the network can receive this frame.
When main frame sent SYNC, the clock synchronization apparatus of main frame can detect sending of SYNC, and the sequence number TxSyncSeq of record SYNC and local transmitting time stamp TxSyncTime.The clock synchronization apparatus of main frame can be ignored the data that SYNC carries.
Step S202: slave writes down sequence number RxSyncSeq and the local reception timestamp RxSyncTime of described SYNC.
When the clock synchronization apparatus of slave detects SYNC, only write down sequence number RxSyncSeq and the local reception timestamp RxSyncTime of described SYNC, can ignore the data that described SYNC carries.
Step S203: main frame stabs TxSyncTime with the sequence number TxSyncSeq of SYNC of record and local transmitting time and is packaged into FOLLOW UP (second packet) and sends.
After main frame sends SYNC, the CPU of main frame takes out sequence number TxSyncSeq and the local transmitting time of SYNC immediately and stabs TxSyncTime from the clock synchronization apparatus of main frame, with TxSyncSeq as sequence number, TxSyncTime is as data, being packaged into a new packet FOLLOW_UP sends, FOLLOW_UP sends as the broadcast frame of media access control sublayer or multicast frame, and all slaves in the network can receive this frame.
Step S204: the sequence number RxFollowSeq of slave record FOLLOW_UP and the data TxSyncTime that carries, it is right to obtain the TxSyncTime-RxSyncTime timestamp.
After slave received FOLLOW_UP, the clock synchronization apparatus of slave not only can write down the sequence number RxFollowSeq of FOLLOW_UP, can also obtain the data TxSyncTime that carries among the FOLLOW_UP, and record TxSyncTime.Slave can also judge further whether RxSyncSeq is identical with RxFollowSeq, if it is right then to have obtained a TxSyncTime-RxSyncTime timestamp.
Step S205: slave sends DELAY_REQ to main frame, and the sequence number TxReqSeq of record DELAY_REQ (the 3rd packet) and local transmitting time stamp TxReqTime.
When slave receives SYNC or FOLLOW_UP, just obtained the physical address of main frame.Receive after the FOLLOW_UP, slave initiatively sends DELAY_REQ to main frame, and DELAY_REQ is the unicast frame of a media access control sublayer, has only main frame just can receive.The clock synchronization apparatus of slave detects sending of DELAY_REQ, and sequence number TxReqSeq and the local transmitting time of record DELAY_REQ are stabbed TxReqTime.
Source physical address SlavePhyAddr, the sequence number RxReqSeq of step S206: host record DELAY_REQ and local reception timestamp RxReqTime.
When DELAY_REQ arrived main frame, the clock synchronization apparatus of main frame detected the arrival of DELAY_REQ, source physical address SlavePhyAddr, sequence number RxReqSeq and the local reception timestamp RxReqTime of record DELAY_REQ.
Owing to may exist a plurality of slaves to send DELAY_REQ and main frame can not be handled the situation of all DELAY_REQ rapidly to main frame simultaneously, so main frame can use formation to preserve SlavePhyAddr, RxReqSeq and RxReqTime, handle all DELAY_REQ in regular turn according to FIFO (First-In First-Out, first in first out) principle.The clock synchronization apparatus of main frame is when detecting a new Frame and arrive, the write pointer of backup current queue, continuous reception along with data, deposit the data corresponding to the SlavePhyAddr among the DELAY_REQ, RxReqSeq and RxReqTime position in the receiving data stream in formation, and the data of RxReqTime position are replaced with the local reception timestamp of this frame of host record.When this frame received, whether the clock synchronization apparatus of main frame just identifies it was DELAY_REQ, if not, then the write pointer with formation reverts to that value that backs up when just beginning to receive this frame, if then do not do any operation.In order to prevent under unexpected situation, the CPU of main frame is different from the analysis result of clock synchronization apparatus to same received frame to the analysis result of received frame, cause the information such as RxReqTime of a synchronizing cycle to be stayed not being read in the formation and cause harmful effect, the clock synchronization apparatus of main frame all is set at the read pointer of formation the value of current write pointer when detecting SYNC at every turn and send.
Step S207: main frame is packaged into SlavePhyAddr, RxReqSeq, RxReqTime DELAY_RESP (the 4th packet) and sends to slave.
Main frame is received after the DELAY_REQ that slave sends, from clock synchronization apparatus, take out SlavePhyAddr, RxReqSeq, RxReqTime, be packaged into DELAY_RESP and send, wherein, SlavePhyAddr is as target physical address, RxReqSeq is as sequence number, and RxReqTime is as general data.
Step S208: the sequence number of slave record DELAY_RESP and the data RxReqTime that DELAY_RESP carries, it is right to obtain a TxReqTime-RxReqTime timestamp.
When DELAY_RESP arrives slave, the sequence number RxRespSeq of slave record DELAY_RESP and the data RxReqTime that DELAY_RESP carries, if TxReqSeq is identical with RxRespSeq, it is right then to have obtained a TxReqTime-RxReqTime timestamp.
Step S209: the TxSyncTime-RxSyncTime timestamp that utilize to obtain to and the TxReqTime-RxReqTime timestamp postpone calculating the Network Transmission of SYNC when main frame propagates into slave.
Can calculate the value that Network Transmission postpones OneWayDelay by following formula:
OneWayDelay＝(RxReqTime-TxReqTime)/2-(TxSyncTime-RxSyncTime)/2，
Wherein, TxSyncTime-RxSyncTime is that the last timestamp that obtains is right before obtaining RxReqTime-TxReqTime.
In order to reduce fluctuation that Network Transmission postpones influence to subsequent calculations, can use the method for mean filter, that is, the OneWayDelay that repeatedly calculates is recently averaged the value that this mean value postpones as the Network Transmission of SYNC when main frame propagates into slave.Experiment shows, the mean value that nearest 16 OneWayDelay are tried to achieve is more satisfactory as the value that the Network Transmission of SYNC when main frame propagates into slave postpones.
Step S210: the TxSyncTime-RxSyncTime timestamp that utilize to obtain to and the value computation host clock counter that postpones of the Network Transmission of SYNC when main frame propagates into slave and slave clock counter between the deviation of count value.
Can calculate the deviation Offset of count value between slave clock counter and the host clock counter by following formula:
Offset＝TxSyncTime-RxSyncTime+OneWayDelay，
Wherein, when host clock was faster than slave clock, Offset was greater than zero, and when host clock was slower than slave clock, Offset was less than zero.
Step S211: according to the deviation calculation frequency compensation value of the count value between host clock counter and the slave clock counter.
Step S212: the regulating frequency offset, so that the deviation of the count value between host clock counter and the slave clock counter gradually becomes zero within a certain period of time.
Suppose that the deviation that last synchronometer is calculated is Offset 0, the deviation that a current synchronometer is calculated is Offset 1, can predict that then the deviation calculated of synchronometer will be Offset next time 2=2*Offset 1-Offset 0Therefore, should the regulating frequency offset, make the slave clock current this synchronizing cycle the internal clock counter value recruitment than on a synchronizing cycle many Offset 2So,, the deviation calculated of synchronometer will be zero next time.
Under the condition that has obtained Offset, the frequency compensation value that calculating makes new advances realizes the trace of clock counter counting rate is regulated, make between the host clock counter with the slave clock counter between counting rate consistent, eliminate the deviation of count value, reach the purpose of clock synchronization.
Need to prove, SYNC, FOLLOW_UP, DELAY_REQ and DELAY_RESP are UDP (User Datagram Protocol, user datagram protocol) frame, the sequence number and the timestamp that in the field payload of UDP frame, are comprising the PTP frame, wherein, the numerical value of the timestamp among FOLLOW_UP and the DELAY_RESP is significant, and the numerical value of the timestamp among SYNC and the DELAY_REQ can be filled in arbitrarily.
No matter be main frame or slave identify the Frame that is sending afterwards frame beginning flag position (Start Frame Delimiter) of lead code (preamble) time, can write down the local transmitting time of this frame and stab.If it is SYNC that main frame identifies this frame, then preserves this timestamp and supply the CPU of main frame to read; If it is DELAY_REQ that slave identifies this frame, then preserves this timestamp and be used for the calculated rate offset.
No matter be main frame or slave identify the Frame that is receiving afterwards frame beginning flag position (Start Frame Delimiter) of lead code (preamble) time, can write down the local reception timestamp of this frame.If it is DELAY_REQ that main frame identifies this frame, then preserves this timestamp and supply the CPU of main frame to read; If it is SYNC that slave identifies this frame, then preserves this timestamp and be used for the calculated rate offset.
Now clock synchronization apparatus of the present invention and operation principle thereof are described.
Fig. 3 is a kind of structural representation of apparatus of the present invention.As shown in Figure 3, clock synchronization apparatus 31 comprises: send grabber (transmit capture) 311, be used to monitor the data that flow to the physical layer equipment transceiver from media access controller, and judge whether the current Frame that flows through is the PTP frame; Receive grabber (receive capture) 312, be used to monitor the data that flow to media access controller from the physical layer equipment transceiver, and judge whether the current Frame that flows through is the PTP frame; Cpu i/f (CPU interface) 313 is used for and CPU interaction data and control information, and for CPU, this interface is equivalent to a RAM (Random Access Memory, random access memory); Controller (controller) 314 is used to calculate the frequency compensation value of clock counter; Frequency compensation clock (frequencycompensation clock) 315 is 64 adjustable clock counters, is used for counting with the metering time according to crystal oscillator frequency and described frequency compensation value.
Need to prove that main frame and slave all can have clock synchronization apparatus 31.
Main frame sends SYNC at regular intervals, and the transmission grabber 311 of main frame can detect sending of SYNC, and the sequence number TxSyncSeq of record SYNC and local transmitting time stamp TxSyncTime.The data that 311 couples of SYNC of the transmission grabber of main frame carry can be ignored.When the reception grabber 312 of slave detects SYNC, only write down sequence number RxSyncSeq and the local reception timestamp RxSyncTime of described SYNC, also can ignore the data that described SYNC carries.
After main frame sends SYNC, the CPU of main frame takes out sequence number TxSyncSeq and the local transmitting time stamp TxSyncTime of SYNC immediately from the clock synchronization apparatus 31 of main frame by the cpu i/f 313 of main frame, with TxSyncSeq as sequence number, TxSyncTime is packaged into a new packet FOLLOW_UP and sends as data.After slave receives FOLLOW_UP, the reception grabber 312 of slave not only can write down FOLLOW_UP sequence number RxFollowSeq, can also obtain the data TxSyncTime that carries among the FOLLOW_UP, and the record TxSyncTime.Slave can also judge further whether RxSyncSeq is identical with RxFollowSeq, if it is right then to have obtained a TxSyncTime-RxSyncTime timestamp.
When slave receives SYNC or FOLLOW_UP, just obtained the physical address of main frame.Receive after the FOLLOW_UP, slave initiatively sends DELAY_REQ to main frame, and the transmission grabber 311 of slave detects sending of DELAY_REQ, and sequence number TxReqSeq and the local transmitting time of record DELAY_REQ are stabbed TxReqTime.When DELAY_REQ arrived main frame, the reception grabber 312 of main frame detected the arrival of DELAY_REQ, source physical address SlavePhyAddr, sequence number RxReqSeq and the local reception timestamp RxReq_Time of record DELAY_REQ.
Owing to may exist a plurality of slaves to send DELAY_REQ and main frame can not be handled the situation of all DELAY_REQ rapidly to main frame simultaneously, so main frame can use formation to preserve SlavePhyAddr, RxReqSeq and RxReqTime, handle all DELAY_REQ in regular turn according to FIFO (First-In First-Out, first in first out) principle.The reception grabber 312 of main frame is when detecting a new Frame and arrive, the write pointer of backup current queue, continuous reception along with data, deposit the data corresponding to the SlavePhyAddr among the DELAY_REQ, RxReqSeq and RxReqTime position in the receiving data stream in formation, and the data of RxReqTime position are replaced with the local reception timestamp of this frame of host record.When this frame received, whether the reception grabber 312 of main frame just identifies it was DELAY_REQ, if not, then the write pointer with formation reverts to that value that backs up when just beginning to receive this frame, if then do not do any operation.In order to prevent under unexpected situation, the CPU of main frame is different from the analysis result that receives 312 pairs of same received frames of grabber to the analysis result of received frame, cause the information such as RxReqTime of a synchronizing cycle to be stayed not being read in the formation and cause harmful effect, when the transmission grabber 311 of main frame detected SYNC at every turn and sends, main frame all was set at the read pointer of formation the value of current write pointer.
Main frame is received after the DELAY_REQ that slave sends, cpu i/f 313 by main frame takes out SlavePhyAddr, RxReqSeq, RxReqTime from clock synchronization apparatus 31, be packaged into DELAY_RESP and send, wherein, SlavePhyAddr is as target physical address, RxReqSeq is as sequence number, and RxReqTime is as general data.When DELAY_RESP arrives slave, the sequence number RxRespSeq of the reception grabber 312 record DELAY_RESP of slave and the data RxReqTime that DELAY_RESP carries, if TxReqSeq is identical with RxRespSeq, it is right then to have obtained a TxReqTime-RxReqTime timestamp.
The TxSyncTime-RxSyncTime timestamp that controller 314 utilization obtains to and the TxReqTime-RxReqTime timestamp postpone calculating the Network Transmission of SYNC when main frame propagates into slave.
Can calculate the value that Network Transmission postpones OneWayDelay by following formula:
OneWayDelay＝(RxReqTime-TxReqTime)/2-(TxSyncTime?-RxSyncTime)/2，
Wherein, RxReqTime-TxReqTime is the last timestamp that obtains behind the acquisition TxSyncTime-RxSyncTime.
In order to reduce fluctuation that Network Transmission postpones influence to subsequent calculations, can use the method for mean filter, that is, the OneWayDelay that repeatedly calculates is recently averaged the value that this mean value postpones as the Network Transmission of SYNC when main frame propagates into slave.Experiment shows, the mean value that nearest 16 OneWayDelay are tried to achieve is more satisfactory as the value that the Network Transmission of SYNC when main frame propagates into slave postpones.
Controller 314 utilize again the TxSyncTime-RxSyncTime timestamp that obtains to and the frequency compensation clock 315 of the frequency compensation clock 315 of the value computation host that postpones of the Network Transmission of SYNC when main frame propagates into slave and slave between the deviation of count value.
Can calculate the deviation Offset of count value between the frequency compensation clock 315 of the frequency compensation clock 315 of main frame and slave by following formula:
Offset＝TxSyncTime-RxSyncTime+OneWayDelay，
Wherein, when host clock was faster than slave clock, Offset was greater than zero, and when host clock was slower than slave clock, Offset was less than zero.
Controller 314 is according to the deviation calculation frequency compensation value of count value between the frequency compensation clock 315 of the frequency compensation clock 315 of main frame and slave.
Frequency compensation clock 315 is accepted new frequency compensation value, so that the deviation of count value gradually becomes zero within a certain period of time between the frequency compensation clock 315 of the frequency compensation clock 315 of main frame and slave.
The structure of frequency compensation clock 315 as shown in Figure 4, comprise a p bit clock counter (p-bitClock Counter), a q bit accumulator (q-bit Accumulator) and a r position addened register (r-bit Addend Register) composition, Tx/Rx Signals represents transmission/received signal, MessageDetection represents that information detects, Time Stamping Logic represents the logic that acquisition time stabs, Frequency Compensaion Value represents the frequency compensation value, and Frequency CompensationClock represents the frequency compensation clock.The numerical value of preserving in the addened register of r position promptly is the current frequency compensation value of using.Every a clock cycle, the frequency compensation value is added in the q bit accumulator once, if the q bit accumulator overflows, then the value of p bit clock counter increases a fixed value, this value is exactly the resolution of clock, if the q bit accumulator does not overflow, then p bit clock counter keeps initial value.Therefore, the counting rate of p bit clock counter is by the common decision of crystal oscillator frequency and frequency compensation value, and it is little deviation between recoverable main frame and the slave crystal oscillator frequency that the frequency compensation value is finely tuned.
Suppose that the deviation that last synchronometer is calculated is Offset 0, the deviation that a current synchronometer is calculated is Offset 1, can predict that then the deviation calculated of synchronometer will be Offset next time 2=2*Offset 1-Offset 0Therefore, should the regulating frequency offset, make the slave clock current this synchronizing cycle the internal clock counter value recruitment than on a synchronizing cycle many Offset 2So,, the deviation calculated of synchronometer will be zero next time.
Under the condition that has obtained Offset, the frequency compensation value that calculating makes new advances, realization is regulated the trace of frequency compensation clock count speed, make that the counting rate of frequency compensation clock 315 of main frame is consistent with the counting rate of the frequency compensation clock 315 of slave, eliminate the deviation of count value, reach the purpose of clock synchronization.
Need to prove, SYNC, FOLLOW_UP, DELAY_REQ and DELAY_RESP are UDP (User Datagram Ptorocol, user datagram protocol) frame, the sequence number and the timestamp that in the field payload of UDP frame, are comprising the PTP frame, wherein, the numerical value of the timestamp among FOLLOW_UP and the DELAY_RESP is significant, and the numerical value of the timestamp among SYNC and the DELAY_REQ can be filled in arbitrarily.
When no matter being afterwards frame beginning flag position (Start Frame Delimiter) of the transmission grabber 311 of main frame or the lead code (preamble) that the transmission grabber 311 of slave identifies the Frame that is sending, can writing down the local transmitting time of this frame and stab.If it is SYNC that the transmission grabber 311 of main frame identifies this frame, then preserves this timestamp and supply the CPU of main frame to read; If it is DELAY_REQ that the transmission grabber 311 of slave identifies this frame, then preserve the frequency compensation value that this timestamp is used for calculated rate compensating clock 315.
When no matter being afterwards frame beginning flag position (Start Frame Delimiter) of the reception grabber 312 of main frame or the lead code (preamble) that the reception grabber 312 of slave identifies the Frame that is receiving, can write down the local reception timestamp of this frame.If it is DELAY_REQ that the reception grabber 312 of main frame identifies this frame, then preserves this timestamp and supply the CPU of main frame to read; If it is SYNC that the reception grabber 312 of slave identifies this frame, then preserve the frequency compensation value that this timestamp is used for calculated rate compensating clock 315.
The present invention also provides a kind of system that realizes clock synchronization.The structure of system comprises as shown in Figure 5: CPU52 is used for handle packet; Media access controller (MAC Controller) 53 is used for data cached bag; Physical layer equipment transceiver (PHY Transceiver) 54 is used for packet is carried out conversion of signals; FPGA (Field Programmable Gate Array, field programmable gate array) 51, be used to monitor all signals between media access controller 53 and the physical layer equipment transceiver 54, FPGA51 can further comprise each entity in the clock synchronization apparatus shown in Figure 3.Wherein, media access controller 53 sends to physical layer equipment transceiver 54 according to the order of CPU52 with cached data packet, and/or, cached data packet is sent to CPU52.
FPGA51 is by bus and CPU52 interaction data and control information.CPU52 is connected respectively to media access controller 53 and FPGA51 by bus.CPU52, media access controller 53, physical layer equipment transceiver 54 be common to constitute a complete data communication passage, and the interactive information that realizes the system of clock synchronization and miscellaneous equipment is channel transfer thus all, comprises the PTP frame.Media access controller 53 is realized the function of media access control sublayer in the Ethernet protocol, by MII (Media Independent Interface, medium independent interface) links to each other with physical layer equipment transceiver 54, also link to each other the data and the control information that send alternately, receive with CPU52 with CPU52 by bus.Conversion on analog signal on the physical layer equipment transceiver 54 realization communication lines and the circuit board between the digital signal, be connected to switching equipment by network transformer, RJ-45 (a kind of twisted-pair Ethernet interface) on the one hand, as HUB (hub), special-purpose SWITCH (switch) etc., be connected to media access controller 53 by MII interface (defining among the IEEE802.3-1998) on the other hand.
No matter need to prove, be main frame or slave, all can have clock system shown in Figure 5.
Operation logic to clock system shown in Figure 5 describes now.
Host CPU 52 initiatively sends SYNC at regular intervals, and main frame FPGA51 detects sending of SYNC between media access controller 53 and physical layer equipment transceiver 54, writes down sequence number TxSyncSeq and the local transmitting time of this SYNC and stabs TxSyncTime.When SYNC arrived slave, slave FPGA51 detected the arrival of SYNC between media access controller 53 and physical layer equipment transceiver 54, write down sequence number RxSyncSeq and the local reception timestamp RxSyncTime of this SYNC.
After main frame sent SYNC, host CPU 52 took out TxSyncSeq and TxSyncTime immediately from FPGA51, was packaged into a new packet FOLLOW_UP and sent, and wherein TxSyncSeq is as sequence number, and TxSyncTime is as general data.When FOLLOW_UP arrived slave, slave FPGA51 detected the arrival of FOLLOW_UP between media access controller 53 and physical layer equipment transceiver 54, write down the data TxSyncTime that comprises in the sequence number RxFollowSeq of this FOLLOW_UP and the frame.If RxSyncSeq is identical with RxFollowSeq, it is right then to have obtained a TxSyncTime-RxSyncTime timestamp.
When slave receives SYNC or FOLLOW_UP, just obtained the physical address of main frame.Receive after the FOLLOW_UP, slave CPU52 initiatively sends DELAY_REQ to main frame, slave FPGA51 detects sending of DELAY_REQ between media access controller 53 and physical layer equipment transceiver 54, write down sequence number TxReqSeq and the local transmitting time of this DELAY_REQ and stab TxReqTime.When DELAY_REQ arrives main frame, main frame FPGA51 detects the arrival of DELAY_REQ between media access controller 53 and physical layer equipment transceiver 54, write down source physical address SlavePhyAddr, sequence number RxReqSeq and the local reception timestamp RxReqTime of this DELAY_REQ.Need to prove that slave CPU52 is after receiving FOLLOW_UP, it is proper initiatively sending DELAY_REQ to main frame immediately, and certainly, slave can initiatively send DELAY_REQ to main frame in the random time behind the physical address that obtains main frame.
Owing to may exist a plurality of slaves to send DELAY_REQ and main frame can not be handled the situation of all DELAY_REQ rapidly to main frame simultaneously, so main frame can use formation to preserve SlavePhyAddr, RxReqSeq and RxReq_Time, handle all DELAY_REQ in regular turn according to FIFO (First-In First-Out, first in first out) principle.The FPGA51 of main frame is when detecting a new Frame and arrive, the write pointer of backup current queue, continuous reception along with data, deposit the data corresponding to the SlavePhyAddr among the DELAY_REQ, RxReqSeq and RxReqTime position in the receiving data stream in formation, and the data of RxReqTime position are replaced with the local reception timestamp of this frame of host record.When this frame received, whether the FPGA51 of main frame just identifies it was DELAY_REQ, if not, then the write pointer with formation reverts to that value that just begins to receive this frame backup, if then do not do any operation.In order to prevent under unexpected situation, the CPU52 of main frame is different from the analysis result of FPGA51 to same received frame to the analysis result of received frame, cause the information such as RxReqTime of a synchronizing cycle to be stayed not being read in the formation and cause harmful effect, when the FPGA51 of main frame detected SYNC at every turn and sends, main frame all was set at the read pointer of formation the value of current write pointer.
Main frame is received after the DELAY_REQ that slave sends, be replied a DELAY_RESP immediately.Host CPU 52 takes out SlavePhyAddr, RxReqSeq, RxReqTime from FPGA51, encapsulate a new DELAY_RESP and send, wherein, SlavePhyAddr is as target physical address, RxReqSeq is as sequence number, and RxReqTime is as general data.When DELAY_RESP arrived slave, slave FPGA51 detected the arrival of DELAY_RESP between media access controller 53 and physical layer equipment transceiver 54, write down the data RxReqTime that comprises in the sequence number RxRespSeq of this DELAY_RESP and the frame.If TxReqSeq is identical with RxRespSeq, it is right then to have obtained a TxReqTime-RxReqTime timestamp.
Need to prove that FPGA51 is passive equipment, all PTP frames all are that CPU52 order media access controller 53 sends, and the work of FPGA51 is to monitor and resolve, CPU52 can't directly notify FPGA51 it sending or receiving the PTP frame.
For main frame, when sending FOLLOW_UP and DELAY_RESP, FPGA51 does not do any operation, and in fact, FPGA51 is used as these two kinds of frames as common Frame and handles, and can not identify this two kinds of frames.When receiving DELAY_REQ, CPU52 take out SlavePhyAddr, RxReqSeq and RxReqTime from FPGA51, and encapsulation DELAY_RESP sends after receiving and parse DELAY_REQ from media access controller 53.
For slave, when receiving SYNC, CPU52 directly abandons it after receiving and parse SYNC from media access controller 53, does not do any additional operation.After receiving FOLLOW_UP, slave CPU52 initiatively sends DELAY_REQ immediately, and FOLLOW_UP is abandoned.When receiving DELAY_RESP, CPU52 directly abandons it.
Slave obtain the TxSyncTime-RxSyncTime timestamp to and the TxReqTime-RxReqTime timestamp to after, these two timestamps of the FPGA51 of slave postpone calculating the Network Transmission of SYNC when main frame propagates into slave.
Can calculate the value that Network Transmission postpones OneWayDelay by following formula:
OneWayDelay＝(RxReqTime-TxReqTime)/2-(TxSyncTime-RxSyncTime)/2，
Wherein, RxReqTime-TxReqTime is the last timestamp that obtains behind the acquisition TxSyncTime-RxSyncTime.
In order to reduce fluctuation that Network Transmission postpones influence to subsequent calculations, can use the method for mean filter, that is, the OneWayDelay that repeatedly calculates is recently averaged the value that this mean value postpones as the Network Transmission of SYNC when main frame propagates into slave.Experiment shows, the mean value that nearest 16 OneWayDelay are tried to achieve is more satisfactory as the value that the Network Transmission of SYNC when main frame propagates into slave postpones.
The TxSyncTime-RxSyncTime timestamp that the FPGA51 of slave utilizes acquisition again to and the clock counter of the clock counter of the value computation host that postpones of the Network Transmission of SYNC when main frame propagates into slave and slave between the deviation of count value.
Can calculate the deviation Offset of count value between the clock counter of the clock counter of main frame and slave by following formula:
Offset＝TxSyncTime-RxSyncTime+OneWayDelay，
Wherein, when host clock was faster than slave clock, Offset was greater than zero, and when host clock was slower than slave clock, Offset was less than zero.
The FPGA51 of slave is according to the deviation calculation frequency compensation value of count value between the clock counter of the clock counter of main frame and slave.
Clock counter is accepted new frequency compensation value, so that the deviation of count value gradually becomes zero within a certain period of time between the clock counter of the clock counter of main frame and slave.
Suppose that the deviation that last synchronometer is calculated is Offset 0, the deviation that a current synchronometer is calculated is Offset 1, can predict that then the deviation calculated of synchronometer will be Offset next time 2=2*Offset 1-Offset 0Therefore, should the regulating frequency offset, make the slave clock current this synchronizing cycle the internal clock counter value recruitment than on a synchronizing cycle many Offset 2So,, the deviation calculated of synchronometer will be zero next time.
Under the condition that has obtained Offset, the frequency compensation value that calculating makes new advances, realization is regulated the trace of frequency compensation clock count speed, make that the counting rate of clock counter of main frame is consistent with the counting rate of the clock counter of slave, eliminate the deviation of count value, reach the purpose of clock synchronization.
Need to prove, SYNC, FOLLOW_UP, DELAY_REQ and DELAY_RESP are UDP (User Datagram Ptorocol, user datagram protocol) frame, the sequence number and the timestamp that in the field payload of UDP frame, are comprising the PTP frame, wherein, the numerical value of the timestamp among FOLLOW_UP and the DELAY_RESP is significant, and the numerical value of the timestamp among SYNC and the DELAY_REQ can be filled in arbitrarily.
When no matter being afterwards frame beginning flag position (Start Frame Delimiter) of the FPGA51 of main frame or the lead code (preamble) that the FPGA51 of slave identifies the Frame that is sending, can writing down the local transmitting time of this frame and stab.If it is SYNC that the FPGA51 of main frame identifies this frame, then preserves this timestamp and supply the CPU of main frame to read; If it is DELAY_REQ that the FPGA51 of slave identifies this frame, then preserve the frequency compensation value that this timestamp is used for the calculated rate compensating clock.
When no matter being afterwards frame beginning flag position (Start Frame Delimiter) of the FPGA51 of main frame or the lead code (preamble) that the FPGA51 of slave identifies the Frame that is receiving, can write down the local reception timestamp of this frame.If it is DELAY_REQ that the FPGA51 of main frame identifies this frame, then preserves this timestamp and supply the CPU of main frame to read; If it is SYNC that the FPGA51 of slave identifies this frame, then preserve the frequency compensation value that this timestamp is used for the calculated rate compensating clock.
The present invention also provides a kind of distributed system, and described distributed system comprises at least one main frame and slave, and described main frame and slave comprise respectively: CPU is used for handle packet; Media access controller is used for data cached bag; The physical layer equipment transceiver is used for packet is carried out conversion of signals; Described slave also comprises: clock synchronizer, being used for obtaining between described media access controller and described physical layer equipment transceiver the local reception timestamp of first packet that main frame sends and the local transmitting time that main frame sends first packet stabs, local reception timestamp and local transmitting time according to described first packet are stabbed the deviation of calculating count value between the clock counter, and described deviation is proofreaied and correct.
Described main frame also comprises: clock synchronizer is used to monitor all signals between media access controller and the physical layer equipment transceiver.
Main frame in the distributed system and slave all can comprise clock system shown in Figure 5, clock system also can further comprise clock synchronization apparatus shown in Figure 3, the operation logic of distributed system can repeat no more here with reference to the explanation of the above-mentioned operation principle that relates to about Fig. 5 and Fig. 3.
Need to prove, in the above-described embodiment, the calculating of frequency compensation value all is to realize in FPGA, if but the cpu interface logic among the FPGA is made an amendment slightly, just the calculating of frequency compensation value can be transferred among the CPU and be realized, in this case, CPU writes FPGA with the frequency compensation value that calculates and uses for clock counter and get final product.
Now how the present invention is prevented from losing of packet and repeats the influence of clock synchronization is described again.
Because the SYNC-FOLLOW_UP packet is to reaching the DELAY_REQ-DELAY_RESP packet to having identical sequence number respectively, and CPU send at every turn new SYNC-FOLLOW_UP to DELAY_REQ-DELAY_RESP to the time all can use different sequence numbers, so, if lost SYNC, then the sequence number of FOLLOW_UP subsequently becomes invalid FOLLOW_UP because of different with the sequence number of previous effective SYNC, if lost FOLLOW_UP, next effectively SYNC can reset and be about to the sequence number of the FOLLOW_UP that receives, and the situation that DELAY_REQ-DELAY_RESP is right is also identical.
What the clock counter of slave adopted is the frequency compensation clock, when system normally moves, the counting rate of the counting rate of slave clock counter and host clock counter almost is identical, so it is right to lose several SYNC-FOLLOW_UP once in a while, once in a while not synchronously several times promptly, the influence to synchronization accuracy is not very little.It is almost nil to the influence of synchronization accuracy to lose the right situation of DELAY_REQ-DELAY_RESP, because when system normally moves, it is more stable that Network Transmission postpones, and has only the random error of some normal distributions, once do not upgrade Network Transmission once in a while and postpone, old numerical value remains accurately.
If same PTP frame has occurred continuously twice or repeatedly, just might cause serious consequence on the network, so will take measures to deal with the generation of this situation.In the right transmission receiving course of SYNC-FOLLOW_UP, when slave receives SYNC, start a timer, if identical SYNC is received again before timer expiry, then the SYNC of this repetition will be regarded as invalid.When starting timer, also with a flag bit set, when receiving corresponding FOLLOW_UP by the time, again flag bit is resetted, if identical FOLLOW_UP is received again, because flag bit is zero, represents that identical FOLLOW_UP has been received, then this FOLLOW_UP afterwards will be regarded as invalid.In the right transmission receiving course of DELAY_REQ-DELAY_RESP, when slave sends DELAY_REQ, with a flag bit set, when receiving corresponding D ELAY_RESP by the time, again flag bit is resetted, if identical DELAY_RESP is received again, because flag bit is zero, represent that identical DELAY_RESP has been received, then the DELAY_RESP of this repetition will be regarded as invalid.When main frame is received the DELAY_REQ that repeats to arrive, this DELAY_REQ is used as normal DELAY_REQ handles, promptly reply a DELAY_RESP, this DELAY_RESP is equivalent to the DELAY_RESP of a repetition, the processing that slave can be correct.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (13)

1. method that realizes clock synchronization is characterized in that comprising:
Between media access controller and physical layer equipment transceiver, obtain main frame and send the local transmitting time stamp of the first packet SYNC and the local reception timestamp that slave receives SYNC, and obtain slave and send the local transmitting time stamp of the 3rd packet DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, the main frame that utilization is obtained sends the local transmitting time of SYNC and stabs, slave receives the local reception timestamp of SYNC, the local transmitting time that slave sends DELAY_REQ is stabbed and main frame receives the local reception timestamp of DELAY_REQ, calculates the Network Transmission delay of SYNC when main frame propagates into slave;
Send the local reception timestamp that local transmitting time is stabbed, slave receives SYNC of SYNC and the SYNC Network Transmission when main frame propagates into slave according to main frame and postpone, calculate the deviation of count value between the clock counter;
Described deviation is proofreaied and correct.
2. the method for realization clock synchronization as claimed in claim 1 is characterized in that obtaining that local transmitting time that main frame sends SYNC is stabbed and the process of the local reception timestamp of slave reception SYNC is realized by following step:
After receiving SYNC, write down the sequence number of described SYNC and the local reception timestamp that slave receives SYNC;
After receiving the second packet FOLLOW_UP that carries timestamp, write down sequence number and the described timestamp of described FOLLOW_UP, if the sequence number of described FOLLOW_UP is identical with the sequence number of described SYNC, then described timestamp is the local transmitting time stamp that described main frame sends SYNC.
3. the method for realization clock synchronization as claimed in claim 1 is characterized in that the deviation according to count value between the following formula calculating clock counter:
Offset＝TxSyncTime-RxSyncTime+OneWayDelay，
Wherein, Offset is the deviation of count value between the clock counter, TxSyncTime is the local transmitting time stamp that described main frame sends SYNC, RxSyncTime is the local reception timestamp that described slave receives SYNC, the Network Transmission that OneWayDelay is described SYNC when main frame propagates into slave postpones, wherein, the acquisition mode of TxSyncTime and RxSyncTime comprises:
Main frame sends SYNC at regular intervals, and the sequence number TxSyncSeq of record SYNC and local transmitting time stamp TxSyncTime; Slave writes down sequence number RxSyncSeq and the local reception timestamp RxSyncTime of described SYNC; Main frame stabs TxSyncTime with the sequence number TxSyncSeq of SYNC of record and local transmitting time and is packaged into FOLLOW_UP and sends; The sequence number RxFollowSeq of slave record FOLLOW_UP and the data TxSyncTime that carries, it is right to obtain the TxSyncTime-RxSyncTime timestamp.
4. the method for realization clock synchronization as claimed in claim 3 is characterized in that obtaining that local transmitting time that slave sends DELAY_REQ is stabbed and the process of the local reception timestamp of main frame reception DELAY_REQ is realized by following step:
Send DELAY_REQ;
Write down the sequence number of described DELAY_REQ and the local transmitting time stamp that slave sends DELAY_REQ;
The 4th packet DELAY_RESP of timestamp is carried in reception;
Write down sequence number and the described timestamp of described DELAY_RESP, if the sequence number of described DELAY_RESP is identical with the sequence number of described DELAY_REQ, then described timestamp is the local reception timestamp that described main frame receives DELAY_REQ.
5. the method for realization clock synchronization as claimed in claim 4 is characterized in that calculating the Network Transmission of described SYNC when main frame propagates into slave by following formula postpones OneWayDelay:
OneWayDelay＝(RxReqTime-TxReqTime)/2-(TxSyncTime-RxSyncTime)/2，
Wherein, RxReqTime is the local reception timestamp that described main frame receives DELAY_REQ, and TxReqTime is the local transmitting time stamp that described slave sends DELAY_REQ.
6. the method for realization clock synchronization as claimed in claim 5, it is characterized in that: the Network Transmission of the described SYNC that continuous several times is calculated when main frame propagates into slave postpones OneWayDelay averages, with described mean value as calculating the employed OneWayDelay of Offset.
7. the method for realization clock synchronization as claimed in claim 1 is characterized in that the process that described deviation is proofreaied and correct is realized by following step:
According to described deviation calculation frequency compensation value;
Regulate described frequency compensation value, so that the deviation of count value is zero between the clock counter.
8. a device of realizing clock synchronization is characterized in that, this device is integrated in respectively in main frame and the slave, and described device comprises:
Receive grabber, be used between media access controller and physical layer equipment transceiver, obtaining that local transmitting time that local reception timestamp, main frame that slave receives SYNC send SYNC is stabbed and the local reception timestamp of main frame reception DELAY_REQ;
Send grabber, be used between media access controller and physical layer equipment transceiver, obtaining the local transmitting time stamp that slave sends DELAY_REQ;
Controller, be connected with the reception grabber with described transmission grabber respectively, the local transmitting time that is used to utilize the main frame that obtains to send SYNC is stabbed, slave receives the local reception timestamp of SYNC, slave sends the local transmitting time stamp of DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, calculating the Network Transmission of SYNC when main frame propagates into slave postpones, and receive the local reception timestamp of SYNC according to described slave, the local transmitting time that main frame sends SYNC is stabbed and the Network Transmission of SYNC when main frame propagates into slave postpones, the deviation of count value and according to described deviation calculation frequency compensation value between the calculating clock counter;
The frequency compensation clock is connected with controller, is used for according to crystal oscillator frequency and described frequency compensation value, adjusts counting rate.
9. the device of realization clock synchronization as claimed in claim 8 is characterized in that: described clock counter is the frequency compensation clock.
10. a system that realizes clock synchronization is integrated in respectively in main frame and the slave, and described system comprises:
CPU is used for handle packet;
Media access controller is used for data cached bag;
The physical layer equipment transceiver is used for packet is carried out conversion of signals;
Wherein, described media access controller sends to described physical layer equipment transceiver according to the order of described CPU with described cached data packet, and/or, described cached data packet is sent to described CPU;
It is characterized in that also comprising:
Clock synchronizer, be used between described media access controller and described physical layer equipment transceiver, obtaining main frame and send the local transmitting time stamp of SYNC and the local reception timestamp that slave receives SYNC, and obtain slave and send the local transmitting time stamp of DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, the main frame that utilization is obtained sends the local transmitting time of SYNC and stabs, slave receives the local reception timestamp of SYNC, slave sends the local transmitting time stamp of DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, calculating the Network Transmission of SYNC when main frame propagates into slave postpones, send the local transmitting time of SYNC stabs according to main frame, slave receives the local reception timestamp of SYNC and the SYNC Network Transmission when main frame propagates into slave to postpone, calculate the deviation of count value between the clock counter, and described deviation is proofreaied and correct.
11. the system of realization clock synchronization as claimed in claim 10 is characterized in that: described clock synchronizer is an on-site programmable gate array FPGA.
12. a distributed system comprises at least one main frame and at least one slave, described main frame and slave comprise respectively:
CPU is used for handle packet;
Media access controller is used for data cached bag;
The physical layer equipment transceiver is used for packet is carried out conversion of signals;
It is characterized in that described slave also comprises:
Clock synchronizer, be used between described media access controller and described physical layer equipment transceiver, obtaining main frame and send the local transmitting time stamp of SYNC and the local reception timestamp that slave receives SYNC, and obtain slave and send the local transmitting time stamp of DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, the main frame that utilization is obtained sends the local transmitting time of SYNC and stabs, slave receives the local reception timestamp of SYNC, slave sends the local transmitting time stamp of DELAY_REQ and the local reception timestamp that main frame receives DELAY_REQ, calculating the Network Transmission of SYNC when main frame propagates into slave postpones, send the local transmitting time of SYNC stabs according to main frame, slave receives the local reception timestamp of SYNC and the SYNC Network Transmission when main frame propagates into slave to postpone, calculate the deviation of count value between the clock counter, and described deviation is proofreaied and correct.
13. distributed system as claimed in claim 12 is characterized in that: described main frame also comprises: clock synchronizer is used to monitor all signals between media access controller and the physical layer equipment transceiver.
CN2006101409425A 2006-10-17 2006-10-17 Method, device, system for implementing clock synchronization, and distribution system Expired - Fee Related CN1960242B (en)

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