CN1941614A - Differential amplifier - Google Patents
Differential amplifier Download PDFInfo
- Publication number
- CN1941614A CN1941614A CNA2006101317226A CN200610131722A CN1941614A CN 1941614 A CN1941614 A CN 1941614A CN A2006101317226 A CNA2006101317226 A CN A2006101317226A CN 200610131722 A CN200610131722 A CN 200610131722A CN 1941614 A CN1941614 A CN 1941614A
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- nmos pass
- pass transistor
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- signal
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.
Description
Technical field
The present invention is about differential amplifier; And more specifically, the present invention is about being used for carrying out reliably the differential amplifier of amplifieroperation.
Background technology
Differential amplifier with the voltage difference multiplication by constants factor between two inputs to obtain differential gain.Many integrated circuits of DRAM (Dynamic Random Access Memory) (DRAM) that comprise use differential amplifier to be used for the signal amplification.
Fig. 1 is the exemplary block diagram of differential amplifier.
As shown in Figure 1, differential amplifier 1 amplifies the voltage difference between the first input IN and the second input INB and exports the first output OUT and the second output OUTB.
Fig. 2 is the schematic circuit diagram of the differential amplifier shown in Fig. 1.
As shown in FIG. 2, differential amplifier 1 comprises first amplifying unit, 10, the second amplifying units 20 and initialization unit 30.First amplifying unit 10 is exported the second output OUTB by amplify the voltage difference between the first input IN and the second input INB in response to enable signal EN.Second amplifying unit 20 is exported the first output OUT by amplify the voltage difference between the first input IN and the second input INB in response to enable signal EN.Initialization unit 30 is stablized the level of first and second output OUT and OUTB and is exported first and second output OUT and OUTB in response to cancelling of enable signal EN.
First amplifying unit 10 comprises four NMOS transistors NM1 to NM4 and two PMOS transistor PM1 and PM2.First and second nmos pass transistor NM1 that is connected in parallel with each other and NM2 receive enable signal EN via its grid, and are connected to earthed voltage VSS terminal.The the 3rd and the 4th nmos pass transistor NM3 and NM4 are connected in parallel with each other, and receive the first input IN and the second input INB via its grid respectively.The common node of the 3rd nmos pass transistor NM3 and the 4th nmos pass transistor NM4 is coupled to the common node of the first nmos pass transistor NM1 and the second nmos pass transistor NM2.The one PMOS transistor PM1 is connected between the 3rd nmos pass transistor NM3 and supply voltage vdd terminal, and the 4th PMOS transistor PM2 is connected between the 4th nmos pass transistor and supply voltage vdd terminal.Receive the voltage at the node A place that is connected to the 4th nmos pass transistor NM4 at the grid place of transistor PM1 and PM2.The output of first amplifying unit 10 at the voltage at the common node place of a PMOS transistor PM1 and the 3rd nmos pass transistor NM3 to export OUTB as second.
Second amplifying unit 20 has and the similar circuit of the circuit of first amplifying unit 10.Yet with as the first output OUT, this nmos pass transistor receives the second input INB via its grid to the output of second amplifying unit 20 at the voltage at the common node place of PMOS transistor AND gate nmos pass transistor.
As indicated above, differential amplifier comprises first and second amplifying unit 10 and 20 of realizing with current mirror, to amplify the voltage difference between the first input IN and the second input INB.If the voltage difference between the first input signal IN and the second input signal INB is too little, then the possibility differential amplifier can not amplify the voltage difference between the first input signal IN and the second input signal INB fully, and therefore, first and second output signal OUT and OUTB can not correctly be discerned.
Fig. 3 is for showing the waveform of differential amplifier operation shown in Figure 1.
As shown in Figure 3, differential amplifier amplifies the voltage difference (being approximately 10mV) between the first input signal IN and the second input signal INB, and exports first and second output signal OUT and OUTB, and its voltage difference is approximately 330mV.In the case, the logic level of first and second output signal OUT and OUTB can not correctly be discerned.
Summary of the invention
Therefore, target of the present invention is to provide a kind of differential amplifier that is used for carrying out reliably amplifieroperation.
According to aspects of the present invention, provide a kind of differential amplifier, it comprises amplifying unit and feedback unit.Amplifying unit amplifies the voltage difference between first input signal and second input signal, and exports first output signal and second output signal.Feedback unit amplifies based on first feedback signal of first output signal and based on the voltage difference between second feedback signal of second output signal.
The aspect in addition according to the present invention provides a kind of differential amplifier, and it comprises the first feedback amplifying unit and the second feedback amplifying unit, and initialization unit.The first feedback amplifying unit receives first and second input signal and first and second feedback signal in response to enable signal, and exports second output signal.The second feedback amplifying unit receives first and second input signal and first and second feedback signal in response to enable signal, and exports first output signal.Initialization unit is first and second output node of initialization in response to enable signal.First feedback signal based on first output signal loads at the second output node place, and loads at the first output node place based on second feedback signal of second output signal.
Description of drawings
Fig. 1 is the calcspar of conventional differential amplifier;
Fig. 2 is the schematic circuit diagram of differential amplifier shown in Figure 1;
Fig. 3 is for showing the waveform of differential amplifier operation shown in Figure 1;
Fig. 4 is the calcspar of differential amplifier according to an embodiment of the invention;
Fig. 5 is the schematic diagram of differential amplifier shown in Figure 3; And
Fig. 6 is for showing the waveform of differential amplifier operation shown in Figure 4.
Embodiment
Hereinafter, will describe in detail according to differential amplifier of the present invention referring to accompanying drawing.
Fig. 4 shows the calcspar of differential amplifier according to an embodiment of the invention.
As shown in Figure 4, differential amplifier amplifies the voltage difference between the first input IN and the second input INB and exports the first output OUT and the second output OUTB.In addition, differential amplifier receives first and second output OUT and OUTB exports the OUT and second voltage difference of exporting between the OUTB as first and second feedback signal OUT_FD and OUTB_FD to amplify first again.
Fig. 5 is a schematic diagram of describing differential amplifier shown in Figure 4.
As shown in Figure 5, differential amplifier comprises first amplifying unit 100, second amplifying unit 200 and initialization unit 300.First amplifying unit 100 is exported the second output OUTB by amplify the voltage difference between the first input IN and the second input INB in response to enable signal EN.First amplifying unit 100 further receives first and second feedback signal OUT_FD and OUTB_FD, and the level of the modulation second output OUTB.Second amplifying unit 200 is exported the first output OUT by amplify the voltage difference between the first input IN and the second input INB in response to enable signal EN.Second amplifying unit 200 receives first and second feedback signal OUT_FD and OUTB_FD, and the level of the modulation first output OUT.Initialization unit 300 is stablized the level of first and second output OUT and OUTB in response to cancelling of enable signal EN, and exports first and second output OUT and OUTB.
First amplifying unit 100 comprises input unit 140, feedback unit 160, loading unit 180 and bias voltage feeding unit 120.Bias voltage feeding unit 120 provides bias current in response to enable signal EN to input unit 140, loading unit 180 and feedback unit 160.Input unit 140 is controlled the voltage level of the first output node A according to the voltage difference between the first input signal IN and the second input signal INB.The voltage that loads at the first output node A place is exported as the second output signal OUTB.Loading unit 180 provides the electric current of being determined by input unit 140 and feedback unit 160 to input unit 140 and feedback unit 160.Feedback unit 160 is controlled the voltage level of the first output node A according to the voltage difference between the first feedback signal OUT_FD and the second feedback signal OUTB_FD.
In detail, bias voltage feeding unit 120 comprises two nmos pass transistor NM5 and NM6, and it is connected between input unit 140 and the earthed voltage VSS terminal, and receives enable signal EN via its grid.Input unit 140 comprises two the nmos pass transistor NM7 and the NM8 that are connected in parallel with each other.The 7th nmos pass transistor NM7 is connected between the first output node A and the bias voltage supplier 120, and receives the first input signal IN via its grid.The 8th nmos pass transistor NM8 is connected between loading unit 180 and the bias voltage supplier 120, and receives the second input signal INB via its grid.Feedback unit 160 comprises two nmos pass transistor NM9 and NM10.The 9th nmos pass transistor NM9 receives the first feedback signal OUT_FD via its grid.First and second terminal of transistor NM9 is connected to first and second terminal of the 7th nmos pass transistor NM7.The tenth nmos pass transistor NM10 receives the second feedback signal OUTB_FD via its grid.First and second terminal of transistor NM10 is connected to first and second terminal of the 8th nmos pass transistor NM8.Loading unit 180 comprises two PMOS transistor PM3 and PM4.The 4th PMOS transistor PM4 that is connected to the 8th nmos pass transistor NM8 receives the voltage at the B place, common node place of the 4th PMOS transistor PM4 and the 8th nmos pass transistor NM8 via its grid.The 3rd PMOS transistor PM3 is connected to the 7th nmos pass transistor NM7 at the first output node A place, and is received in the voltage at common node B place via its grid.
Second amplifying unit 200 comprises input unit 240, feedback unit 260, loading unit 280 and bias voltage feeding unit 220.Bias voltage feeding unit 220 provides bias current in response to enable signal EN to input unit 240, loading unit 280 and feedback unit 260.Input unit 240 is controlled the voltage level of the second output node C according to the voltage difference between the first input signal IN and the second input signal INB.The voltage that loads at the second output node C place is exported as the first output signal OUT.Loading unit 280 provides the electric current of being determined by input unit 240 and feedback unit 260 to input unit 240 and feedback unit 260.Feedback unit 260 is controlled the voltage level of the second output node C according to the voltage difference of the first feedback signal OUT_FD and the second feedback signal OUTB_FD.
In detail, bias voltage feeding unit 120 comprises two nmos pass transistor NM11 and NM12, and it is connected between input unit 240 and the earthed voltage VSS terminal, and receives enable signal EN via its grid.Input unit 240 comprises two nmos pass transistor NM13 and NM14.The 13 nmos pass transistor NM13 that is connected between loading unit 280 and the bias voltage supplier 220 receives the first input signal IN via its grid.The 14 nmos pass transistor NM14 that is connected between the second output node C and the bias voltage supplier 220 receives the second input signal INB via its grid.Feedback unit 260 comprises two nmos pass transistor MN15 and MN16.The 15 nmos pass transistor MN15 receives the first feedback signal OUT_FD via its grid.First and second terminal of transistor MN15 is connected to first and second terminal of the 13 nmos pass transistor N13.The 16 nmos pass transistor NM16 receives the second feedback signal OUTB_FD via its grid.First and second terminal of transistor MN16 is connected to first and second terminal of the 14 nmos pass transistor NM14.Loading unit 280 comprises two PMOS transistor PM5 and PM6.The 5th PMOS transistor PM5 that is connected to the 13 nmos pass transistor NM13 receives the voltage at the common node D place of the 5th PMOS transistor PM5 and the 13 nmos pass transistor NM13 at its grid place.The 6th PMOS transistor PM6 that is connected to the 14 nmos pass transistor NM14 via the second output node C receives the voltage at common node D place at its grid place.
As indicated above, differential amplifier further comprises feedback unit 160 and 260, and it receives first and second feedback signal OUT_FD and OUTB_FD to amplify the voltage difference between first and second output OUT and the OUTB again.
Fig. 6 is for showing the waveform of differential amplifier operation shown in Figure 4.
As shown in the figure, the difference of input signal IN and INB is about 10mV.When enable signal EN is logic high through starting, the voltage difference of differential amplifier amplification input signal, and export first and second output signal OUT and OUTB, its voltage difference is approximately 1.3V.
Differential amplifier is fed the voltage difference of also amplifying output signal OUT and OUTB again with output signal OUT and OUTB.Therefore, the voltage difference of the output signal of differential amplifier increases.That is, differential amplifier is carried out amplifieroperation reliably.
The present invention contains and on September 29th, 2005 and korean patent application case 2005-91546 number and the 2005-123979 number relevant invention of on December 15th, 2005 in the application of Korean Patent office, and the full text of these application cases is incorporated herein by reference.
Though about specific embodiment the present invention has been described, for those skilled in the art will be apparent, under the condition of spirit of the present invention that does not depart from claim and defined and category, can make various changes and modification to the present invention.
Claims (25)
1. differential amplifier, it comprises:
Input unit, it is configured to control the voltage level of first output node and second output node according to the voltage difference between first input signal and second input signal;
The feedback input unit, it is configured to according to respectively to control the voltage level of this first output node and this second output node from first feedback signal of this first output node and this second output node feedback and the voltage difference between second feedback signal; And
Loading unit, it is configured to provide the electric current of being determined by this input unit and this feedback unit to this input unit and this feedback unit,
Wherein exported as first output signal and second output signal respectively at the voltage of this first output node and the loading of this second output node place.
2. differential amplifier as claimed in claim 1, it further comprises:
Initialization unit, it is configured to this first output node of initialization and this second output node in response to enable signal; And
Bias voltage supplier, it is configured to control the startup of this differential amplifier by providing bias current in response to this enable signal to this input unit, this loading unit and this feedback unit.
3. differential amplifier as claimed in claim 2, wherein this input unit comprises:
First input unit, it possesses first and second nmos pass transistor that is connected between this loading unit and this bias voltage supplier, to receive this first input signal and this second input signal via its grid respectively; And
Second input unit, it possesses the 3rd and the 4th nmos pass transistor that is connected between loading unit and this bias voltage supplier, receiving this first input signal and this second input signal via its grid respectively,
Wherein the first terminal of this first nmos pass transistor is connected to this second output node, and the first terminal of the 4th nmos pass transistor is connected to this first output node.
4. differential amplifier as claimed in claim 3, wherein this loading unit comprises:
First loading unit, it possesses first and second PMOS transistor that is connected between this first input unit and the power supply voltage terminal; And
Second loading unit, it possesses the 3rd and the 4th PMOS transistor that is connected between this second input unit and this power supply voltage terminal.
5. differential amplifier as claimed in claim 4, wherein a PMOS transistor is connected to this first nmos pass transistor via this second output node, and receives the voltage at the first common node place of the 2nd this second nmos pass transistor of PMOS transistor AND gate at its grid place.
6. differential amplifier as claimed in claim 5, wherein the 2nd PMOS transistor is connected to this second nmos pass transistor, and receives this voltage at this first common node place at its grid place.
7. differential amplifier as claimed in claim 6, wherein the 3rd PMOS transistor is connected to the 3rd nmos pass transistor, and receives the voltage at the second common node place of the 3rd PMOS transistor AND gate the 3rd nmos pass transistor at its grid place.
8. differential amplifier as claimed in claim 7, wherein the 4th PMOS transistor is connected to the 4th nmos pass transistor via this first output node, and receives this voltage at this second common node place at its grid place.
9. differential amplifier as claimed in claim 8, wherein this bias voltage supplier comprises a plurality of nmos pass transistors that are connected between this input unit and the earthed voltage terminal, each in these nmos pass transistors receives this enable signal at its grid place.
10. differential amplifier as claimed in claim 9, wherein this feedback unit comprises:
The 5th nmos pass transistor, it receives this first feedback signal at its grid place, and its first and second terminal is connected to first and second terminal of this first nmos pass transistor;
The 6th nmos pass transistor, it receives this second feedback signal at its grid place, and its first and second terminal is connected to first and second terminal of this second nmos pass transistor;
The 7th nmos pass transistor, it receives this first feedback signal at its grid place, and its first and second terminal is connected to first and second terminal of the 3rd nmos pass transistor; And
The 8th nmos pass transistor, it receives this second feedback signal at its grid place, and its first and second terminal is connected to first and second terminal of the 4th nmos pass transistor.
11. a differential amplifier, it comprises:
The first feedback amplifying unit, it is configured to receive in response to enable signal first input signal and second input signal and first feedback signal and second feedback signal, and exports second output signal;
The second feedback amplifying unit, it is configured to receive this first input signal and this second input signal and this first feedback signal and this second feedback signal in response to this enable signal, and exports first output signal; And
Initialization unit, it is configured in response to this enable signal and first and second output node of initialization,
Wherein, load at this first output node place, and load at this second output node place based on this second feedback signal of this second output signal based on this first feedback signal of this first output signal.
12. differential amplifier as claimed in claim 11, wherein this first feedback amplifying unit comprises:
Input unit, it is configured to control according to the voltage difference between this first input signal and this second input signal voltage level of this second output node;
Feedback unit, it is configured to amplify the voltage difference between this first feedback signal and this second feedback signal; And
Loading unit, it is configured to provide the electric current of being determined by this input unit and this feedback unit to this input unit and this feedback unit.
13. differential amplifier as claimed in claim 12, wherein this first feedback amplifying unit further comprises:
Bias voltage supplier, it is configured to provide bias current in response to this enable signal to this input unit, this loading unit and this feedback unit.
14. differential amplifier as claimed in claim 13, wherein this feedback unit is controlled this voltage level of this first output node according to this voltage difference between this first feedback signal and this second feedback signal.
15. differential amplifier as claimed in claim 14, wherein this input unit comprises:
First nmos pass transistor, it is connected between this second output node and this bias voltage supplier, is used for receiving at its grid place this first input signal; And
Second nmos pass transistor, it is connected between this loading unit and this bias voltage supplier, is used for receiving at its grid place this second input signal.
16. differential amplifier as claimed in claim 15, wherein this loading unit comprises:
The one PMOS transistor, it is connected to this second nmos pass transistor, receives the voltage of the common node place loading of this second nmos pass transistor of PMOS transistor AND gate at its grid place; And
The 2nd PMOS transistor, it is connected to this first nmos pass transistor via this second output node, is received in this voltage that this common node place loads at its grid place.
17. differential amplifier as claimed in claim 16, wherein this bias voltage supplier comprises:
The 3rd nmos pass transistor, it is connected between this first nmos pass transistor and the earthed voltage terminal, is used for receiving this enable signal at its grid place; And
The 4th nmos pass transistor, it is connected between this second nmos pass transistor and this earthed voltage terminal, is used for receiving this enable signal at its grid place.
18. differential amplifier as claimed in claim 17, wherein this feedback unit comprises:
The 5th nmos pass transistor, it receives this first feedback signal at its grid place, and its first and second terminal is connected to first and second terminal of this first nmos pass transistor; And
The 6th nmos pass transistor, it receives this second feedback signal at its grid place, and its first and second terminal is connected to first and second terminal of this second nmos pass transistor.
19. differential amplifier as claimed in claim 12, wherein this second feedback amplifying unit comprises:
Input unit, it is configured to control according to this voltage difference between this first input signal and this second input signal voltage level of this first output node;
Feedback unit, it is configured to amplify the voltage difference between this first feedback signal and this second feedback signal; And
Loading unit, it is configured to provide the electric current of being determined by this input unit and this feedback unit to this input unit and this feedback unit.
20. differential amplifier as claimed in claim 19, wherein this second feedback amplifying unit further comprises: bias voltage supplier, it is configured to provide bias current in response to this enable signal to this input unit, this loading unit and this feedback unit.
21. differential amplifier as claimed in claim 20, wherein this feedback unit is controlled this voltage level of this first output node according to this voltage difference between this first feedback signal and this second feedback signal.
22. differential amplifier as claimed in claim 21, wherein this input unit comprises:
First nmos pass transistor, it is connected between this loading unit and this bias voltage supplier, is used for receiving at its grid place this first input signal; And
Second nmos pass transistor, it is connected between this first output node and this bias voltage supplier, is used for receiving at its grid place this second input signal.
23. differential amplifier as claimed in claim 22, wherein this loading unit comprises:
The one PMOS transistor, it is connected to this first nmos pass transistor, receives the voltage at the common node place of this first nmos pass transistor of PMOS transistor AND gate at its grid place; And
The 2nd PMOS transistor, it is connected to this second nmos pass transistor via this first output node, receives this voltage at this common node place at its grid.
24. differential amplifier as claimed in claim 23, wherein this bias voltage supplier comprises:
The 3rd nmos pass transistor, it is connected between this first nmos pass transistor and the earthed voltage terminal, is used for receiving this enable signal at its grid place; And
The 4th nmos pass transistor, it is connected between this second nmos pass transistor and this earthed voltage terminal, is used for receiving this enable signal at its grid place.
25. differential amplifier as claimed in claim 24, wherein this feedback unit comprises:
The 5th nmos pass transistor, it receives this first feedback signal at its grid place, and its first and second terminal is connected to first and second terminal of this first nmos pass transistor; And
The 6th nmos pass transistor, it receives this second feedback signal at its grid place, and its first and second terminal is connected to first and second terminal of this second nmos pass transistor.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR91546/05 | 2005-09-29 | ||
| KR20050091546 | 2005-09-29 | ||
| KR123979/05 | 2005-12-15 | ||
| KR1020050123979A KR100744028B1 (en) | 2005-09-29 | 2005-12-15 | Differantial amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1941614A true CN1941614A (en) | 2007-04-04 |
| CN1941614B CN1941614B (en) | 2010-05-12 |
Family
ID=37959467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101317226A Expired - Fee Related CN1941614B (en) | 2005-09-29 | 2006-09-29 | Differential amplifier |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR100744028B1 (en) |
| CN (1) | CN1941614B (en) |
| TW (1) | TWI318496B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108694962A (en) * | 2017-04-10 | 2018-10-23 | 爱思开海力士有限公司 | Amplifier and use its semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8310308B1 (en) * | 2011-05-31 | 2012-11-13 | Texas Instruments Incorporated | Wide bandwidth class C amplifier with common-mode feedback |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275942A (en) * | 1992-03-25 | 1993-10-22 | Yokogawa Electric Corp | Differential amplifier circuit |
| JP2588368B2 (en) * | 1994-05-24 | 1997-03-05 | 日本電気アイシーマイコンシステム株式会社 | Differential amplifier circuit |
| JP2713182B2 (en) * | 1994-09-26 | 1998-02-16 | 日本電気株式会社 | Receiver device |
| JP2000031759A (en) * | 1998-07-10 | 2000-01-28 | Fujitsu Ltd | Differential amplifier circuit |
| JP3647828B2 (en) * | 2002-08-23 | 2005-05-18 | シリンクス株式会社 | Comparator circuit |
| KR100695510B1 (en) * | 2004-01-10 | 2007-03-15 | 주식회사 하이닉스반도체 | Differential amplifier |
| KR20190000930U (en) * | 2017-10-12 | 2019-04-22 | 두리기농업회사법인 주식회사 | roaster of tea |
-
2005
- 2005-12-15 KR KR1020050123979A patent/KR100744028B1/en not_active IP Right Cessation
-
2006
- 2006-06-30 TW TW095123957A patent/TWI318496B/en not_active IP Right Cessation
- 2006-09-29 CN CN2006101317226A patent/CN1941614B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108694962A (en) * | 2017-04-10 | 2018-10-23 | 爱思开海力士有限公司 | Amplifier and use its semiconductor device |
| CN108694962B (en) * | 2017-04-10 | 2022-03-15 | 爱思开海力士有限公司 | Amplifier and semiconductor device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI318496B (en) | 2009-12-11 |
| KR20070036555A (en) | 2007-04-03 |
| CN1941614B (en) | 2010-05-12 |
| TW200713804A (en) | 2007-04-01 |
| KR100744028B1 (en) | 2007-07-30 |
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