CN1921018A - Shifting register depressing coupling effect and liquid crystal display - Google Patents
Shifting register depressing coupling effect and liquid crystal display Download PDFInfo
- Publication number
- CN1921018A CN1921018A CN 200610154243 CN200610154243A CN1921018A CN 1921018 A CN1921018 A CN 1921018A CN 200610154243 CN200610154243 CN 200610154243 CN 200610154243 A CN200610154243 A CN 200610154243A CN 1921018 A CN1921018 A CN 1921018A
- Authority
- CN
- China
- Prior art keywords
- coupled
- output terminal
- control circuit
- shift register
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a shift register used in liquid crystal display, whose output has low couple effect to provide better grid driving signal, wherein the output circuit of shift register has two switches; the control end of first switch is coupled to the control end of second switch; one end of first switch receives one clock signal, whose another end is coupled to one end of second switch; another end of second switch outputs one grid driving signal; and it uses one control signal to switch the first and second switches.
Description
Technical field
The present invention relates to a kind of shift register that has than low coupling effect.Or rather, the present invention relates to a kind of shift register of having that is used for LCD than low coupling effect.
Background technology
Please refer to Fig. 1.Fig. 1 is the synoptic diagram of the LCD 100 of a prior art.LCD 100 comprises an image element circuit 110, a shift register district 120.Image element circuit 110 comprises a plurality of pixels 111.Shift register district 120 comprises a plurality of shift register S1-Sn, in order to receive voltage level signal VSS, clock signal XCK and the CK that the outside sends, reach signal ST at the beginning, and, transmit gate drive signal G1-Gn and give image element circuit 110 according to above signal.110 gate drive signal G1-Gn that send according to shift register 120 of image element circuit drive the pixel 111 that is comprised respectively, in order to display frame.
Please refer to Fig. 2.Fig. 2 is the synoptic diagram in the shift register district 120 of prior art.As shown in the figure, shift register S1-Sn all receives voltage level signal VSS, clock signal XCK and CK.And first shift register S1 is in order to receiving commencing signal ST, and according to voltage level signal VSS, clock signal XCK and CK, transmits first gate drive signal G1 to image element circuit 110, also is sent to second shift register S2 simultaneously.And second shift register S2 is in order to receive first gate drive signal G1, and according to voltage level signal VSS, clock signal XCK and CK, transmit second gate drive signal G2 to pixel region 110, also be sent to second shift register S3 simultaneously, the rest may be inferred.Therefore, each shift register in the shift register district 120 just can send gate drive signal in regular turn and drive pixel 111 in the image element circuit 110.
Please refer to Fig. 3.Fig. 3 is the signal schematic representation in the shift register district 120 of prior art.As shown in the figure, when first shift register S1 receives commencing signal, can begin the action in flip-flop shift district 120.Begin to produce gate drive signal G1, then produce gate drive signal G2, the rest may be inferred.Therefore, produce the mode of gate drive signal like this, can start the pixel 111 of image element circuit 110 in regular turn, and finish the purpose of display frame.
Please refer to Fig. 4.Fig. 4 is the block schematic diagram of the shift register 400 of prior art.Shift register 400 comprises switch Q1-Q7, and control circuit 410-430 is with output-stage circuit 440.Output-stage circuit 440 comprises a switch Q8.Control circuit 410 via switch Q2 and Q3, comes the current potential of difference Control Node B and C according to clock signal C K.When control circuit 410 was opened according to clock signal C K and with switch Q2 and Q3, the current potential of Node B and C can be pulled to voltage level VSS.Control circuit 420 via switch Q4 and Q5, comes the current potential of difference Control Node B and C according to clock signal XCK.When control circuit 420 was opened according to clock signal XCK and with switch Q4 and Q5, the current potential of Node B and C can be pulled to voltage level VSS.Control circuit 430 via switch Q6 and Q7, comes the current potential of difference Control Node B and C according to the gate drive signal Gn+1 of next stage.When control circuit 430 was opened according to the gate drive signal Gn+1 of next stage and with switch Q6 and Q7, the current potential of Node B and C can be pulled to voltage level VSS.Output stage circuit 440 then according to the current potential of Node B and C, is sent to node C with clock signal C K, with as gate drive signal Gn.In this way, when the gate drive signal Gn-1 of previous stage input shift register 400, just shift register 400 can after delay a period of time, be exported gate drive signal Gn again according to the function mode as Fig. 3.
Please refer to Fig. 5.Fig. 5 is the gate drive signal Gn synoptic diagram of the shift register of prior art.Because the switch Q8 in the output-stage circuit 440 between Node B and node A, has a stray capacitance C1, can make in the electric current of node A, be circulated to Node B, and influence the switch motion of switch Q8, can't be when closing and cause fully with signal at stop at switch Q8, and the phenomenon of leakage current is arranged.That is to say that as switch Q8 in off position the time, clock signal C K still has part can be circulated to node C, and makes that gate drive signal Gn is influenced.Above-mentioned this situation after switch Q8 has used of a specified duration, produce catabiosis, and more shape is serious, causes as shown in Figure 5, and gate drive signal Gn signal when output is bad, causes misoperation, and reduces quality of display pictures.
Summary of the invention
The invention provides a kind of shift register that reduces coupling effect, comprise a first node; One first switch comprises one first end, is coupled to the output terminal of a previous stage shift register; One second end is coupled to this first node; Reach a control end, be coupled to the output terminal of this previous stage shift register; One output terminal; One first control circuit comprises a first input end, in order to receive one first clock signal; One second input end is in order to receive a second clock signal; One the 3rd input end is coupled to the output terminal of this previous stage shift register; One first output terminal is coupled to this first node; Reach one second output terminal, be coupled to the output terminal of this shift register; One second control circuit comprises: a first input end, in order to receive this second clock signal; One second input end is coupled to the output terminal of this previous stage shift register; One first output terminal is coupled to this first node; Reach one second output terminal, be coupled to the output terminal of this shift register; One the 3rd control circuit comprises: an input end is coupled to the output terminal of a next stage shift register; One first output terminal is coupled to this first node; Reach one second output terminal, be coupled to the output terminal of this shift register; One second switch comprises: one first end, in order to receive this first clock signal; One second end; And a control end, be coupled to this first node; And one the 3rd switch, comprise: one first end is coupled to second end of this second switch; One second end is coupled to the output terminal of this shift register; And a control end, be coupled to this first node.
The present invention provides a kind of LCD that reduces coupling effect in addition, comprises one first glass substrate, comprises a plurality of shift registers that couple that pile up, and each shift register comprises: a first node; One first switch comprises: one first end is coupled to the output terminal of a previous stage shift register; One second end is coupled to this first node; Reach a control end, be coupled to the output terminal of this previous stage shift register; One output terminal; One first control circuit comprises a first input end, in order to receive one first clock signal; One second input end is in order to receive a second clock signal; One the 3rd input end is coupled to the output terminal of this previous stage shift register; One first output terminal is coupled to this first node; Reach one second output terminal, be coupled to the output terminal of this shift register; One second control circuit comprises: a first input end, in order to receive this second clock signal; One second input end is coupled to the output terminal of this previous stage shift register; One first output terminal is coupled to this first node; Reach one second output terminal, be coupled to the output terminal of this shift register; One the 3rd control circuit comprises: an input end is coupled to the output terminal of a next stage shift register; One first output terminal is coupled to this first node; Reach one second output terminal, be coupled to the output terminal of this shift register; One second switch comprises: one first end, in order to receive this first clock signal; One second end; And a control end, be coupled to this first node; And one the 3rd switch, comprise: one first end is coupled to second end of this second switch; One second end is coupled to the output terminal of this shift register; And a control end, be coupled to this first node; And an image element circuit, be coupled to this a plurality of output terminals that pile up at least one shift register in the shift register that couples; One second glass substrate; And a liquid crystal layer, this liquid crystal layer is between this first glass substrate and this second glass substrate.
Description of drawings
Fig. 1 is the synoptic diagram of the LCD of a prior art.
Fig. 2 is the synoptic diagram in the shift register district of prior art.
Fig. 3 is the signal schematic representation in the shift register district of prior art.
Fig. 4 is the block schematic diagram of the shift register of prior art.
Fig. 5 is the gate drive signal synoptic diagram of the shift register of prior art.
Fig. 6 is the synoptic diagram of output-stage circuit of the present invention.
Fig. 7 is the block schematic diagram of shift register of the present invention.
Fig. 8 is the synoptic diagram of another embodiment of output-stage circuit of the present invention.
Fig. 9 is the circuit diagram of shift register of the present invention.
Figure 10 is the synoptic diagram of LCD of the present invention.
The reference numeral explanation
Shift register district 120 1120
Shift register S1-Sn 400 700
Voltage level signal VSS
Clock signal XCK CK
Commencing signal ST
Gate drive signal G1-Gn
The gate drive signal Gn+1 of next stage
The gate drive signal Gn-1 of previous stage
Switch Q1-Q23
Output-stage circuit 440 600 740 810 940
Stray capacitance C1 C2
Glass substrate 1,100 1300
Node A B C D E F G H I J K L M
Embodiment
Please refer to Fig. 6.Fig. 6 is an output-stage circuit 600 of the present invention.Output-stage circuit 600 comprises two switch Q9 and Q10.The control end of switch Q9 and Q10 is coupled to node F, in order to the control signal of receiving node F and according to the signal of this control signal transmission node E to node G.In actual conditions, because the existence of stray capacitance C2 is arranged between node E and the node F, and cause at switch Q9 bad for the switch of signal, this situation can more shape be serious after switch Q9 is aging, and cause the shortcoming of prior art, therefore, the present invention couples a switch Q10 again at the output terminal of switch Q9.When switch Q9 and Q10 all are in closed condition, though owing to stray capacitance C2 can be coupled to the signal of node E the action that node F influences switch Q9, but because switch Q10 still is a closed condition, therefore, the noise exported in the suffered coupling influence of closed condition of switch Q9 can't export node G to.Therefore, the mode that the present invention just couples with this kind circuit is reached the purpose that reduces coupling effect and influence the output performance.
Please refer to Fig. 7.Fig. 7 is the block schematic diagram of shift register 700 of the present invention.Shift register 700 comprises switch Q11-Q19, and control circuit 710-730 is with output-stage circuit 740.Output-stage circuit 740 comprises two switch Q18 and Q19.Control circuit 710 via switch Q12 and 013, comes the current potential of difference Control Node I and J according to clock signal C K.When control circuit 710 was opened according to clock signal C K and with switch Q12 and Q13, the current potential of node I and J can be pulled to voltage level VSS.Control circuit 720 via switch Q14 and Q15, comes the current potential of difference Control Node I and J according to clock signal XCK.When control circuit 720 was opened according to clock signal XCK and with switch Q14 and Q15, the current potential of node I and J can be pulled to voltage level VSS.Control circuit 730 via switch Q16 and Q17, comes the current potential of difference Control Node I and J according to the gate drive signal Gn+1 of next stage.When control circuit 730 was opened according to the gate drive signal Gn+1 of next stage and with switch Q16 and Q17, the current potential of node I and J can be pulled to voltage level VSS.Output stage circuit 740 then according to the current potential of node I and J, is sent to node J with clock signal C K, with as gate drive signal Gn.In this way, when the gate drive signal Gn-1 of previous stage input shift register 700, just shift register 700 can after delay a period of time, be exported gate drive signal Gn again according to the function mode as Fig. 3.
Please refer to Fig. 8.Fig. 8 is the synoptic diagram of another embodiment 810 of output-stage circuit 740.As shown in the figure, output-stage circuit 740 can change output-stage circuit 810 into and be used among the shift register 700 of the present invention.Output-stage circuit 810 comprises four switch Q20-Q23, and switch Q20-Q23 all is coupled to node I, moves with gauge tap in order to the control signal on the receiving node I.The end of switch Q20 and Q22 jointly is coupled to node H, and in order to the signal on the receiving node H, the other end is coupled to switch Q21 and Q23 respectively.The end of switch Q21 and Q23 is coupled to switch Q20 and Q22 respectively, and the other end jointly is coupled to node J, in order to send a signal to node J.With foregoing circuit, finish function as output-stage circuit 740.
Please refer to Fig. 9.Fig. 9 is the circuit diagram of shift register 900 of the present invention, and it is the thin portion key diagram of Fig. 7.Control circuit 910,920,930 all can be analogous to control circuit 710,720,730.Output-stage circuit 940 can be analogous to output-stage circuit 740.All the other functions do not repeat them here all as described above.
Please refer to Figure 10.Figure 10 is the synoptic diagram of LCD 1000 of the present invention.As shown in the figure, LCD 1000 comprises one first glass substrate, 1100, one liquid crystal layers 1200, and one second glass substrate 1300.First glass substrate 1100 comprises an image element circuit 1110 and a shift register district 1120.Shift register 1120 comprises a plurality of shift registers 900 that couple (cascaded) that pile up.Shift register district 1120 can receive outside commencing signal ST and come display frame to send gate drive signal to image element circuit 1110 in regular turn to drive pixel.And, can make the noise of gate drive signal reduce, and then promote the quality that picture shows via the shift register 900 that the present invention improved.
In addition, switch Q9-Q23 of the present invention all can realize by membrane transistor.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (18)
1. shift register that reduces coupling effect comprises:
One first node;
One first switch comprises:
One first end is coupled to the output terminal of a previous stage shift register;
One second end is coupled to this first node; And
One control end is coupled to the output terminal of this previous stage shift register;
One output terminal;
One first control circuit comprises:
One first input end is in order to receive one first clock signal;
One second input end is in order to receive a second clock signal;
One the 3rd input end is coupled to the output terminal of this previous stage shift register;
One first output terminal is coupled to this first node; And
One second output terminal is coupled to the output terminal of this shift register;
One second control circuit comprises:
One first input end is in order to receive this second clock signal;
One second input end is coupled to the output terminal of this previous stage shift register;
One first output terminal is coupled to this first node; And
One second output terminal is coupled to the output terminal of this shift register;
One the 3rd control circuit comprises:
One input end is coupled to the output terminal of a next stage shift register;
One first output terminal is coupled to this first node; And
One second output terminal is coupled to the output terminal of this shift register;
One second switch comprises:
One first end is in order to receive this first clock signal;
One second end; And
One control end is coupled to this first node; And
One the 3rd switch comprises:
One first end is coupled to second end of this second switch;
One second end is coupled to the output terminal of this shift register; And
One control end is coupled to this first node.
2. shift register as claimed in claim 1, wherein, this first, second, third switch is respectively a membrane transistor, and the control end of this first, second, third switch is respectively the grid of a membrane transistor.
3. shift register as claimed in claim 1, wherein, the phase differential of this first clock signal and this second clock signal is 180 degree.
4. shift register as claimed in claim 1, wherein, this first control circuit comprises in addition:
One first switch comprises:
One first end is coupled to a first node;
One second end is coupled to a common ends; And
One control end is coupled to the 3rd input end of this first control circuit;
One second switch comprises:
One first end is coupled to this first node;
One second end is coupled to this common ends; And
One control end is coupled to second input end of this first control circuit;
One the 3rd switch comprises:
One first end is coupled to the first input end of this first control circuit;
One second end is coupled to this first node; And
One control end is coupled to the first input end of this first control circuit;
One the 4th switch comprises:
One first end is coupled to first output terminal of this first control circuit;
One second end is coupled to this common ends; And
One control end is coupled to this first node;
One the 5th switch comprises:
One first end is coupled to second output terminal of this first control circuit;
One second end is coupled to this common ends; And
One control end is coupled to this first node; And
One the 6th switch comprises:
One first end is coupled to this first node;
One second end is coupled to this common ends; And
One control end is coupled to second output terminal of this first control circuit.
5. shift register as claimed in claim 4, wherein, this first, second, third and fourth, five, six switches are membrane transistors, and this first, second, third and fourth, the control end of five, six switches is grids of a membrane transistor.
6. shift register as claimed in claim 1, wherein, this second control circuit comprises in addition:
One first switch comprises:
One first end is coupled to first output terminal of this second control circuit;
One second end is coupled to second input end of this second control circuit; And
One control end is coupled to the first input end of this second control circuit; And
One second switch comprises:
One first end is coupled to second output terminal of this second control circuit;
One second end is coupled to a common ends; And
One control end is coupled to the first input end of this second control circuit.
7. shift register as claimed in claim 6, wherein, this first and second switch is a membrane transistor, and the control end of this first and second switch is the grid of a membrane transistor.
8. shift register as claimed in claim 1, wherein, the 3rd control circuit comprises in addition:
One first switch comprises:
One first end is coupled to first output terminal of this 3rd control circuit;
One second end is coupled to a common ends; And
One control end is coupled to the input end of the 3rd control circuit; And
One second switch comprises:
One first end, second output terminal of the 3rd control circuit;
One second end is coupled to this common ends; And
One control end is coupled to the input end of the 3rd control circuit.
9. shift register as claimed in claim 8, wherein, this first and second switch is a membrane transistor, and the control end of this first and second switch is the grid of a membrane transistor.
10. LCD that reduces coupling effect comprises:
One first glass substrate comprises:
A plurality of shift registers that couple that pile up, each shift register comprises:
One first node;
One first switch comprises:
One first end is coupled to the output terminal of a previous stage shift register;
One second end is coupled to this first node; And
One control end is coupled to the output terminal of this previous stage shift register;
One output terminal;
One first control circuit comprises:
One first input end is in order to receive one first clock signal;
One second input end is in order to receive a second clock signal;
One the 3rd input end is coupled to the output terminal of this previous stage shift register;
One first output terminal is coupled to this first node; And
One second output terminal is coupled to the output terminal of this shift register;
One second control circuit comprises:
One first input end is in order to receive this second clock signal;
One second input end is coupled to the output terminal of this previous stage shift register;
One first output terminal is coupled to this first node; And
One second output terminal is coupled to the output terminal of this shift register;
One the 3rd control circuit comprises:
One input end is coupled to the output terminal of a next stage shift register;
One first output terminal is coupled to this first node; And
One second output terminal is coupled to the output terminal of this shift register;
One second switch comprises:
One first end is in order to receive this first clock signal;
One second end; And
One control end is coupled to this first node; And
One the 3rd switch comprises:
One first end is coupled to second end of this second switch;
One second end is coupled to the output terminal of this shift register; And
One control end is coupled to this first node; And
One image element circuit is coupled to this a plurality of output terminals that pile up at least one shift register in the shift register that couples;
One second glass substrate; And
One liquid crystal layer, this liquid crystal layer is between this first glass substrate and this second glass substrate.
11. LCD as claimed in claim 10, wherein, this first, second, third switch is respectively a membrane transistor, and the control end of this first, second, third switch is respectively the grid of a membrane transistor.
12. LCD as claimed in claim 10, wherein, the phase differential of this first clock signal and this second clock signal is 180 degree.
13. LCD as claimed in claim 10, wherein, this first control circuit comprises in addition:
One first switch comprises:
One first end is coupled to a first node;
One second end is coupled to a common ends; And
One control end is coupled to the 3rd input end of this first control circuit;
One second switch comprises:
One first end is coupled to this first node;
One second end is coupled to this common ends; And
One control end is coupled to second input end of this first control circuit;
One the 3rd switch comprises:
One first end is coupled to the first input end of this first control circuit;
One second end is coupled to this first node; And
One control end is coupled to the first input end of this first control circuit;
One the 4th switch comprises:
One first end is coupled to first output terminal of this first control circuit;
One second end is coupled to this common ends; And
One control end is coupled to this first node;
One the 5th switch comprises:
One first end is coupled to second output terminal of this first control circuit;
One second end is coupled to this common ends; And
One control end is coupled to this first node; And
One the 6th switch comprises:
One first end is coupled to this first node;
One second end is coupled to this common ends; And
One control end is coupled to second output terminal of this first control circuit.
14. LCD as claimed in claim 13, wherein, this first, second, third and fourth, five, six switches are membrane transistors, and this first, second, third and fourth, the control end of five, six switches is grids of a membrane transistor.
15. LCD as claimed in claim 10, wherein, this second control circuit comprises in addition:
One first switch comprises:
One first end is coupled to first output terminal of this second control circuit;
One second end is coupled to second input end of this second control circuit; And
One control end is coupled to the first input end of this second control circuit; And
One second switch comprises:
One first end is coupled to second output terminal of this second control circuit;
One second end is coupled to a common ends; And
One control end is coupled to the first input end of this second control circuit.
16. LCD as claimed in claim 15, wherein, this first and second switch is a membrane transistor, and the control end of this first and second switch is the grid of a membrane transistor.
17. LCD as claimed in claim 10, wherein, the 3rd control circuit comprises in addition:
One first switch comprises:
One first end is coupled to first output terminal of this 3rd control circuit;
One second end is coupled to a common ends; And
One control end is coupled to the input end of the 3rd control circuit; And
One second switch comprises:
One first end, second output terminal of the 3rd control circuit;
One second end is coupled to this common ends; And
One control end is coupled to the input end of the 3rd control circuit.
18. LCD as claimed in claim 17, wherein, this first and second switch is a membrane transistor, and the control end of this first and second switch is the grid of a membrane transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101542436A CN100461303C (en) | 2006-09-18 | 2006-09-18 | Shifting register depressing coupling effect and liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101542436A CN100461303C (en) | 2006-09-18 | 2006-09-18 | Shifting register depressing coupling effect and liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1921018A true CN1921018A (en) | 2007-02-28 |
| CN100461303C CN100461303C (en) | 2009-02-11 |
Family
ID=37778703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101542436A Active CN100461303C (en) | 2006-09-18 | 2006-09-18 | Shifting register depressing coupling effect and liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100461303C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2182509A3 (en) * | 2008-11-04 | 2010-08-11 | AU Optronics Corporation | Gate driver and method for generating gate-line signals |
| CN101339809B (en) * | 2007-07-02 | 2011-01-05 | 上海天马微电子有限公司 | Shift register and LCD using the same |
| CN101593561B (en) * | 2009-06-19 | 2011-11-09 | 友达光电股份有限公司 | Liquid crystal display |
| CN104021772A (en) * | 2014-03-28 | 2014-09-03 | 友达光电股份有限公司 | liquid crystal pixel circuit of liquid crystal display panel and driving method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0597535B1 (en) * | 1992-11-12 | 1998-08-12 | Philips Composants Et Semiconducteurs | Numerical shift register with boosted functioning and a circuit comprising such a register |
| US9386241B2 (en) * | 2003-07-02 | 2016-07-05 | Verity Instruments, Inc. | Apparatus and method for enhancing dynamic range of charge coupled device-based spectrograph |
| JP4520204B2 (en) * | 2004-04-14 | 2010-08-04 | 三菱電機株式会社 | High frequency power amplifier |
| JP4732709B2 (en) * | 2004-05-20 | 2011-07-27 | 株式会社半導体エネルギー研究所 | Shift register and electronic device using the same |
| CN100426421C (en) * | 2006-03-08 | 2008-10-15 | 友达光电股份有限公司 | Dynamic shift scratch circuit |
-
2006
- 2006-09-18 CN CNB2006101542436A patent/CN100461303C/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101339809B (en) * | 2007-07-02 | 2011-01-05 | 上海天马微电子有限公司 | Shift register and LCD using the same |
| EP2182509A3 (en) * | 2008-11-04 | 2010-08-11 | AU Optronics Corporation | Gate driver and method for generating gate-line signals |
| US7872506B2 (en) | 2008-11-04 | 2011-01-18 | Au Optronics Corporation | Gate driver and method for making same |
| CN101593561B (en) * | 2009-06-19 | 2011-11-09 | 友达光电股份有限公司 | Liquid crystal display |
| CN104021772A (en) * | 2014-03-28 | 2014-09-03 | 友达光电股份有限公司 | liquid crystal pixel circuit of liquid crystal display panel and driving method thereof |
| CN104021772B (en) * | 2014-03-28 | 2016-04-13 | 友达光电股份有限公司 | liquid crystal pixel circuit of liquid crystal display panel and driving method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100461303C (en) | 2009-02-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108319385B (en) | Shift register and touch display device with same | |
| CN100435203C (en) | Display device | |
| CN1677575B (en) | Shift register and driving method thereof | |
| JP7267935B2 (en) | SHIFT REGISTER AND DRIVING METHOD, GATE DRIVE CIRCUIT AND DISPLAY DEVICE | |
| US11373614B2 (en) | Shift register unit and driving method thereof, gate drive circuit, and display device | |
| US20060187177A1 (en) | Shift register units, display panels utilizing the same, and methods for improving current leakage thereof | |
| KR20070035223A (en) | Display device and shift register therefor | |
| JP7395503B2 (en) | Shift register and its driving method, gate drive circuit and display device | |
| CN101978428A (en) | Shift register and active matrix device | |
| CN103956133B (en) | shift register circuit and shift register | |
| CN1921018A (en) | Shifting register depressing coupling effect and liquid crystal display | |
| CN103021321B (en) | Shift register and liquid crystal indicator | |
| TW201232502A (en) | Display driving circuit and display panel using the same | |
| CN110942742B (en) | Gate driving unit, gate driving method, gate driving circuit and display device | |
| CN101046940A (en) | Grid drive circuit, liquid crystal display device and electronic device | |
| CN1545099A (en) | Control circuit of bidirectional shift register | |
| CN110689839B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN1928635A (en) | Apparatus and method for transition controlled in LCD | |
| CN101673526B (en) | Liquid crystal display device and related drive method | |
| TWI708227B (en) | Bidirectional gate on array circuit | |
| WO2017096687A1 (en) | Scan driving method for display panel | |
| CN113643643B (en) | Gate driving circuit and display device | |
| CN101620830B (en) | Data driver | |
| CN1889190A (en) | Shift register | |
| CN111063316A (en) | Driving circuit and display panel applying same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |