CN101046940A - Grid drive circuit, liquid crystal display device and electronic device - Google Patents
Grid drive circuit, liquid crystal display device and electronic device Download PDFInfo
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- CN101046940A CN101046940A CN 200610066066 CN200610066066A CN101046940A CN 101046940 A CN101046940 A CN 101046940A CN 200610066066 CN200610066066 CN 200610066066 CN 200610066066 A CN200610066066 A CN 200610066066A CN 101046940 A CN101046940 A CN 101046940A
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Abstract
The present invention relates to a grid drive circuit. It includes first shift register for outputting first signal, second shift register for outputting second signal, NAND gate, first switch device, second switch device, control unit and inverter. The NAND gate has two input ends which are respectively coupled with first signal and second signal. The input end of the first switch device is coupled with output end of NAND gate, the output end of second switch device is coupled with output end of first switch device, its input end is coupled with high voltage level. The control unit can output control signal, and is coupled with first switch device and second switch device. The input end of said inverter is coupled with output end of second switch device, and the output end of said inverter can output grid drive signal.
Description
Technical field
The present invention relates to a kind of gate driver circuit, particularly relate to a kind of gate driver circuit that solves the power-off ghost shadow problem.
Background technology
LCD screen is after shutdown, if the design of drive circuit of LCD screen is not good, just the problem of ghost might take place, gets off for a long time and can cause bad influence to LCD screen.Fig. 1 is known to solve the liquid crystal panel synoptic diagram of LCD screen power-off ghost shadow.In Fig. 1, tft array 10 is controlled by gate driver circuit 12 and data drive circuit 11, and is the problem that solves power-off ghost shadow, and gate driver circuit 12 couples a control circuit 15 to eliminate the problem of power-off ghost shadow.In the control circuit 15, utilize the voltage VDD of electric pressure converter 14 outputs, when LCD screen is started shooting, electric capacity 106 is charged, when LCD screen is shut down, by PMOS transistor 102, the voltage VDD that stores in the electric capacity 106 is sent in the gate driver circuit 12, in order in and the image voltage of TFT unit (as TFT unit 13) in the tft array 10, to reach the mode of eliminating ghost.But in this design, when liquid crystal panel normally shows, be used as the VEE that closes voltage because must be sent to gate driver circuit 12 through resistance 194, can cause the driving force of electric current to reduce, the pass voltage VEE that makes liquid crystal panel receive in resolution panels is subjected to the interference of other signal and produces the problem of image colour cast.
Summary of the invention
Purpose of the present invention is for providing a kind of gate driver circuit that solves LCD screen power-off ghost shadow problem.
The invention provides a kind of gate driver circuit, comprise one first shift register, one second shift register, a Sheffer stroke gate, a selected cell, a control signal generating unit and a phase inverter.First shift register is in order to export one first signal.Second shift register is in order to export a secondary signal.Sheffer stroke gate (NAND gate) has two input ends and an output terminal, and described input end couples this first signal, this secondary signal respectively.Selected cell can be that one first switchgear and a second switch device are formed.Wherein, first switchgear has a control end, an input end and an output terminal, and wherein this input end couples the output terminal of this Sheffer stroke gate.The second switch device has a control end, an input end and an output terminal, and wherein this output terminal couples the output terminal of this first switchgear, and this input end couples a low voltage level.Control signal generating unit is exported a control signal, couples the control end of this first switchgear and this second switch device, makes this first switchgear and the not conducting simultaneously of this second switch device.Phase inverter has an input end and an output terminal, and wherein this input end of this phase inverter couples the output terminal of this second switch device, and this output terminal of this phase inverter is exported a gate drive signal.
The present invention also provides a kind of gate driver circuit, comprises one first shift register, one second shift register, a Sheffer stroke gate, one first switchgear, a second switch device, a control signal generating unit and a phase inverter.First shift register is in order to export one first signal.Second shift register is in order to export a secondary signal.Sheffer stroke gate (NAND gate) has two input ends and an output terminal, and described input end couples this first signal, this secondary signal respectively.Phase inverter has an input end and an output terminal, and wherein this input end of this phase inverter couples the output terminal of this Sheffer stroke gate.First switchgear has a control end, an input end and an output terminal, and wherein this input end couples this gate drive signal.The second switch device has a control end, an input end and an output terminal, and wherein this output terminal couples the output terminal of this first switchgear, and this input end couples one second voltage level.Control signal generating unit is exported a control signal, couples the control end of this first switchgear and this second switch device, makes this first switchgear and the not conducting simultaneously of this second switch device.
The present invention also provides a kind of liquid crystal indicator, comprises a pel array, a data drive circuit and a kind of above-mentioned gate driver circuit, and wherein this data drive circuit and this gate driver circuit are in order to drive this pel array.
The present invention also provides a kind of electronic installation, comprises an a kind of above-mentioned liquid crystal indicator and a control device, in order to control this liquid crystal indicator.
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 is known to solve the liquid crystal panel synoptic diagram of LCD screen power-off ghost shadow.
Fig. 2 is the synoptic diagram according to an embodiment of gate driver circuit of the present invention.
Fig. 3 is the signal waveforms of gate driver circuit running among Fig. 2.
Fig. 4 is the synoptic diagram according to another embodiment of gate driver circuit of the present invention.
Fig. 5 is the synoptic diagram of an embodiment of the liquid crystal panel of use gate driver circuit of the present invention.
Fig. 6 is the synoptic diagram of use as an embodiment of the electronic installation of the liquid crystal panel of Fig. 5.
The reference numeral explanation
10～tft array, 11～gate driver circuit
12～data drive circuit, 13～TFT unit
14～electric pressure converter, 15～control circuit
102～PMOS transistor, 194～resistance
106～electric capacity, 201～the first shift registers
202～the second shift registers 203～the 3rd shift register
204～Sheffer stroke gate, 205～Sheffer stroke gate
206～PMOS transistor, 207～nmos pass transistor
208～PMOS transistor, 209～nmos pass transistor
210～phase inverter, 211～phase inverter
213～control module, 214～end points
215～ end points 215a, 215b～selected cell
60～pel array, 61～gate driver circuit
62～data drive circuit, 80～electronic installation
71～control module, 70～liquid crystal panel
Embodiment
Fig. 2 is the synoptic diagram according to an embodiment of gate driver circuit of the present invention.In gate driver circuit 61, comprise a plurality of shift registers, only do explanation in the present embodiment with 3 shift registers, non-in order to restriction the present invention.Control module 213 is in order to export a control signal Dreset, and in the present embodiment, when liquid crystal panel was started shooting, control signal Dreset was a logic low, and when liquid crystal panel shut down, control signal Dreset was a logic high.Sheffer stroke gate 204 has two input ends, couples first shift register 201 and second shift register 202 respectively.Sheffer stroke gate 204 couples the input end of phase inverter 210 by selected cell 215a.Selected cell 215a is controlled by a control signal Dreset, makes phase inverter 210 receive the voltage signal of a logic low.Selected cell 215a comprises at least two switchgears, and for example PMOS transistor 206 and nmos pass transistor 207 receive the voltage signal of logic low to guarantee phase inverter 210.The output terminal of Sheffer stroke gate 204 couples first source/drain electrode of PMOS transistor 206.Second source/drain electrode of PMOS transistor 206 and first source/drain electrode of nmos pass transistor 207 couple the input end of phase inverter 210.The grid of the grid of PMOS transistor 206 and nmos pass transistor 207 couples the control signal Dreset of control module 213, utilizes control signal Dreset to make the grid and the not conducting simultaneously of nmos pass transistor 207 of PMOS transistor 206.Second source/drain electrode of nmos pass transistor 207 couples a low-voltage source VSS.The output terminal of phase inverter 210 is in order to output first grid drive signal Gate 1.Sheffer stroke gate 205 has two input ends, couples second shift register 220 and the 3rd shift register 203 respectively.Sheffer stroke gate 205 couples the input end of phase inverter 211 by selected cell 215b.Selected cell 215b is controlled by a control signal Dreset, makes phase inverter 211 receive the voltage signal of a logic low.Selected cell 215b comprises at least two switchgears, and for example PMOS transistor 208 and nmos pass transistor 209 receive the voltage signal of logic low to guarantee phase inverter 211.The output terminal of Sheffer stroke gate 205 couples first source/drain electrode of PMOS transistor 208.Second source/drain electrode of PMOS transistor 208 and first source/drain electrode of nmos pass transistor 209 couple the input end of phase inverter 211, the grid of the grid of PMOS transistor 208 and nmos pass transistor 209 couples the control signal Dreset of control module 213, and second source/drain electrode of nmos pass transistor 209 couples a low-voltage source VSS.The output terminal of phase inverter 211 is in order to output second grid drive signal Gate 2.
The running of gate driver circuit please refer to Fig. 3 among Fig. 2.Fig. 3 is the signal waveforms of gate driver circuit running among Fig. 2.The output signal SR2 of the output signal SR1 of first shift register 201 and second shift register 202 is positioned at logic high simultaneously and control signal Dreset is a low voltage level, makes first grid drive signal Gate 1 be logic high.Then, the output signal SR3 of the output signal SR2 of second shift register 202 and the 3rd shift register 203 is positioned at logic high simultaneously and control signal Dreset is a low voltage level, makes second grid drive signal Gate 2 be logic high.Afterwards, control signal Dreset changes into high-voltage level when outage takes place, at the same time, make first grid drive signal Gate 1 and second grid drive signal Gate 2 be logic high simultaneously, and then the image voltage of TFT unit (as TFT unit 13) in all tft array 10 that neutralize, and reach the mode of eliminating ghost.
Fig. 4 is the synoptic diagram according to another embodiment of gate driver circuit of the present invention.In gate driver circuit 61, comprise a plurality of shift registers, only do explanation in the present embodiment with 3 shift registers, non-in order to restriction the present invention.Control module 213 is in order to export a control signal Dreset, makes grid and nmos pass transistor 207 and the PMOS transistor 208 and the not conducting simultaneously of nmos pass transistor 209 of PMOS transistor 206.In the present embodiment, when liquid crystal panel was started shooting, control signal Dreset was a logic low, and when liquid crystal panel shut down, control signal Dreset was a logic high.Sheffer stroke gate 204 has two each and every one input ends, couples first shift register 201 and second shift register 202 respectively.The output terminal of Sheffer stroke gate 204 couples the input end of phase inverter 210.The output terminal of phase inverter 210 couples first source/drain electrode of PMOS transistor 206.Second source/drain electrode of PMOS transistor 206 couples in order to output first grid drive signal Gate 1 with first source/drain electrode of nmos pass transistor 207.The grid of the grid of PMOS transistor 206 and nmos pass transistor 207 couples the control signal Dreset of control module 213.Second source/drain electrode of nmos pass transistor 207 couples a high voltage source VDD.Sheffer stroke gate 205 has two input ends, couples second shift register 202 and the 3rd shift register 203 respectively.The output terminal of Sheffer stroke gate 205 couples the input end of phase inverter 211.The output terminal of phase inverter 211 couples first source/drain electrode of PMOS transistor 208.Second source/drain electrode of PMOS transistor 208 couples in order to output second grid drive signal Gate2 with first source/drain electrode of nmos pass transistor 209.The grid of the grid of PMOS transistor 208 and nmos pass transistor 209 couples the control signal Dreset of control module 213.Second source/drain electrode of nmos pass transistor 209 couples a high voltage source VDD.The running of gate driver circuit among Fig. 4 can be with reference to figure 3.
Fig. 5 is the synoptic diagram of an embodiment of the liquid crystal panel of use gate driver circuit of the present invention.In the liquid crystal panel 70 of Fig. 5, pel array 60 is subjected to comprising the driving of aforesaid gate driver circuit 61 or data drive circuit 62 and shows specific picture.
Fig. 6 is the synoptic diagram of use as an embodiment of the electronic installation of the liquid crystal panel of Fig. 5.In Fig. 6, the control module 71 in the electronic installation 80 is in order to control liquid crystal panel 70, and when electronic installation 80 shutdown, transmits a signal (as control signal Dreset among Fig. 2) and close liquid crystal panel 70, to avoid liquid crystal panel 70 the situation appearance of power-off ghost shadow arranged.Electronic installation 80 can be a display, a mobile computer, a flat computer, a mobile phone or a PDA(Personal Digital Assistant), digital camera, mobile phone.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (10)
1. gate driver circuit comprises:
One first shift register is exported one first signal;
One second shift register is exported a secondary signal;
One Sheffer stroke gate has two input ends and an output terminal, and described input end couples this first signal and this secondary signal respectively;
One first switchgear has a control end, an input end and an output terminal, and wherein this input end couples the output terminal of this Sheffer stroke gate;
One second switch device has a control end, an input end and an output terminal, and wherein this output terminal couples the output terminal of this first switchgear, and this input end couples a high-voltage level;
One control signal generating unit is exported a control signal, couples the control end of this first switchgear and this second switch device, makes this first switchgear and the not conducting simultaneously of this second switch device; And
One phase inverter has an input end and an output terminal, and wherein this input end of this phase inverter couples the output terminal of this second switch device, and this output terminal of this phase inverter is exported a gate drive signal.
2. gate driver circuit as claimed in claim 1, wherein this first switchgear is a PMOS transistor, this second switch device is a nmos pass transistor.
3. gate driver circuit as claimed in claim 1, wherein this first switchgear is a nmos pass transistor, this second switch device is a PMOS transistor.
4. gate driver circuit comprises:
One signal output terminal;
One first shift register is exported one first signal;
One second shift register is exported a secondary signal;
One Sheffer stroke gate has two input ends and an output terminal, and described input end receives this first signal and this secondary signal respectively;
One phase inverter has an input end and an output terminal, and wherein this input end of this phase inverter couples the output terminal of this Sheffer stroke gate;
One first switchgear has a control end, an input end and an output terminal, and wherein this input end couples this gate drive signal;
One second switch device has a control end, an input end and an output terminal, and wherein this output terminal couples the output terminal of this first switchgear, and this input end couples a high-voltage level; And
One control signal generating unit is exported a control signal, couples the control end of this first switchgear and this second switch device, makes this first switchgear and the not conducting simultaneously of this second switch device.
5. gate driver circuit as claimed in claim 4, wherein this first switchgear is a PMOS transistor, this second switch device is a nmos pass transistor.
6. gate driver circuit as claimed in claim 4, wherein this first switchgear is a nmos pass transistor, this second switch device is a PMOS transistor.
7. liquid crystal indicator comprises:
One pel array;
One data drive circuit; And
A kind of gate driver circuit as claimed in claim 1, wherein this data drive circuit and this gate driver circuit are in order to drive this pel array.
8. liquid crystal indicator comprises:
One pel array;
One data drive circuit; And
A kind of gate driver circuit as claimed in claim 4, wherein this data drive circuit and this gate driver circuit are in order to drive this pel array.
9. electronic installation comprises:
A kind of liquid crystal indicator as claimed in claim 7; And
One control device is in order to control this liquid crystal indicator.
10. electronic installation as claimed in claim 9, wherein above-mentioned electronic installation are a display, a mobile computer, a flat computer, a mobile phone or a personal digital assistant, digital camera, mobile phone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100660666A CN100538806C (en) | 2006-03-28 | 2006-03-28 | Gate driver circuit, liquid crystal indicator and electronic installation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100660666A CN100538806C (en) | 2006-03-28 | 2006-03-28 | Gate driver circuit, liquid crystal indicator and electronic installation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101046940A true CN101046940A (en) | 2007-10-03 |
| CN100538806C CN100538806C (en) | 2009-09-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100660666A Expired - Fee Related CN100538806C (en) | 2006-03-28 | 2006-03-28 | Gate driver circuit, liquid crystal indicator and electronic installation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100538806C (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101739937B (en) * | 2010-01-15 | 2012-02-15 | 友达光电股份有限公司 | Gate driving circuit |
| CN102592542A (en) * | 2012-02-27 | 2012-07-18 | 深圳市明微电子股份有限公司 | Blanking control circuit for LED (light-emitting diode) display screens and LED drive chip |
| WO2013075506A1 (en) * | 2011-11-22 | 2013-05-30 | 上海天马微电子有限公司 | Gate-driving circuit for display panel and display screen |
| CN103280198A (en) * | 2013-02-06 | 2013-09-04 | 友达光电股份有限公司 | Display panel and gate driver thereof |
| WO2015010360A1 (en) * | 2013-07-23 | 2015-01-29 | 合肥京东方光电科技有限公司 | Circuit, method and display for eliminating shutdown image sticking |
| CN104485081A (en) * | 2014-12-26 | 2015-04-01 | 上海天马微电子有限公司 | Touch display panel, array substrate and scanning line driving method thereof |
| CN105551447A (en) * | 2016-02-18 | 2016-05-04 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display device |
| CN109637411A (en) * | 2017-10-05 | 2019-04-16 | 群创光电股份有限公司 | Show equipment |
| CN110266302A (en) * | 2018-03-12 | 2019-09-20 | 爱思开海力士有限公司 | Power gating circuit and power gating control system |
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2006
- 2006-03-28 CN CNB2006100660666A patent/CN100538806C/en not_active Expired - Fee Related
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101739937B (en) * | 2010-01-15 | 2012-02-15 | 友达光电股份有限公司 | Gate driving circuit |
| EP2784770A4 (en) * | 2011-11-22 | 2016-02-24 | Shanghai Tianma Micro Elect Co | Gate-driving circuit for display panel and display screen |
| WO2013075506A1 (en) * | 2011-11-22 | 2013-05-30 | 上海天马微电子有限公司 | Gate-driving circuit for display panel and display screen |
| CN103137081A (en) * | 2011-11-22 | 2013-06-05 | 上海天马微电子有限公司 | Display panel gate driving circuit and display screen |
| CN103137081B (en) * | 2011-11-22 | 2014-12-10 | 上海天马微电子有限公司 | Display panel gate driving circuit and display screen |
| KR101475243B1 (en) * | 2011-11-22 | 2014-12-22 | 상하이 티안마 마이크로-일렉트로닉스 컴퍼니., 리미티드 | Gate driving circuit of display panel and display screen with the same |
| US9418606B2 (en) | 2011-11-22 | 2016-08-16 | Shanghai Tianma Micro-electronics Co., Ltd. | Gate driving circuit of display panel and display screen with the same |
| CN102592542A (en) * | 2012-02-27 | 2012-07-18 | 深圳市明微电子股份有限公司 | Blanking control circuit for LED (light-emitting diode) display screens and LED drive chip |
| CN102592542B (en) * | 2012-02-27 | 2015-03-18 | 深圳市明微电子股份有限公司 | Blanking control circuit for LED (light-emitting diode) display screens and LED drive chip |
| CN103280198A (en) * | 2013-02-06 | 2013-09-04 | 友达光电股份有限公司 | Display panel and gate driver thereof |
| CN103280198B (en) * | 2013-02-06 | 2015-07-01 | 友达光电股份有限公司 | Display panel and gate driver thereof |
| WO2015010360A1 (en) * | 2013-07-23 | 2015-01-29 | 合肥京东方光电科技有限公司 | Circuit, method and display for eliminating shutdown image sticking |
| US9865204B2 (en) | 2013-07-23 | 2018-01-09 | Boe Technology Group Co., Ltd. | Circuit and method for eliminating shutdown after-image, and display device |
| CN104485081A (en) * | 2014-12-26 | 2015-04-01 | 上海天马微电子有限公司 | Touch display panel, array substrate and scanning line driving method thereof |
| CN104485081B (en) * | 2014-12-26 | 2017-07-14 | 上海天马微电子有限公司 | Touch display panel, array substrate and scanning line driving method thereof |
| CN105551447A (en) * | 2016-02-18 | 2016-05-04 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display device |
| CN109637411A (en) * | 2017-10-05 | 2019-04-16 | 群创光电股份有限公司 | Show equipment |
| CN110266302A (en) * | 2018-03-12 | 2019-09-20 | 爱思开海力士有限公司 | Power gating circuit and power gating control system |
| CN110266302B (en) * | 2018-03-12 | 2023-05-23 | 爱思开海力士有限公司 | Power gating circuit and power gating control system |
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| Publication number | Publication date |
|---|---|
| CN100538806C (en) | 2009-09-09 |
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