CN101620830B - Data driver - Google Patents
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- CN101620830B CN101620830B CN2008101279168A CN200810127916A CN101620830B CN 101620830 B CN101620830 B CN 101620830B CN 2008101279168 A CN2008101279168 A CN 2008101279168A CN 200810127916 A CN200810127916 A CN 200810127916A CN 101620830 B CN101620830 B CN 101620830B
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Abstract
The invention discloses a data driver comprising two data processing circuits and a multiplexer circuit. The two data processing circuits respectively provide a positive pixel voltage and a negative pixel voltage according to first pixel data and second pixel data. The multiplexer circuit comprises a plurality of multiplexer units, a first input end and a second input end thereof receive the positive pixel voltage and the negative pixel voltage, respectively, and the output end is coupled to a data wire. The first and second switches of a first switcher are connected in series between the first input end and the second input end, a node between the two switches is selectively grounded via a third switch. The fourth and fifth switches of a second switcher are connected in series between the second input end and the output end, a node between the two switches is selectively grounded via a sixth switch. When the first and the second switches are turned on, the sixth switch is turned on. When the fourth and fifth switches are turned on, the third switch is turned on.
Description
Technical field
The relevant a kind of driver of the present invention, and particularly relevant for a kind of data driver.
Background technology
In the type of drive of LCD, for fear of the physical characteristics of destroying liquid crystal molecule, must use the voltage of opposed polarity in turn, drive liquid crystal molecule.In the type of drive of using changeless common voltage, data driver is by changing the polarity of its voltage of exporting, suitably to drive liquid crystal molecule.
In the tradition, when the data driver drive liquid crystal molecule, the level range of driving voltage is to be about-6 volts to 6 volts.At this moment, the required maximum cross-pressure that bears of employed circuit component may be 12 volts (6～6 volts) in data driver.In order in the process that drives LCD, to bear 12 volts cross-pressure, the circuit component that the essential use of data driver can high pressure resistant (high voltage).Yet the data driver that use can high voltage bearing circuit component but has problem oversize and with high costs.Therefore, how reducing the size of data driver and reduce cost, is one of direction of endeavouring of industry.
Summary of the invention
The purpose of this invention is to provide a kind of data driver, can reduce can high pressure resistant circuit component use, can under the prerequisite of the consumed power that can not increase system, reduce the size and the chip area of data driver, and reduce cost.
According to a first aspect of the invention, a kind of data driver is proposed, in order to drive many data lines of a display panel accordingly according to a plurality of pixel datas.These pixel datas comprise one first pixel data and one second pixel data.This data driver comprises one first data processing circuit, one second data processing circuit and a multiplexer circuit.First data processing circuit and one second data processing circuit are in order to handle these pixel datas.First data processing circuit provides a positive pixel voltage according to first pixel data, and second data processing circuit provides a negative pixel voltage according to second pixel data.The multiplexer circuit comprises a plurality of multiplexers unit, and each these multiplexer unit comprises a first input end, one second input end, an output terminal, one first switch and one second switch.First input end and one second input end are respectively in order to receive positive pixel voltage and negative pixel voltage.Output terminal is coupled to one of these data lines.First switch has one first switch, a second switch and one the 3rd switch.First and second switch series connection is coupled between first input end and the output terminal, and the first node between first and second switch passes through optionally ground connection of the 3rd switch.Second switch has one the 4th switch, one the 5th switch and one the 6th switch.The series connection of the 4th and the 5th switch is coupled between second input end and the output terminal, and the Section Point between the 4th and the 5th switch passes through optionally ground connection of the 6th switch.When first and second switch conduction, the 6th switch conduction.When the 4th and the 5th switch conduction, the 3rd switch conduction.
According to a second aspect of the invention, propose a kind of data driver, comprise one first pixel data and one second pixel data in order to these pixel datas of many data lines that drive a display panel according to a plurality of pixel datas accordingly.Data driver comprises one first data processing circuit, one second data processing circuit and a multiplexer circuit.First data processing circuit is in order to provide a positive pixel voltage according to first pixel data.Second data processing circuit comprises a level shifter, a digital analog converter and an output buffer.Level shifter is in order to receive second pixel data.The voltage level of second pixel data is between an earth level and one first positive level, and be the level between one first negative level and first positive level in order to the voltage level of adjusting second pixel data, the voltage level of then adjusting second pixel data is the level between first negative level and earth level, and the voltage level of adjusting second pixel data afterwards is the level between one second negative level and earth level.Output buffer is in order to temporary negative pixel voltage.The multiplexer circuit in order to positive pixel voltage and negative pixel voltage are exported to these data lines its two.The absolute value of first negative level is the absolute value less than second negative level.
According to a third aspect of the invention we, a kind of data driver is proposed, in order to drive many data lines of a display panel accordingly according to a plurality of pixel datas.These pixel datas comprise a plurality of first pixel datas and a plurality of second pixel data.Data driver comprises one first data processing circuit, one second data processing circuit and a multiplexer circuit.First data processing circuit is in order to provide a plurality of positive pixel voltage according to these first pixel datas.Second data processing circuit comprises a prime level shifter, a shift register, a shift register, a line buffer, a back grade level shifter, digital analog converter and an output buffer.The prime level shifter is in order to receive these second pixel datas sequentially, the pairing voltage level of these second pixel datas is between an earth level and one first positive level, and the voltage level of adjusting these second pixel datas is the voltage level between one first negative level and earth level.These second pixel datas and the parallel type ground output of shift register in order to receive the output of prime level shifter sequentially.Line buffer is in order to these second pixel datas of temporary shift register output.Level level shifter in back is a voltage level between one second negative level and earth level in order to the voltage level of these second prime number certificates of adjusting line buffer output.Digital analog converter is a plurality of negative pixel voltages in order to these second pixel datas of changing back level level shifter output.Output buffer is in order to temporary these negative pixel voltages.The multiplexer circuit is in order to export these positive pixel voltage to corresponding these data lines with these negative pixel voltages.The absolute value of first negative level is the absolute value less than second negative level.
Description of drawings
For foregoing of the present invention can be become apparent, below conjunction with figs. is elaborated to preferred embodiment of the present invention, wherein:
Fig. 1 illustrates a kind of calcspar of data driver.
Fig. 2 A illustrates the synoptic diagram according to two multiplexer unit of the multiplexer circuit of first embodiment of the invention.
Fig. 2 B illustrates the synoptic diagram of two multiplexer unit of traditional multiplexer circuit.
Fig. 3 illustrates the example of circuit diagram of the multiplexer unit of Fig. 2 A.
Fig. 4 illustrates the oscillogram of an example of the employed switching signal in multiplexer unit of Fig. 3.
Fig. 5 A illustrates the calcspar according to the level shifter of second embodiment of the invention.
Fig. 5 B illustrates the calcspar into traditional level shifter.
Fig. 6 illustrates and is the shift register of the data driver of third embodiment of the invention and the calcspar of line buffer.
Embodiment
Please refer to Fig. 1, it illustrates the calcspar into a kind of data driver.Data driver 100 is in order to drive many data line DL1～DL2m of a display panel accordingly according to a plurality of pixel data D1～D2m.Pixel data D1～D2m comprises first pixel data Dp1～Dpm and second pixel data Dn1～Dnm.Data driver 100 comprises one first data processing circuit 110, one second data processing circuit 120 and a multiplexer circuit 140.First and 1 second data processing circuit 110 and 120 is in order to handle these pixel datas D1～D2m.First data processing circuit 110 comprises a level shifter 111, a digital analog converter 112 and an output buffer 113.Second data processing circuit 120 comprises a level shifter 121, a digital analog converter 122 and an output buffer 123.First and second data processing circuit 110 and 120 is also shared a shift register 160 and a line buffer 180.
Shift register 160 receives these pixel datas D1～D2m in order to (sequentially) sequentially, and these pixel datas of parallel type ground output D1～D2m.Line buffer 180 is in order to receiving from these pixel datas D1～D2m of shift register 160 outputs, and exports first pixel data Dp1～Dpm (positive polarity pixel data) and second pixel data Dn1～Dnm (negative polarity pixel data) respectively to level shifter 111 and 121.
Digital analog converter 112 and 122 is positive pixel voltage Vp1～Vpm and negative pixel voltage Vn1～Vnm in order to first and second pixel data Dp1～Dpm and the Dn1～Dnm of switching levels shift unit 111 and 121 outputs respectively. Output buffer 113 and 123 is respectively in order to temporary positive pixel voltage Vp1～Vpm and negative pixel voltage Vn1～Vnm.Multiplexer circuit 140 comes driving data lines DL1～DL2m according to positive pixel voltage Vp1～Vpm and negative pixel voltage Vn1～Vnm.Each element that is comprised in first data processing circuit 110 and second data processing circuit 120 herein only is an example, is not in order to restriction the present invention.As long as the data processing circuit that first pixel data Dp1～Dpm and second pixel data Dn1～Dnm can be converted to first pixel data Dp1～Dpm and second pixel data Dn1～Dnm respectively all within the scope of the present invention.Below will represent one of first pixel data Dp1～Dpm with the first pixel data Dp, on behalf of one of first pixel data Dn1～Dnm, the second pixel data Dn each embodiment is described.
In embodiments of the invention, circuit component that can high pressure resistant (high voltage) for example may be defined as: by 2.5 microns circuit components that technology realized, it for example is the voltage that can bear less than 32 volts.Press the circuit component of (medium voltage) in can be anti-, for example may be defined as: by 0.6 micron circuit component that technology realized, it for example is the voltage that can bear less than 6 volts.In the process of design data driver 100, the applicant finds that because the maximum level of the voltage that must bear of the multiplexer circuit 140 of Fig. 1 and level shifter 121 is 12 volts (6～6 volts), therefore need use can high voltage bearing circuit component.
In one embodiment of the invention, be the configuration of improvement multiplexer circuit 140, with reduce can high voltage bearing circuit component use.Moreover, in another embodiment of the present invention, be the configuration of improvement level shifter 121, with reduce can high voltage bearing circuit component use.Whereby, make in data driver proposed by the invention, can reduce can high pressure resistant circuit component use, and can also under the prerequisite of the consumed power that can not increase system, reduce the size and the chip area of data driver, and reduce cost.With a plurality of embodiment data driver of the present invention is described below.
First embodiment
Present embodiment is the configuration of improvement multiplexer circuit 140, with reduce can high voltage bearing circuit component use.Now the multiplexer cell descriptions to present embodiment is as follows.
The first switch 141a has a switch SW 1, a switch SW 2 and a switch SW 3.Switch SW 1 and SW2 coupled in series are between first input end I1 and output terminal O1, and the node n1 between switch SW 1 and the switch SW 2 passes through optionally ground connection of switch SW 3.The second switch 141b has a switch SW 4, a switch SW 5 and a switch SW 6.Switch SW 4 and SW5 coupled in series are between the second input end I2 and output terminal O1, and the node n2 between switch SW 4 and the SW5 passes through optionally ground connection of switch SW 6.
When switch SW 1 and SW2 conducting, switch SW 6 conductings, make the node n2 between switch SW 4 and the SW5 be coupled to ground, so that the maximum cross-pressure of the maximum cross-pressure of switch SW 4 and switch SW 5 is the maximum voltage difference half between the second input end I2 and the output terminal O1 by switch SW 6.When switch SW 4 and SW5 conducting, switch SW 3 conductings make that the node n1 between switch SW 1 and the SW2 is coupled to ground by switch SW 3, so that the maximum cross-pressure of switch SW 1 and SW2 is the maximum voltage difference half between first input end I1 and the output terminal O1.
Existing being compared as follows to the multiplexer unit of present embodiment and traditional multiplexer unit as flowing mode.Wherein, the level that is hypothesis positive pixel voltage Vp is between 0 volt and 6 volts, and the level of negative pixel voltage Vn is between-6 volts and 0 volt.
Please refer to Fig. 2 B, it illustrates the synoptic diagram of two multiplexer unit of traditional multiplexer circuit.In traditional multiplexer circuit 140 ', when switch SW 1 ' conducting and switch SW 2 ' not conducting, output terminal O1 output positive pixel voltage Vp.This moment, the cross-pressure that bears of two ends of switch SW 2 ' was the voltage difference of negative pixel voltage Vn (6～0 volts) with the positive pixel voltage Vp (0～6 volt) of output terminal O1 of input end I2, and the maximal value of this voltage difference is 12 volts.Therefore, this moment, employed switch SW 2 ' must be for can anti-12 volts switch.In like manner as can be known, when output terminal O1 output negative pixel voltage Vn, switch SW 1 ' also will be born and will be 12 volts cross-pressure to the maximum.Therefore, in traditional multiplexer circuit 140 ', switch SW 1 ' and SW2 ' all need use and can realize by high voltage bearing circuit component.
Please refer to aforesaid Fig. 2 A.Yet, in the multiplexer circuit 140 of present embodiment, when switch SW 1 and SW2 conducting and switch SW 4 and not conducting of SW5, output terminal O1 output positive pixel voltage Vp.This moment, switch SW 6 will conducting, make node n2 ground connection, this moment, the maximum cross-pressure of switch SW 4 and switch SW 5 was maximum voltage difference half between the second input end I2 and the output terminal O1, and 12 volts of maximum voltage difference that also are positive pixel voltage Vp (0～6 volt) and negative pixel voltage Vn (6～0 volts) partly.At this moment, the maximum cross-pressure of each switch SW 4 and SW5 is 6 volts.In like manner as can be known, when switch SW 1 and not conducting of SW2 and switch SW 4 and SW5 conducting, output terminal O1 output negative pixel voltage Vn.This moment, switch SW 3 will conducting, made that the maximum cross-pressure of switch SW 1 and SW2 is 6 volts.Therefore, switch SW 1, SW2, SW3 and SW4 can be by realizing by anti-middle circuit component of pressing.
Because the circuit component size is to be relevant to length breadth ratio (L/W), so can know by inference: one can high voltage bearing circuit component size be more than 16 times of size greater than the circuit component of pressure in can be anti-.Therefore as can be known, in multiplexer unit 141, be to use two switch SW 1 and SW2 that press in can be anti-, replacing in traditional multiplexer unit 141 ' one can high voltage bearing switch SW 1 ', and the voltage of ground connection is provided by switch SW 3.Generally speaking, the total area of switch SW 1, SW2 and SW3 still is less than the area of switch SW 1 '.Therefore since the multiplexer circuit of present embodiment need not use can high voltage bearing circuit component, so can reduce to use the size of the data driver of multiplexer unit.
In Fig. 2 A, the configuration of multiplexer unit 142 and multiplexer unit 141 are similar, so do not repeat in this.Wherein, first and second input end of multiplexer unit 142 is first and second input end I1 and the I2 that is coupled to multiplexer unit 141 respectively, illustrates as Fig. 2 A.Mode of operation between the multiplexer unit 141 and 142 is: when output terminal O1 output positive pixel voltage Vp, and output terminal O2 output negative pixel voltage Vn.When output terminal O1 output negative pixel voltage Vn, output terminal O2 output positive pixel voltage Vp.
Please refer to Fig. 3, it illustrates an example of multiplexer unit 141 and 142 the circuit diagram of Fig. 2 A.In this example, switch SW 1, SW2, SW4 and SW5 are that (Transmission Gate TG), and is by being realized by anti-middle transistor of pressing to transmission gate.Moreover switch SW 7, SW8, SW10, SW11 also can be transmission gate and are realized by the transistor of pressing in can be anti-.Each transmission gate comprises a P-type mos transistor and a N type metal oxide semiconductor transistor.Switch SW 3 and SW6 are transistors.Moreover switch SW 9, SW12 also can be realized by transistor.Please be simultaneously with reference to Fig. 4, it illustrates the oscillogram into an example of the employed switching signal in multiplexer unit of Fig. 3.In this example, switching signal comprises a plurality of control signal S1～S8, and wherein control signal S1B～S8B is respectively the inversion signal of control signal S1～S8.
In addition, multiplexer circuit 140 also comprises a basic voltage commutation circuit BD, in order to each P-type mos transistor one negative basic voltage to be provided according to switching signal, and provides each N type metal oxide semiconductor transistor one positive substrate voltage.So, in the period of Fig. 4 tm, control signal S3 and S7 are preferably and are converted to ground voltage.So can avoid when opening or closing transmission gate, producing basis coherent with the orientation substrate biasing (forwardbody bias), and make the P-type mos transistor AND gate N type metal oxide semiconductor transistor of transmission gate correctly to move.
In the timing diagram of detailed circuit diagram that Fig. 3 and Fig. 4 illustrated and various signals, be an example that can realize multiplexer circuit of the present invention in real the work, be not in order to limit the present invention.Therefore, have and know that usually the knowledgeable can be revised at disclosed technology contents herein, also can reach the purpose that realizes the multiplexer circuit that present embodiment proposed.
In present embodiment since the employed multiplexer circuit of data driver need not use can high voltage bearing circuit component, so can reduce the size of data driver, and reduce cost.
Second embodiment
Present embodiment is the configuration of level shifter 121 of improvement Fig. 1, with reduce can high voltage bearing circuit component use.Now the level shifter to present embodiment is described as follows.
Please be simultaneously with reference to Fig. 1 and Fig. 5 A, Fig. 5 A illustrates the calcspar according to the level shifter 121 of second embodiment of the invention.Level shifter 121 comprises a plurality of electrical level shift units, for example is four electrical level shift units LS1～LS4.Electrical level shift units LS1 is in order to receive the second pixel data Dn, and the pairing voltage level of the second pixel data Dn is the voltage level between an earth level GND and one first positive level PL1.Electrical level shift units LS2 is a voltage level between the one first negative level NL1 and the first positive level PL1 in order to the voltage level of the second pixel data Dn that adjusts electrical level shift units LS1 output.Electrical level shift units LS3 is a voltage level between the first negative level NL1 and earth level GND in order to the voltage level of the second pixel data Dn that adjusts electrical level shift units LS2 output.Electrical level shift units LS4 is a voltage level between one second negative level NL2 and earth level GND in order to the voltage level of the second pixel data Dn that adjusts electrical level shift units LS3 output.Then, the digital analog converter 122 of Fig. 1 is a negative pixel voltage Vn with the second pixel data Dn of switching levels shift unit NL4 output.
In present embodiment, the absolute value of the first negative level NL1 is the absolute value less than the second negative level NL2.Preferably, the absolute value of the first positive level PL1 is the absolute value that is equal to the first negative level NL1 in fact.The first positive level PL1 is a low voltage level, and the first negative level NL1 is a low voltage level, and the second negative level NL2 is middle voltage level.For instance, the first positive level PL1 is essentially 1.8 volts, and the first negative level NL1 is essentially-1.8 volts, and the second negative level NL2 is essentially-6 volts.
By using the level shifter 121 that proposes in the present embodiment, can reduce the size of data driver, existing that cause description is as follows.
Please refer to Fig. 5 B, it illustrates the calcspar into traditional level shifter.Owing to use in the data driver of traditional level shifter 121 ', needing to use can high voltage bearing circuit component, so data driver can have bigger size.Traditional level shifter 121 ' comprises four electrical level shift units A～D.In electrical level shift units C, be to adjust the second pixel data Dn of electrical level shift units B output between-6 volts and 6 volts.That is the difference of the voltage level that electrical level shift units C need bear is 12 volts, surpasses the scope of pressing (6 volts) in can be anti-, so need use can high voltage bearing circuit component for electrical level shift units C.
Please refer to aforesaid Fig. 5 A.In the level shifter 121 of present embodiment, the cross-pressure that assembly bore among employed four electrical level shift units LS1～LS4 is neither to surpass 6 volts, can high voltage bearing circuit component so need not use.That is, because the cross-pressure that assembly bore among electrical level shift units LS1 and the LS3 is up to 1.8 volts, so electrical level shift units LS1 and LS3 can be realized by circuit component that can anti-low-voltage.And because the cross-pressure best result that assembly bore among electrical level shift units LS2 and the LS4 is not 3.6 volts (1.8～1.8 volts) and 6 volts (6～0 volts), so electrical level shift units LS2 and LS4 can be realized by circuit component that can anti-middle voltage.
Since one can high voltage bearing circuit component size be more than 16 times of size greater than the circuit component of pressing in can be anti-, and compared to traditional level shifter, the level shifter of present embodiment need not use can high voltage bearing circuit component, therefore, in the data driver of the level shifter that uses present embodiment, need not use can high voltage bearing circuit component, thus can reduce the size of data driver, and reduce cost.
The 3rd embodiment
Please refer to Fig. 6, it illustrates the calcspar according to the data driver of third embodiment of the invention.Data driver 600 is in order to drive many data lines of a display panel accordingly according to a plurality of pixel datas, these pixel datas comprise a plurality of first pixel data Dp1～Dpm (positive polarity pixel data) and a plurality of second pixel data Dn1～Dnm (negative polarity pixel data).Data driver 600 comprises one first data processing circuit 610, one second data processing circuit 620 and a multiplexer circuit 640.First data processing circuit 610 comprises a shift register 612, a line buffer 613, a level shifter 614, a digital analog converter 615 and an output buffer 616.First data processing circuit 610 is in order to provide a plurality of positive pixel voltage Vp1～Vpm according to first pixel data Dp1～Dpm.
Second data processing circuit 620 comprises a prime level shifter 621, a shift register 622, a line buffer 623, a back grade level shifter 624, a digital analog converter 625 and an output buffer 626.Now each assembly and the mode of operation to second data processing circuit 620 is described as follows.
Prime level shifter 621 is in order to receive second pixel data Dn1～Dnm sequentially, for example is to receive k data (k＜m) at every turn.The pairing voltage level of these second pixel datas Dn1～Dnm is PL1 between an earth level GND and one first positive level.The voltage level that prime level shifter 621 is adjusted these second pixel datas Dn1～Dnm is between the voltage level between the PL1 between the one first negative level NL1 and first positive level.Prime level shifter 621 is three electrical level shift units LS1～LS3 that comprise among Fig. 5 A, and its mode of operation is not repeat in this.
These second pixel data Dn1～Dnms and the parallel type ground output of shift register 622 in order to receive prime level shifter 621 output sequentially for example is k data of reception (k＜m), and after receiving m data m data being exported together at every turn.Line buffer 723 is in order to second pixel data Dn1～Dnm of temporary shift register 622 outputs.
Level level shifter 624 in back is voltage level between one second negative level NL2 and earth level GND in order to second prime number of adjusting line buffer 623 outputs according to the voltage level of Dn1～Dnm.Back level level shifter 624 is the electrical level shift units LS4 that comprise among Fig. 5 A.Digital analog converter 625 is a plurality of negative pixel voltage Vn1～Vnm in order to these the second pixel datas Dn1～Dnm that changes back level level shifter 624 outputs.Output buffer 626 is in order to temporary negative pixel voltage Vn1～Vnm.Multiplexer circuit 640 is in order to export positive pixel voltage Vp1～Vpm and negative pixel voltage Vn1～Vnm to corresponding data line DL1～DL2m.
In present embodiment, the absolute value of the first negative level NL1 is the absolute value less than the second negative level NL2.Preferably, the absolute value of the first positive level PL1 is the absolute value that is equal to the first negative level NL1 in fact.The first positive level PL1 is a low voltage level, and the first negative level NL1 is a low voltage level, and the second negative level NL2 is middle voltage level.For instance, the first positive level PL1 is essentially 1.8 volts, and the first negative level NL1 is essentially-1.8 volts, and the second negative level NL2 is essentially-6 volts.Similarly be in second embodiment, because prime is not 3.6 volts (1.8～1.8 volts) and 6 volts (6～0 volts) with the best result of the voltage that assembly bore of back level level shifter 621 and 624, therefore, level shifter need not use and can realize by high voltage bearing circuit component.
Compared to second embodiment, present embodiment more can reduce the size of data driver, and is existing that its cause description is as follows.Suppose that second pixel data Dn1～Dnm is 512 data (m=512), and each group electrical level shift units LS1～LS3 can receive 8 data (k=8).In second embodiment, because being parallel type ground, electrical level shift units LS1～LS3 of Fig. 5 A receives these data, so level displacement shifter 121 needs to use 64 (512/8=64) group electrical level shift units LS1～LS3, comes parallel type ground to adjust 512 the second pairing voltage levels of pixel data.
And in present embodiment.Be with one group of electrical level shift units LS1～LS3 as prime level shifter 621, and be arranged at before the shift register.Prime level shifter 621 is to receive 8 data sequentially, adjusts 512 the second pairing voltage levels of pixel data with string type ground.Therefore, be only to use one group of electrical level shift units LS1～LS3 in present embodiment, and can reduce to use the size of the data driver of level shifter widely.
In addition, in present embodiment, the voltage level of second pixel data that prime level shifter 621 is exported is for the voltage level between the first negative level NL1 and earth level GND, so the employed voltage level of circuit component of shift register 622 and line buffer 623 is also between the first negative level NL1 and earth level GND.And in Fig. 6, the employed voltage level of circuit component of shift register 622 and line buffer 623 is between the first positive level PL1 and earth level GND.Among the Yu Shizuo, because the first positive level PL1 and the absolute value of the first negative level NL1 are to be essentially identically, therefore, the data driver of present embodiment is can not increase the power that system consumes.
In the above-mentioned disclosed data driver of first embodiment of the present invention, because the multiplexer circuit must not use can high voltage bearing circuit component, so can reduce the number of high voltage bearing circuit component, come the purpose of the size that reduces data driver with the size that reduces the multiplexer circuit.Moreover, in second embodiment since level shift circuit must not use can high voltage bearing circuit component, so also can reach the circuit component of minimizing high pressure, can reach the purpose that reduces the data driver size with the size that reduces level shift circuit.And the level shifter of third embodiment of the invention can also string type ground be adjusted the level of data, so can more effectively reduce the size of data driver, reduces cost, and also can not increase the consumed power of system.
In sum, though the present invention with some preferred embodiments exposure as above, yet it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when doing various changes that are equal to or replacement.Therefore, protection scope of the present invention is when looking accompanying being as the criterion that the application's claim scope defined.
Claims (21)
1. data driver, in order to drive many data lines of a display panel accordingly according to a plurality of pixel datas, these pixel datas comprise one first pixel data and one second pixel data, this data driver comprises:
One first data processing circuit is in order to provide a positive pixel voltage according to this first pixel data;
One second data processing circuit comprises:
One level shifter, in order to receive this second pixel data, the voltage level of this second pixel data is between an earth level and one first positive level, and be the level between one first negative level and this first positive level in order to the voltage level of adjusting this second pixel data, the voltage level of then adjusting this second pixel data is the level between this first negative level and this earth level, and the voltage level of adjusting this second pixel data afterwards is the level between one second negative level and this earth level;
One digital analog converter is a negative pixel voltage in order to this second pixel data of changing this level shifter output; And
One output buffer is in order to temporary this negative pixel voltage; And
One multiplexer circuit, in order to this positive pixel voltage and this negative pixel voltage are exported to these data lines its two;
Wherein, the absolute value of this first negative level is the absolute value less than this second negative level.
2. data driver according to claim 1 is characterized in that, this level shifter comprises:
One first electrical level shift units, in order to receive this second pixel data, the pairing voltage level of this second pixel data is the voltage level between an earth level and one first positive level;
One second electrical level shift units is the voltage level between one first negative level and this first positive level in order to the voltage level of this second pixel data of adjusting the output of this first electrical level shift units;
One the 3rd electrical level shift units is the voltage level between this first negative level and this earth level in order to the voltage level of this second pixel data of adjusting the output of this second electrical level shift units; And
One the 4th electrical level shift units is the voltage level between one second negative level and this earth level in order to the voltage level of this second pixel data of adjusting the 3rd electrical level shift units output.
3. data driver according to claim 1 is characterized in that, the absolute value of this first positive level is the absolute value that is equal to this first negative level.
4. data driver according to claim 1 is characterized in that, this first positive level is not to be higher than 1.8 volts, and this first negative level is not to be higher than 1.8 volts, and this second negative level is not to be higher than 6 volts.
5. data driver according to claim 1 is characterized in that, this first positive level is 1.8 volts, and this first negative level is-1.8 volts, and this second negative level is-6 volts.
6. data driver according to claim 2, it is characterized in that, this the first and the 3rd electrical level shift units is can realize by the anti-circuit unit that is not higher than 1.8 volts that this second and the 4th electrical level shift units is realizing by the anti-circuit unit that is not higher than 6 volts.
7. data driver according to claim 1 is characterized in that also comprising:
One shift register, in order to receiving these pixel datas sequentially, and these pixel datas of parallel type ground output; And
One line buffer in order to receiving from these pixel datas of this shift register output, and is exported this first pixel data and this second pixel data respectively to this first data processing circuit and this second data processing circuit.
8. data driver according to claim 1 is characterized in that, this multiplexer circuit comprises a plurality of multiplexers unit, and each multiplexer unit comprises:
One first input end and one second input end are respectively in order to receive this positive pixel voltage and this negative pixel voltage;
One output terminal is coupled to one of these data lines;
One first switch, have one first switch, a second switch and one the 3rd switch, this first and this second switch coupled in series between this first input end and this output terminal, and this first and this second switch between a first node by the 3rd switch ground connection optionally; And
One second switch, have one the 4th switch, one the 5th switch and one the 6th switch, the series connection of the 4th and the 5th switch is coupled between this second input end and this output terminal, and the Section Point between the 4th and the 5th switch passes through optionally ground connection of the 6th switch.
9. data driver according to claim 8 is characterized in that, when this first and during this second switch conducting, the 6th switch conduction, when the 4th and the 5th switch conduction, the 3rd switch conduction.
10. data driver according to claim 8, it is characterized in that one of these multiplexer unit this first and this second input end, be coupled to respectively these multiplexer unit another this first and this second input end.
11. data driver according to claim 8, the level that it is characterized in that this positive pixel voltage is between 0 volt and 6 volts, and the level of this negative pixel voltage is between-6 volts and 0 volt.
12. a data driver, in order to drive many data lines of a display panel accordingly according to a plurality of pixel datas, these pixel datas comprise a plurality of first pixel datas and a plurality of second pixel data, and this data driver comprises:
One first data processing circuit is in order to provide a plurality of positive pixel voltage according to these first pixel datas;
One second data processing circuit comprises:
One prime level shifter, in order to receive these second pixel datas sequentially, the pairing voltage level of these second pixel datas is between an earth level and one first positive level, and the voltage level of adjusting these second pixel datas is the voltage level between one first negative level and this earth level;
One shift register is in order to these second pixel datas and the output of parallel type ground that receives this prime level shifter output sequentially;
One line buffer is in order to these second pixel datas of temporary this shift register output;
One back grade level shifter is the voltage level between one second negative level and this earth level in order to the voltage level of these second prime number certificates of adjusting the output of this line buffer;
One digital analog converter is a plurality of negative pixel voltages in order to these second pixel datas of changing this back level level shifter output; And
One output buffer is in order to temporary these negative pixel voltages; And
One multiplexer circuit is in order to export these positive pixel voltage to corresponding these data lines with these negative pixel voltages;
Wherein, the absolute value of this first negative level is the absolute value less than this second negative level.
13. data driver according to claim 12 is characterized in that, the absolute value of this first positive level is the absolute value that is equal to this first negative level.
14. data driver according to claim 12 is characterized in that this prime level shifter comprises:
One first electrical level shift units, in order to receive these second pixel datas sequentially, the pairing voltage level of these second pixel datas is between this earth level and this first positive level;
One second electrical level shift units, in order to the voltage level of these second pixel datas of adjusting the output of this first electrical level shift units between this first negative level and this first positive level; And
One the 3rd electrical level shift units is the voltage level between this first negative level and this earth level in order to the voltage level of these second pixel datas of adjusting the output of this second electrical level shift units.
15. data driver according to claim 14, it is characterized in that, this the first and the 3rd electrical level shift units is can realize by the anti-circuit unit that is not higher than 1.8 volts that this second electrical level shift units and this back level level shifter are realizing by the anti-circuit unit that is not higher than 6 volts.
16. data driver according to claim 12 is characterized in that, this first positive level is not to be higher than 1.8 volts, and this first negative level is not to be higher than 1.8 volts, and this second negative level is not to be higher than 6 volts.
17. data driver according to claim 12 is characterized in that, this first positive level is 1.8 volts, and this first negative level is-1.8 volts, and this second negative level is-6 volts.
18. data driver according to claim 12 is characterized in that, this multiplexer circuit comprises a plurality of multiplexers unit, and each multiplexer unit comprises:
One first input end and one second input end are respectively in order to receive this positive pixel voltage and this negative pixel voltage;
One output terminal is coupled to one of these data lines;
One first switch, have one first switch, a second switch and one the 3rd switch, this first and this second switch coupled in series between this first input end and this output terminal, and this first and this second switch between a first node by the 3rd switch ground connection optionally; And
One second switch, have one the 4th switch, one the 5th switch and one the 6th switch, the series connection of the 4th and the 5th switch is coupled between this second input end and this output terminal, and the Section Point between the 4th and the 5th switch passes through optionally ground connection of the 6th switch.
19. data driver according to claim 18 is characterized in that, when this first and during this second switch conducting, the 6th switch conduction, when the 4th and the 5th switch conduction, the 3rd switch conduction.
20. data driver according to claim 18, it is characterized in that one of these multiplexer unit this first and this second input end, be coupled to respectively these multiplexer unit another this first and this second input end.
21. data driver according to claim 18, the level that it is characterized in that this positive pixel voltage is between 0 volt and 6 volts, and the level of this negative pixel voltage is between-6 volts and 0 volt.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101279168A CN101620830B (en) | 2008-07-02 | 2008-07-02 | Data driver |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101279168A CN101620830B (en) | 2008-07-02 | 2008-07-02 | Data driver |
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| Publication Number | Publication Date |
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| CN101620830A CN101620830A (en) | 2010-01-06 |
| CN101620830B true CN101620830B (en) | 2011-12-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008101279168A Active CN101620830B (en) | 2008-07-02 | 2008-07-02 | Data driver |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102654700A (en) * | 2011-10-25 | 2012-09-05 | 北京京东方光电科技有限公司 | Liquid crystal display panel, liquid crystal display and driving method thereof |
| CN103716032B (en) * | 2013-12-13 | 2016-10-05 | 中国科学院微电子研究所 | A kind of Straight-through high-voltage data transmission interface circuit |
| TWI540559B (en) * | 2015-05-28 | 2016-07-01 | 矽創電子股份有限公司 | Source driving circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003195820A (en) * | 2001-12-21 | 2003-07-09 | Casio Comput Co Ltd | Liquid crystal driving device |
| JP2003295834A (en) * | 2002-03-29 | 2003-10-15 | Matsushita Electric Ind Co Ltd | Method of driving liquid crystal display device and liquid crystal display device |
| CN1648981A (en) * | 2003-12-17 | 2005-08-03 | Lg.菲利浦Lcd株式会社 | Liquid crystal display and driving method thereof |
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2008
- 2008-07-02 CN CN2008101279168A patent/CN101620830B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003195820A (en) * | 2001-12-21 | 2003-07-09 | Casio Comput Co Ltd | Liquid crystal driving device |
| JP2003295834A (en) * | 2002-03-29 | 2003-10-15 | Matsushita Electric Ind Co Ltd | Method of driving liquid crystal display device and liquid crystal display device |
| CN1648981A (en) * | 2003-12-17 | 2005-08-03 | Lg.菲利浦Lcd株式会社 | Liquid crystal display and driving method thereof |
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| CN101620830A (en) | 2010-01-06 |
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