TWI486944B - Data driver - Google Patents

Description

Data driver

This invention relates to a drive and, more particularly, to a data drive.

In the driving method of the liquid crystal display, in order to avoid damaging the physical properties of the liquid crystal molecules, it is necessary to alternately use voltages of different polarities to drive the liquid crystal molecules. In a driving method using a fixed common voltage, the data driver appropriately drives the liquid crystal molecules by converting the polarity of the voltage outputted therefrom.

Conventionally, when a data driver drives liquid crystal molecules, the level of the driving voltage is about -6 volts to 6 volts. At this point, the maximum voltage across the circuit components used in the data driver may be 12 volts (-6 to 6 volts). In order to withstand a voltage of 12 volts during the driving of the liquid crystal display, the data driver must use circuit components that can withstand high voltages. However, the use of data drivers that can withstand high voltage circuit components is problematic in size and cost. Therefore, how to reduce the size of the data driver and reduce the cost is one of the direction of the industry.

The invention relates to a data driver, which is capable of reducing high voltage resistance The use of circuit components can reduce the size and wafer area of the data driver and reduce the cost without increasing the power consumption of the system.

According to a first aspect of the present invention, a data driver is provided for driving a plurality of data lines of a display panel correspondingly according to a plurality of pixel data. The pixel data includes a first pixel data and a second pixel data. The data driver includes a first data processing circuit, a second data processing circuit, and a multiplexer circuit. The first data processing circuit and a second data processing circuit are configured to process the pixel data. The first data processing circuit provides a positive pixel voltage based on the first pixel data, and the second data processing circuit provides a negative pixel voltage based on the second pixel data. The multiplexer circuit includes a plurality of multiplexer units, each of the multiplexer units including a first input end, a second input end, an output end, a first switch, and a second switch. The first input end and the second input end are respectively configured to receive a positive pixel voltage and a negative pixel voltage. The output end is coupled to one of the data lines. The first switch has a first switch, a second switch and a third switch. The first and second open relationships are coupled in series between the first input end and the output end, and one of the first nodes between the first and second switches is selectively grounded via the third switch. The second switch has a fourth switch, a fifth switch and a sixth switch. The fourth and fifth open relationships are coupled in series between the second input end and the output end, and one of the second nodes between the fourth and fifth switches is selectively grounded via the sixth switch. When the first and second switches are turned on, the sixth switch is turned on. When the fourth and fifth switches are turned on, the third switch is turned on.

According to a second aspect of the present invention, a data driver is provided for driving a plurality of data lines of a display panel correspondingly according to a plurality of pixel data. The pixel data includes a first pixel data and a second pixel data. The data driver includes a first data processing circuit, a second data processing circuit, and a multiplexer circuit. The first data processing circuit is configured to provide a positive pixel voltage according to the first pixel data. The second data processing circuit includes a one-bit shifter, a digital analog converter, and an output buffer. The level shifter is configured to receive the second pixel data. The voltage level of the second pixel data is between a ground level and a first positive level, and is used to adjust the voltage level of the second pixel data to be between a first negative level and the first The level between the positive levels is adjusted, and then the voltage level of the second pixel data is adjusted to be between the first negative level and the ground level, and then the voltage level of the second pixel data is adjusted to be The level between a second negative level and the ground level. The output buffer is used to temporarily store the negative pixel voltage. The multiplexer circuit is used to output the normal pixel voltage and the negative pixel voltage to the second of the data lines. The absolute value of the first negative level is less than the absolute value of the second negative level.

According to a third aspect of the present invention, a data driver is provided for driving a plurality of data lines of a display panel correspondingly according to a plurality of pixel data. The pixel data includes a plurality of first pixel data and a plurality of second pixel data. The data driver includes a first data processing circuit, a second data processing circuit, and a multiplexer circuit. The first data processing circuit. The first data processing circuit is configured to provide a plurality of positive pixel voltages based on the first pixel data. The second data processing circuit comprises a pre-level shifter, a shift register, a shift register, a line buffer, a post-level shifter, a digital analog converter and an output buffer. The pre-level shifter is configured to sequentially receive the second pixel data, wherein the voltage level corresponding to the second pixel data is between a ground level and a first positive level, and Adjust these The voltage level of the two pixel data is a voltage level between a first negative level and a ground level. The shift register is configured to sequentially receive the second pixel data output by the front level shifter and output it in parallel. The line buffer is used to temporarily store the second pixel data of the shift register output. The level level shifter is configured to adjust the voltage level of the second element data of the line buffer output to be a voltage level between a second negative level and a ground level. The digital analog converter converts the second pixel data output by the subsequent level shifter into a plurality of negative pixel voltages. The output buffer is used to temporarily store the negative pixel voltages. The multiplexer circuit is configured to output the positive pixel voltage and the negative pixel voltages to the corresponding data lines. The absolute value of the first negative level is less than the absolute value of the second negative level.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100, 400, 640‧‧‧ multiplexer circuits

110, 410, 610‧‧‧ first data processing circuit

120, 420, 620‧‧‧ second data processing circuit

140, 140', 440, 640‧‧‧ multiplexer circuits

141, 142‧‧‧ multiplexer unit

141a~141d‧‧‧Switcher

BD‧‧‧Base voltage switching circuit

111, 121, 121' ‧ ‧ position shifter

112, 122, 625‧‧‧ digital analog converter

113, 123, 626‧‧‧ output buffer

160, 622‧‧‧ shift register

180, 623‧‧ ‧ line buffer

621‧‧‧Pre-level shifter

624‧‧‧After level shifter

LS1~LS4, A~D‧‧‧ level shifting unit

SW1~SW12, SW1', SW2'‧‧‧ switch

IN1‧‧‧First Inverter

IN2‧‧‧Secondary reverser

Figure 1 is a block diagram of a data driver.

2A is a schematic diagram showing two multiplexer units 141 and 142 of the multiplexer circuit 140 in accordance with the first embodiment of the present invention.

FIG. 2B is a schematic diagram showing two multiplexer units of a conventional multiplexer circuit.

FIG. 3 is a diagram showing an example of a circuit diagram of the multiplexer units 141 and 142 of FIG. 2A.

FIG. 4 is a waveform diagram showing an example of a switching signal used by the multiplexer unit of FIG. 3.

Fig. 5A is a block diagram showing a level shifter 121 in accordance with a second embodiment of the present invention.

Figure 5B is a block diagram of a conventional level shifter.

FIG. 6 is a block diagram showing a shift register and a line buffer of a data driver according to a third embodiment of the present invention.

Please refer to FIG. 1 , which is a block diagram of a data driver. The data driver 100 is configured to drive a plurality of data lines DL1 DL DL2m of a display panel correspondingly according to the plurality of pixel data D1 D D2m. The pixel data D1~D2m include the first pixel data Dp1~Dpm and the second pixel data Dn1~Dnm. The data driver 100 includes a first data processing circuit 110, a second data processing circuit 120, and a multiplexer circuit 140. The first and second data processing circuits 110 and 120 are configured to process the pixel data D1 to D2m. The first data processing circuit 110 includes a one-bit shifter 111, a digital analog converter 112, and an output buffer 113. The second data processing circuit 120 includes a one-bit shifter 121, a digital analog converter 122, and an output buffer 123. The first and second data processing circuits 110 and 120 share a shift register 160 and a line buffer 180.

The shift register 160 is configured to sequentially receive the pixel data D1 D D2m and output the pixel data D1 D D2m in parallel. The line buffer 180 is configured to receive the pixel data D1~D2m outputted from the shift register 160, and output the first pixel data Dp1~Dpm (positive pixel data) and the second pixel data Dn1, respectively. ~Dnm (negative pixel data) to level shifters 111 and 121.

The digital analog converters 112 and 122 respectively convert the first and second pixel data Dp1~Dpm and Dn1~Dnm outputted by the level shifters 111 and 121 into positive pixel voltages Vp1 to Vpm and negative pixel voltage Vn1. ~Vnm. The output buffers 113 and 123 are used to temporarily store the normal pixel voltages Vp1 to Vpm and the negative pixel voltages Vn1 to Vnm, respectively. The multiplexer circuit 140 drives the data lines DL1 to DL2m in accordance with the normal pixel voltages Vp1 to Vpm and the negative pixel voltages Vn1 to Vnm. The components included in the first data processing circuit 110 and the second data processing circuit 120 are merely examples, and are not intended to limit the present invention. The data processing circuit capable of converting the first pixel data Dp1~Dpm and the second pixel data Dn1~Dnm into the first pixel data Dp1~Dpm and the second pixel data Dn1~Dnm respectively is within the scope of the present invention. within. Hereinafter, each embodiment will be described with the first pixel data Dp representing one of the first pixel data Dp1 to Dpm, and the second pixel data Dn representing one of the first pixel data Dn1 to Dnm.

In an embodiment of the invention, a high voltage circuit component can be defined, for example, as a circuit component implemented by a 2.5 micron process that can withstand, for example, a voltage of less than 32 volts. A circuit component that can withstand a medium voltage can be defined, for example, as a circuit component implemented by a 0.6 micron process that can withstand, for example, a voltage of less than 6 volts. In the process of designing the data driver 100, the Applicant has found that since the maximum level of the voltage tolerated by the multiplexer circuit 140 and the level shifter 121 of FIG. 1 is 12 volts (-6-6 volts), Therefore, it is necessary to use circuit components that can withstand high voltage.

In one embodiment of the invention, the architecture of the multiplexer circuit 140 is modified to reduce the use of circuit components that are resistant to high voltages. Moreover, in another embodiment of the invention, the architecture of the level shifter 121 is modified to reduce the use of circuit components that are resistant to high voltages. Thereby, in the data driver proposed by the invention, the use of the high voltage resistant circuit component can be reduced, and It is also possible to reduce the size and wafer area of the data driver and reduce the cost without increasing the power consumption of the system. The data drive of the present invention is illustrated in a number of embodiments.

First embodiment

This embodiment is an improved architecture of multiplexer circuit 140 to reduce the use of circuit components that are resistant to high voltages. The multiplexer unit of this embodiment will be described below.

The multiplexer circuit 140 includes m multiplexer units. Referring to FIG. 2A, a schematic diagram of two multiplexer units 141 and 142 of the multiplexer circuit 140 in accordance with the first embodiment of the present invention is shown. The multiplexer unit 141 includes a first input terminal I1, a second input terminal I2, an output terminal O1, a first switcher 141a, and a second switcher 141b. The first input terminal I1 and the second input terminal I2 are respectively configured to receive the positive pixel voltage Vp and the negative pixel voltage Vn. The output terminal O1 is coupled to one of the data lines DL1 DL DL2m, for example, to the data line DL1.

The first switch 141a has a switch SW1, a switch SW2, and a switch SW3. The switches SW1 and SW2 are coupled in series between the first input terminal I1 and the output terminal O1, and one node n1 between the switch SW1 and the switch SW2 is selectively grounded via the switch SW3. The second switch 141b has a switch SW4, a switch SW5 and a switch SW6. The switches SW4 and SW5 are coupled in series between the second input terminal I2 and the output terminal O1, and one node n2 between the switches SW4 and SW5 is selectively grounded via the switch SW6.

When the switches SW1 and SW2 are turned on, the switch SW6 is turned on, so that the node n2 between the switches SW4 and SW5 is coupled to the ground via the switch SW6, so that the maximum voltage across the switch SW4 and the maximum voltage across the switch SW5 are the second input. Half of the maximum voltage difference between I2 and output O1. When the switches SW4 and SW5 are turned on, the switch SW3 is turned on, so that the switches SW1 and SW2 are turned on. The node n1 is coupled to ground via the switch SW3 such that the maximum voltage across the switches SW1 and SW2 is half the maximum voltage difference between the first input terminal I1 and the output terminal O1.

The operation of the multiplexer unit of the present embodiment and the conventional multiplexer unit are compared as follows. Among them, it is assumed that the level of the positive pixel voltage Vp is between 0 volts and 6 volts, and the level of the negative pixel voltage Vn is between -6 volts and 0 volts.

Please refer to FIG. 2B, which shows a schematic diagram of two multiplexer units of a conventional multiplexer circuit. In the conventional multiplexer circuit 140', when the switch SW1' is turned on and the switch SW2' is not turned on, the output terminal O1 outputs the positive pixel voltage Vp. At this time, the voltage across the switch SW2' is the voltage difference between the negative pixel voltage Vn (-6~0 volts) of the input terminal I2 and the positive pixel voltage Vp (0~6 volts) of the output terminal O1. The maximum value of this voltage difference is 12 volts. Therefore, the switch SW2' used at this time must be a switch that can withstand 12 volts. Similarly, when the output terminal O1 outputs the negative pixel voltage Vn, the switch SW1' will also withstand a voltage across a maximum of 12 volts. Therefore, in the conventional multiplexer circuit 140', both of the switches SW1' and SW2' need to be implemented using high voltage resistant circuit components.

Please refer to Figure 2A above. However, in the multiplexer circuit 140 of the present embodiment, when the switches SW1 and SW2 are turned on and the switches SW4 and SW5 are not turned on, the output terminal O1 outputs the positive pixel voltage Vp. At this time, the switch SW6 will be turned on, so that the node n2 is grounded. At this time, the maximum voltage across the switch SW4 and the switch SW5 is half of the maximum voltage difference between the second input terminal I2 and the output terminal O1, that is, the positive pixel. The maximum voltage difference between voltage Vp (0~6 volts) and negative pixel voltage Vn (-6~0 volts) is half of 12 volts. At this time, the maximum voltage across the switches SW4 and SW5 is 6 volts. Similarly, when the switches SW1 and SW2 are not turned on and the switches SW4 and SW5 are turned on, the output terminal O1 outputs a negative pixel voltage Vn. At this time, the switch SW3 will be turned on, so that the switches SW1 and SW2 The maximum crossover voltage is 6 volts. Therefore, the switches SW1, SW2, SW3, and SW4 can be realized by circuit elements that can withstand medium voltage.

Since the circuit component size is related to the aspect ratio (L/W), it can be inferred that the size of a circuit element capable of withstanding high voltage is more than sixteen times larger than the size of a circuit component capable of withstanding medium voltage. Therefore, in the multiplexer unit 141, two intermediate voltage-resistant switches SW1 and SW2 are used instead of one of the conventional multiplexer units 141' which can withstand high voltage, and the switch SW3 is used. To provide the voltage of the ground. Overall, the total area of the switches SW1, SW2, and SW3 is still smaller than the area of the switch SW1'. Therefore, since the multiplexer circuit of the present embodiment does not require the use of circuit components that can withstand high voltage, the size of the data driver using the multiplexer unit can be reduced.

In FIG. 2A, the architecture of the multiplexer unit 142 is similar to that of the multiplexer unit 141, and therefore will not be repeated here. The first and second input ends of the multiplexer unit 142 are respectively coupled to the first and second input terminals I1 and I2 of the multiplexer unit 141, as shown in FIG. 2A. The operation mode between the multiplexer units 141 and 142 is such that when the output terminal O1 outputs the positive pixel voltage Vp, the output terminal O2 outputs the negative pixel voltage Vn. When the output terminal O1 outputs the negative pixel voltage Vn, the output terminal O2 outputs the positive pixel voltage Vp.

Referring to FIG. 3, an example of a circuit diagram of the multiplexer units 141 and 142 of FIG. 2A is shown. In this example, the switches SW1, SW2, SW4, and SW5 are transmission gates (TGs) and are implemented by a medium voltage-resistant transistor. Furthermore, the switches SW7, SW8, SW10, and SW11 may also be transmission gates and implemented by a transistor that is resistant to medium voltage. Each of the transfer gates includes a P-type MOS transistor and an N-type MOS transistor. The switch SW1, the switch SW2, the switch SW4 and the switch SW5 respectively comprise one PMOS coupled in parallel. A transistor and an NMOS transistor. The switches SW3 and SW6 are transistors. Furthermore, the switches SW9 and SW12 can also be realized by a transistor. Please also refer to FIG. 4, which is a waveform diagram showing an example of a switching signal used by the multiplexer unit of FIG. In this example, the switching signal includes a plurality of control signals S1 to S8, wherein the control signals S1B to S8B are respectively inverted signals of the control signals S1 to S8.

In addition, the multiplexer circuit 140 further includes a base voltage switching circuit BD for providing a negative base voltage of each of the N-type MOS transistors according to the switching signal S4, and providing a positive base voltage of each of the P-type MOS transistors. . As shown in FIG. 3, the substrate voltage switching circuit BD includes a first inverter IN1 and a second inverter IN2. The first inverter IN1 is coupled between a positive voltage (for example, 6 volts) and a ground voltage (for example, 0 volts) for providing a first substrate voltage according to the switching signal S4. The second inverter IN2 is coupled between a negative voltage (-6 volts) and a ground voltage for providing a second substrate voltage according to the switching signal S4. The substrate voltage switching circuit BD can respectively supply the first substrate voltage and the second substrate voltage to the switch SW2 of the first switch 141a and the switch SW5 of the second switch 141b. Further, the substrate voltage switching circuit BD can provide a first substrate voltage to the base of the PMOS transistor of the switch SW2 and the base of the PMOS transistor of the switch SW5, and provide the second substrate voltage to the base and switch of the NMOS transistor of the switch SW2. The base of the NMOS transistor of SW5. Please also refer to Figure 4. The switch SW2 and the switch SW5 are also controlled by the switching signal S3. As shown in FIG. 3, the switch SW2 and the switch SW5 are controlled by the switching signal S3, and the switching signal S3 is coupled to a gate of the NMOS transistor of the switch SW2 and a gate of the PMOS transistor of the switch SW5. Switching between switching signal S4 to a positive level and a negative level During the time period, the switching signal S3 is converted to a ground level. In addition, when the switching signal S4 is respectively at the negative level and the positive level, the switching signal S3 is respectively at the positive level and the negative level. Thus, in the period tm of FIG. 4, the control signals S3 and S7 are preferably converted to a ground voltage. This avoids the forward body bias when the transfer gate is turned on or off, and enables the P-type MOS transistor and the N-type MOS transistor to operate correctly.

The detailed circuit diagrams and the timing diagrams of the various signals shown in Figures 3 and 4 are examples of multiplexer circuits in which the present invention can be implemented, and are not intended to limit the present invention. Therefore, those having ordinary knowledge can modify the technical content disclosed herein, and can achieve the purpose of implementing the multiplexer circuit proposed in the embodiment.

In the present embodiment, since the multiplexer circuit used by the data driver does not need to use a circuit component that can withstand high voltage, the size of the data driver can be reduced and the cost can be reduced.

Second embodiment

This embodiment improves the architecture of the level shifter 121 of Figure 1 to reduce the use of circuit components that are resistant to high voltages. The level shifter of this embodiment will be described below.

Please refer to FIG. 1 and FIG. 5A simultaneously, and FIG. 5A is a block diagram of the level shifter 121 according to the second embodiment of the present invention. The level shifter 121 includes a plurality of level shifting units, for example, four level shifting units LS1 to LS4. The level shifting unit LS1 is configured to receive the second pixel data Dn, and the voltage level corresponding to the second pixel data Dn is a voltage level between a ground level GND and a first positive level PL1. . The level shifting unit LS2 is configured to adjust the voltage level of the second pixel data Dn output by the level shifting unit LS1 to be between a first negative level NL1 and The voltage level between a positive level PL1. The level shifting unit LS3 is configured to adjust the voltage level of the second pixel data Dn output by the level shifting unit LS2 to be a voltage level between the first negative level NL1 and the ground level GND. The level shifting unit LS4 is configured to adjust the voltage level of the second pixel data Dn output by the level shifting unit LS3 to be a voltage level between a second negative level NL2 and a ground level GND. Then, the digital analog converter 122 of FIG. 1 converts the second pixel data Dn outputted by the conversion level shifting unit NL4 to a negative pixel voltage Vn.

In this embodiment, the absolute value of the first negative level NL1 is less than the absolute value of the second negative level NL2. Preferably, the absolute value of the first positive level PL1 is substantially equal to the absolute value of the first negative level NL1. The first positive level PL1 is a low voltage level, the first negative level NL1 is a low voltage level, and the second negative level NL2 is a medium voltage level. For example, the first positive level PL1 is substantially 1.8 volts, the first negative level NL1 is substantially -1.8 volts, and the second negative level NL2 is substantially -6 volts.

By using the level shifter 121 proposed in the embodiment, the size of the data driver can be reduced, and the reason will be explained as follows.

Please refer to FIG. 5B, which is a block diagram of a conventional level shifter. Since the data driver using the conventional level shifter 121' requires a high voltage resistant circuit component, the data driver has a large size. The conventional level shifter 121' includes four level shifting units A to D. In the level shifting unit C, the second pixel data Dn output by the level shifting unit B is between -6 volts and 6 volts. That is to say, the difference between the voltage level to be withstood by the level shifting unit C is 12 volts, which has exceeded the range of the medium voltage (6 volts), so the level shifting unit C needs to use a circuit capable of withstanding high voltage. element.

Please refer to Figure 5A above. In the level shifter 121 of the embodiment, The components of the four level shifting units LS1 to LS4 used do not exceed 6 volts across the voltage, so that high voltage resistant circuit components are not required. That is, since the components in the level shifting units LS1 and LS3 are subjected to a maximum voltage of 1.8 volts, the level shifting units LS1 and LS3 can be realized by circuit components resistant to low voltage. Since the components in the level shifting units LS2 and LS4 are subjected to a maximum voltage of 3.6 volts (-1.8 to 1.8 volts) and 6 volts (-6 to 0 volts), respectively, the level shifting units LS2 and LS4 are used. It can be realized by circuit components that can withstand medium voltage.

Since the size of a circuit element capable of withstanding high voltage is more than sixteen times larger than the size of the circuit element capable of withstanding medium voltage, the level shifter of this embodiment does not need to be compared with the conventional level shifter. Since the circuit element capable of withstanding high voltage is used, in the data driver using the level shifter of the present embodiment, the circuit element capable of withstanding high voltage is not required, so that the size of the data driver can be reduced and the cost can be reduced.

Third embodiment

Please refer to FIG. 6, which is a block diagram of a data driver in accordance with a third embodiment of the present invention. The data driver 600 is configured to drive a plurality of data lines of a display panel correspondingly according to the plurality of pixel data, wherein the pixel data includes a plurality of first pixel data Dp1~Dpm (positive pixel data) and a plurality of Two pixel data Dn1 ~ Dnm (negative pixel data). The data driver 600 includes a first data processing circuit 610, a second data processing circuit 620, and a multiplexer circuit 640. The first data processing circuit 610 includes a shift register 612, a line buffer 613, a one-bit shifter 614, a digital analog converter 615, and an output buffer 616. The first data processing circuit 610 is configured to provide a plurality of positive pixel voltages Vp1 VVpm according to the first pixel data Dp1 DDpm.

The second data processing circuit 620 includes a pre-level shifter 621, a shift register 622, a line buffer 623, a post-level shifter 624, a digital analog converter 625, and an output buffer. 626. The components and operation of the second data processing circuit 620 are described below.

The pre-level shifter 621 is configured to sequentially receive the second pixel data Dn1~Dnm, for example, each time receiving k-gram data (k<m). The voltage level corresponding to the second pixel data Dn1~Dnm is between a ground level GND and a first positive level PL1. The pre-level shifter 621 adjusts the voltage level of the second pixel data Dn1~Dnm to a voltage level between a first negative level NL1 and a ground level GND. The pre-level shifter 621 includes three level shifting units LS1 LS LS3 in FIG. 5A, and the operation mode thereof is not described again.

The shift register 622 is configured to sequentially receive the second pixel data Dn1~Dnm outputted by the pre-level shifter 621 and output them in parallel, for example, receiving k-gram data each time (k<m) And after receiving the m pen data, the m pen data is output together. The line buffer 723 is used to temporarily store the second pixel data Dn1~Dnm outputted by the shift register 622.

The post level shifter 624 is configured to adjust the voltage level of the second prime data Dn1~Dnm outputted by the line buffer 623 to be a voltage level between a second negative level NL2 and a ground level GND. The post level shifter 624 includes the level shifting unit LS4 in FIG. 5A. The digital analog converter 625 is configured to convert the second pixel data Dn1 DDnm outputted by the subsequent level shifter 624 into a plurality of negative pixel voltages Vn1 VVnm. The output buffer 626 is used to temporarily store the negative pixel voltages Vn1 VVnm. The multiplexer circuit 640 is configured to output the front pixel voltages Vp1 to Vpm and the negative pixel voltages Vn1 to Vnm to the corresponding data lines DL1 to DL2m.

In this embodiment, the absolute value of the first negative level NL1 is less than the second negative position. The absolute value of quasi-NL2. Preferably, the absolute value of the first positive level PL1 is substantially equal to the absolute value of the first negative level NL1. The first positive level PL1 is a low voltage level, the first negative level NL1 is a low voltage level, and the second negative level NL2 is a medium voltage level. For example, the first positive level PL1 is substantially 1.8 volts, the first negative level NL1 is substantially -1.8 volts, and the second negative level NL2 is substantially -6 volts. Similar to the second embodiment, since the components of the pre-stage and post-level shifters 621 and 624 are subjected to voltages of up to 3.6 volts (-1.8 to 1.8 volts) and 6 volts (-6 to 0), respectively. Volts) Therefore, the level shifter does not need to be implemented with high voltage resistant circuit components.

Compared with the second embodiment, the embodiment can reduce the size of the data driver more, and the reason is explained as follows. Assume that the second pixel data Dn1~Dnm is 512 pieces of data (m=512), and each group of level shifting units LS1~LS3 can receive 8 pieces of data (k=8). In the second embodiment, since the level shifting units LS1 to LS3 of FIG. 5A receive the data side by side, the level shifter 121 needs to use 64 (512/8=64) group level shifts. Units LS1~LS3 adjust the voltage level corresponding to 512 second pixel data in parallel.

In the present embodiment. A set of level shifting units LS1 LS LS3 is used as the pre-level shifter 621 and is placed before the shift register. The pre-level shifter 621 sequentially receives eight pieces of data to adjust the voltage level corresponding to the 512 second pixel data in a serial manner. Therefore, in this embodiment, only one set of level shifting units LS1 to LS3 is required, and the size of the data driver using the level shifter can be greatly reduced.

In addition, in this embodiment, the voltage level of the second pixel data output by the pre-level level shifter 621 is a voltage level between the first negative level NL1 and the ground level GND, so The voltage level used by the circuit components of the shift register 622 and the line buffer 623 is also Between the first negative level NL1 and the ground level GND. In FIG. 6, the voltage level used by the circuit components of the shift register 622 and the line buffer 623 is between the first positive level PL1 and the ground level GND. In practice, since the absolute values of the first positive level PL1 and the first negative level NL1 are substantially the same, the data driver of the present embodiment does not increase the power consumed by the system.

In the data driver disclosed in the first embodiment of the present invention, since the multiplexer circuit does not need to use a circuit component capable of withstanding high voltage, the number of circuit components resistant to high voltage can be reduced to reduce the multiplexer circuit. Size comes to the purpose of reducing the size of the data drive. Furthermore, in the second embodiment, since the level shifting circuit does not need to use a circuit element capable of withstanding high voltage, the circuit component for reducing the high voltage can be reduced to reduce the size of the level shifting circuit and can be reduced. The purpose of the small data drive size. Moreover, the level shifter of the third embodiment of the present invention can also adjust the level of the data in series, so that the size of the data driver can be more effectively reduced, the cost is reduced, and the power consumption of the system is not increased. .

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

141‧‧‧Multiplexer unit

141a, 141b‧‧‧Switch

SW1~SW6‧‧‧ switch

Claims (20)

A data driver for driving a plurality of data lines of a display panel correspondingly according to a plurality of pixel data, the pixel data comprising a first pixel data and a second pixel data, the data driver comprising: The first data processing circuit and the second data processing circuit are configured to process the pixel data, the first data processing circuit provides a positive pixel voltage according to the first pixel data, and the second data processing circuit is configured according to the The second pixel data provides a negative pixel voltage; and a multiplexer circuit includes a plurality of multiplexer units, each of the plurality of multiplexer units including: a first input end and a second input end, respectively Receiving the positive pixel voltage and the negative pixel voltage; an output end coupled to one of the data lines; a first switch having a first switch, a second switch, and a third switch, The first and the second open relationship are coupled in series between the first input end and the output end, and the voltage level of the first node between the first and the second switch is controlled by the a third switch; a second switch a fourth switch, a fifth switch, and a sixth switch, wherein the fourth and the fifth open relationship are coupled in series between the second input end and the output end, and the fourth and the fifth switch a voltage level of the second node is controlled by the sixth switch; and a base voltage switching circuit for respectively providing a first substrate voltage and a second substrate voltage according to a first switching signal a first switch and the second switch; The first substrate voltage is simultaneously applied to the first switch and the second switch, and the second substrate voltage is simultaneously applied to the first switch and the second switch. The data driver of claim 1, wherein the sixth switch is turned on when the first switch and the second switch are turned on, and the third switch is turned on when the fourth switch and the fifth switch are turned on. Turn on. The data driver of claim 1, wherein the substrate voltage switching circuit respectively supplies the first substrate voltage and the second substrate voltage to the second switch and the second switch of the first switch The fifth switch. The data driver of claim 3, wherein the second switch and the fifth open relationship are controlled by a second switching signal, and the first switching signal is switched to a positive level and a negative position. The second switching signal is converted to a ground level during a transition period between the standards. The data driver of claim 4, wherein when the first switching signal is respectively at the negative level and the positive level, the second switching signal is respectively at the positive level and the negative position. quasi. The data driver of claim 1, wherein the first substrate voltage is varied between a 0 volt level and a positive level according to the first switching signal, and the second substrate voltage is based on The first switching signal varies between the 0 volt level and a negative level. The data driver of claim 6, wherein when the second substrate voltage is at the 0 volt level, the first substrate voltage is at the positive level, and when the second substrate voltage is at the negative At the level of time, the first substrate voltage is at the 0 volt level. For example, the data driver described in claim 1 of the patent scope, The first and the second input of the one of the plurality of multiplexer units are respectively coupled to the first and second input ends of the multiplexer unit. The data driver of claim 1, wherein the first switch, the second switch, the fourth switch, and the fifth switch are a transmission gate (TG). The data driver of claim 9, wherein the transmission gate is implemented by a medium voltage resistant transistor. The data driver of claim 9, wherein the first switch, the second switch, the fourth switch, and the fifth switch respectively comprise a PMOS transistor and an NMOS transistor coupled in parallel. The data driver of claim 11, wherein the substrate voltage switching circuit provides the first substrate voltage to one of the PMOS transistors of the second switch and one of the PMOS transistors of the fifth switch a substrate, and providing the second substrate voltage to a substrate of the NMOS transistor of the second switch and a substrate of the NMOS transistor of the fifth switch. The data driver of claim 12, wherein the second switch and the fifth open relationship are controlled by a second switching signal, and the second switching signal is coupled to the NMOS of the second switch a gate of the transistor and a gate of the PMOS transistor of the fifth switch. The data driver of claim 13, wherein the second switching signal is converted to a grounding position when the first switching signal is switched to a transition period between a positive level and a negative level. quasi. The data driver of claim 1, wherein the third switch and the sixth open relationship are respectively implemented by a transistor. For example, the data driver described in claim 1 of the patent scope, wherein the painting is The level of the prime voltage is between 0 volts and a medium voltage level, and the level of the negative pixel voltage is between a negative medium voltage level and 0 volts. The data driver of claim 16, wherein the first substrate voltage varies between a 0 volt level and the medium and medium voltage level according to the first switching signal, and the second substrate voltage is based on The first switching signal varies between a 0 volt level and the negative medium voltage level. The data driver of claim 1, wherein the substrate voltage switching circuit comprises: a first inverter coupled between a positive voltage and a ground voltage for providing the first switching signal a first substrate voltage; and a second inverter coupled between a negative voltage and the ground voltage for providing the second substrate voltage according to the first switching signal. The data driver of claim 1, wherein the voltage level of the first node between the first and the second switch is selectively grounded through the third switch, and the fourth The voltage level of the second node between the fifth switches is selectively grounded through the sixth switch. A data driver for driving a plurality of data lines of a display panel correspondingly according to a plurality of pixel data, the pixel data comprising a first pixel data and a second pixel data, the data driver comprising: The first data processing circuit and the second data processing circuit are configured to process the pixel data, the first data processing circuit provides a positive pixel voltage according to the first pixel data, and the second data processing circuit is configured according to the The second pixel data provides a negative pixel voltage; and a multiplexer circuit comprising a plurality of multiplexer units, each of the plurality of multiplexer units comprising: a first input end and a second input end respectively for receiving the positive pixel voltage and the negative pixel voltage; an output end coupled to one of the data lines; a first switch having a a first switch, a second switch, and a third switch, wherein the first and the second open relationship are coupled in series between the first input end and the output end, and between the first switch and the second switch a voltage level of the first node is controlled by the third switch; a second switch has a fourth switch, a fifth switch and a sixth switch, the fourth and the fifth open relationship a series connection between the second input end and the output end, and a voltage level of the second node between the fourth and the fifth switch is controlled by the sixth switch, wherein the second The switch and the fifth switch respectively comprise a PMOS transistor and an NMOS transistor coupled in parallel; and a substrate voltage switching circuit, comprising: a first inverter coupled between a positive voltage and a ground voltage, a PMOS transistor for providing a first substrate voltage to the second switch and the P of the fifth switch a MOS transistor; and a second inverter coupled between a negative voltage and the ground voltage to provide the second substrate voltage to the NMOS transistor of the second switch and the NMOS of the fifth switch Transistor.