CN1912793A - High temp stability reference voltage source corrected by 1V power supply non-linear technology - Google Patents

Abstract

The invention belongs to the technical field of integrated circuit reference voltage sources, and is characterized in that the reference voltage source uses nonlinear correction technology to offset the logarithmic term in the temperature coefficient of the output current, so that the output reference voltage source has high temperature stability , Moreover, a level shift circuit is used to replace the traditional voltage divider resistor, which reduces the area and the temperature influence brought by the resistor. In addition, the value of the parallel internal resistance at the output terminal is changed, so that the output voltage value of the reference voltage source can be guaranteed. Under the condition of high temperature stability, a wide range of changes is realized. At the same time, the startup and bias circuit are also designed to enable the designed circuit to start correctly. The invention can be used in mobile equipment circuit systems with low supply voltage.

Description

High temperature stable reference voltage source with 1V power supply nonlinearity correction

technical field

The invention relates to the technical field of the power supply of an integrated circuit, especially the temperature stability of a reference voltage source.

Background technique

Voltage reference sources are widely used in many analog circuits and digital-analog hybrid circuits, such as: A\D, D\A converters, memories, etc. With the continuous reduction of process feature size, considering the reliability of the device, the power supply voltage allowed for circuit work must also be gradually reduced; at the same time, due to the gradual increase in transistor integration, the power consumption of the circuit must also be limited. Therefore, under the conditions of low voltage, low power consumption and increasingly harsh working environment, the requirements of the circuit system for the voltage reference source module are becoming more and more stringent.

For the traditional bandgap reference source circuit, there are two obvious factors restricting the realization of the circuit under the power supply voltage of 1V. One is that the output of the bandgap reference is about 1.2V, which is outside the range of the supply voltage; the other is that the input common-mode range of the operational amplifier (OPA) used in the reference circuit is limited. These two constraints can be solved by current mode and resistor divider respectively. Some reference source circuits with 1V power supply voltage have been reported, but these reference source circuits use Bipolar or BiCMOS technology, and the cost is relatively high, such as: P.Malcovati, F.Maloberti, et al. "Curvature compensated BiCMOS bandgap with 1-V supply voltage,” IEEE Journal of Solid-State Circuits, vol.37, pp.526-529, April 2002. Other reported CMOS reference source circuits have high temperature stability characteristics, but for those with temperature dependence The logarithmic term, they are only the first order, second order, or the corresponding curve correction, but not all offset the logarithmic term, such as: Hironori Banba, Hitoshi Shiga, et al. "A CMOS Bandgap Reference Circuit with Sub-1-v Operation," IEEE Journal of Solid-State Circuits, vol.34, no.5, May 1999. In the present invention, we propose a non-linear correction CMOS reference voltage source with a power supply voltage of 1V, trying to High temperature stability is obtained by essentially canceling out the logarithmic term with respect to temperature. The implementation of the circuit does not use resistor divider, but uses a level shift method, which can minimize the area and the temperature impact caused by the resistor.

Contents of the invention

The object of the present invention is to provide a reference voltage source with high temperature stability for nonlinear correction of 1V power supply by fully canceling the logarithmic term with respect to temperature.

The present invention is characterized in that:

The first operational amplifier (OPA1), the output terminal is connected to the grid of MOS transistors (M0) and (M1) at the same time, and the source electrodes of the (M0) transistor and (M1) transistor are connected to the power supply VDD at the same time; the first operational amplifier The positive input of the operational amplifier ₍ OPA1) is the node (V _p ), which is connected to the drain of the transistor (M0) and connected to the PNP transistor (Q ₀ ) through a resistor (R0) In the emitter stage, the remaining two ends of the (Q ₀ ) tube are grounded; the negative input terminal of the first operational amplifier (OPA1) is the node (Vn), which is connected to the drain of the (M1) tube _{At the same time, it is also connected to the emitter of the PNP transistor (Q 1 )} . (V _P ) and node (Vn) are equal in voltage;

The second operational amplifier (OPA2), the output terminal is connected to the gate of the MOS tube (M4), and the source of the (M4) tube is connected to the power supply VDD; the negative input terminal of the second operational amplifier (OPA2) is connected to the node ( Vn), the positive input terminal of the second operational amplifier (OPA2) is also grounded through a resistor (R1) while receiving the drain of the (M4) tube;

The third operational amplifier (OPA3), the output terminal is connected to the gate of the MOS tube (M7), and the drain of the (M7) tube is fed back to the positive input terminal of the third operational amplifier (OPA3), and the third operational amplifier (OPA3) The positive input terminal of the resistor (R2) is grounded, while the negative input terminal is connected to the emitter of the PNP transistor (Q ₂ ), and the other two ends of the transistor (Q ₂ ) are grounded;

MOS tubes (M5), (M2), the sources of the two are connected to the power supply VDD, and the drains are connected to the negative input terminal of the third operational amplifier (OPA3) after being connected, and the gate of the (M5) tube is connected to the said third operational amplifier (OPA3). The output terminal of the 2nd operational amplifier (OPA2), and the gate of the (M2) tube is then connected to the output terminal of the 1st operational amplifier (OPA1);

MOS tubes (M8), (M9), the source of the (M8) tube is connected to the power supply VDD, and the drain is connected to the drain and gate of the (M9) tube at the same time, and the source of the (M9) tube is grounded;

MOS tubes (M6), (M10), the source of the (M6) tube is connected to the power supply VDD, and the gate is connected to the output of the second operational amplifier (OPA2), while the drain of the (M6) tube is connected to The drain of the (M10) tube forms the output terminal Vbg of the reference voltage source, and the grid of the (M10) tube is connected to the grid of the (M9) tube, but the source of the (M10) tube is grounded;

MOS tube (M3), the source is connected to the power supply VDD, the gate is connected to the output terminal of the first operational amplifier (OPA1), and the drain of the (M3) is connected in series between the output terminal Vbg and ground midpoint of resistors (R3) and (R4);

The (R ₀ )=8kΩ～12kΩ;

(R ₁ ) is derived from the temperature under the condition that the current passing through (Q ₂ ) basically does not change with the temperature T,

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}}<span\; class="notranslate">\; )</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; no</span>}}$

Among them, V _g0 is the extrapolated pn junction diode voltage at 0K, V _be (T _r ) is the voltage between the base and emitter at the temperature T _r , x is the temperature-dependent parameter of the current flowing through the transistor, η It is a parameter that has nothing to do with temperature but is related to the process, and its value is between 3.6 and 4. V _T =kT/q is the thermal voltage, k is the Boltzmann constant (1.38×10 ^-23 J/K), and q is the electronic charge (1.6×10 ^-19 C), T is the absolute temperature, n is the ratio of the emitter areas of the transistors (Q ₀ ) and (Q ₁ );

(R ₂ ) is obtained under the condition that the logarithmic term of the temperature in the output current _Ibg of the reference voltage source is zero,

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&eta;</span>}}{\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="A20061011259700101.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}$

(R3), (R4) are obtained according to the required linear compensation relationship and the required output reference voltage,

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; bg</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}$

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; bg</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}}\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}$

The advantages of the present invention are:

1. In the present invention, the non-linear correction technology is adopted to offset the temperature non-linear term in V _be , and the obtained reference voltage source has very high temperature stability.

2. The resistance values of R ₃ and R ₄ in the core circuit can be changed according to actual needs, and the output voltage of the reference source can be varied in a wide range, and both have high temperature stability and good adjustability.

3. The invented reference voltage source circuit can be realized by standard CMOS technology, and the level shift circuit is integrated in the operational amplifier, which replaces the traditional voltage divider resistor and saves the area.

4. The starting circuit is practical and effective, and easy to control, which ensures that the core circuit can be started correctly after power-on.

5. The designed bandgap reference source can be used in the circuit system of mobile equipment with low power supply voltage.

Description of drawings

Figure 1. Circuit diagram of a reference voltage source for nonlinear correction;

The circuit diagram of the operational amplifier that Fig. 2. the present invention adopts;

Fig. 3. the start-up and bias circuit schematic diagram that the present invention adopts;

Figure 4. The temperature characteristic curve of the reference voltage source under 1V power supply;

Figure 5. The characteristic curve of the output voltage of the reference voltage source as a function of the power supply voltage.

Detailed ways

For a forward-working bipolar transistor, the voltage V _be between its base and emitter does not change linearly with temperature, and its relationship with temperature can be expressed as:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Among them, V _g0 is the extrapolated pn junction diode voltage at 0K, T is the absolute temperature, V _be (T _r ) is the voltage between the base and emitter at the temperature T _r , x is the current flowing through the transistor Temperature-dependent parameters, η is a temperature-independent, but process-related parameter, the value is between 3.6 and 4, V _T =kT/q is the thermal voltage, k is the Boltzmann constant (1.38×10 ^-23 J/K) , q is the electronic charge (1.6×10 ^-19 C). A common method of temperature compensation is to carry out Taylor expansion on (1) at the temperature _Tr , so the first-order, second-order and higher-order correlation coefficients about temperature can be obtained. Thus, a corresponding inverse temperature dependence can be employed for cancellation. However, our goal is to cancel out the nonlinear term as a whole without Taylor expansion, that is, almost completely cancel out the temperature-dependent logarithmic term in _Vbe .

Figure 1 is the core circuit structure of the reference voltage source using nonlinear correction technology, including 3 OPAs, matching current mirrors, resistors and some vertical PNP transistors (parasitic devices available in CMOS standard processes).

The collector current of a bipolar transistor can be approximated as:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}{\mathrm{<span\; class="notranslate">\; e</span>}}^{\frac{\mathrm{<span\; class="notranslate">\; q</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}}}{\mathrm{<span\; class="notranslate">\; kT</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Among them, I _c is the current flowing through the transistor, I _s is the reverse saturation bias current, then the voltage between the base and the emitter can be obtained from the formula (2):

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

It can be seen from Fig. 1 that due to the feedback effect of the operational amplifier OPA1 and MOS transistors M0 and M1, the voltages at the nodes _Vp and _Vn will be equal. Therefore, using formula (3), we can get a current proportional to temperature (PTAT) as shown in the following formula:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; PTAT</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; no</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

In the above formula, n is the ratio of the emitter areas of transistors Q0 and Q1. Similarly, it can be seen that there are two other feedback loops in Figure 1: one is composed of OPA2, M4 and R1; the other is composed of OPA3, M7 and R2. Then we can get two current expressions with negative temperature coefficient (CTAT) as:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; CTAT</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; CTAT</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

Substituting equation (1) into equations (5) and (6) respectively, then the CTAT current can be transformed into:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; CTAT</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; CTAT</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

In FIG. 1 , the PTAT current flows through the transistor Q1 , so it can be seen that x ₁ =1; meanwhile, the current of the transistor Q2 is the sum of the PTAT current flowing through M2 and the CTAT current flowing through M5 . According to equations (4) and (5), we can get:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; Q</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; PTAT</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="I\; CTAT"\; filenames="A20061011259700101.png"\; state="\{\{state\}\}">I</figure-callout></span><figure-callout\; id="1"\; label="I\; CTAT"\; filenames="A20061011259700101.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; no</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9</span>}<span\; class="notranslate">\; )</span>$

This means that if the resistors R ₀ and R ₁ are chosen properly, the current flowing through Q2 can achieve first-order compensation with respect to temperature, that is, x ₂ ≈0. Therefore, according to equations (7) and (8), the current I _CTAT1 flowing through M6 is subtracted from the current I _CTAT2 flowing through M10, resulting in:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; CTAT</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; CTAT</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; \&eta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 10</span>}<span\; class="notranslate">\; )</span>$

In equation (10), the first term is a constant, the second term is a linear term with respect to temperature, and the last term is a logarithmic term with respect to temperature. Since η is a value that has nothing to do with temperature, the logarithmic term can be completely eliminated by choosing the appropriate ratio of resistors R ₁ and R ₂ . However, even though the logarithmic term in (10) has been eliminated, the linear term with respect to temperature may still exist. Then we need an additional PTAT current to compensate, and the current I _PTAT flowing through the transistor M3 in Figure 1 solves this problem. We can get the related expression and output reference voltage as:

$<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; no</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; bg</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; )</span>$

It can be seen from equations (11) and (12) that by adjusting the values of resistors _R3 and _R4 , we can obtain a wide range of reference voltages with high temperature stability.

Since the operational amplifier used in the reference voltage source circuit operates at a power supply voltage of 1V, we have adopted a two-pole folded structure as shown in Figure 2.

At room temperature _Tr , the voltages between the base and emitters of bipolar transistors Q1 and Q2 are approximately equal, approximately:

V _be1 (V _T )≈V _be2 (V _T )≈0.65V (13)

It can be seen from formula (13) that the input common-mode level of the OPA is about 0.65V when the reference voltage source is stable. We use a level shift circuit to reduce the input common-mode level of the op amp. The level shift circuit is composed of M1-M4 tubes, which are used to replace the voltage divider resistors. Under stable working conditions, M7-M9 will work in the saturation area, while M5 and M6 are cut-off. In the startup stage of the circuit, even though M1, M3, M7 and M8 are in the cut-off state, but M5, M6 and M10 are working in the saturation region, which can provide almost stable gain to ensure that the circuit can start quickly, that is, no matter what At this time, at least one pair of differential pairs M5 and M6, M7 and M8 is working.

When powering up the bandgap reference source, in order to make the circuit work normally, a corresponding start-up and bias circuit is required, and its topology is shown in Figure 3. En is the control enabling signal, and vbiasp and vbiasn are output bias voltages, which are provided to the operational amplifier shown in Figure 2. The working process of the circuit in Figure 3 is as follows: when En is low level, vbiasp and vbiasn are VDD and VSS respectively, OPA will not work, so the entire bandgap reference source is disabled; when En becomes high level, M2- M4 will work in the saturation region, providing appropriate vbiasp and vbiasn to OPA to start the reference source circuit.

The temperature characteristics of the output voltage of the reference voltage source are shown in Figure 4. When the temperature changes between 15°C and 100°C, the output voltage has only a 0.5mV deviation, and the temperature coefficient is about 16.7ppm/°C. What Fig. 5 shows is at room temperature, the characteristic curve of the output voltage reference changing with the supply voltage. It can be seen that when the power supply voltage is 0.98V, the bandgap reference source can already work normally. Under the power supply voltage of 1V, the output voltage is 351.9mV; when the power supply voltage varies from 1V to 1.4V, the output voltage deviation is 1.4mV, reaching 0.4%.

Claims (3)

A high temperature stable reference voltage source for 1.1V power supply nonlinearity correction, characterized in that it contains: The first operational amplifier (OPA1), the output terminal is connected to the grid of MOS transistors (M0) and (M1) at the same time, and the source electrodes of the (M0) transistor and (M1) transistor are connected to the power supply VDD at the same time; the first operational amplifier The positive input of the operational amplifier (OPA1) is the node (V _P ), which is connected to the drain of the transistor (M0) and connected to the PNP transistor (Q ₀ ) through _a resistor (R0) In the emitter stage, the remaining two ends of the (Q ₀ ) tube are grounded; the negative input terminal of the first operational amplifier (OPA1) is the node (Vn), which is connected to the drain of the (M1) tube _{At the same time, it is also connected to the emitter of the PNP transistor (Q 1 )} . (V _P ) and node (Vn) are equal in voltage; The second operational amplifier (OPA2), the output terminal is connected to the gate of the MOS tube (M4), and the source of the (M4) tube is connected to the power supply VDD; the negative input terminal of the second operational amplifier (OPA2) is connected to the node ( Vn), the positive input terminal of the second operational amplifier (OPA2) is also grounded through a resistor (R1) while receiving the drain of the (M4) tube; The third operational amplifier (OPA3), the output terminal is connected to the gate of the MOS tube (M7), and the drain of the (M7) tube is fed back to the positive input terminal of the third operational amplifier (OPA3), and the third operational amplifier (OPA3) The positive input terminal of the resistor (R2) is grounded, while the negative input terminal is connected to the emitter of the PNP transistor (Q ₂ ), and the other two ends of the transistor (Q ₂ ) are grounded; MOS tubes (M5), (M2), the sources of the two are connected to the power supply VDD, and the drains are connected to the negative input terminal of the third operational amplifier (OPA3) after being connected, and the gate of the (M5) tube is connected to the said third operational amplifier (OPA3). The output terminal of the 2nd operational amplifier (OPA2), and the gate of the (M2) tube is then connected to the output terminal of the 1st operational amplifier (OPA1); MOS tubes (M8), (M9), the source of the (M8) tube is connected to the power supply VDD, and the drain is connected to the drain and gate of the (M9) tube at the same time, and the source of the (M9) tube is grounded; MOS tubes (M6), (M10), the source of the (M6) tube is connected to the power supply VDD, and the gate is connected to the output of the second operational amplifier (OPA2), while the drain of the (M6) tube is connected to The drain of the (M10) tube forms the output terminal Vbg of the reference voltage source, and the grid of the (M10) tube is connected to the grid of the (M9) tube, but the source of the (M10) tube is grounded; MOS tube (M3), the source is connected to the power supply VDD, the gate is connected to the output terminal of the first operational amplifier (OPA1), and the drain of the (M3) is connected in series between the output terminal Vbg and ground midpoint of resistors (R3) and (R4); The (R ₀ )=8kΩ～12kΩ; (R ₁ ) is derived from the temperature under the condition that the current passing through (Q ₂ ) basically does not change with the temperature T, ${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}}<span\; class="notranslate">\; )</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; ,</span>$ Among them, V _g0 is the extrapolated pn junction diode voltage at 0K, V _be (T _r ) is the voltage between the base and emitter at the temperature T _r , x is the temperature-dependent parameter of the current flowing through the transistor, η It is a parameter that has nothing to do with temperature but is related to the process, and its value is between 3.6 and 4. V _T =kT/q is the thermal voltage, k is the Boltzmann constant (1.38×10 ^-23 J/K), and q is the electronic charge (1.6×10 ^-19 C), T is the absolute temperature, n is the ratio of the emitter areas of the transistors (Q ₀ ) and (Q ₁ ); (R ₂ ) is obtained under the condition that the logarithmic term of the temperature in the output current T _bg of the reference voltage source is zero, ${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&eta;</span>}}{\mathrm{<span\; class="notranslate">\; \&eta;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; ,</span>$ (R3), (R4) are obtained according to the required linear compensation relationship and the required output reference voltage, ${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; bg</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; ,</span>$ ${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; bg</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}}\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; .</span>$ 2. The high temperature stable reference voltage source of 1V power supply nonlinear correction according to claim 1, characterized in that said operational amplifiers (OPA1), (OPA2) and (OPA3) adopt a two-pole folded structure. 3. The high temperature stability reference voltage source according to claim 1 or 2 described 1V power supply nonlinear correction, it is characterized in that the input terminal of described operational amplifier (OPA1), (OPA2) and (OPA3) connects a startup and a bias circuit that contains: The first parallel branch is composed of MOS tube (M101), resistor (R6), and MOS tube (M102) connected in series, wherein one end of the resistor (R6) is connected to the drain of the (M101) tube, and the other end is connected to (M102) the drain of the tube; The second parallel branch is formed by connecting MOS tubes (M201) and (M202) in series, and the drain of the (M201) tube is connected to the drain of the (M202) tube; The sources of the (M101) and (M201) tubes are connected to the power supply VDD, and the sources of the (M102) and (M202) tubes are grounded, and the gate of the (M102) tube is connected to the enabling control signal En, the The drain of the (M202) tube is connected to the gate to output vbiasn, and the gates of the (M101) tube and the (M201) tube are connected and connected to the drain of the (M101) tube to form a second output vbiasp.

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