CN1910939A - Method and apparatus for measuring jitter - Google Patents
Method and apparatus for measuring jitter Download PDFInfo
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- CN1910939A CN1910939A CN 200580003071 CN200580003071A CN1910939A CN 1910939 A CN1910939 A CN 1910939A CN 200580003071 CN200580003071 CN 200580003071 CN 200580003071 A CN200580003071 A CN 200580003071A CN 1910939 A CN1910939 A CN 1910939A
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Abstract
In a method for measuring jitter, a signal under test is inputted to generate signal transition locations. A signal transition location is latched using a sampling clock signal, and the signal transition location is converted to a delay value. The delay value is converted to an edge position output, and a value of the edge position output is detected.
Description
Technical field
The present invention relates generally to transfer of data, more specifically, the present invention relates to the method and apparatus of the shake in a kind of measurement data signals.
Background technology
In modern digital transmission systems, data-signal is converted into 0,1 sequence that is called as bit.In idealized system, all bits of data signal that send on transmission channel or the transmission line have identical length and interval.This receiver end for transmission channel is extremely important, and such 1 and 0 stream can be converted back to original data signal.
Unfortunately, the several factors in the transmission channel can change or disturb and is sent out or the accurate timing of the expectation of data signals transmitted bit.In fact this be applicable in all types of data communication, comprises telephone line, computer network, optical fiber, radio communication or the like.The change at random that produces in the timing of signal is called as " shake ".
" jitter measurement " has been placed on the feature and the total amount of the timing uncertainty (or shake) on the data bit when referring to the receiving terminal that the variation analyzed in the bit timing and specified data signal arrive transmission line.This measurement has shown the amplitude of shake and the frequency of shake.
The amplitude of shake is exactly the total amount or the size of timing error in each bit.That is to say that jitter amplitude is exactly the difference between the time of time that bit should arrive and the actual arrival of bit.
The frequency of shake is exactly that amount of jitter changes how soon there is and has how slow tolerance.Therefore, for example, the frequency of shake be bit a moment too early, the tolerance of the frequency that early or the like switches back and forth so then too late constantly again, and then too at another.Therefore chattering frequency is exactly the change frequency in the timing of data bit.
Certainly, chattering frequency is different from the frequency of data bit actual in the transmission channel.Chattering frequency is usually at several percentages of about 10Hz data bit frequency in about transmission channel.Therefore, the required bandwidth of jitter measurement can be very big.For example, a regulation measuring shake in per second 155Mb signal need be measured the ability of the shake that reaches 1.3MHz exactly.
Show and show that many jitter sources are arranged.A source is exactly " data are relevant " shake.For the relevant shake of data, this shake is associated with the non-repeatability of 1 and 0 string in the data-signal.For example, if 0 a long string is being followed 1 a long string, or opposite, the result can be slight, the instantaneous transition point of data timing signal so.This can be caused by several factors, such as the power supply noise of reflector, cross-talk, the delay from other signals, reflection of transmission line or the like.
Other forms of shake can appear in the multiplexed signals.Some of them are from independent source data signals is combined into single multiplexed signals.For example, in the 155Mb/s multiplexed signals, can have 63 T1 signals, each is on the frequency of 1.5Mhz.(term " T1 " is commonly referred to as high-speed data circuits line speed form, and it carries 24 subscriber channels on the group speed of 1.5MHz).Timing from these unlike signal bits of various different T1 signals needn't be in multiplexing 155Mb/s channel evenly at interval.This different fixed time interval is shown as the shake of data channel receiving terminal then.
Between the difficulty of chattering frequency and compensate for jitter, relation is arranged.Usually, chattering frequency is high more, and manageable jitter amplitude is more little.Therefore importantly can measure jitter amplitude and chattering frequency (or frequency band).The frequency spectrum that can measure shake in addition also is useful especially.
Traditional jitter measurement is to use analog circuit to carry out.Unfortunately, this analog circuit has many shortcomings.For example, it is subject to signal noise, variations in temperature, the influence of power supply noise, calibration problem or the like.
Along with the network and the data system bit rate speeds that improve, analog circuit also is faced with bigger challenge.Be difficult to allow analog circuit on high speed and frequency, work satisfactorily.
High frequency sunykatuib analysis circuit also is difficult to be minimized in the portable applications in the data transmission link of analyzing in this zone.It also is difficult in the congested and variations in temperature that takes place when its place from the zone moves to another place and keeps this portable simulation circuit to be calibrated and stablize.
Another limitation of analog machine is exactly a power consumption, especially because oscillator power consumption improves along with the raising of frequency.Similarly, the needs of shielding also improve along with the raising of frequency.
Usually, all these have produced bigger equipment, perhaps are acceptable in laboratory environment, but are unacceptable in mobile test equipment, are more unacceptable in the handheld device of especially planning to use at the scene.
Limitation except such as the size of the unsteadiness of the shielding of the power consumption that improves, raising, raising and raising also has the other technologies problem in the speed that improves analog circuit.These have also produced the problem of accuracy.For example, each small resistor and capacitor have fabrication tolerance (normally from 1% to 10%) in the analog circuit.When design circuit, must consider all these tolerances, and must compensate all tolerance variations in conjunction with enough calibration capacitance.In addition, these equipment have in time the value with temperature drift.Therefore, needing to carry out a factory in per 6 months sometimes calibrates again.
Therefore, still wish to improve jitter measurement method and device.Consider the lasting raising in data rate, transmission frequency and the component miniaturization, just need to find the answer that addresses these problems more.
Solution to these problems has been sought for a long time, but any solution all not have instruction or suggestion to the development of prior art, so the solution of these problems has been perplexed those skilled in the art for a long time.
Summary of the invention
The invention provides a kind of method of measuring shake.Input test signal is so that produce signal transition location (transition location).Use the transition position of sampled clock signal latch signal, and this signal transition location is converted into length of delay.This length of delay is converted into the output of position, edge, and this position, edge output valve is detected.This causes having produced the method that improved jitter measurement is provided in data transfer signal.
Some embodiment of the present invention have except or replace other advantages of above-mentioned advantage.By after having read following detailed description with reference to the accompanying drawings, these advantages are apparent to one skilled in the art.
Description of drawings
Fig. 1 is to use the general introduction figure of the network of dithering measuring circuit.
Fig. 2 is the circuit block diagram according to the dithering measuring circuit of Fig. 1 of the present invention.
Fig. 3 is with clock and postpones to convert to the circuit block diagram of transducer of the time value of Fig. 2.With
Fig. 4 is the flow chart according to the method for measurement shake of the present invention.
Embodiment
In the following description, provide many specific detail so that fully understand the present invention.But clearly, the present invention can realize without these details.For fear of fuzzy the present invention, some well-known circuit and system configuration do not have detailed disclosing.The same numbers of using in institute's drawings attached is represented components identical.
The objective of the invention is the shake in the measurement data signals, comprise the sampling delay line of forming by the cascade delay element.In one embodiment, these delay elements are digital electrical buffers, are appreciated that other suitable equipments of inhibit signal also can be used.
Delay line between selecteed delay element along its length by tap, the state at the circuit of each tap can be sampled like this.This sampling is by sampling clock control, and this sampling clock is sampled with enough fast speed so that guarantee that signal condition changes can not be delivered to the other end from delay line one end under situation about not being sampled along some points of delay line.
For digital signal, line status is by 0 or 1 expression.In this case, sampling can be carried out by the flip-flop circuit by the sampling clock timing along delay line.For example, if signal from 0 to 1 change state, because signal is propagated by this delay line, the element in the delay line also will sequentially change into 1 from 0 so.
Shown in and among the described embodiment, element changes from the beginning to the end according to priority.If this delay line is sampled when element is changed, the element of front will change so, and the element of back will also not change.The number of elements that has changed is exactly that state changes measuring of timing.Sampling can processedly determine state changes which element of arrival on the time of sampling clock then.Here it is " transformation " position of components, that is, delay line samples changes to the point of another state from a state.Because the delay of each delay element is known, so can obtain the timing property of digital signal.
For example, if sampling clock is sampled with signaling rate, the variation at transition point is relevant with the shake of data signal under test so, thereby characterizes this shake.In addition, because shake is generally defined as the variation that has greater than the frequency of about 10Hz, so signal processing can be used to (as instructing) elimination man-made noise (artifact) relevant with the sampling clock that is different from signaling rate here.A kind of this man-made noise that is caused by different signaling rates can be perceived as transition position residing " slope ".The gradient on this slope is just represented the poor of signaling frequency and sampling clock frequency so.
Certainly, the data bit error also can change being lower than on the frequency of 10Hz, but because at these different needs of more analyzing bit rate errors on the low frequency, this phenomenon is called as " drift " rather than shakes.For example, drift needs much accurate reference signal so that measured satisfactorily.
Sometimes, when in system, needing jitter measurement, may not change for each data bit that is sent out.For example, in non-return-to-zero (" NRZ ") system, the successive bits of identical value (0 or 1) does not change between them.In this case, the present invention remembers last transition point, up to new transformation takes place.
If the timing between two continuous sampling changes too greatly, so super scope (over-range) function detects this situation.In this case, provided such indication, do not had under the further information state, the shake of input does not attempt practically to determine which changes from which data bit location.When jitter amplitude was very big, this more may take place.
The amplitude of shake is the signal timing variable quantity at the receiving terminal place of data transmission channel.Jitter amplitude is measured as the percentage of unit gap (" UI ") usually, and the unit gap refers to the length of a bit or signal element.Therefore, the jitter amplitude of 0.45UI is illustrated in timing on the receiving terminal of data transmission channel and changes and be approximately half-bit.In some cases, for example when data bit signal being multiplexed into higher combined bit speed, amplitude can change in the scope of 10 or 100 UI.
The frequency of shake be amount of jitter change how soon or how slow measuring.Between the difficulty of chattering frequency and compensate for jitter, there is relation.Usually, chattering frequency is high more, and the UI quantity that can manage is just more little.The reduction of managing the ability of big jitter amplitude is reflected in the industrial specification of jitter recovery, and it generally includes fall (roll-off) of UI ability along with the frequency increase.
For example, when chattering frequency was low, so the edge of data bit will move slightly from a bit to another bit, circuit can be handled it by only following the tracks of it like this.Therefore, in addition a hundreds of UI also can be compensated significantly and data can be resumed.On the contrary, on higher frequency and identical amplitude, the bit edge can for example move UI from a bit half to next bit, and it will cause producing loss of data, because it can not determine that a specific bit belongs to a time slot and still belongs to adjacent time slot.
Traditional jitter measurement uses analog circuit to carry out.This analog circuit comprises the phase-locked loop of being made up of oscillator, filter and phase comparator.This has set up a reference clock, several times of the identical or input data signal frequency of the frequency of this clock and input data signal.So, if input data signal changes in timing, the reference signal that is produced by phase-locked loop allows the amount that definite input data signal has regularly changed so.From changing, this timing signal of measuring obtains jitter measurement then.
Unfortunately, this analog circuit has many shortcomings.For example, it is subject to signal noise, variations in temperature, the influence of power supply noise, calibration problem or the like.Along with the increase of their frequencies, analog circuit also becomes very difficult and designs, makes and safeguard.These increases on the frequency are demands every day of network and data system, because along with the lasting raising of the communication technology, data bit-rate also improves constantly.For example, in fiber transmission link, the data rate of 40Gbps is common, and each data bit has the length that is approximately 25 psecs in other words.Allowing analog circuit work satisfactorily on this speed is very big challenge.
Advantageously, such as here instruction and disclosed, have been found that the present invention can realize, comprises field programmable gate array (FPGA) in the modern digital integrated circuit.Some FPGA comprise " carry chain " circuit structure.This carry chain uses for digital arithmetic circuits basically, but as disclosed herein with instructed, this carry chain can be used as has the delay line that magnitude is the tap of 100ps.This realization is than the little and considerably cheaper of conventional jitter measurement that uses analog circuit.
In fact the resolution that has been found that some jitter measurements can improve by the timing noise is added to test signal.Because jitter measurement carries out on interested certain frequency band usually, usually from about 10Hz to about signaling rate of about 1%, therefore can postpone to improve resolution outside the tap resolution at the timing noise of introducing on the frequency band of non-constant width.For this reason, the present invention is added to broadband noise on the data-signal, leaches noise then on interested frequency band, thereby improves resolution.
Can add noise with several method.For example, can by use delay apparatus, by changing the sampling lead-in wire threshold value, add to delay line power supply or the like by adding power supply noise.All these noise addition methods can for example be used for FPGA and realize.
In FPGA according to the present invention realizes, finish filtering by using the Digital Signal Processing (" DSP ") that realizes in the FPGA of delay line.This DSP filtering provides the measurement of satisfying the ITU-T standard 0.171/0/172 that is used for shaking measuring device easily.
In order to provide accurate measurement, will be appreciated that the delay line timing property.The timing of delay line components can be calibrated, and perhaps can know this timing by design.In a FPGA realized, delay line was calibrated by two signals that generation has given frequency and given frequency difference.This calibrating signal uses phase-locked loop to produce.One of them calibrating signal is used as sampling clock; Another calibrating signal is fed to dithering measuring circuit as test signal.Because given frequency is poor, therefore the output from the delay line samples device is exactly the slope of known gradient.Because given frequency, so the output of sampler is relevant with elapsed time.Calibrate each delay line components by the time of each sample transition of storage generation in calibration storage then.
With reference now to Fig. 1,, wherein show network overview Figure 100, wherein used dithering measuring circuit 102.More specifically, dithering measuring circuit 102 is measured the shake on the signal 104 that receivers 106 receive from transmission channel 108.Signal 104 originates from reflector 110, and this reflector 110 is inserted into transmission channel 108 with signal 104 so that allow receiver 106 receive.The part that network 112 (such as the internet) can be used as transmission channel 108 occurs.
With reference now to Fig. 2,, what illustrate is circuit block diagram according to dithering measuring circuit 102 of the present invention.Dithering measuring circuit 102 comprises tapped delay line piece 202, sample register piece 204, priority encoder piece 206, with clock with postpone to be converted to the converter block 208 of time value, super range detector piece 210, DSP filter block 212, peak to peak detector block 214, carry out root mean square (" RMS ") and measure the piece 216 that calculates and pulse (dither) unit certainly 218.
With reference now to piece 202,, this tapped delay line comprise cascaded delay 202A, 202B ... 202N.Each delay element 202x provides a signal time very in a small amount to postpone Δ T.Can be as seen from Figure 2, delay element 202x is linked in sequence, and therefore when data-signal moved by tapped delay line piece 202, the Δ T time delay in each delay element added up.Therefore, if having n Δ T time delay element, the n of Δ T doubly is exactly (at delay element 202A) the postponing total time to end (at delay element 202N) from tapped delay line piece 202 so.
Data signal under test 220 (can be signal 104, Fig. 1), at first be provided to pulsating element piece 218, then to the delay element 202A that begins to locate of tapped delay line piece 202.Then, as mentioned above, after each Delta Time postponed Δ T, data signal under test 220 sequentially entered delay element 202B subsequently ... 202N.Therefore, when data-signal is propagated therein, data signal under test 220 is input to tapped delay line piece 202 will in tapped delay line piece 202, produces the data shift signal position.
As mentioned above, each in several Δ T time delay intervals can be different interval.As mentioned above and following describing in further detail, dithering measuring circuit 102 comprises calibration and calculates the circuit of the variation (if any) in several Δ T time delays.By this method, by accepting the bigger Δ T tolerance in the tapped delay line piece 202, accuracy of the present invention is enhanced, and cost is lowered simultaneously.
Sampled clock signal 222 is provided for dithering measuring circuit 102 so that its operation synchronously.The frequency of sampled clock signal 222 can be identical with the frequency of data signal under test 220, and perhaps as mentioned above, the frequency of this sampled clock signal 222 can have different frequencies.With the frequency-independent of sampled clock signal 222, the total delay by tapped delay line piece 202 is configured to the cycle period greater than sampled clock signal 222.
Each Δ T time delay in delay element 202x is compared very little with the cycle period of sampled clock signal 222.Therefore, can be accurately with the location resolution to of the signal transition of data signal under test 220 (from 0 to 1, or opposite) in the Δ T time interval.
In order to determine the position of signal transition, dithering measuring circuit 102 is sought the edge of signal transition, and perhaps rise (from 0 to 1) or fall (from 1 to 0), because circuit can be measured rising edge, trailing edge, and/or the shake on two kinds of edges.
Therefore, when signal transition entered the delay element 202A of tapped delay line piece 202, it was delayed corresponding Δ T time delay, was repeatedly postponed by similar when it upwards arrives delay element 202N by delay chain then.At the output of each delay element 202x, has tap 224x.These taps (224A, 224B ..., 224N) each all provides output signal separately, and described output signal is reflected in the state of data signal under test 220 on the relevant position of tapped delay line piece 202.
As shown in Figure 2, tap 224x is connected to sample register piece 204 and is reported in the state that each delay element 202x goes up data signal under test 220.Each tap 224x correspondingly is connected to trigger 204A the sample register piece 204 from each delay element 202x, 204B ... separately trigger 204x in the 204N sequence.Therefore trigger 204x corresponds respectively to delay element 202x.
Sampled clock signal 222 also offers trigger 204x sequence so that it is controlled.Then, in each cycle of sampled clock signal 222, the trigger 204x of sample register piece 204 samples to the output of tapped delay line piece 202 on tap 224x.Catch the state of the tap 224x output of tapped delay line piece 202 among each trigger 204x of this sampling seizure in sample register piece 204.This output state is latched to sample register piece 204, up to the next cycle of sampled clock signal 222.
Therefore, in operation, when signal transition is propagated in piece 202 when passing through tapped delay line, the signal condition that occurs on progressive tap 224x will change (for example, from 0 to 1, perhaps opposite).Transformation for from 0 to 1, all towards tapped delay line piece 202 begin will have value 1 to the delay element of the position that changes.Those (towards delay element 202N) on changing will can not change and continue to have value 0 again.
When the cycle of sampled clock signal 222 was provided for the trigger 204x of sample register piece 204 then, will be triggered device piece 204 of transition point was caught, because they constantly will latch corresponding 1 and 0 at that.Because the total delay of tapped delay line piece 202 is greater than the cycle period of (being longer than) sampled clock signal 222, be under certain conditions in the tapped delay line piece 202 so change, and will on its position, be captured, when the trigger 204x that is sampled block of registers 204 then when transition position latchs.
Do not having shake and sampled clock signal 222 to have under the situation with the data-signal same frequency on the data signal under test 220, transition point will always appear on the same position of tapped delay line piece 202.If have shake on data-signal, such as from transmission channel 108, if this shake has the amplitude greater than Δ T, this shake will be shown as moving of signal transition edge so.In addition, if do not have accurate frequency match between the frequency of sampled clock signal 222 and data signal under test 220, so obviously the edge of signal transition will move progressively according to the difference of these frequencies.Yet because the difference of data test signal bit rate and sampling clock speed is known, dithering measuring circuit 102 will calculate easily and be offset and return correct jitter value and result accordingly so.
With regard to the time delay that produces here, because the total length of tapped delay line piece 202 greater than the cycle period of sampled clock signal 222, will be caught by sample register trigger-blocks 204 by each signal transition of tapped delay line piece 202.In fact, in the time of when the beginning that transits out of present tapped delay line piece 202 or near finishing, another transformation may be caught near the end opposite of tapped delay line piece 202 simultaneously.Yet, because circuit tracing change the edge should position (as described below), somewhere will not obscure for the bit edge is actual so.
With reference now to priority encoder piece 206,, all data from trigger 204x are received by priority encoder piece 206.Priority encoder certainly 206 is reported in counting or the position that signal transition takes place in the tapped delay line piece 202 then.In one embodiment, this is directly by to have value be the number counting of 1 trigger 204x and report that this number realizes, because how far the lucky reflected signal of this counting edge has been propagated.More specifically, if the value that trigger 204A has is 1, so binary counting can by from 204A until to have value be that all triggers of 0 trigger are formed.On the contrary, be 0 if trigger 204A has value, counting can be performed until that to have value be 1 trigger 204x so.The result is exactly single (binary system) output number from priority encoder piece 206, and it has shown which tap 224x transformation is positioned at when sampled clock signal 222 triggers a sampling period.
Output from priority encoder piece 206 is provided to converter block 208 by bus 226 (can be parallel data bus line).Output from priority encoder piece 206 on the bus 226 is length of delay, and this length of delay is combined with sampled clock signal 222 converter block 208 so that the time value output that provides shows signal to change the time of taking place.
With reference now to Fig. 3,, shows the more detailed circuit block diagram of converter block shown in Figure 2 208.Converter block 208 comprises calibrator piece 302, (wrap-around) detector block 304 that unrolls, time/phase accumulator piece 306 and UI counter block 308.
Calibrator piece 302 is each delay element 202x (Fig. 2) calibration Δ T time delay intervals, and as mentioned above, each tap 224x of tapped delay line piece 202 measures corresponding to correct time like this.
The detector block 304 (Fig. 3) that unrolls detects the end points (starting point or end point, for example end or top) that when moves through tapped delay line piece 202 from the measured transition point of tapped delay line piece 202 (Fig. 2).Thereby the length of the detector block 304 permission tapped delay line pieces 202 that unroll is reasonably and can be too not expensive.According to the direction of unrolling (up or down), the detector block 304 that unrolls is by detecting and handle the timing variation greater than the length of tapped delay line piece 202, and a corresponding UI finishes by adding deduct in due course.
With respect to position that signal transition was positioned at when not having shake, time/phase accumulator piece 306 determines the phase place (with respect to a signal frequency cycle) that input signals change.Phase place is determined by handling several inputs and the Measurement Phase of position, edge being provided as position, edge output 310 makes.
A critical function of converter block 208 is to regulate in the data signal under test 220 continuous 0 or 1.Certainly, between the successive bits (0 or 1) of identical value, do not change.Do not have to change, just measure less than shake.The amount of bits that UI counter block 308 countings receive from sampled clock signal 222, and with this counting time of reporting to/phase accumulator piece 306.By this information, converter block 208 keeps the counting in this sampling clock cycle, up in fact another data shift signal takes place.Converter block 208 is then based on the position, transformation edge of the quantitative forecast expection of corresponding data signal period of process.Converter block 208 then interpolation with respect to the displacement (if any) of position, edge of prediction position, edge.Because converter block 208 is known the frequency dependence of sampled clock signal 222 frequencies and data signal under test 220 (Fig. 2), so it is only for each cycle count of data signal under test 220 required amount of bits from sampled clock signal 222.Therefore, as previously mentioned, it is identical with the frequency of data signal under test 220 that the frequency of sampled clock signal 222 does not need.
Advantageously, calibrator clock 302 (Fig. 3) can be calibrated in needs, for example can be appropriate, in response to temperature and/or change in voltage.For this calibration, data signal under test 220 (Fig. 2) is by known signal substituting, and this known signal makes the transition point on the tapped delay line piece 202 propagate by tapped delay line piece 202 with known speed.The actual value of report is recorded in the calibrator piece 302 on bus 226 then, like this phase delay element 202x (Fig. 2) thus indivedual Δ T time delays of reality in calibrator piece 302, be correlated with.
UI amplitude or the segment when position, the edge output 310 that is converted 208 reports of device piece is moved beyond setting analyzed and detected to super range detector piece 210 (Fig. 2).For example, when detecting the edge transformation, its position, edge is converted device piece 208 and is reported as position, edge output 310.Yet if 0 or 1 sequence takes place, converter block 208 outputs will can not change, because do not have the data edge in this unchanged sequence.Therefore, converter block 208 can not be upgraded the edge location positioning.At last, data sequence will change and will detect the edge.So far, jitter error can be accumulated fully, and promptly converter block 208 will be reported the major part (for example, near 0.5UI) of UI.In this case, fully certainty determine the transformation that detected from which (before, current, or afterwards) at interval, this expression data analysis may become unreliable.Therefore super range detector piece 210 comprises the definable threshold value that is used to warn of user when this super range event of generation.
Output from DSP filter block 212 is provided to peak to peak detector block 214 by output 228 (for example, data/address buss).Peak to peak detector block 214 is measured the peak to peak value of shake, typically refers to the UI of peak value to peak value.For example, if regularly move around a UI indefinitely, it will form a UI peak to peak so.Thereby how far the transformation of data edge shake that peak to peak detector block 214 is measured in one direction has, and how far its shake has on another direction, deducts this two values, and the result of output is exactly a peak to peak UI height.This measurement can repeat in the interval of setting, and for example one second, and be shown the dynamic output demonstration that the peak to peak of data signal under test 220 flutter behaviour is provided.
Output from DSP filter block 212 also is provided to RMS calculator block 216 by output 228.RMS calculator block 216 is analyzed position, edge output 310 so that calculate and measure the RMS of dither signal, the position at the transformation edge by obtaining dither signal, (for example 1 second) measures the RMS value of this position, edge in the measurement of setting at interval, and exports the RMS value of its generation.This RMS measures and can repeat (for example per second is 1 time) in the measurement of setting at interval so that provide the dynamic output of the RMS flutter behaviour of data signal under test 220 to show.
Peak to peak and RMS value are useful on the debugging telecommunication system very much.For example, the amplitude of peak to peak value representation shake, the RMS value has quantized to be similar to the value of shake " power ".
Pulsating element piece 218 comes to increase accuracy and resolution to jitter measurement by deliberately it was added to data signal under test 220 before additional dither (for example, timing noise) is input to measuring circuit.For example by adding the timing ambiguity in several Δ T time delay cycles, the jitter value on the data signal under test 220 can be broken down into less than 1 Δ T value.This can be for example shows by having of considering to exist on the data signal under test 220 shake less than the value of 1 Δ T.In this case, to those 222 cycles of sampled clock signal, many will in delay element 202x expection or prediction, the generation the transformation edge from the one-period of sampled clock signal 222 to another cycle moves.Therefore, take place even shake is actual, when the device 204x that is triggered latchs, it will not change " non-jitter " output of expection.Thereby in the delay element 202x of expection, occur because change the edge at every turn, so, change the shake conductively-closed on the edge and detect less than.This also is so for having the big jitter value of unit with similar little decimal system Δ T value, especially when jitter value on several measuring periods quite stably the time.
Yet, to pulse to data signal under test 220 by using pulsating element piece 218 to introduce, additional timing uncertainty has been added on the data-signal.The uncertain transformation edge that makes of the timing that should add that is caused by additional pulsation timing noise moves around in bigger excursion.Pulsation that should be additional regularly noise (it is preferably on the high frequency with respect to chattering frequency) is detected now, combines with data signal under test 220.Because the signal excursion that improves, the signal of this combination (dither plus data) are detected by several trigger 204x periodically.The detection of this change has produced the more accurate of actual jitter and has determined then by on average.
Regularly noise is then by the DSP filter filtering in the piece 212 from pulsating element piece 218 high frequencies own, and dither signal no longer appears as from a part of data of dithering measuring circuit 102 outputs like this.In addition,, just do not need to change or adjust DSP filter block 212 by being that high-frequency noise is selected in the input of pulsating element piece 218 because the high frequency of pulsation will outside interested (or a plurality of) frequency band that is passed through by the DSP filter.Therefore, DSP filter block 212 has been configured to abandon such high-frequency noise.
Pulsating element piece 218 can be realized with many diverse ways.For example, noisy power supply can be used for dithering measuring circuit 102.Such power supply is so not expensive usually, thereby has reduced the cost of dithering measuring circuit 102, improves its accuracy simultaneously unexpectedly.Alternatively or additional, the placement that can link to each other with the data signal under test 220 of input of available integrated circuit so that the increase programmable delay, thereby provides the resolution of tuning for certain required dithering measuring circuit 102.
Can find out that as above the present invention can realize without analog circuit.Therefore, can realize significant saving aspect cost, size, energy consumption or the like, because whole dithering measuring circuit 102 can be realized with a FPGA.Thereby this part is owing to found tapped delay line piece 202 and can realize in FPGA as the function tapped delay line of dithering measuring circuit 102 by using the FPGA carry chain.(the FPGA carry chain is often used as and is the arithmetical logic accelerator).Especially, the multiplexer of carry chain cascaded by configured in series so that form tapped delay line piece 202.The time delay that is provided by carry chain cascaded multiplexers is used to make unexpectedly and realizes that in single FPGA whole dithering measuring circuit 102 becomes possibility subsequently.
With reference now to Fig. 4,, shows the flow chart of the method 400 of measuring shake according to the present invention.Method 400 is included in input test signal in the piece 402 so that produce signal transition location; In piece 404, use the transition position of sampled clock signal latch signal; In piece 406, convert signal transition location to length of delay; Converting length of delay to the edge position in piece 408 exports; And the value that in piece 410, detects the output of position, edge.
Have been found that the present invention has a plurality of advantages.For example, dithering measuring circuit 102 can also be used to measuring drift.This can realize that this sampled clock signal 222 has stability at long time in the cycle by using sampled clock signal 222, such as may being for example to obtain from the atomic clock source.To be used for then detecting and by the signal in this bandwidth to the corresponding adjustment of DSP filter block 212.
Can for example be presented on the oscilloscope from the output of peak to peak detector block 214 and/or from the output of RMS calculator block 216, so that the visual form that provides shake to show.
In another embodiment, the output signal from DSP filter block 212 can change (FFT) by fast Flourier so that produce the spectrum signal of shake.This signal can be handled so that disclose the residing frequency of shake by frequency spectrum analyser then.This result can significantly help to diagnose jitter sources.For example, in one embodiment, the shake of 390kHz is isolated is rapidly traced back to the FPGA Switching power that switches with identical 390kHz frequency then.The frequency spectrum fingerprint recognition that provides by FFT is provided this Switching power.
Except real-time diagnosis, the present invention can also be recorded equipment and be used to provide subsequently playback and analysis to dither signal.This not only helps more careful shake evaluation, and compares and trend analysis on the time of the measurement of making on can the different time to various systems.By playback is so that the reason of analysis of failure then at the age at failure interocclusal record, it also can be used for equipment fault analysis.
The present invention can also compensate so that feed back to signal compensator automatically by the result who uses jitter analysis, thereby plays the effect of dynamic Jitter Attenuation device.
The present invention can also Measurement Phase " instantaneous interference (hit) ", that is to say the transient change of the phase place of data-signal.An example of the instantaneous interference of phase place occurs under the multiplexed situation exactly, when starting another sheet equipment, such as adding several additional T1 in multiplexed signals.When it took place, the phase place of signal moved suddenly sometimes.
Based on above-mentioned instruction, the present invention can also be used to measuring that noise has much in the power supply of FPGA.When current FPGA operates in more rapid rate, just need very big concern.Because the present invention can realize on single FPGA that therefore the present invention can be loaded into target FPGA and the aforesaid quality that is used to measure the FPGA power supply.
In another embodiment, the present invention can be used for providing point-device time measurement on respect to the two-forty of required output in the environment that noise testing can be carried out.DSP filter block 212 is calibrated filter away high frequency noise then, measure thereby produce precise time, in a way to the processing of the noise that is added by pulsating element piece 218 with remove similar.
Therefore, have been found that jitter measurement method of the present invention and device provide important and the unknown up to now and unavailable scheme, ability and functional advantage, the diagnosis that is used for data transfer signal is shaken.Process that produces and configuration are direct, economical, uncomplicated, that high pass is used, accurate, responsive and effective, and can realize by the assembly that adaptive known being used to made, used and utilize.
Though the present invention has got in touch specific best mode and described, be appreciated that according to noted earlier, many replacements, modifications and variations it will be apparent to those skilled in the art that.Therefore, the present invention can comprise all such replacements, modifications and variations, and it all drops in the scope of included claim.All contents described up to now or shown in the drawings are understood that exemplary, and are nonrestrictive.
Claims (10)
1. method (400) of measuring shake comprising:
Input (402) test signal (220) is so that produce signal transition location;
Use sampled clock signal (222) to latch (404) signal transition location;
With signal transition location conversion (406) is length of delay;
Length of delay conversion (408) is position, edge output (310); And
Detect the value of (410) position, edge output (310).
2. the method for claim 1 (400) also is included in filtering (212) position, the edge output (310) before of detection (410) position, edge output (310) value.
3. the method for claim 1 (400) also is included in input (402) test signal (220) and added fluctuating signal (218) to test signal (220) before producing signal transition location.
4. the method for claim 1 (400) comprises that also analyzing position, edge output (310) moves so that determine the position, edge that surpasses predetermined amplitude.
5. the method for claim 1 (400) also comprises and analyzes position, edge output (310) so that its root-mean-square value is provided.
6. a device (102) of measuring shake comprises
Tapped delay line (202) is used for from input test signal (220) generation signal transition location wherein wherein;
Sampled clock signal (222);
Sample register (204) is connected and latchs wherein signal transition location in response to sampled clock signal (222);
Priority encoder (206) is connected signal transition location is converted to length of delay;
Transducer (208) is connected length of delay is converted to position, edge output (310); With
Peak to peak detector (214) is connected the value that detects the position, edge.
7. device as claimed in claim 11 (102) also comprises digital signal processor, filtering wave device (212), is connected for before peak to peak detector (214) detects the edge positional value position, filtering edge output (310).
8. device as claimed in claim 11 (102) also comprises pulsating element (218), is connected to be used for being input to tapped delay line (202) before in test signal (220), adds fluctuating signal to test signal (220).
9. device as claimed in claim 11 (102) also comprises super range detector (210), is connected to analyze position, edge output (310) so that report is moved above the position, edge of predetermined amplitude.
10. device as claimed in claim 11 (102) also comprises piece (216), is used for:
Carry out root mean square and measure calculating; With
Be connected and analyze position, edge output (310) so that its root-mean-square value is provided.
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| US53894504P | 2004-01-23 | 2004-01-23 | |
| US60/538,945 | 2004-01-23 | ||
| US10/826,198 | 2004-04-15 |
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| CN1910939A true CN1910939A (en) | 2007-02-07 |
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| CN 200580003071 Pending CN1910939A (en) | 2004-01-23 | 2005-01-14 | Method and apparatus for measuring jitter |
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| CN101232333B (en) * | 2008-01-16 | 2011-06-22 | 中兴通讯股份有限公司 | Clock shake measuring method and oscilloscope for measuring clock shake |
| CN101419259B (en) * | 2007-10-23 | 2011-07-13 | 和硕联合科技股份有限公司 | Automatic measurement method for shake t |
| CN101572579B (en) * | 2009-05-22 | 2011-07-20 | 北京荣达千里科技有限公司 | 2M signal jitter test method |
| CN104283531A (en) * | 2013-07-04 | 2015-01-14 | 辉达公司 | Clock jitter and power supply noise analysis |
| CN105319523A (en) * | 2014-07-29 | 2016-02-10 | 特克特朗尼克公司 | Double quadrature with adaptive phase shift for improved phase reference performance |
| CN106680736A (en) * | 2017-02-28 | 2017-05-17 | 郑州云海信息技术有限公司 | System of automatically testing Jitter in switching mode power supply |
| CN108362990A (en) * | 2016-12-28 | 2018-08-03 | 电子科技大学 | High speed signal jitter test circuit and method in piece |
| WO2019127357A1 (en) * | 2017-12-29 | 2019-07-04 | 深圳市英威腾电气股份有限公司 | Filter method, device and system for signal of quadrature encoder |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101419259B (en) * | 2007-10-23 | 2011-07-13 | 和硕联合科技股份有限公司 | Automatic measurement method for shake t |
| CN101232333B (en) * | 2008-01-16 | 2011-06-22 | 中兴通讯股份有限公司 | Clock shake measuring method and oscilloscope for measuring clock shake |
| CN101572579B (en) * | 2009-05-22 | 2011-07-20 | 北京荣达千里科技有限公司 | 2M signal jitter test method |
| CN104283531A (en) * | 2013-07-04 | 2015-01-14 | 辉达公司 | Clock jitter and power supply noise analysis |
| US9952281B2 (en) | 2013-07-04 | 2018-04-24 | Nvidia Corporation | Clock jitter and power supply noise analysis |
| CN105319523A (en) * | 2014-07-29 | 2016-02-10 | 特克特朗尼克公司 | Double quadrature with adaptive phase shift for improved phase reference performance |
| CN108362990A (en) * | 2016-12-28 | 2018-08-03 | 电子科技大学 | High speed signal jitter test circuit and method in piece |
| CN106680736A (en) * | 2017-02-28 | 2017-05-17 | 郑州云海信息技术有限公司 | System of automatically testing Jitter in switching mode power supply |
| WO2019127357A1 (en) * | 2017-12-29 | 2019-07-04 | 深圳市英威腾电气股份有限公司 | Filter method, device and system for signal of quadrature encoder |
| CN110799807A (en) * | 2017-12-29 | 2020-02-14 | 深圳市英威腾电气股份有限公司 | Orthogonal encoder signal filtering method, device and system |
| CN110799807B (en) * | 2017-12-29 | 2021-10-22 | 深圳市英威腾电气股份有限公司 | Orthogonal encoder signal filtering method, device and system |
| CN113301375A (en) * | 2021-05-24 | 2021-08-24 | 上海绚显科技有限公司 | Data sending method and device |
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