CN101572579B - 2M signal jitter test method - Google Patents
2M signal jitter test method Download PDFInfo
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- CN101572579B CN101572579B CN2009100846885A CN200910084688A CN101572579B CN 101572579 B CN101572579 B CN 101572579B CN 2009100846885 A CN2009100846885 A CN 2009100846885A CN 200910084688 A CN200910084688 A CN 200910084688A CN 101572579 B CN101572579 B CN 101572579B
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Abstract
The invention discloses a 2M signal jitter test method. Clock is extracted from 2M signal coded in HDB3, a standard 2M clock counts the extracted clock, a high frequency clock is used for collecting phase data after frequency division and phase demodulation, jittered phase and amplitude data can be obtained by filtering, and finally phase and amplitude are analysized.
Description
Technical field
The present invention relates to communications and measure, relate in particular to a kind of method of testing of 2M signal jitter.
Background technology
The shake of SDH (SDH (Synchronous Digital Hierarchy)) transmission system is an important indicator weighing optical communication transmission equipment quality.In general, the shake of optical transmission system is divided into non-systemic shake (randomness shake) and systematicness shake (pattern associated jitter) two kinds, randomness shake mainly is that SSB (monolateral band) noise by signal source causes, has Gaussian characteristics, it appears in the single noise apparatus, build-up effect is very little, and is little to the influence of transmission quality; And the generation of systematicness shake is relevant with transmission patterns, and the main cause that such shake produces has: intersymbol interference, AM/FM conversion and clock recovery circuitry off resonance etc.In regenerative system, the systematicness shake has identical variation tendency, so build-up effect is very big, and is therefore bigger to the influence of transmission quality.
In addition, because the SDH system is the transmission system with standard frame, the characteristics of this frame structure have caused the A1 of non-scrambler, A2 sync byte periodically to repeat with the form of pulse, are the shake compositions that plays a decisive role.Damage shows following three aspects to the performance of SDH network in shake: 1. pair digitally coded analog signal, sample value after the random phase shake of digital stream after the decoding makes recovery has irregular phase place, thereby cause the distortion of output analog signal, form so-called jittering noise.2. in regenerator, scrambling regularly makes effective determination point depart from the center that receives eye pattern, thereby has reduced the signal to noise ratio of regenerator, up to error code takes place.3. in SDH net, be furnished with the network element of buffer as Synchronous multiplexer etc., excessive input jiffer can cause overflowing of buffer or get sky, thereby produces the damage of sliding.
Summary of the invention
The object of the present invention is to provide a kind of processing procedure total digitalization, circuit scale is little, the method for testing of the 2M signal jitter of being convenient to realize.
For achieving the above object, the technical solution used in the present invention is as follows:
The present invention carries out Clock Extraction from the 2M signal of HDB3 coding, with the 2M clock of a standard clock that extracts is counted then, behind frequency division and phase demodulation, with high frequency clock acquisition phase data, through frequency and the amplitude data that obtains shaking after the filtering, carry out the analysis of phase place and amplitude again.
The first step, the clock by a 32.768MHz carry out phase-locked to the 2M input signal and extract clock, carry out 16 frequency divisions by the 32.768MHz clock simultaneously and obtain a standard time clock as a reference;
Second step, normative reference clock are tentatively discerned the chattering frequency that has shake 2M clock that extracts, and determine best part-frequency point;
The 3rd step, carry out the precise phase phase demodulation to determining best part-frequency point clock signal, signal is carried out the processing of different frequency range, the data of phase demodulation are divided into two-way handle, the one tunnel is directly used in frequency identification, carries out frequency counting and measures, and another circuit-switched data is used for sampling;
The 4th the step, with the complete errorless particular buffer that is saved in of sampled data;
The 5th goes on foot, according to the requirement of ITU-T 0.171/0.172 the data of sampling is carried out the Filtering Processing of different frequency range;
The 6th the step, by calculating chattering frequency and amplitude test result.
Beneficial effect of the present invention:
Utilize the present invention to carry out the collection of 2M clock jitter information, whole data handling procedure total digitalization can easily realize that with general logical circuit circuit scale is little, is convenient to realize.
Description of drawings
Fig. 1 is a principle schematic of the present invention.
Embodiment
A specific embodiment of the present invention is as follows:
Referring to accompanying drawing 1, the present invention can realize that by the ball bearing made using that FPGA and CPU form CPU wherein can adopt dsp chip to realize.
Utilize the clock signal of the crystal oscillator generation of a 32.768MHz who is connected with FPGA to carry out phase-locked to the 2M input signal and the extraction clock, the clock that extracts is 2048kHz, for measurement accuracy definitely, the shake phase place that must guarantee to extract clock is consistent with 2M input signal shake phase place, promptly when chattering frequency 100KHz, jitter amplitude realizes accurately phase-locked under 0.5UI.
As a reference 2MHz standard time clock carries out 16 frequency divisions by a 32.768MHz clock and obtains during preliminary identification.
Adopt frequency counting, quick search frequency range method is carried out chattering frequency and is tentatively discerned the shake 2M clock that has that extracts, and main purpose is to find out the chattering frequency frequency range, by frequency range this clock is carried out reasonable frequency division, improve certainty of measurement, determine that a best part-frequency point clock signal carries out the precise phase phase demodulation, signal is made different frequency range handle, the data of phase demodulation are divided into the two-way processing, one the tunnel is directly used in frequency identification, carries out frequency counting and measures, and another circuit-switched data is used for sampling.Adopt three cell datas to handle same footwork, be that sampled data and data cached maintenance are synchronous, data cached back notice CPU wants synchronously when obtaining data, with the errorless particular buffer that is saved in CPU of data integrity of sampling, the sampled data of the particular buffer that is saved in CPU is carried out the Filtering Processing of different frequency range and calculated shake phase place peak-to-peak value according to the requirement of ITU-T 0.171/0.172.
The method of calculating jitter amplitude and chattering frequency is:
Carry out the data that digital mean filter obtains one group of signal level by CPU, look for peak-peak and minimum peak in 1 second time cycle, both differences are the amplitude of shake.
After the extraction clock is isolated dither signal by phase demodulation from signal,, and count, obtain the frequency n of zero crossing in 1 second by the hardware detection cycle signal zero-cross point, f=1/n, f is chattering frequency.
Claims (1)
1. the method for testing of a 2M signal jitter is characterized in that comprising the steps:
The clock signal that the first step, the crystal oscillator by a 32.768MHz who is connected with FPGA produce is carried out phase-locked to the 2M input signal and is extracted clock, carries out 16 frequency divisions by the 32.768MHz clock simultaneously and obtains a standard time clock as a reference;
Second step, normative reference clock adopt frequency counting, search for the frequency range method fast, and the chattering frequency that has shake 2M clock that extracts is tentatively discerned, and find out the chattering frequency frequency range, determine best part-frequency point;
The 3rd step, carry out the precise phase phase demodulation to determining best part-frequency point clock signal, signal is carried out the processing of different frequency range, the data of phase demodulation are divided into two-way handle, the one tunnel is directly used in frequency identification, carries out frequency counting and measures, and another circuit-switched data is used for sampling;
The 4th the step, with the complete errorless particular buffer that is saved in of sampled data;
The 5th goes on foot, according to the requirement of ITU-T 0.171/0.172 the data of sampling is carried out the Filtering Processing of different frequency range;
The 6th the step, by calculating chattering frequency and amplitude test result, computational methods are:
Obtain the data of one group of signal level by digital filter, look for peak-peak and minimum peak in 1 second time cycle, both differences are the amplitude of shake;
After the extraction clock is isolated dither signal by phase discriminator from signal, the zero crossing of detection signal, and count, obtain the frequency n of zero crossing in 1 second, f=1/n, f is chattering frequency.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009100846885A CN101572579B (en) | 2009-05-22 | 2009-05-22 | 2M signal jitter test method |
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| CN2009100846885A CN101572579B (en) | 2009-05-22 | 2009-05-22 | 2M signal jitter test method |
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| CN101572579A CN101572579A (en) | 2009-11-04 |
| CN101572579B true CN101572579B (en) | 2011-07-20 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8811463B2 (en) * | 2012-02-02 | 2014-08-19 | Anritsu Corporation | Jitter measuring trigger generator, jitter measuring apparatus using the same, method of generating jitter measuring trigger, and method of measuring jitter |
| CN105162543B (en) * | 2015-08-17 | 2017-12-08 | 华北水利水电大学 | A kind of device and method for the test of SDH clock jitters |
| CN106357353A (en) * | 2016-10-19 | 2017-01-25 | 柳州达迪通信技术股份有限公司 | Detection method and system for E1 link phase jitter |
| CN113514678A (en) * | 2021-04-25 | 2021-10-19 | 深圳市夏光时间技术有限公司 | Jitter generation method and system for 2MHz/2Mbit/s signal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4975634A (en) * | 1989-04-07 | 1990-12-04 | General Signal Corporation | Jitter measurement device |
| CN1567120A (en) * | 2003-06-23 | 2005-01-19 | 华为技术有限公司 | Method and circuit for conducting real time test for single chip clock shaking |
| CN1910939A (en) * | 2004-01-23 | 2007-02-07 | 日出电讯公司 | Method and apparatus for measuring jitter |
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2009
- 2009-05-22 CN CN2009100846885A patent/CN101572579B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4975634A (en) * | 1989-04-07 | 1990-12-04 | General Signal Corporation | Jitter measurement device |
| CN1567120A (en) * | 2003-06-23 | 2005-01-19 | 华为技术有限公司 | Method and circuit for conducting real time test for single chip clock shaking |
| CN1910939A (en) * | 2004-01-23 | 2007-02-07 | 日出电讯公司 | Method and apparatus for measuring jitter |
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