CN1909240A - Indium gallium phosphorus enhanced/depletion type strain high electron mobility transistor material structure - Google Patents

Indium gallium phosphorus enhanced/depletion type strain high electron mobility transistor material structure Download PDF

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CN1909240A
CN1909240A CN 200510088979 CN200510088979A CN1909240A CN 1909240 A CN1909240 A CN 1909240A CN 200510088979 CN200510088979 CN 200510088979 CN 200510088979 A CN200510088979 A CN 200510088979A CN 1909240 A CN1909240 A CN 1909240A
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layer
indium
arsenic
gallium
indium gallium
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李海鸥
尹军舰
张海英
叶甜春
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Abstract

The utility model provides an indium gallium phosphorus strengthens/depletion type strain high electron mobility transistor material structure, it adopts indium gallium phosphorus/indium aluminium arsenic/indium gallium arsenic material structure, on semi-insulating gallium arsenide substrate material, uses the gradual growth technique to grow linear gradual indium aluminium gallium arsenic epitaxial layer as the buffer layer, then grows in proper order on the buffer layer: the indium-aluminum-arsenic layer, the indium-gallium-arsenic layer, the indium-aluminum-arsenic layer, the plane doping layer, the indium-aluminum-arsenic layer, the strained indium-gallium-phosphorus layer and the indium-gallium-arsenic layer; the ninth indium gallium arsenic epitaxial layer is used as a cap layer, the eighth strained indium gallium phosphorus epitaxial layer is used as a depletion type barrier layer, the seventh indium aluminum arsenic epitaxial layer is used as an enhancement type barrier layer, the fifth indium aluminum arsenic epitaxial layer is used as an isolation layer, and the fourth indium gallium arsenic layer is used as a channel layer.

Description

Indium, gallium, phosphor enhancing is strong/depletion type strain high electron mobility transistor material structure
Technical field
The invention belongs to the compound semiconductor technical field, be meant the material structure of the integrated indium gallium phosphorus of the basic monolithic of a kind of GaAs (GaAs)/indium aluminium arsenic/indium gallium arsenic (InGaP/InAlAs/InGaAs) enhancing/depletion type strain high electron mobility transistor (MHEMT) especially.
Background technology
High Electron Mobility Transistor devices (HEMT) has the highest up to now unit current gain cut-off frequency and lowest noise coefficient.Yet up to the present, in the circuit design of using the HEMT device, have only depletion type HEMT device to be used widely, for example traditional buffering field effect transistor logical circuit (BFL) or source coupling field effect tube logical circuit (SCFL) are applied in the actual circuit design, owing to adopt depletion type HEMT device in these circuit, consequence of bringing and weak point are exactly that circuit structure complexity and power consumption are big.
For overcoming above-mentioned weak point, directly coupling field effect tube logical circuit (DCFL) structure is more and more paid close attention to and is paid attention to, the DCFL circuit is made of enhancing/depletion type (E/D) HEMT device, up to now, it is one of best logical circuit technology in large scale integrated circuit design, is widely used in frequency divider, encircles on the circuit design such as device, microwave switch of shaking.Relative other logic circuit structure, the DCFL logic circuit structure has the advantage and the characteristics of highly significant, show its low-power consumption, at a high speed, aspects such as simplicity of design (as there not being level-shift) and single supply work.Yet its disadvantage is that low noise content and it are very sensitive to variations in threshold voltage, and therefore, the DCFL circuit of a superior performance is the threshold voltage of control device accurately.The difficult point part of integrated enhancement/depletion-type HEMT element manufacturing success just is---how to design transistor material structure and how accurately to control the making of enhancement device well in technology, this is the bottleneck of restriction DCFL circuit structure extensive use always.At present at home and abroad, strain gallium aluminium arsenic/(representational document is seen M.Tong to indium gallium arsenic pseudomorphic high electron mobility transistor structure to the enhancing of extensive use/depletion device typical structure in order to hang down, K.Nummila, J.-W.Seo.A.Ketterson andI.Adesida, " Process for enhancement/depletion-modeGaAs/InGaAs/AlGaAs pseudomorphic MODFETs using selective wet gaterecessing ", Electronics Letters 13 ThAugust 1992 Vol.28 No.17).With the low strained-channel In of GaAs base xGa 1-xAs (indium component x<=0.22) HEMT device is compared, and the GaAs high strained-channel MHEMT device of base (indium component x>0.22) is owing to the performance that can significantly improve device, as DC performance (leaking saturation current and mutual conductance), microwave property (f TAnd f Max), low-frequency noise (Hooge parameter) and high-frequency noise (minimal noise coefficient and noise gain), and obtain more concern and attention.Low counterfeit high electron transistor (PHEMT) the device typical material structure of joining of strained-channel of the monolithic-integrated enhancement/depletion-type that is widely used at present, has reported is as shown in table 1.
Table 1: the low strained-channel PHEMT material structure signal of existing typical GaAs base monolithic-integrated enhancement/depletion-type table.
Sequence number Material Mol ratio % Thickness Doping content
12 Heavy doping GaAs 300 dusts Doped source (Si) 5.0E+18cm-3
11 AlAs undopes 15 dusts
10 Al undopes xGa 1-xAs 0.17 150 dusts
9 AlAs undopes 15 dusts
8 Al undopes xGa 1-xAs 0.17 200 dusts
7 Plane doping Si3.0E+12cm-2
6 Al undopes xGa 1-xAs 0.17 20 dusts
5 In undopes xGa 1-xAs 0.20 170 dusts
4 GaAs undopes 500 dusts
3 Al undopes xGa 1-xAs 0.45 50 dusts
2 Resilient coating
1 Semi-insulating substrate GaAs (100)
This transistor material structure mainly has following several characteristics:
1, utilizes Al xGa 1-xAs/In yGa 1-yConduction band between two kinds of materials of As is poor, forms two-dimensional electron gas (2DEG), Al in having the InGaAs raceway groove epitaxial loayer of low energy gap, high electron mobility characteristic xGa 1-xThe component X=0.17 of Al in the As epitaxial loayer, In yGa 1-yThe component Y=0.2 of In belongs to low strained-channel in the As raceway groove epitaxial loayer, and their conduction band difference is about 0.27eV, and enhancing all is Al with the barrier layer of depletion type PHEMT device xGa 1-xThe As epitaxial loayer.
2, since strengthen with depletion type PHEMT element manufacturing in very key also be that one of difficult point is the consistency of maintenance enhancing/depletion type threshold voltage, therefore in typical case's enhancing and depletion type PHEMT device material structure, keep the consistency of threshold voltage as enhancing/depletion type corrosion cutoff layer by two thin layer of aluminum arsenic (AlAs) epitaxial loayers of growing.
Summary of the invention
The objective of the invention is to design the integrated high indium component indium gallium phosphorus of a kind of gallium arsenide base monolithic/indium aluminium arsenic/indium gallium arsenic enhancing/depletion type strain high electron mobility transistor (MHEMT) material structure, to overcome the some shortcomings of current material structure.
For achieving the above object, technical solution of the present invention provide a kind of indium, gallium, phosphor enhancing strong/depletion type strain high electron mobility transistor material structure, it adopts indium gallium phosphorus/indium aluminium arsenic/indium gallium arsenic material structure, on the semi-insulating GaAs backing material, use gradual growing technology and grow linear gradual indium algaas epitaxial layer, order growth on resilient coating then: indium aluminum arsenic layer, ingaas layer, indium aluminum arsenic layer, plane doping layer, indium aluminum arsenic layer, strain indium gallium phosphorus layer, ingaas layer as resilient coating; Wherein, the 9th layer of indium gallium arsenic epitaxial loayer is as the cap layer, and the 8th ply strain indium gallium phosphorus epitaxial loayer is as the barrier layer of depletion type, and layer 7 indium aluminium arsenic epitaxial loayer is as the barrier layer of enhancement mode, layer 5 indium aluminium arsenic epitaxial loayer is as separator, and the 4th layer of indium gallium arsenic is as channel layer.
Described transistor material structure, each layer of its described order growth on the gradual indium algaas epitaxial layer of linearity is for the indium aluminum arsenic layer that undopes, the ingaas layer that undopes, the indium aluminum arsenic layer that undopes, plane doping layer, the indium aluminum arsenic layer that undopes, strain indium gallium phosphorus layer, heavy doping ingaas layer undope.
Described transistor material structure, its described the 9th layer of indium gallium arsenic epitaxial loayer is that the n type is highly doped, indium component X=0.53 ± 0.05 wherein, al composition Y=0.47 ± 0.05, X+Y=1, thickness is 100 ± 10 dusts, is doped to silicon doping, concentration is (1.0 ± 0.1) * 10 19Cm -3The barrier layer of depletion type MHEMT is the 8th layer of strain indium gallium phosphorus epitaxial loayer that undopes, indium component X=0.8 ± 0.05 wherein, and al composition Y=0.2 ± 0.05, X+Y=1, thickness are 100 ± 10 dusts; The barrier layer of enhancement mode MHEMT is the layer 7 algaas epitaxial layer that undopes, indium component X=0.52 ± 0.05 wherein, and al composition Y=0.48 ± 0.05, X+Y=1, thickness are 100 ± 10 dusts; The plane doping layer is silicon doping, and doping content is designed to (1.5 ± 0.1) * 10 12Cm -2Channel layer is the 4th layer of indium gallium arsenic epitaxial loayer that undopes, indium component X=0.53 ± 0.05 wherein, and al composition Y=0.47 ± 0.05, X+Y=1, thickness are 200 ± 10 dusts.
The present invention has very remarkable advantages with respect to existing typical monolithic-integrated enhancement/depletion-type PHEMT material structure, is mainly reflected in following four aspects:
1) high indium component I n yAl 1-y-As (indium component Y=0.52) compares Al xGa 1-xAs (indium component X=0.17) has bigger energy gap, simultaneously high indium component I n xGa 1-xAs (indium component Y=0.53) is than low indium component I n yGa 1-yAs (indium component X=0.2) has littler energy gap, so In yAl 1-yAs/In xGa 1-xConduction band difference between the As heterojunction is bigger.In yAl 1-yAs/In xGa 1-xConduction band difference between the As is about 0.47eV, than typical PHEMT material structure Al yGa 1-yAs/In xGa 1-xThe conduction band difference 0.27eV of As is much bigger.Like this at In yAl 1-yAs/In xGa 1-xForm higher potential barrier between the As, make 2DEG be strapped in In better xGa 1-xThe As channel layer.
2) adopt high indium component strain In 0.8Ga 0.2P epitaxial loayer rather than AlGaAs epitaxial loayer are as the barrier layer of depletion type.InGaP has two advantages as the barrier layer of depletion type MHEMT: a) InGaP/InAlAs has very high corrosion selection ratio to some corrosive liquid, and it both can be used as the barrier layer of depletion type, can be used as the corrosion cutoff layer again, had double action; B) it does not have deep energy level to produce (as the DX center) and has low surface potential;
3) with respect to typical PHEMT device material structure, because the InGaP epitaxial loayer has dual effect, do not need specially to design the corrosion cutoff layer, reduce the difficulty of material growth and helped improving the quality of material growth.
4) owing to adopt In 0.3Ga 0.47The As epitaxial loayer is as the cap layer, and its low forbidden band makes device can form good ohmic with highly doped rate characteristic and contacts.
Description of drawings
Fig. 1: the present invention's enhancing/depletion type MHEMT device architecture schematic diagram;
Fig. 2: enhancement mode MHEMT device simulation direct current transconductance characteristic curve chart of the present invention;
Fig. 3: depletion type MHEMT device simulation direct current transconductance characteristic curve chart of the present invention.
Embodiment
A kind of indium, gallium, phosphor enhancing is strong/depletion type strain high electron mobility transistor material structure, as shown in table 2, it adopts indium gallium arsenic/indium gallium phosphorus/indium aluminium arsenic/indium gallium arsenic material structure, on the semi-insulating GaAs backing material, use gradual growing technology and grow the gradual indium algaas epitaxial layer of second layer line as resilient coating, thickness is 1.5 μ m, order growth on resilient coating then: the 3rd layer of indium aluminum arsenic layer that undopes, and thickness is 200 dusts; The 4th layer of ingaas layer that undopes, indium component X=0.53 ± 0.05 wherein, al composition Y=0.47 ± 0.05, X+Y=1, thickness are 200 ± 10 dusts; The layer 5 indium aluminum arsenic layer that undopes, thickness is 40 dusts; Layer 6 plane doping layer is silicon doping, and concentration is designed to (1.5 ± 0.1) * 10 12Cm -2The layer 7 indium aluminum arsenic layer that undopes, indium component X=0.52 ± 0.05 wherein, al composition Y=0.48 ± 0.05, X+Y=1, thickness are 100 ± 10 dusts; The 8th layer of strain indium gallium phosphorus layer that undopes, indium component X=0.8 ± 0.05 wherein, gallium component Y=0.2 ± 0.05, X+Y=1, the thickness of strain indium gallium phosphorus epitaxial loayer selects to have considered In 0.86Ga 0.2As and the 9th layer of In 0.53Ga 0.47As epitaxial loayer and layer 7 In 0.52Al 0.48Nearly 1.4% lattice mismatch between the As epitaxial loayer, design thickness are 100 ± 10 dusts, less than its strain thickness; The 9th layer of heavy doping ingaas layer, for the n type highly doped, indium component X=0.53 ± 0.05 wherein, al composition Y=0.47 ± 0.05, X+Y=1, thickness is 100 ± 10 dusts, is doped to silicon doping, concentration is (1.0 ± 0.1) * 10 19Cm -3Wherein, the 9th layer of indium gallium arsenic epitaxial loayer is as the cap layer, and the 8th ply strain indium gallium phosphorus epitaxial loayer is as the barrier layer of depletion type, and layer 7 indium aluminium arsenic epitaxial loayer is as the barrier layer of enhancement mode, layer 5 indium aluminium arsenic epitaxial loayer is as separator, and the 4th layer of indium gallium arsenic is as channel layer.
Table 2: GaAs base monolithic-integrated enhancement/depletion-type MHEMT material structure signal table of the present invention.
Sequence number Material Mol ratio % Thickness (dust) Doping content
9 Heavy doping In xGa 1-xAs 0.53 100 dusts Doped source (Si) 1.0E+19cm-3
8 In undopes xGa 1-xP 0.8 100 dusts
7 In undopes xAl 1-xAs 0.52 100 dusts
6 Plane doping Si 1.5E+12cm- 2
5 In undopes xAl 1-xAs 0.52 40 dusts
4 In undopes xGa 1-xAs 0.53 200 dusts
3 In undopes xAl 1-xAs 0.52 500 dusts
2 Linear gradual growth i-InAlGaAs 1.5 μ m
1 Semi-insulating substrate GaAs (100)
At transistor material structure of the present invention, the relation between each epitaxy layer thickness of material structure, doping content, schottky barrier height and the transistorized threshold voltage has been carried out Theoretical Calculation and analysis, simulated the DC characteristic of material structure.The device threshold voltage Theoretical Calculation is as follows: V T = φB - ΔEc - qNsd ϵ , V TBe device threshold voltage, φ B is a schottky barrier height, and Δ Ec is that the heterojunction conduction band is poor, and q is an electron charge, and d is the thickness of barrier layer to the plane doping layer, and Ns is a plane doping concentration, and ε is a dielectric constant.Material structure relevant parameter and Theoretical Calculation threshold voltage are as shown in table 3.
Table 3: material structure relevant parameter of the present invention and threshold voltage calculate the signal table.
The material structure relevant parameter Enhancement mode Depletion type
Plane doping concentration Ns Si 1.5E+12cm-2 Si 1.5E+12cm-2
The barrier layer epitaxial loayer InAlAs InGaP
Schottky barrier height φ B 0.75~0.8eV 0.6~0.65eV
Thickness d
100 dusts 200 dusts
DIELECTRIC CONSTANT 12.2 11.9
Threshold voltage V T 0.05~0.1V -0.45~-0.6V
For further verifying the feasibility of material structure of the present invention, adopt heterojunction device material structure simulation softward to simulate heterojunction and can be with relation, simulated the direct current transconductance characteristic of device in conjunction with the setting of device geometrical structure parameter (grid length, grid width, the following distance of grid) and technological parameter (contact resistance, metal semiconductor junction barrier height) to the 2DEG layer.Fig. 1 strengthens/depletion type MHEMT device schematic diagram for material structure of the present invention.In the device property simulation, set the long L=1.0 μ of enhancing/depletion type MHEMT device grid m, grid width W=100 μ m, it is 5.0 μ m that spacing is leaked in the source, it highly is 0.65eV that the metal semiconductor junction structure is built, contact resistance is 2.5 Ω .mm, and simulation enhancing/depletion type direct current transconductance characteristic curve as shown in Figures 2 and 3.It is 0V that analog result draws the enhancement mode threshold voltage, and its maximum transconductance is 300mS/mm; The depletion type threshold voltage is-0.5V that its maximum transconductance is 250mS/mm.

Claims (3)

1, a kind of indium, gallium, phosphor enhancing strong/depletion type strain high electron mobility transistor material structure, it is characterized in that, adopt indium gallium phosphorus/indium aluminium arsenic/indium gallium arsenic material structure, on the semi-insulating GaAs backing material, use gradual growing technology and grow linear gradual indium algaas epitaxial layer, order growth on resilient coating then: indium aluminum arsenic layer, ingaas layer, indium aluminum arsenic layer, plane doping layer, indium aluminum arsenic layer, strain indium gallium phosphorus layer, ingaas layer as resilient coating; Wherein, the 9th layer of indium gallium arsenic epitaxial loayer is as the cap layer, and the 8th ply strain indium gallium phosphorus layer epitaxial loayer is as the barrier layer of depletion type, and layer 7 indium aluminium arsenic epitaxial loayer is as the barrier layer of enhancement mode, layer 5 indium aluminium arsenic epitaxial loayer is as separator, and the 4th layer of indium gallium arsenic is as channel layer.
2, transistor material structure as claimed in claim 1, it is characterized in that, each layer of described order growth on the gradual indium algaas epitaxial layer of linearity is for the indium aluminum arsenic layer that undopes, the ingaas layer that undopes, the indium aluminum arsenic layer that undopes, plane doping layer, the indium aluminum arsenic layer that undopes, strain indium gallium phosphorus layer, heavy doping ingaas layer undope.
3, transistor material structure as claimed in claim 1 or 2, it is characterized in that, described the 9th layer of indium gallium arsenic epitaxial loayer is that the n type is highly doped, indium component X=0.53 ± 0.05 wherein, al composition Y=0.47 ± 0.05, X+Y=1, thickness are 100 ± 10 dusts, be doped to silicon doping, concentration is (1.0 ± 0.1) * 10 19Cm -3The barrier layer of depletion type MHEMT is the 8th layer of strain indium gallium phosphorus epitaxial loayer that undopes, indium component X=0.8 ± 0.05 wherein, and al composition Y=0.2 ± 0.05, X+Y=1, thickness are 100 ± 10 dusts; The barrier layer of enhancement mode MHEMT is the layer 7 algaas epitaxial layer that undopes, indium component X=0.52 ± 0.05 wherein, and al composition Y=0.48 ± 0.05, X+Y=1, thickness are 100 ± 10 dusts; The plane doping layer is silicon doping, and doping content is designed to (1.5 ± 0.1) * 10 12Cm -2Channel layer is the 4th layer of indium gallium arsenic epitaxial loayer that undopes, indium component X=0.53 ± 0.05 wherein, and al composition Y=0.47 ± 0.05, X+Y=1, thickness are 200 ± 10 dusts.
CN 200510088979 2005-08-04 2005-08-04 Indium gallium phosphorus enhanced/depletion type strain high electron mobility transistor material structure Pending CN1909240A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446957A (en) * 2010-10-13 2012-05-09 稳懋半导体股份有限公司 Heterostructure field effect transistor and manufacturing method thereof
CN102969341A (en) * 2012-11-09 2013-03-13 中国电子科技集团公司第五十五研究所 Nitride high electronic mobility transistor extension structure of component gradually-changed ALyGal-yN buffer layer
CN109742143A (en) * 2018-12-29 2019-05-10 苏州汉骅半导体有限公司 Integrated enhanced and depletion type HEMT and its manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446957A (en) * 2010-10-13 2012-05-09 稳懋半导体股份有限公司 Heterostructure field effect transistor and manufacturing method thereof
CN102446957B (en) * 2010-10-13 2013-09-25 稳懋半导体股份有限公司 Heterostructure field effect transistor and manufacturing method thereof
CN102969341A (en) * 2012-11-09 2013-03-13 中国电子科技集团公司第五十五研究所 Nitride high electronic mobility transistor extension structure of component gradually-changed ALyGal-yN buffer layer
CN109742143A (en) * 2018-12-29 2019-05-10 苏州汉骅半导体有限公司 Integrated enhanced and depletion type HEMT and its manufacturing method

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