CN1897238A - Chip packing structure and method - Google Patents
Chip packing structure and method Download PDFInfo
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- CN1897238A CN1897238A CN 200510085936 CN200510085936A CN1897238A CN 1897238 A CN1897238 A CN 1897238A CN 200510085936 CN200510085936 CN 200510085936 CN 200510085936 A CN200510085936 A CN 200510085936A CN 1897238 A CN1897238 A CN 1897238A
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- chip package
- packing
- package structure
- conductive layer
- wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
A wafer sealing structure and the sealing method: sets the adhere layer, the conducting layer and the metal layer on the panel in turn, forms the perforative design groove on the conducting layer and the metal layer, divides the metal layer into one or several wafer loading areas and several conducting point areas that is isolation or connection with each other, forms a wafer on every wafer loading area, wafer electric connect with the conducting point area, uses the sealing colloid to cover on the conducting layer, the metal layer and the wafer, removes the loading board, processes incision that every wafer or the wafer group is as the unit, forms several wafer sealing structures. The invention can improve the trustiness of the sealing process, and reduce the height of the seal.
Description
Technical field
The present invention is relevant for a kind of chip package structure and method for packing thereof, particularly about a kind of more smooth, chip package structure and method for packing thereof that packaging height is lower.
Background technology
Semiconductor science and technology is along with product functions such as computer and network communication promote rapidly; the demand that therefore must possess diversification, portability and frivolous microminiaturization; make wafer package process industry can break away from conventional art and develop towards high precision processing procedures such as high power, high density, light, thin and microminiaturizations; in addition; Electronic Packaging (ElectronicsPackaging) more need possess characteristics such as high-reliability, thermal diffusivity be good; with as transmitting signals, electric energy, and provide good heat radiation approach and effects such as structural defence and support.
Volume is little, speed is fast and highdensity semiconductor encapsulated element has become a kind of trend, adds the more and more big result of consumed power of potted element because of making, and it is quite important to make that the heat dissipation problem of potted element becomes.
And when circuit board manufacturing, be that each element is welded on the circuit board one by one at present, therefore when producing an electronic component, the coplanarity on entire circuit plate surface has the influence of certain degree to the reliability of electronic component.
In view of this, the present invention is directed to above-mentioned puzzlement, propose a kind of chip package structure and method for packing thereof, to improve above-mentioned shortcoming.
Summary of the invention
Main purpose of the present invention, be to provide a kind of method for packing of chip package structure, it utilizes a support plate as support component earlier, so that potted element is provided with thereon one by one, in step thereafter, support plate is removed again, make encapsulating structure more firm, and improve the reliability in the encapsulation process, more because of the more smooth characteristic of tool, and can apply to the circuit board strict to copline.
Another object of the present invention is to provide a kind of chip package structure and method for packing thereof, it can constantly upwards pile up in regular turn and form a stacked structure, to be made into multilayer circuit board, has multipurpose, applicable to multiple semiconductor packages.
A further object of the present invention is to provide a kind of chip package structure and method for packing thereof, it is installed on wafer in the crystal chip bearing district of metal level, with the raising radiating effect, and because of a plurality of conductive junction points of tool, and can be when the tool radiating effect, the while is with the function of high number of pins.
Another purpose of the present invention is to provide a kind of support plate that reduces the chip package structure height, and it can provide extremely several microns support plate of a thin thickness, is hundreds of microns with respect to present support plate thickness, therefore can significantly reduce overall packaging height.
For achieving the above object, the present invention proposes a kind of method for packing of chip package structure, one support plate at first is provided, from bottom to top be sequentially provided with the above conductive layer of the above adhesion coating of one deck and one deck on its surface, then forming a patterned film and a film respectively on the conductive layer and under the support plate, and fill a metal level in patterned film, and with metal level or patterned film is mask, on support plate and run through adhesion coating and conductive layer forms several patterning grooves, and metal level is divided into several crystal chip bearing districts and several conductive junction point regions isolated mutually or that link mutually, then with patterned film and thin film removing, and in each crystal chip bearing district, form a wafer or a plurality of wafer, and wafer forms with conductive junction point region respectively and electrically connects, then on adhesion coating, form a packing colloid, and the coated with conductive layer, metal level and wafer then remove support plate, and with each wafer or wafer set is that unit cuts, to form several chip package structures.
At above-mentioned method for packing, the present invention proposes a kind of chip package structure in addition, comprise a wafer carrier and several conductive junction point isolated mutually or that link mutually, wafer carrier and several conductive junction points are made up of a conductive layer and a metal level, and conductive layer and metal level are formed with a patterning groove that runs through, to be separated out wafer carrier and conductive junction point, and wafer carrier is provided with a wafer or a plurality of wafer, itself and conductive junction point form and electrically connect, and utilize a packing colloid to be formed on the upper surface of conductive layer, to envelope metal level and wafer.
Illustrate in detail below by the specific embodiment conjunction with figs., when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached.
Description of drawings
Fig. 1 (a) is each step structure cutaway view of the method for packing of chip package structure of the present invention to Fig. 1 (h).
Fig. 2 is the structure cutaway view of chip package structure of the present invention.
Fig. 3 (a) is each step structure cutaway view of another embodiment of the method for packing of chip package structure of the present invention to Fig. 3 (i).
Fig. 4 offers the structure cutaway view of several grooves for support plate of the present invention.
Fig. 5 is that adhesion coating of the present invention and conductive layer are arranged at the structure cutaway view in the groove.
Fig. 6 to Fig. 9 is the structure cutaway view that utilizes the different embodiment of the made chip package structure of Fig. 5.
Fig. 7 fills up the structure cutaway view of groove for adhesion coating of the present invention and conductive layer.
Fig. 8 to Figure 11 is the structure cutaway view that utilizes the different embodiment of the made chip package structure of Fig. 7.
Embodiment
Below by different embodiment wafer package method proposed by the invention and made encapsulating structure thereof are described.
Fig. 1 (a) is depicted as each step structure cutaway view of the method for packing of chip package structure of the present invention to Fig. 1 (h), at first as Fig. 1 (a), one support plate 20 is provided, its material is a metal, glass, pottery or macromolecule material, on these support plate 20 surfaces, from bottom to top be sequentially provided with an adhesion coating 22 and a conductive layer 24, wherein, support plate 20, adhesion coating 22 and conductive layer 24 can be integrated commercialization structure, perhaps, can be divided into three steps carries out, utilize bonding method earlier, printing, rotary coating, sputtering method, non-electrolytic plating method or galvanoplastic, as sputtering method adhesion coating 22 is arranged on the support plate 20, utilize bonding method again, printing, sputtering method, non-electrolytic plating method or galvanoplastic are arranged on conductive layer 24 on the adhesion coating 22, and the material of adhesion coating 22 is a metal, conduction material or polymer substance.
Then shown in Fig. 1 (b), on conductive layer 24 and support plate utilize for 20 times image transfer to form a patterned film 26 and a film 28 respectively, and as Fig. 1 (c), filler metal level 30 is in patterned film 26, remove patterned film 26 and film 28, and be mask (Mask) with metal level 30, on support plate 20 and run through adhesion coating 22 and conductive layer 24 and utilize etching method or control molding mode deeply and form several patterning grooves 32, and metal level 30 divided into several crystal chip bearing districts and several conductive junction point region isolated mutually or that link mutually, with as wafer carrier 34 and conductive junction point 36, shown in Fig. 1 (d).
Then carry out the step of Fig. 1 (e), form more than one wafer 38 in each wafer carrier 34, and wafer 38 utilizes several materials to form electric connection for the lead-in wire 40 of metal with conductive junction point 36 respectively, and on adhesion coating 22, form a packing colloid 42, and coated with conductive layer 24, metal level 30 and wafer 38 or adhesion coating 22, then as Fig. 1 (f), support plate 20 is removed, to form the structure shown in Fig. 1 (g), and along the dotted line shown in the figure, with each wafer 38 or wafer set is that unit cuts, to form several chip package structures shown in Fig. 1 (h).
In this, describe the chip package structure of Fig. 1 (h) again in detail, this chip package structure comprises a wafer carrier 34, and be provided with several conductive junction points 36 isolated mutually or that link mutually around, and wafer carrier 34 and conductive junction point 36 are by an adhesion coating 22, one conductive layer 24 and a position metal level 30 are thereon formed, and adhesion coating 22, conductive layer 24 and metal level 30 are formed with a patterning groove 32 that runs through, to be separated out wafer carrier 34 and conductive junction point 36, and on wafer carrier 34, be provided with more than one wafer 38, and form electric connection with conductive junction point 36, and have a packing colloid 42 to be formed on the upper surface of adhesion coating 22, to envelope conductive layer 24, metal level 30 and wafer 38 or adhesion coating 22.
And before or after the cutting step of Fig. 1 (g), several projections 44 also can be set in adhesion coating 22 times, and encapsulate colloid 42 bottoms certainly and expose, to form r structure as shown in Figure 2, be soldered on other electronic installations to utilize projection 44 to provide, except that projection 44 was set, all the other elements of Fig. 2 were not added to give unnecessary details in this with the structure of above-mentioned Fig. 1 (h).
Fig. 3 (a) is each step structure cutaway view of another method for packing of the present invention to Fig. 3 (i); Fig. 3 (a) is identical to Fig. 1 (c) with above-mentioned Fig. 1 (a) to the method for Fig. 3 (c); so do not add to give unnecessary details in this; and after the step that metal level 30 is filled in the patterned film 26; remove patterned film 26 and film 38; shown in Fig. 3 (d); utilize the image transfer method to form a protective layer 46 and on conductive layer 24, reach support plate 20 times; and being positioned at protective layer 46 on the conductive layer 24 coats respectively and is filled in metal level 30; to utilize etching method or to control molding mode deeply on the support plate 20 and after running through adhesion coating 22 and conductive layer 24 formation patterning grooves 32; protective layer 46 is removed; and partially conductive layer 24 surface are exposed; shown in Fig. 3 (e); go forward side by side Fig. 3 (f) behind the Xingqi to the step of Fig. 3 (h); to form the chip package structure shown in Fig. 3 (i); shown in same Fig. 1 of this structure (h); unique difference is that metal level 30 is when forming the step of patterning groove 32; partially conductive layer 24 surface are exposed; and before and after cutting step; projection 44 also can be set in adhesion coating 22 times, not add to give unnecessary details in this.
Wherein, above-mentioned support plate 20 also can utilize dark control moulding or etching method to offer several grooves 48 earlier, as shown in Figure 4, and adhesion coating 22 and conductive layer 24 are arranged in the groove 48, as shown in Figure 5, to utilize the method for packing of Fig. 1 (b) to Fig. 1 (g), through forming patterned film 26 and film 28, and form several patterning grooves 32, and remove patterned film 26 and film 28, wafer 38 is set again, lead-in wire 40 and packing colloid 42, and remove support plate 20, be that unit cuts with each wafer or wafer set 38 again, to form as Fig. 6 to encapsulating structure shown in Figure 7; And utilize Fig. 3 (b) to the method for packing shown in Fig. 3 (h), through forming patterned film 26 and film 28, and formation protective layer 46, and form several patterning grooves 32, and remove protective layer 46, patterned film 26 and film 28, wafer 38, lead-in wire 40 and packing colloid 42 are set again, and remove support plate 20, be that unit cuts with each wafer or wafer set 38 again, to form as Fig. 8 to encapsulating structure shown in Figure 9; To encapsulating structure shown in Figure 9, part adhesion coating 22, conductive layer 24 and part metals layer 30 expose from encapsulating colloid 42 bottoms at Fig. 6.
Perhaps, support plate 20 utilizes dark control moulding or etching method to offer several grooves 48 earlier, as shown in Figure 4, adhesion coating 22 or metal level 24 can be filled up groove 48, as shown in figure 10, utilize two method for packing of above-mentioned Fig. 1 (b) again, to form respectively as Figure 11 encapsulating structure shown in Figure 14 extremely to Fig. 1 (g) and Fig. 3 (b) to Fig. 3 (h), to encapsulating structure shown in Figure 14, part adhesion coating 22 and conductive layer 24 expose from encapsulating colloid 42 bottoms at Figure 11.
In addition, in above-mentioned all method for packing, also can be when removing carrier 20, in the lump adhesion coating 22 is removed, so that each encapsulating structure does not have the structure of adhesion coating 22, and comprise a wafer carrier 34, and be provided with several conductive junction points 36 isolated mutually or that link mutually around, and wafer carrier 34 and conductive junction point 36 are made up of a conductive layer 24 and a position metal level 30 thereon, and conductive layer 24 and metal level 30 are formed with a patterning groove 32 that runs through, to be separated out wafer carrier 34 and conductive junction point 36, and on wafer carrier 34, be provided with more than one wafer 38, and form with conductive junction point 36 and to electrically connect, and have a packing colloid 42 to be formed on the upper surface of conductive layer 24, to envelope metal level 30 and wafer 38; And can repeat the step before wafer 38 is installed,, the step behind the wafer 38 is installed again with behind formation one stacked structure.
The present invention proposes a kind of method for packing of chip package structure, in encapsulation process, utilize a support plate as support component, have adhesion coating and conductive layer on the support plate, or only be provided with conductive layer, and potted element is set one by one thereon, circuit with pattern-makingization, in encapsulation step thereafter, support plate is removed again, make that encapsulating structure is more firm in whole encapsulation process, and improved the reliability of encapsulation process, and utilize support plate to obtain a very complete surface, in order to follow-up encapsulation procedure, to apply to the circuit board strict to outward appearance; And this chip package structure can repeat the step before wafer is installed, and forms a stacked structure constantly upwards to pile up in regular turn, being made into multilayer circuit board, so that the tool multipurpose, applicable to multiple semiconductor packages; And, make radiating effect improve because of wafer is installed on metal level.
The above is by embodiment characteristics of the present invention to be described, its purpose is familiar with this technical field person and can be understood content of the present invention and implement according to this making, and non-limiting claim of the present invention, the equivalence finished is modified so all other do not break away from disclosed spirit or revise, and must be included in the claim of the following stated.
Claims (52)
1. the method for packing of a chip package structure comprises:
One support plate is provided, from bottom to top is sequentially provided with at least one adhesion coating and at least one conductive layer on its surface;
Form a patterned film and a film respectively on this conductive layer and under this support plate;
Fill at least one metal level in this patterned film;
Remove this patterned film and this film;
On this support plate and run through this conductive layer and form several patterning grooves, and this metal level is divided into several crystal chip bearing districts and several isolated mutually conductive junction point regions;
In each this crystal chip bearing district, form at least one wafer, and these wafers form electric connection with these conductive junction point regions respectively;
On this adhesion coating, form a packing colloid, and coat this conductive layer, this metal level and these wafers;
Remove this support plate; And
With each this wafer or wafer set is that unit cuts, to form several chip package structures.
2. the method for packing of chip package structure as claimed in claim 1 is characterized in that, this support plate is by metal, glass, pottery or macromolecule material institute constitutor.
3. the method for packing of chip package structure as claimed in claim 1 is characterized in that, this support plate system is provided with several grooves, and this adhesion coating of part, this conductive layer of part and this metal level of part expose from this packing colloid bottom.
4. the method for packing of chip package structure as claimed in claim 3 is characterized in that, this adhesion coating and this conductive layer fill up these grooves.
5. the method for packing of chip package structure as claimed in claim 1 is characterized in that, this support plate, this adhesion coating and this conductive layer are formed in one.
6. the method for packing of chip package structure as claimed in claim 1 is characterized in that, this adhesion coating utilizes bonding method, coating, vapour deposition method, sputtering method, non-electrolytic plating method or galvanoplastic to be arranged on this support plate.
7. the method for packing of chip package structure as claimed in claim 1 is characterized in that, these conduction series of strata utilize bonding method, coating, vapour deposition method, sputtering method, non-electrolytic plating method or galvanoplastic to be arranged on this adhesion coating.
8. the method for packing of chip package structure as claimed in claim 1 is characterized in that, this patterned film and this film utilize image transfer to form.
9. the method for packing of chip package structure as claimed in claim 1 is characterized in that, these patterning grooves utilize laser carved method, etching method or control molding mode deeply and form.
10. the method for packing of chip package structure as claimed in claim 1; it is characterized in that; after this metal level is filled in the interior step of this patterned film; also comprise forming the step of a protective layer on this conductive layer or this metal level respectively, and the protective layer that is positioned on this conductive layer coats the metal level that is filled between this patterned film respectively.
11. the method for packing of chip package structure as claimed in claim 10 is characterized in that, after the step that these patterning grooves form, comprises that also one removes the step of these protective layers.
12. the method for packing of chip package structure as claimed in claim 1 is characterized in that, on this support plate and run through in the step that this conductive layer forms these patterning grooves, this conductive layer of part or this adhesion coating surface is exposed.
13. the method for packing of chip package structure as claimed in claim 1, it is characterized in that, being that unit cuts, before the step that forms these chip package structures with each this wafer, also comprise several projections being set under this adhesion coating, and the step exposed of this packing colloid bottom certainly.
14. the method for packing of chip package structure as claimed in claim 1, it is characterized in that, being that unit cuts, after the step that forms these chip package structures with each this wafer, also comprise several projections being set under this adhesion coating, and the step exposed of this packing colloid bottom certainly.
15. the method for packing as claim 13 or the 14th described chip package structure is characterized in that these projections utilize surface mounting method, print process, vapour deposition method, non-electrolytic plating method, galvanoplastic or sputtering method to be arranged under this adhesion coating.
16. the method for packing as claim 13 or the 14th described chip package structure is characterized in that the material of these projections is conductivity material or metal material.
17. the method for packing of chip package structure as claimed in claim 1 is characterized in that, the step before can repeating to be formed up to this wafer in each this crystal chip bearing district is to form a stacked structure.
18. the method for packing of chip package structure as claimed in claim 1 is characterized in that, these wafers utilize several projections and these conductive junction point regions to form respectively and electrically connect.
19. the method for packing of chip package structure as claimed in claim 1 is characterized in that, these wafers utilize several lead-in wires to form with these conductive junction point regions respectively and electrically connect.
20. the method for packing of chip package structure as claimed in claim 1 is characterized in that, on this support plate and run through this adhesion coating and this conductive layer to form these patterning grooves.
21. the method for packing of chip package structure as claimed in claim 1 is characterized in that, in the step that this support plate removes, this adhesion coating can be removed in the lump.
22. the method for packing of chip package structure as claimed in claim 1 is characterized in that, in the step that these patterning grooves form, is mask with this metal level.
23. the method for packing of chip package structure as claimed in claim 1, it is characterized in that, in the step that these patterning grooves form, form second patterned film and second film respectively on this conductive layer and this metal level and under this support plate, and be mask with this second patterned film, forming these patterning grooves, and after it forms, with this second patterned film and this second thin film removing.
24. the method for packing of a chip package structure comprises:
One support plate is provided, from bottom to top is sequentially provided with at least one conductive layer on its surface;
Form a patterned film and a film respectively on this conductive layer and under this support plate;
Fill at least one metal level in this patterned film;
Remove this patterned film and this film;
On this support plate and run through this conductive layer and form several patterning grooves, and this metal level is divided into several crystal chip bearing districts and several isolated mutually conductive junction point regions;
In each this crystal chip bearing district, form at least one wafer, and these wafers form electric connection with these conductive junction point regions respectively;
On this support plate, form a packing colloid, and coat this conductive layer, this metal level and these wafers;
Remove this support plate; And
With each this wafer or wafer set is that unit cuts, to form several chip package structures.
25. the method for packing of chip package structure as claimed in claim 24 is characterized in that, this support plate is provided with several grooves, and this conductive layer of part and this metal level of part expose from this packing colloid bottom.
26. the method for packing of chip package structure as claimed in claim 25 is characterized in that, this conductive layer can select to fill up or do not fill up these grooves.
27. the method for packing of chip package structure as claimed in claim 24 is characterized in that, this support plate and this conductive layer are formed in one.
28. the method for packing of chip package structure as claimed in claim 24 is characterized in that, this conductive layer utilizes bonding method, coating, vapour deposition method, sputtering method, non-electrolytic plating method or galvanoplastic to be arranged on this support plate.
29. the method for packing of chip package structure as claimed in claim 24 is characterized in that, this patterned film and this film utilize image transfer to form.
30. the method for packing of chip package structure as claimed in claim 24 is characterized in that, these patterning grooves utilize laser carved method, etching method or control molding mode deeply and form.
31. the method for packing of chip package structure as claimed in claim 24; it is characterized in that; after this metal level is filled in the interior step of this patterned film; also comprise forming the step of a protective layer on this conductive layer or this metal level respectively, and the protective layer that is positioned on this conductive layer coats the metal level that is filled between this patterned film respectively.
32. the method for packing of chip package structure as claimed in claim 31 is characterized in that, after the step that these patterning grooves form, comprises that also one removes the step of these protective layers.
33. the method for packing of chip package structure as claimed in claim 24 is characterized in that, on this support plate and run through in the step that this conductive layer forms these patterning grooves, this conductive layer surface of part is exposed.
34. the method for packing of chip package structure as claimed in claim 24, it is characterized in that, being that unit cuts, before the step that forms these chip package structures with each this wafer, also comprise several projections being set under this conductive layer, and the step exposed of this packing colloid bottom certainly.
35. the method for packing of chip package structure as claimed in claim 24, it is characterized in that, being that unit cuts, after the step that forms these chip package structures with each this wafer, also comprise several projections being set under this conductive layer, and the step exposed of this packing colloid bottom certainly.
36. the method for packing as claim 34 or 35 described chip package structures is characterized in that, these projections utilize surface mounting method, print process, vapour deposition method, non-electrolytic plating method, galvanoplastic or sputtering method to be arranged under this conductive layer.
37. the method for packing as claim 34 or 35 described chip package structures is characterized in that, these projection materials are conductivity material or metal material.
38. the method for packing of chip package structure as claimed in claim 24 is characterized in that, the step before can repeating to be formed up to this wafer in each this crystal chip bearing district is to form a stacked structure.
39. the method for packing of chip package structure as claimed in claim 24 is characterized in that, these wafers utilize several projections and these conductive junction point regions to form respectively and electrically connect.
40. the method for packing of chip package structure as claimed in claim 24 is characterized in that, these wafers utilize several lead-in wires to form with these conductive junction point regions respectively and electrically connect.
41. the method for packing of chip package structure as claimed in claim 24 is characterized in that, in the step that these patterning grooves form, is mask with this metal level.
42. the method for packing of chip package structure as claimed in claim 24, it is characterized in that, in the step that these patterning grooves form, form second patterned film and second film respectively on this conductive layer and this metal level and under this support plate, and be mask with this second patterned film, forming these patterning grooves, and after it forms, with this second patterned film and this second thin film removing.
43. a chip package structure comprises:
One wafer carrier;
Several conductive junction points, be arranged at this crystal chip bearing panel area and isolated mutually, and this wafer carrier and these conductive junction points are made up of at least one conductive layer and position at least one metal level thereon, and this conductive layer and this metal level are formed with a patterning groove that runs through, to be separated out this wafer carrier and these conductive junction points;
At least one wafer, it is arranged on this wafer carrier, and forms electric connection with these conductive junction points; And
One packing colloid, it is formed at the upper surface of this conductive layer, to envelope this metal level and this wafer.
44. chip package structure as claimed in claim 43 is characterized in that, this conductive layer is arranged on the adhesion coating.
45. chip package structure as claimed in claim 43 is characterized in that, these adhesion series of strata are made of metal, conduction material or polymer substance.
46. chip package structure as claimed in claim 43 is characterized in that, this conductive layer has several grooves, and this conductive layer of part and this metal level of part expose from this packing colloid bottom.
47. chip package structure as claimed in claim 46 is characterized in that, this conductive layer fills up these grooves.
48. chip package structure as claimed in claim 43 is characterized in that, this conductive layer material is conductive material or metal material.
49. chip package structure as claimed in claim 43 is characterized in that, this conductive layer has several protuberances down, and this conductive layer of part exposes from this packing colloid bottom.
50. chip package structure as claimed in claim 43 is characterized in that, this wafer utilizes several lead-in wires to be connected to these conductive junction points, electrically connects to form with these conductive junction points.
51. chip package structure as claimed in claim 50 is characterized in that, these lead-in wires are made of metal material.
52. chip package structure as claimed in claim 43 is characterized in that, also includes several projections, it is arranged under this conductive layer, and expose this packing colloid bottom certainly.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200510085936 CN1897238A (en) | 2005-07-13 | 2005-07-13 | Chip packing structure and method |
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|---|---|---|---|
| CN 200510085936 CN1897238A (en) | 2005-07-13 | 2005-07-13 | Chip packing structure and method |
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| CN1897238A true CN1897238A (en) | 2007-01-17 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103036401A (en) * | 2012-12-10 | 2013-04-10 | 上海空间电源研究所 | Power supply controller flatness ensuring method based on modular design |
| CN104217967A (en) * | 2013-05-31 | 2014-12-17 | 宏启胜精密电子(秦皇岛)有限公司 | Semiconductor device and manufacturing method thereof |
| CN104241145A (en) * | 2013-06-11 | 2014-12-24 | 英飞凌科技股份有限公司 | Method for Producing a Semiconductor Module by Using an Adhesion Carrier |
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2005
- 2005-07-13 CN CN 200510085936 patent/CN1897238A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103036401A (en) * | 2012-12-10 | 2013-04-10 | 上海空间电源研究所 | Power supply controller flatness ensuring method based on modular design |
| CN103036401B (en) * | 2012-12-10 | 2014-12-24 | 上海空间电源研究所 | Power supply controller flatness ensuring method based on modular design |
| CN104217967A (en) * | 2013-05-31 | 2014-12-17 | 宏启胜精密电子(秦皇岛)有限公司 | Semiconductor device and manufacturing method thereof |
| CN104241145A (en) * | 2013-06-11 | 2014-12-24 | 英飞凌科技股份有限公司 | Method for Producing a Semiconductor Module by Using an Adhesion Carrier |
| CN104241145B (en) * | 2013-06-11 | 2017-12-08 | 英飞凌科技股份有限公司 | Method for manufacturing semiconductor module in the case of using carrier is adhered to |
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