CN1222252A - Methods for mfg. semiconductor package - Google Patents
Methods for mfg. semiconductor package Download PDFInfo
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- CN1222252A CN1222252A CN97195605A CN97195605A CN1222252A CN 1222252 A CN1222252 A CN 1222252A CN 97195605 A CN97195605 A CN 97195605A CN 97195605 A CN97195605 A CN 97195605A CN 1222252 A CN1222252 A CN 1222252A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4941—Connecting portions the connecting portions being stacked
- H01L2224/49429—Wedge and ball bonds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A method of manufacturing a semiconductor chip package. A sacrificial layer (100) is used as a base to selectively form an array of conductive pads (110) such that a central region (114) is defined by the pads. A back surface (122) of a semiconductor chip is attached to the sacrificial layer within the central region between the pads so that the contact bearing surface (121) of the chip faces away from the sacrificial layer. The chip contacts are then electrically connected to the respective pads, typically by wire bonding wires (130) therebetween. A liquid encapsulant (140) is then deposited. The encapsulant is cured and the sacrificial layer is either completely removed or is selectively removed to expose a surface of the pads for electrical attachment to a PWB and the back surface of the chip for creating a direct thermal path from the chip to the PWB.
Description
Technical field
The present invention relates to micromodule, relate in particular to semiconductor die package.
Background technology
Semiconductor die package industry is the industry of a high competition, and the encapsulation company of the sector constantly competes, to reduce and the relevant cost of the chip of the chip that encapsulates them and other company (many time).Have similar or better result's encapsulating structure and technology in order to reduce packaging cost and to produce, and constantly study new technology.In addition, another pressure that advances comes from electronics industry, thereby it is to make the semiconductor maker can accelerate the speed of its chip and can not produce tangible Signal Degrade for the internal driving that reduces semiconductor packages, shortens processing and/or response time that the user of electronics finished product may need when requiring electronic product to carry out given task then.In addition, electronics industry also need be come packaged chip with little and little form factor, thereby packed chip occupies less space on the substrate (such as printed wiring board " PWB ") of supporting circuitization.The gauge that reduces packed chip also is important, thereby can be installed to less zone to the circuit of identical function, thereby makes the electronics finished product of acquisition lighter (size, weight etc.), with and/or can strengthen the disposal ability of product and not increase its size.Along with packed chip manufacturing gets more and more forr a short time, and more and more compacter on PWB, these chips can produce more heat and will receive more heat from adjacent chip.Therefore, it also is very important providing the thermal conducting path of being convenient to remove from the heat of packed chip.
For these considerations, in order to help convention, seldom use grid pin (pin) array (" PGA ") product (wherein big relatively conductive pin is attached to circuit on the PWB to the circuit in the particular semiconductor encapsulation) and other big encapsulation convention such as less encapsulation such as ball grid array (" BGA ") encapsulation.In the BGA encapsulation, generally replace above-mentioned pin, thereby reduce to encapsulate height from PWB with soldered ball, reduce the required area of packaged chip and further allow exquisiter encapsulation scheme.Generally, the soldered ball on the BGA device is placed the rule mesh trellis pattern (being called " area array " usually) that covers packed chip surface basically, or place every limit that is parallel to contiguous packed chip front side and the elongate strip of extending.
BGA and even littler chip scale (scale) encapsulation (" CSP ") technology refer to large-scale semiconductor packages, generally being used as middle Connection Step, so that the package terminal of chip contacts and exposure is interconnected such as silk bonding (wiredonding), beam lead, tape automated bonding (" TAB ") or similar interconnection process.So just mechanical attachment on the support substrates bonding weld zone (pad) but the preceding test component that obtained.Then, generally using standard tin-lead welding to connect interconnects the packed chip of BGA/CSP on PWB.
Some package design has satisfied above-mentioned industrial needs well.An example of this design is as 5,148, and 265 and 5,148, shown in No. 266 United States Patent (USP)s, comprise its content here by reference.In one embodiment, these patents have disclosed and have used chip carrier and provide saving cost and the low CSP of profile in conjunction with suitable layer.
In this area these are attempted, also want interconnection technique is done further to improve.
Summary of the invention
Method of the present invention has solved above-mentioned all problems.
In one embodiment of the invention, the method for manufacturing semiconductor die package comprises the step that at first preparation consumes (sacrificial) layer.Then, optionally form conductive welding region or terminals (post) array at the first surface top of exhaustion layer, thereby middle section is limited by these weld zones and between these weld zones.Then, semiconductor chip backside is appended to exhaustion layer in the middle section, thereby the contact of chip carrying (or active) surface separates with exhaustion layer.Generally, the small pieces connection adhesive with heat conduction arrives exhaustion layer to chip attach.Then, with the silk bonding apparatus chip contacts is connected electrically to each weld zone, to connect conductive wire betwixt.Then, the curable liquid dielectric sealant of deposit on the first surface of exhaustion layer, thus weld zone, wire and semiconductor chip are all sealed.Then, be sealant cures the self-supporting form.Generally, before the deposit sealant, mould is placed the first surface top of exhaustion layer, thereby can after sealant is injected mould and curing, make the outside (sealant) of encapsulation form required shape.Then, remove a part of exhaustion layer at least, with the bottom surface that exposes the weld zone and be that chip provides thermal conducting path.In certain embodiments, remove all exhaustion layers and the sealant that stays curing is connected the bottom of adhesive as encapsulation with small pieces.Can encapsulate many chips simultaneously, thereby make this technology can produce the chip of encapsulation separately, or produce multi-chip module after being used in the cutting operation of optionally cutting apart packed chip.
In another embodiment of the present invention, can between exhaustion layer and weld zone, place the polymer flake of dielectric, thereby conductive trace (trace) makes the weld zone make chip interconnect among the multicore sheet embodiment then.
In another embodiment of the present invention, can be on first surface etch consumption layer optionally, thereby make conductive welding region from wherein outstanding.Then, the back side of chip is appended between the weld zone in the middle section that is limited by the weld zone.The chip contacts silk is bonded to each weld zone, and the deposit sealant, thereby this sealant sealing chip, wire (wire) and weld zone.Then, remove exhaustion layer from a lateral erosion that exposes, thus can be directly near each weld zone and chip back.
Summary of drawings
Figure 1A illustrates the end view of making the method for semiconductor die package according to the present invention to 1G-1.
Fig. 1 D-2 illustrates the vertical view according to Fig. 1 D-1 of the present invention, wherein before the sealing step, several chip backs are bonded to exhaustion layer and are electrically connected with it.
Fig. 1 D-3 is the top of chip and exhaustion layer assembly.
Fig. 1 G-2 illustrate according to of the present invention after removing exhaustion layer the upward view of the embodiment of multicore sheet shown in Fig. 1 G-1.
Fig. 2 A illustrates the end view of making another method of semiconductor die package according to the present invention to 2E.
Fig. 2 F illustrates the vertical view according to the encapsulation of multicore sheet shown in Fig. 2 E of the present invention embodiment.
Fig. 3 illustrates the end view according to Chip Packaging of the present invention, and this encapsulation has from encapsulating the vertically extending projection of a side direction opposite side, and these projectioies are electrically connected with some weld zones at least.
Fig. 4 A illustrates the end view according to Chip Packaging of the present invention, and this is encapsulated in the electronic component that has separation in the sealed package above the chip.
Fig. 4 B illustrates the end view according to Chip Packaging of the present invention, and this encapsulation has second semiconductor chip that the back side is bonded to first chip, thereby the chip contacts of these two chips can interconnect with the weld zone.
Fig. 5 A illustrates the end view of making another method of semiconductor die package according to the present invention to 5H.
Fig. 5 I illustrates the end view to other embodiment of weld zone/terminal structure shown in the 5H according to Fig. 5 A of the present invention to 5J.
Fig. 6 A-1 illustrates end view according to another method of manufacturing semiconductor packages of the present invention to 6F-1, and this encapsulation has the through hole that extends from a side direction opposite side of encapsulation.
Fig. 6 A-2 illustrates the vertical view according to Fig. 6 A-1 of the present invention.
Fig. 6 B-2 illustrates the vertical view according to Fig. 6 B-1 of the present invention.
Fig. 6 F-2 illustrates the upward view according to Fig. 6 F-1 of the present invention.
Fig. 7 A illustrates according to the end view of manufacturing semiconductor chip of the present invention up to another method of sealing step to 7E.
Fig. 7 F-1 and 7G-1 illustrate first method according to Chip Packaging shown in the Fig. 7 of the finishing E of the present invention.
Fig. 7 F-2 and 7G-2 illustrate second method according to Chip Packaging shown in the Fig. 7 of the finishing E of the present invention.
Better embodiment of the present invention
Figure 1A-G illustrates the technology that is used to make cheap semiconductor die package according to of the present invention.Figure 1A illustrates the end view of exhaustion layer 100, and it has first surface 101 and second surface 102.Exhaustion layer 100 can comprise the mixture of conductive metallic material, polymeric material or conductive metallic material and polymeric material.Possible exhaustion layer examples of material comprises aluminium, copper, steel, iron, bronze, brass, polyimides, Polyetherimide (polyetherimide), fluoropolymer (fluropolymer) and alloys and mixts thereof.Though in certain embodiments, consuming sheet can be thicker or thinner; But in Figure 1A, exhaustion layer comprises having the uniform basically aluminium flake of about 100-200 micron thickness.
In Figure 1B, generally optionally form a plurality of weld zones 110, thereby weld zone 110 is placed and appended to the first surface 101 of exhaustion layer 100 by electroplating operations.Weld zone 110 is so arranged on the first surface 101 of exhaustion layer 100, thereby limits a middle section 114 between the weld zone of special package group.The weld zone can be arranged in delegation around middle section 114, perhaps becomes several row with the layout arrangement that is essentially grid array, and its example is shown in Fig. 1 D-3.Weld zone 100 in the present embodiment comprises the first bronze medal layer 111 and the second gold medal layer 112.Generally, the central barrier layer (not shown) that also has nickel to make is to guarantee copper and the not counterdiffusion mutually of gold layer.As described in detail below, gold layer 112 helps by the bonding that is carried out that is electrically connected to chip contacts.The height of weld zone 110 is not conclusive, as long as can form good being electrically connected to it.In certain embodiments, the weld zone can be similar to terminals.Other example of the weld zone material that allows comprises copper, nickel, gold, rhodium, platinum, silver and alloys and mixts thereof.Generally, in the few encapsulation of number of pins, weld zone 110 can be all identical from the height of exhaustion layer 100.Yet for the more encapsulation of number of pins or because other reason, weld zone 110 may be inequality from the height of exhaustion layer 100.The weld zone that higher weld zone 110 can be used for the outer ring guarantee between contact and the interior welds district electrical connecting wires not and the line electric short circuit between contact and the outside weldings district.This is applicable to the situation that chip contacts separates subtly, and perhaps the contact is arranged in the situation of an area array on the surface 121 of chip 100, and its example is shown in Fig. 1 D-3.
Shown in Fig. 1 C, then exhaustion layer 100 is coupled at the back side 122 of semiconductor chip 120 (or several chip), thereby the contact load-bearing surface 121 of chip 120 separates with exhaustion layer 100.Usually " back side bonding " that this layout is called semiconductor chip.Can use any suitable couplant 135 to carry out this back side bonding.Preferably use the small pieces of heat conduction to connect adhesive, thereby when additional heat sink as described below (heat sink), have the path of more heat conduction during thermal cycle, heat to be derived from chip.The example of this preferable adhesive material comprises epoxy, tin-plumbous welding compound, boron-nitride, the silicone that is filled with aluminium, alumina that is filled with silver and the epoxy that is filled with copper.
Then, shown in Fig. 1 D-1, the silk bonding by mutual is connected electrically to each weld zone 110 to each the chip contacts (not shown) on chip 120 surfaces 121.The form of ball formula bonding/stitch (or wedge bonding) bonding combination shown in the line 130 of silk bonding can adopt perhaps can be bonded to chip contacts and weld zone 110 to wire with stitch.Also available other convention is chip contacts and weld zone interconnection, such as TAB lead-in wire, electroforming beam lead etc.Fig. 1 D-2 illustrates the vertical view of Fig. 1 D-1.
Then, shown in Fig. 1 E, seal (or over-molded) this assembly by the molded technology of the semiconductor of routine with the dielectric material 140 that can flow and solidify, this assembly comprises first surface 101, weld zone 110, chip 120 and the electrical connecting wires of exhaustion layer 100.Dielectric material generally comprises employed filling or unfilled standard thermosetting or thermoplastic resin in this industry, such as epoxy resin, silicone resin or other plastic seal material.Then, the dielectric material full solidification.
Then, shown in Fig. 1 F, remove exhaustion layer 100.Here, use etching operation to remove exhaustion layer, thereby expose the bottom surface 113 of weld zone 110.The step of removing exhaustion layer 100 also exposes the heat conduction small pieces and connects adhesive 135.If desired, can more optionally remove exhaustion layer, providing additional feature, such as from the outstanding higher weld zone 110 of this package bottom, and/or be positioned at below the package bottom of being finished and give prominence to and append to the fin of chip back 122 from this bottom in the package bottom of finishing.
In Fig. 1 G-1, the chip of " cutting " each encapsulation or they are separated from each other.At this moment, can append to each bonding weld zone on the PWB to the exposure bottom surface 113 of weld zone 110.Forming this additional method is the bottom surface 113 that soldered ball 160 is connected to weld zone 110.Soldered ball 160 generally comprises tin and plumbous mixture, thereby but also can be coated with firm Metal Ball soldered ball 160 is not broken.Fig. 1 G-2 illustrates the upward view of multi-chip module embodiment of the present invention, wherein encapsulation is cut, thereby comprise more than one chip 120 in the encapsulation that obtains.Fig. 1 G-2 can also be the vertical view that does not cut encapsulation shown in Fig. 1 F.Though represent and describe above technology that with the embodiment that encapsulates an above chip simultaneously this technology also can be used for encapsulating an independently chip where necessary.
In another manufacture method shown in Fig. 2 A-E, shown in Fig. 2 A, exhaustion layer comprises dielectric polymer thin slice 100 ', this thin slice have 100 ' one lip-deep conductive layers 101 of the exhaustion layer of being positioned at ', conductive layer generally is the thin layer that copper becomes.Then, by etching away that conductive layer 101 ' is gone up undesired part and to conductive welding region 110 ' array carry out photoetching, thereby therebetween middle section 114 of weld zone 110 ' qualifying bit '.Middle section 114 ' in, also can by the weld zone shown in Fig. 2 B form photoetching process limit central conduction region 115 '.Then, as with reference to figure 1 in detail as described in, use the small pieces of heat conduction connect adhesive 135 ' semiconductor chip 120 ' the back side 122 ' be bonded to conduction region 115 '.Then, by therebetween the silk bonding wire 130 ', chip 120 ' exposed surface 121 ' on the chip contacts (not shown) be connected electrically to each weld zone 110 '.As mentioned above, then shown in Fig. 2 D, use the fluid sealant that is fit to this application to seal these elements, and sealant is cured.Then, by chemical etching or laser ablation operate remove partial polymer thin slice 100 ', thereby expose weld zone 110 ' and central conduction region 115 '.Then, can cut into encapsulation the encapsulation of each encapsulation or multicore sheet and they are connected to PWB with the welding compound of routine.Generally, central area 115 ' so be connected to PWB, thus can during encapsulation operation, import PWB to heat from chip.Shown in the plan view from above of Fig. 2 F, the encapsulation of multicore sheet can comprise the chip of the different size of carrying out difference in functionality.Additional dielectric polymer flake 100 ' this multi-chip module of permission have allow the conductive path 118 of at least some weld zones 110 ' interconnection in the multi-chip module ', thereby signal is transmitted in permission between chip.It should be noted that if do not need or do not want wiring layer described in this multicore sheet embodiment, then can be simply by the central conduction region that makes the thin slice chemolysis stay weld zone and exposure remove whole polymer flake 100 '.
Fig. 3 illustrates another embodiment of packed chip, and it is similar to the packed chip shown in Fig. 1 G-1.Yet in Fig. 3, conductive bumps 116 " is connected electrically to each weld zone 110 " and extends to the encapsulation 150 finished " upper surface 155 ", thereby exposes projection 116 " end face 117 ".This layout allow weld zone 110 ' bottom surface 113 ' be welded on the support substrates (such as PWB), also allow simultaneously to make another electronic component and/or semiconductor chip be connected electrically to packed chip 150 via projection 116 " end faces 117 of exposure " "; Like this, produced chip-stacked technology.Projection can begin from each weld zone to extend; Yet generally they are not to begin from all weld zones to extend.
In another embodiment, Fig. 4 A illustrates the microelectronic element 170 that appends on chip 120 " end view.Contact on this microelectronic element can be electrically connected between each contact on chip 120 and/or can be connected to each weld zone 110 .Shown in Fig. 4 B, when microelectronic element is second semiconductor chip 170 " ", to be bonded to the back side, the back side of second chip 170 " " surface of first chip 120 " ", can be connected electrically to the contact on second chip contact and/or each weld zone 110 " " on first chip 120 " ".Weld zone 110 " " itself also can be an electric interconnection.
Shown in Fig. 5 A-H, in yet another embodiment of the present invention, above-mentioned weld zone can have more the shape of " being similar to rivet ".Fig. 5 A illustrates aforesaid exhaustion layer, and it has first surface 201 and second surface 202.In Fig. 5 B, remove a plurality of pits from the first surface 201 of exhaustion layer 200.Preferably can be etched layer be used for exhaustion layer, thereby can in exhaustion layer 200, etch pit 203 with required form simply.But, use standard photolithography techniques to manifest and remove hole 205, thereby the generation and the location of control pit at second dielectric layer 204 of deposited on top such as the photo-patternable such as standard photo resist of the first surface 201 of exhaustion layer 200.
Then, shown in Fig. 5 C, conductive welding region 210 is plated in pit 203 and the hole 205, thereby produces the weld zone 210 that is similar to rivet.These weld zones 210 have close exhaustion layer 200 and the whole base flange 213 that appends to weld zone 211, back, from then the weld zone is outstanding from flange 213.Second flange 212 integrally appends to the other end of weld zone 211, back.Flange 212/213 all has the ledge zone beyond the diameter that extends to weld zone 211, back.Fig. 5 I-5J illustrates the weld zone structure according to another section of the present invention.In the embodiment shown in Fig. 5 I, the weld zone comprise base flange 213 ' and the back weld zone 211 '.Compare with the slyness/oval flange shown in other figure, the edge of the flange among Fig. 5 J is more square.Also can use the flange of other shape.
In Fig. 5 D, but remove the layer 204 and stay weld zone 210 of photo-patternable, thereby the weld zone in the particular group limits central area betwixt.Then, as described above in Example, chip 220 back sides are bonded to the first surface of exhaustion layer 200 with the small pieces connection adhesive 235 of heat conduction.Fig. 5 E illustrates the chip contacts (not shown) on the surface 221 with chip 200 and the electrical connecting wires 230 of weld zone 210 interconnection.Two ends wiry stitch is bonded to weld zone 210 to a use silk bonding apparatus and chip contacts forms electrical connecting wires 230.Stitch is bonded in and has produced being electrically connected of low profile (profile) between contact and the weld zone, makes the encapsulation of finishing thinner then.Then, as described in reference to figure 1 and among Fig. 5 F further shown in, seal welding district 210, chip 220 and wire 230.Then, shown in Fig. 2 G, etch away exhaustion layer and expose base flange 213.Shown in Fig. 5 H, packed chip cutting is become independently packed chip or packed multi-chip module then.
In also having an embodiment, Fig. 6 A-6F illustrates another stackable chip layout.Fig. 6 A-1 illustrates dielectric substrate material layer 305 is placed end view on the end face 302 of exhaustion layer 300.Base material 305 preferably includes such as sheet dielectric layers such as polyimides.Generally, base material 305 is layered on the exhaustion layer 300.Conductive welding region 310 places on the base material 305.Can base material is appended to before the exhaustion layer 300 or after, weld zone 310 is plated on the base material 305.Fig. 6 A-2 illustrates the plan view from above of Fig. 6 A-1.Weld zone 310 among Fig. 6 A-2 has bonding position 315 and lead to the hole site 316.Weld zone 310 also defines the pit 314 of central authorities.Shown in Fig. 6 B-1, then semiconductor chip 320 back sides are bonded to the first surface 302 of central pit internal consumption layer 300.Then, the chip contacts (not shown) is connected electrically to each bonding position 315 on the weld zone 310.Generally, the contact silk is bonded to each bonding position 315.Fig. 6 B-2 illustrates the plan view from above of Fig. 6 B-1.
Shown in Fig. 6 C, follow curable fluid sealant 340 sealing chips, weld zone and wire and curing as mentioned above.Then, the second conduction exhaustion layer 345 is placed on the exposed surface of sealant 340.Generally second exhaustion layer 345 is laminated on the sealant 340.Shown in Fig. 6 D, then get out the hole 350 of the dielectric material of break-through curing, thereby the sidewall in hole extends to the bottom surface from end face by encapsulation, produce the through hole of at least some conductive welding regions 310 of break-through then at lead to the hole site 316 places.Shown in Fig. 6 E, then plating conducting metal 360 on the sidewall in hole 350 encapsulates the conductive path that extends fully thereby produce from a side in hole to break-through.Generally, conducting metal 360 terminates on the either side in hole 350 of flange portion 365.Control the shape and size of flange portion by the standard light engraving device, this standard light engraving device is added to second exhaustion layer to dielectric photoresist 363 and develops, thereby can therefrom remove ledge zone.Photoresist also can optionally be plated to heat-conducting metal layer 368 on the second surface 301 of first exhaustion layer 300.
Shown in Fig. 6 F-1 and 6F-2, first exhaustion layer 300 and second exhaustion layer 345 are carried out etching, thereby only stay flange portion 365 and the part of metal level below 368.Perhaps, can carry out selective etch, and this layer is used as ground connection/bus plane or wiring layer second exhaustion layer 345.Flange portion 365 and metal level 368 are by the resistive material of the etching solution that is used for the etch consumption layer is made.Then, use such as welding compound or the electric conducting materials such as epoxy 370 that are filled with metal and fill, thereby electric conducting material 370 is outstanding from through hole 371 bottoms and through hole 372 tops by the conductive through hole of plating.To pile up layout the same with vertical chip, and this layout makes via bottoms can be connected electrically to PWB, makes through hole 372 tops can link another Chip Packaging simultaneously.Metal level can be linked the fin among the PWB, thereby can derive heat during operation from chip.If the combination of first exhaustion layer 300 and metal level 368 is enough thick, then they also can play the effect that expansion encapsulation is connected with any welding compound between the PWB, more can bear the expansion of encapsulation/PWB during the thermal cycle of chip 320 and the welding rod of contraction in order to acquisition.
At another embodiment of the present invention shown in Fig. 7 A-7G.In Fig. 7 A, at first preparation comprises the consumption thin slice 400 of copper.Then, shown in 7B, gold optionally is electroplated onto on the first surface 401 that consumes thin slice 400, thereby limits weld zone 410 and the central conduction region 415 between weld zone 410.Shown in 7C, cover the second surface 402 that consumes thin slice 400 with photoresist 418 then, and the first surface 401 that consumes thin slice 400 is carried out etching.Employed etchant should be than the easier consumption thin slice that etches away of etch gold weld zone/central area.Copper chloride is to consume a kind of like this etchant that uses when thin slice comprises copper.Controlled etch process makes weld zone 410 and central area 415 give prominence to from the surface that consumes thin slice 400.Those skilled in the art should be understood that consuming thin slice 400 can use other material to obtain identical result with weld zone/central area 410/415.Shown in Fig. 7 D, then semiconductor chip 420 back sides are bonded to central area 415, and use silk bonding apparatus additional metal the silk 430 and chip contacts (not shown) on chip 420 exposed surfaces is connected electrically to each weld zone 410 betwixt.Then, shown in Fig. 7 E, the next procedure of this technology comprises the element that seals Chip Packaging with suitable curable liquid sealant 440, then curing sealant 440.
At this moment, can use two diverse ways.Shown in Fig. 7 F-1 and 7G-1, a method is gold district 450 optionally to be electroplated onto on the exposed surface that consumes thin slice 400 and to consuming thin slice 400 carry out etching, thereby only stays weld zone 410 and central area 415.In the case, central area is outstanding from the bottom of encapsulation, thereby it derives the thermal conducting path of heat from chip during the easier PWB of appending to is provided at this device operation.Outstanding central area 415 also can provide a kind of method, is extended to welding rod with the soldered ball that the weld zone 410 that is used for exposing is appended on the PWB, thereby their easier encapsulation/PWB differences during this device operation of bearing expand and contraction.Shown in Fig. 7 F-2 and 7G-2, with second method, carry out etching to consuming thin slice 400, be smooth thereby make weld zone 410 and central area 415 with respect to the bottom that encapsulates.Then, can be connected electrically to this device PWB and this device is thermally connected to PWB by weld zone 410 by central area 415.In another embodiment, can during consuming the thin slice etching step, carry out etching, in each weld zone, to produce a pit to weld zone 410.These pits can help soldered ball is placed on the weld zone 410.
Intactly describe several embodiments of the present invention, it is apparent that the secondary technology personnel in this area, had the various distortion and the equivalent that do not deviate from the invention described above.Therefore, should understand and the invention is not restricted to above description, and be only limited to additional claims.
Claims (45)
1. method of making semiconductor die package is characterized in that following steps:
The preparation exhaustion layer;
On the first surface of exhaustion layer, optionally form the conductive welding region array, thereby limit central area by these weld zones;
Semiconductor chip backside is appended to central area with interior exhaustion layer, thereby the contact load-bearing surface of chip separates with exhaustion layer;
Each contact is connected electrically to each weld zone;
The curable dielectric material of deposit on the first surface of exhaustion layer, thus weld zone, electrical connecting wires and chip are all sealed, and solidify this dielectric material; And
Optionally remove at least a portion of exhaustion layer.
2. the method for claim 1 is characterized in that using same exhaustion layer to make a plurality of semiconductor die package simultaneously, and this method also is included in and optionally removes the step of cutting apart at least some encapsulation after the step.
3. method as claimed in claim 2 is characterized in that segmentation procedure provides a plurality of independently Chip Packaging.
4. method as claimed in claim 2 is characterized in that segmentation procedure provides a plurality of chip modules that comprise at least two chips.
5. the method for claim 1, it is characterized in that the step of before the weld zone forms step, removing the part exhaustion layer, thereby in exhaustion layer, produce a plurality of pits, the weld zone forms step and also is included in formation conductive welding region in each pit, thereby the conductive welding region material is basically filling up each pit.
6. method as claimed in claim 5, the step that it is characterized in that removing the part exhaustion layer comprises carries out optionally etching to exhaustion layer.
7. method as claimed in claim 5, it is characterized in that the weld zone forms step and also is included in the step that forms first conductive bumps in the pit, thereby each weld zone integrally is connected to each projection and therefrom outstanding, and each projection has width or the diameter flange portion in addition that extends to the weld zone.
8. method as claimed in claim 7 is characterized in that second conductive bumps is integrally formed on the top that weld zone formation method is included in each weld zone.
9. method as claimed in claim 8, the entire combination that it is characterized in that first and second projectioies and weld zone is a rivet shape.
10. the method for claim 1 is characterized in that the weld zone is with the grid array arrangement around central area.
11. method as claimed in claim 10 is characterized in that the weld zone forms step and also comprises the step of formation from the weld zone of exhaustion layer differing heights.
12. method as claimed in claim 10 is characterized in that at least some weld zones have not by the conductive prominence of dielectric material complete seal.
13. method as claimed in claim 12 is characterized in that conductive prominence extends orthogonally with the contact load-bearing surface of chip basically.
14. the method for claim 1, thereby it is characterized in that the weld zone forms step and also is included in the step of placing between exhaustion layer and the conductive welding region that the base material weld zone forms and being supported by this material on base material.
15. method as claimed in claim 14, it is characterized in that following steps, promptly pass the dielectric material boring of curing, thereby the sidewall in hole encapsulates the through hole that extends to the bottom surface and produce at least some conductive welding regions of break-through from the end face break-through, and the sidewall in hole is metallized.
16. method as claimed in claim 15 is characterized in that the step with electric conducting material filling plated-through hole.
17. method as claimed in claim 15, the sidewall that it is characterized in that the hole basically with the contact load-bearing surface quadrature of chip.
18. method as claimed in claim 10 is characterized in that additional step also comprises the step that microelectronic element is appended to the contact load-bearing surface of chip, is electrically connected step and also comprises the contact on this element is connected to each weld zone.
19. method as claimed in claim 18 is characterized in that this element comprises second semiconductor chip, additional step also comprises the contact load-bearing surface that the back side of second chip is appended to first chip.
20. method as claimed in claim 18 is characterized in that being electrically connected step and also comprises at least one contact on this element is connected to each contact on the chip.
21. method as claimed in claim 4, the step that it is characterized in that making at least some weld zones that link to each other with first chip in the particular module and the weld zone that links to each other with second chip to be electrically connected.
22. method as claimed in claim 21, it is characterized in that before the weld zone forms step the sheet dielectric layer being placed the step on the first surface top of exhaustion layer, the step that the weld zone of first chip is connected electrically to the weld zone of second chip is included in the conductive trace that each weld zone is interconnected is provided on the dielectric layer.
23. the method for claim 1 is characterized in that selecting exhaustion layer from the group that is made of copper, aluminium, iron, steel, bronze, brass, polyimides, Polyetherimide, fluoropolymer and alloys and mixts thereof.
24. the method for claim 1 is characterized in that being electrically connected step and comprises the contact silk is bonded to each weld zone.
25. the method for claim 1 is characterized in that removing step and comprises exhaustion layer is carried out etching.
26. the method for claim 1 is characterized in that removing step and is included between the back side of chip and the fin thermal conducting path is provided.
27. a method of making semiconductor die package is characterized in that following steps:
The preparation exhaustion layer;
On the first surface of exhaustion layer, optionally form outstanding conductive welding region array and outstanding central substrate, thereby central substrate is positioned at the zone that is limited by these weld zones;
Semiconductor chip backside is appended to central substrate, thereby the contact load-bearing surface of chip separates with exhaustion layer;
Each contact is connected electrically to each weld zone;
The curable dielectric material of deposit on the first surface of exhaustion layer, thus weld zone, substrate, electrical connecting wires and chip are all sealed, and solidify this dielectric material; And
Optionally remove the part exhaustion layer, thereby on the bottom surface of encapsulation, expose weld zone and central substrate.
28. method as claimed in claim 27 is characterized in that using same exhaustion layer to make a plurality of semiconductor die package simultaneously, this method also is included in and optionally removes the step of cutting apart at least some encapsulation after the step.
29. method as claimed in claim 28 is characterized in that segmentation procedure provides a plurality of independently Chip Packaging.
30. method as claimed in claim 28 is characterized in that segmentation procedure provides a plurality of chip modules that comprise at least two chips.
31. method as claimed in claim 27 is characterized in that the weld zone forms step and comprises that the first surface to exhaustion layer carries out optionally etching.
32. method as claimed in claim 27 is characterized in that removing step and comprises that second exposed surface to exhaustion layer carries out optionally etching.
33. method as claimed in claim 32 is characterized in that central substrate is outstanding from the bottom surface of encapsulation.
34. method as claimed in claim 33 is characterized in that removing step and is included between chip back and the fin thermal conducting path is provided.
35. method as claimed in claim 27 is characterized in that being electrically connected step and comprises the contact silk is bonded to each weld zone.
36. a method of making semiconductor die package is characterized in that following steps:
Preparation sheet dielectric layer;
On the first surface of dielectric layer, optionally form conductive welding region array and central substrate, thereby central substrate is positioned at the zone that is limited by these weld zones;
Semiconductor chip backside is appended to central substrate, thereby the contact load-bearing surface of chip separates with dielectric layer;
Each contact is connected electrically to each weld zone;
The curable dielectric material of deposit on the first surface of dielectric layer, thus weld zone, electrical connecting wires and chip are all sealed, and solidify this dielectric material; And
Optionally remove the part dielectric layer, thus expose portion weld zone and central substrate on the bottom surface of encapsulation.
37. method as claimed in claim 36 is characterized in that removing step and comprises dielectric layer is carried out optionally etching.
38. method as claimed in claim 36 is characterized in that removing step and comprises that an emittance of concentrating optionally is added to dielectric layer.
39. method as claimed in claim 36 is characterized in that removing step and is included between chip back and the fin thermal conducting path is provided.
40. method as claimed in claim 36 is characterized in that being electrically connected step and comprises the contact silk is bonded to each weld zone.
41. method as claimed in claim 36 is characterized in that using same exhaustion layer to make a plurality of semiconductor die package simultaneously, the feature of this method also is to cut apart the step of at least some encapsulation after optionally removing step.
42. method as claimed in claim 41 is characterized in that segmentation procedure provides a plurality of independently Chip Packaging.
43. method as claimed in claim 41 is characterized in that segmentation procedure provides a plurality of chip modules that comprise at least two chips.
44. method as claimed in claim 43 is characterized in that being electrically connected the step that step is electrically connected at least some weld zones that link to each other with first chip in the particular module and the weld zone that links to each other with second chip.
45. method as claimed in claim 44, the step that it is characterized in that being electrically connected the weld zone are included in the conductive trace that makes each weld zone interconnection are provided on the dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97195605A CN1222252A (en) | 1996-04-18 | 1997-04-17 | Methods for mfg. semiconductor package |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/634,464 | 1996-04-18 | ||
| CN97195605A CN1222252A (en) | 1996-04-18 | 1997-04-17 | Methods for mfg. semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1222252A true CN1222252A (en) | 1999-07-07 |
Family
ID=5179262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97195605A Pending CN1222252A (en) | 1996-04-18 | 1997-04-17 | Methods for mfg. semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1222252A (en) |
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| CN102842515A (en) * | 2011-06-23 | 2012-12-26 | 飞思卡尔半导体公司 | Method for assembling semiconductor device |
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| US8785253B2 (en) | 2009-04-03 | 2014-07-22 | Kaixin, Inc. | Leadframe for IC package and method of manufacture |
| US9362138B2 (en) | 2009-09-02 | 2016-06-07 | Kaixin, Inc. | IC package and method for manufacturing the same |
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| CN104867898A (en) * | 2014-02-26 | 2015-08-26 | 英飞凌科技股份有限公司 | Semiconductor device with plated lead frame, and method for manufacturing thereof |
| CN104867898B (en) * | 2014-02-26 | 2017-12-15 | 英飞凌科技股份有限公司 | The semiconductor devices and its manufacture method of lead frame with plating |
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