CN1886803B - Flash memory device - Google Patents

Flash memory device Download PDF

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Publication number
CN1886803B
CN1886803B CN2004800347670A CN200480034767A CN1886803B CN 1886803 B CN1886803 B CN 1886803B CN 2004800347670 A CN2004800347670 A CN 2004800347670A CN 200480034767 A CN200480034767 A CN 200480034767A CN 1886803 B CN1886803 B CN 1886803B
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China
Prior art keywords
dielectric layers
storage arrangement
layer
conductive structure
conductive layer
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CN2004800347670A
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CN1886803A (en
Inventor
W·E·希尔
汪海宏
Y·吴
俞斌
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Cypress Semiconductor Corp
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Spansion LLC
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A memory device (100) includes a conductive structure (210), a number of dielectric layers (410430) and a control gate (510). The dielectric layers (410-430) are formed around the conductive structure (210) and the control gate (510) is formed over the dielectric layers (410-430). A portion of the conductive structure (210) functions as a drain region (1005) for the memory device (100) and at least one of the dielectric layers (410-430) functions as a charge storage structure for the memory device (100). The dielectric layers (410-430) may include oxide-nitride-oxide layers.

Description

Flash memory device
Technical field
The present invention system is about the method for storage arrangement and this storage arrangement of manufacturing.The present invention has special applicability for non-volatile memory device.
Background technology
For the expansion demand gradually of high density that is relevant to non-volatile memory device and performance, and need little design features, high fiduciary level and the manufacturing output of increase.Yet, reduce design features, with the limit of challenge prior art method.For example, reduce design features, meet its desired file maintenance demand with making storage arrangement be difficult to, for example, data was preserved demand in 10 years.
US-A-6 440 801 discloses the array of the high density deflation of the vertical semiconductor device with pillar (pillars).This array has the row (row) of word line and the row (column) of bit line.This array needs vertical pillar, and each pillar has two word lines, and one is that initiatively another is for passing through storage element.Article two, word line is formed on along the opposite side of the pillar sidewall of this column direction.On pillar one side of the word line that contact is passed through, the critical voltage of this pillar device raises, and therefore for good and all shuts this pillar in storage element operating period, and isolate this pillar and the word line that passes through on voltage change.The word line of this isolation allows other storage element access and writing via directly wearing tunnel.Use for Gbit DRAM, pile up with the channel capacitor device and can be formed on these pillars, or respectively on the irrigation canals and ditches of these pillars.
US-A-5 379 255 discloses memory cell transistor, wherein forms pillar structure or row structure on the face of Semiconductor substrate.Form floating grid and contiguous these pillar structure of control grid or row structure.Arrange these floating grids and control grid by gate oxide level and insulation course with insulating.In Semiconductor substrate, inject the source region.Also in this pillar structure or row structure, inject the drain zone.
Summary of the invention
Embodiments of the invention provide a kind of use pillar structure formed non-volatile memory device.Oxide-nitride thing-oxide (ONO) layer can be formed at pillar structure (pillarstructures) around, and polysilicon or metal level can be formed at the ONO layer on.Nitride layer in the ONO layer can act as charge storage or the floating gate electrode that is used for non-volatile memory device.Polysilicon or metal level can act as the control grid that is used for non-volatile memory device, and can separate with floating grid by the top oxide layer of ONO layer.
Part additional advantage of the present invention and further feature will be proposed in following explanation, and these part additional advantage and further feature will become clear owing to following explanation for being familiar with this operator, or can be by implementing the present invention these additional advantage of acquistion and further feature.Every advantage of the present invention and feature can be realized and acquisition by the pointed item of appended claims.
According to the present invention, reach above-mentioned and other advantage of part by storage arrangement, this storage arrangement comprises first conductive layer, conductive structure, many dielectric layer and control grid.Conductive structure is formed on this first conductive layer, and the part of first conductive layer act as the source region that is used for storage arrangement.Conductive structure has first end and with respect to second end of this first end.First end is arranged in abutting connection with the part that act as first conductive layer of source region, and second end act as the drain region that is used for storage arrangement.Around at least a portion of conductive structure and form dielectric layer, and dielectric layer at least wherein one act as the floating gate electrode that is used for storage arrangement.Control grid be formed at this dielectric layer on.
According to another aspect of the present invention, provide a kind of substrate, first insulation course, conductive structure, many dielectric layer and storage arrangement of control grid of comprising.This first insulation course is formed on the substrate, and conductive structure is formed on this first insulation course.Conductive structure act as the channel region that is used for storage arrangement.Dielectric layer forms at least a portion around this conductive structure, and one of them dielectric layer act as the charge-storage electrode that is used for storage arrangement.The control grid is formed on these dielectric layers.
According to another aspect of the present invention, provide a kind of first conductive layer, many structure, many dielectric layer and nonvolatile memory array of at least one conductive layer of comprising.This first conductive layer is formed on the substrate, and the partial action of this first conductive layer is the source region of the storage unit (cell) in the memory array.These structures are formed on first conductive layer, and each these structure function is the channel region that is used for one of them storage unit.Dielectric layer forms and centers on the respectively each several part of this structure, and wherein, one of them dielectric layer act as and is used for one of them charge storing unit storage electrode.This at least one conductive layer is formed on a plurality of dielectric layers that are used for each these storage unit.
With regard to being familiar with this operator, will become clear easily for other advantage of the present invention and feature by following detailed description.Each shows and the embodiment of explanation provides design to implement the example of optimal mode of the present invention.The present invention can do the modification on the various apparent and easy to know aspect, and these all modifications will can not depart from the scope of the present invention.Therefore, each is graphic to be about exemplary in essence, but not is used for limiting the present invention.
Description of drawings
With reference to appended graphic, each assembly that wherein has the indication of same reference number among each figure can be represented identical assembly.
Fig. 1 shows the drawing in side sectional elevation that can be used to form the exemplary layers of pillar structure according to embodiments of the invention.
Fig. 2 shows the skeleton view according to the formed many pillar structure of enforcement example of the present invention.
Fig. 3 shows the drawing in side sectional elevation that forms insulation course according to enforcement example of the present invention on the device of Fig. 2.
Fig. 4 shows the drawing in side sectional elevation that forms dielectric layer according to enforcement example of the present invention around the pillar structure of Fig. 3.
Fig. 5 shows the drawing in side sectional elevation that forms the control grid material according to enforcement example of the present invention on the device of Fig. 4.
Fig. 6 shows according to the top view of enforcement example of the present invention after the device of Fig. 5 has deposited the control grid material.
Fig. 7 shows according to the drawing in side sectional elevation of enforcement example of the present invention in the etching control grid material of Fig. 5.
Fig. 8 shows the top view according to the semiconductor device of enforcement example Fig. 7 of the present invention.
Fig. 9 shows the drawing in side sectional elevation that forms bit line according to enforcement example of the present invention on the device of Fig. 7.
Figure 10 shows according to the drawing in side sectional elevation that be installed on column direction of enforcement example of the present invention in Fig. 9.
Embodiment
Below present invention will be described in detail with reference to the accompanying.Identical reference number can be known and think same or analogous assembly in difference is graphic.And following detailed description does not limit the present invention.Otherwise the present invention's scope will be defined by appended claims and impartial content thereof.
Provide for example fast lightning can wipe the non-volatile memory device of ROM (read-only memory) (EEPROM) device off according to embodiments of the invention, and the method for making these devices is provided.Storage arrangement can comprise the pillar structure with dielectric layer and be formed at this pillar structure control grid layer on every side.One or more layers dielectric layer can act as the floating grid that is used for storage arrangement.
Fig. 1 is for showing the example drawing in side sectional elevation according to the formed semiconductor device 100 of embodiments of the invention.With reference to Fig. 1, semiconductor device 100 can comprise silicon-on-insulator (SOI) structure, and this soi structure comprises silicon substrate 110 and the buried oxide layer (buried oxide layer) 120 that is formed on this substrate 110.Buried oxide layer 120 can be formed at known mode on this substrate 110.In implementing example, buried oxide layer 120 can comprise for example SiO 2Monox, and can have from about 500 dusts ( ) to the interior thickness of the scope of about 2000 dusts.
For example silicide (silicide) that mixes and the conductive formation 130 of aiming at silicide (salicide) voluntarily can be formed on the buried oxide layer 120, act as source region or ground connection for semiconductor device 100, below will be described in more detail.In implementing example, the thickness in conductive formation 130 can have from about 100 dusts to the scope of about 500 dusts.
Silicon layer 140 can be formed on the layer 130.Silicon layer 140 can comprise monocrystalline silicon or polysilicon and thickness in having from about 200 dusts to the scope of about 1000 dusts.Can use silicon layer 140 to form pillar structure, following is described in more detail.
According to the selected embodiment of the present invention, substrate 110 and layer 140 can comprise other semiconductor material of germanium for example, or the semiconductor material combinations of silicon-germanium for example.Buried oxide layer 120 also can comprise other dielectric substance.
Silicon layer 140 patternables or be etched with and form structure 210 are shown in the skeleton view of Fig. 2.For example, photoresist can be deposited on the silicon layer 140 and patterning, and then etching is by the part of the silicon layer 140 that photoresistance covered, with the row that form many cylindrical, pillar shape structures 210 (also being referred to as pillar structure 210 or pillar 210)/OK.In implementing example, available traditional approach uses etch-stop on layer 130, and etch silicon layer 140.The height of pillar structure 210 can be from about 100 dusts to the scope of about 1000 dusts, the width of pillar structure 210 can be from about 100 dusts to the scope of about 1000 dusts in.In an embodiment, the height of pillar structure 210 and width can be respectively 500 dusts and 200 dusts.Pillar structure 210 can also be separated about 100nm to about 1000nm in transverse direction each other.For the purpose of simplifying, Fig. 2 has shown the pillar structure 210 of two row, and each row comprises 5 pillar structure 210.Should be appreciated that the row that can form extra pillar structure 210/OK.
After forming pillar structure 210, can form insulation course 310 on layer 130, as shown in Figure 3.Insulation course 310 reliably is connected to the base portion of pillar 210.In implementing example, insulation course 310 can comprise for example SiO 2Oxide material, and the thickness of insulation course 310 can be at about 100 dusts to the scope of about 500 dusts.Also can use other insulating material for insulation course 310.Insulation course 310 can be isolated colonnade 210 and another colonnade 210.
Many films can be formed at then pillar 210 around.In implementing example, oxide-nitride thing-oxide (ONO) thin dielectric film can be formed at pillar 210 around.For example, oxide skin(coating) 410 can be formed at pillar 210 around, as shown in Figure 4.In implementing example, oxide skin(coating) 410 can deposit or heat grow in pillar 210 around, thickness from about 100 dusts to the scope of about 500 dusts in.Purpose for the sake of simplicity, Fig. 4 shows the drawing in side sectional elevation of two pillars 210.Should be appreciated that oxide skin(coating) 410 can be formed at similar mode each pillar 210 around.Also should be appreciated that oxide skin(coating) 410 can be formed at each pillar 210 all exposed vertical surfaces around.In addition, in some embodiment, oxide skin(coating) 410 can be formed on the top surface.In these embodiment, in successive process, will remove end face and cover, will be in hereinafter being described in more detail.
Secondly, nitride layer 420 can be formed at oxide skin(coating) 41 0 around, as shown in Figure 4.In implementing example, the thickness in nitride layer 420 can deposit from about 100 dusts to the scope of about 500 dusts.Other then oxide skin(coating) 430 can be formed at nitride layer 420 around, as shown in Figure 4.In implementing example, oxide skin(coating) 430 can deposit or the thickness of heat growth in from about 100 dusts to the scope of about 500 dusts.Layer 410 to 430 is formed for the ONO charge storage dielectric of the storage arrangement of follow-up formation.In detail, nitride layer 420 can act as floating gate electrode, and top oxide layer 430 can act as dielectric between grid.
Silicon layer 510 can be formed on the semiconductor device 100, as shown in Figure 5 then.Silicon layer 510 is available as the electrode material for the control grid electrode of follow-up formation.In implementing example, silicon layer 5 10 can comprise and use the known polysilicon that chemical vapor deposition (CVD) deposited, the thickness in reaching from about 100 dusts to the scope of about 1000 dusts.Maybe can select other semiconductor material or the various metal of the combination of germanium for example or silicon and germanium for use, as grid material.
Can and etch into insulation course 310 and end silicon layer 510 patternings then.For example, Fig. 6 show according to the present invention in silicon layer 510 etching form be marked with 610 and 620 silicon row after, the top view of semiconductor device 100.With reference to Fig. 6, row 610 and 620 respectively comprise 5 pillars 210 (with dashed lines demonstration), round the ONO layer 410 to 430 (with dashed lines demonstration) of pillar 210 and round the silicon layer 510 of ONO layer 410 to 430.Insulation course 310 is isolated row 610 and 620 electricity.The silicon layer 510 that is shown among Fig. 6 can become the plane in fact with the upper surface of pillar 210.In this implements, but etching or complanation are shown in the silicon layer 510 among Fig. 5, and make this silicon layer 510 to become the plane with the upper surface of pillar 210 in fact.
But etch silicon layer 510 and expose the top of pillar 210 then.For example, but top surface and the top of etch-back pillar 210 to expose pillar 210 to the open air, as shown in Figure 7.In implementing example, after etching, can expose the top of about 100 dusts to the open air to the pillar 210 of about 500 dusts.During etch process, perhaps erosion is led to the part of the silicon layer 510 between pillar 210 to insulation course 310, as shown in Figure 7.
After Fig. 8 is shown in etch silicon layer, expose the top view of semiconductor device 100 on the top of pillar 210.With reference to Fig. 8, semiconductor device 100 comprises that several rowers are shown 810 to 850, by 510 of ONO layer 410 to 430 and polysilicons around pillar 210.Insulation course 310 separable row 810 to 850.
Secondly, such as the metal of aluminium or copper can deposit and be patterned in and form metal level 910 on the semiconductor device 100, as shown in Figure 9.The thickness of metal level 910 can be from about 200 dusts to about 2000 dust scopes.With reference to Fig. 9, metal level 910 can act as the bit line that is used for semiconductor device 100.The bit line decoder (not shown) can be coupled to metal level 910, to promote internal memory body device 100 sequencing or to read data from internal memory body device 100.
Figure 10 shows the illustration drawing in side sectional elevation of semiconductor device 100 in column direction.Each pillar 210, the ONO layer 410 to 430 of encirclement, and grid layer 510 can act as the storage unit in the memory array.With reference to Figure 10, the top that is labeled as 1005 pillar 210 can act as the drain region of storage unit in the semiconductor device 100, and layer 130 part that are labeled as 1010 the bottom of being abutted against pillar 210 can act as the source region of the storage unit of semiconductor device 100.Therefore, the channel shape of storage unit is formed in the vertical columns 210.
Can be according to special resulting device demand, and doped source/drain areas 1010 and 1005.For example, n type or p type impurity are implantable in regions and source 1010 and 1005.For example, such as the implantable dosage of n type alloy about 1 * 10 of phosphorus 19Atom/square centimeter (atoms/cm 2) to about 1 * 10 20Atom/square centimeter, and implant the about 10KeV of energy to about 50KeV.Maybe can select for example p type alloy of boron for use, implant with similar dosage and implantation energy.Can be according to specific resulting device demand, and select specific implant dosage and energy for use.General be familiar with this operator can be according to circuit requirements and optimization source/drain implantation process.In addition, can be in forming semiconductor device 100 early step, for example before forming ONO layer 410, doped source/drain areas 1010 and 1050.Moreover, can be according to special circuit requirements, use various between spacing body (spacers) and angle of inclination (tilt angle) implantation process control source electrode/and the position of drain junction.Can carry out activation annealing (activation annealing) then with activation regions and source 1010 and 1005.
The semiconductor device 100 that obtains shown in Figure 10 has silicon-oxide-nitride--oxide-silicon (SONOS) layer structure.That is to say that semiconductor device 100 can comprise the silicon pillar structure 210 with ONO dielectric layer 410 to 430, and control grid 510 formed thereon.Pillar structure 210 act as channel region or the underlayer electrode that is used for storage arrangement, and ONO layer 410 to 430 can act as charge storing structure.
Semiconductor device 100 is operable as non-volatile memory device, such as NOR type quickflashing EEPROM.Can be by applying bias voltage, for example approximately 10V and finishes sequencing to controlling grid 510.That is to say that if bias voltage is applied to control grid 510, then electronics can be worn tunnel and enter floating gate electrode (for example, nitride layer 420) from regions and source 1010 and 1005.Can finish and wipe off by for example applying approximately being biased into control grid 510 of 10V.During wiping off, electronics can be worn tunnel and enter regions and source 1010 and 1005 from floating gate electrode (for example, nitride layer 420).
Can use the semiconductor device 100 that is shown among Fig. 9 and Figure 10 to form nonvolatile memory array.For example, the semiconductor device 100 among Fig. 9 and Figure 10 has shown that two storage unit respectively are used for storage unit information (single bit of information).According to implementing example, availablely form memory array similar in appearance to the many storage unit shown in Fig. 9 and Figure 10.For example, many bit lines for example are shown in the bit line 910 among Fig. 9, can respectively be coupled to the row (row) or the row (column) of each pillar 210.Many control grids for example are shown in the control grid 510 among Figure 10, can respectively be electrically coupled to the row or column of storage unit, and this row or column storage unit and bit line 910 skews (offset) 90 are spent, and act as the bit line (word lines) of memory array.Bit line decoder (not shown) and bit line decoder (not shown) can be coupled to bit line 910 and bit line 510 respectively then.Can use the sequencing of this bit line and bit line decoder then, or read the data that are stored in each particular memory location with each particular memory location of promotion memory array.Mode can form high-density nonvolatile memory array according to this.
Therefore,, use many vertical pillar structures, and form flash memory device according to the present invention.Advantage is that pillar 210 makes the raceway groove that is used for storage arrangement can be formed at vertical stratification, when comparing with known flash memory device, helps resulting storage arrangement 100 to reach the increase current densities thus.Present invention can also be easily integrated into known manufacture of semiconductor.
In the explanation of front, understand fully in order to provide of the present invention, and proposed many specific detailed descriptions, for example specific material, structure, chemicals, processing procedure etc.Yet, can not rely on the specific details that goes out mentioned herein and implement the present invention.In other example, in order to be unlikely the unnecessary authenticity of the present invention of having blured, and no longer describe known processing procedure structure in detail.
Can deposit the dielectric and the conductive layer that are used to make semiconductor device according to of the present invention by known deposition technique.For example, can use such as comprise the metallization technology of the various types CVD processing procedure of low pressure chemical vapor deposition (LPCVD) and enhancing CVD (ECVD).
The present invention can be applicable to make the FinFET semiconductor device, and especially has design features 100nm and following FinFET device.The present invention can be used to form the semiconductor device of any kind of form, but for fear of having blured real feature of the present invention, and therefore do not reintroduce detailed description.In implementing the present invention, use known photolithography and etching technique, and therefore in the details that proposes these technology herein no longer in detail.In addition, though described the semi-conductive a series of processing procedures of the formation of Fig. 5 in detail, should be appreciated that in other enforcement according to the invention to change the fabrication steps order.
In this disclosure book, only show and illustrated the example of preferred embodiment of the present invention and its variation of minority.To recognize that the present invention can be used in various other combinations and environment, and modify in can be in the like this literary composition represented concept and range of the present invention.
In addition, unless the assembly in the application's case instructions, action or instruction have been done clear and definite explanation, be used in these assemblies, action or instruction in the application's case instructions will be not interpreted as for the present invention must be indispensable or certain necessity.And, will comprise one or more projects as employed indefinite article " a " in the application's case original text instructions, and when really only having one, then will use " one (one) " words and phrases to represent.

Claims (10)

1. a storage arrangement (100) comprising:
First conductive layer (130), wherein the part of this first conductive layer (130) is as the source region (1010) of storage arrangement (100); This memory device features is:
Conductive structure (210), be formed on this first conductive layer (130), this conductive structure (210) has first end and with respect to second end of this first end, wherein this first end is arranged in abutting connection with the part as first conductive layer (130) of the source region (1010) of this storage arrangement (100), and wherein this second end as the drain region (1005) of this storage arrangement (100);
A plurality of dielectric layers (410 to 430), around at least a portion of this conductive structure (210) and form, wherein this dielectric layer (410 to 430) at least one of them as the floating gate electrode of this storage arrangement (100); And
Control grid (510) is formed on these a plurality of dielectric layers (410 to 430) and covers these a plurality of dielectric layers fully, and wherein this of this conductive structure second end does not contact any one deck and this control grid of these a plurality of dielectric layers (410-430).
2. storage arrangement as claimed in claim 1 (100), wherein this conductive structure (210) is cylindrical.
3. storage arrangement as claimed in claim 2 (100), wherein this conductive structure (210) have from about 100 dusts to the scope of about 1000 dusts thickness and from about 100 dusts to the scope of about 1000 dusts in width.
4. storage arrangement as claimed in claim 1 (100), wherein these a plurality of dielectric layers (410 to 430) comprising:
First oxide skin(coating) (410) forms around this conductive structure (210),
Nitride layer (420) forms around this first oxide skin(coating) (410), and
Second oxide skin(coating) (430) forms around this nitride layer (420), and wherein this nitride layer (420) is as this floating gate electrode.
5. storage arrangement as claimed in claim 1 (100) further comprises:
Substrate (110); And
Be formed at the oxide skin(coating) of burying (120) on this substrate (110), wherein this first conductive layer (130) is formed on this oxide skin(coating) of burying (120).
6. a storage arrangement (100) comprises substrate (110) and is formed at first insulation course (120) on this substrate (110), and this storage arrangement (100) is characterised in that:
Conductive structure (210), have first end that is formed on this first insulation course (120), with respect to second end and the middle part between this first end and this second end of this first end, this conductive structure (210) is as the channel region of this storage arrangement (100);
A plurality of dielectric layers (410 to 430), around this middle part of this conductive structure (210) and do not form around this second end of this conductive structure, and one of them individual charge-storage electrode as this storage arrangement (100) of described dielectric layer (410 to 430);
Control grid (510) is formed on these a plurality of dielectric layers (410 to 430) and covers these a plurality of dielectric layers fully, and wherein this of this conductive structure second end does not contact any one deck and this control grid of these a plurality of dielectric layers; And
First conductive layer (130), be formed between this first end of this first insulation course (120) and this conductive structure (210), wherein this first conductive layer (130) is in abutting connection with the part of this first end of this conductive structure (210) source region (1010) as this storage arrangement (100).
7. storage arrangement as claimed in claim 6 (100) further comprises:
Second insulation course (310) is formed on this first conductive layer (130), and contacts this first end of this conductive structure (210).
8. storage arrangement as claimed in claim 6 (100), the combination thickness in wherein these a plurality of dielectric layers (410 to 430) have from about 300 dusts to the scope of about 1500 dusts.
9. a nonvolatile memory array (100) comprising:
First conductive layer (130) is formed on the substrate (110), and wherein the part of this first conductive layer (130) is as the source region of the storage unit in this memory array; This nonvolatile memory array is characterised in that:
A plurality of structures (210), respectively these a plurality of structures have on this source region that is formed at this first conductive layer (130) first end and with respect to second end of this first end, wherein respectively these a plurality of structures (210) as the channel region of one of them storage unit;
A plurality of dielectric layers (410 to 430) form around the part of this a plurality of structures (210) respectively, and wherein one of them of these a plurality of dielectric layers (410 to 430) is individual as one of them charge storing unit storage electrode; And
At least one conductive layer (510), be formed at respectively on a plurality of dielectric layers of this storage unit (410 to 430) and cover these a plurality of dielectric layers (410 to 430) fully, wherein respectively this second end of these a plurality of structures (210) does not contact any one deck and this at least one conductive layer of these a plurality of dielectric layers (410-430).
10. nonvolatile memory array as claimed in claim 9 further comprises:
Multiple bit lines (910), wherein respectively this multiple bit lines (910) contacts many these a plurality of structures (210), wherein this at least one conductive layer (510) comprises a plurality of conductive layers (510), and the last layer of this conductive layer (510) contact this a plurality of dielectric layers relevant respectively wherein, and as the word line of this nonvolatile memory array (100) with a group storage unit.
CN2004800347670A 2003-12-04 2004-10-26 Flash memory device Active CN1886803B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/726,508 2003-12-04
US10/726,508 US6933558B2 (en) 2003-12-04 2003-12-04 Flash memory device
PCT/US2004/035482 WO2005062310A1 (en) 2003-12-04 2004-10-26 Flash memory device

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CN1886803A CN1886803A (en) 2006-12-27
CN1886803B true CN1886803B (en) 2011-09-14

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