TWI722742B - Memory device and method for fabricating the same - Google Patents

Abstract

A memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

Description

Memory element and manufacturing method thereof

This disclosure relates to a semiconductor structure and its manufacturing method. This disclosure more particularly relates to a memory device and its manufacturing method.

Recently, the demand for the use of flash memory has increased day by day. Flash memory devices can be divided into NOR or NAND flash memory devices. Among them, the NAND memory device typically provides faster programming and reading speed by connecting one end of each memory cell to the ground and the other end to the bit line. Generally speaking, the NAND flash memory system is a two-dimensional type, and the memory cells exist in a two-dimensional array of a substrate. However, with more and more applications nowadays, the size limit of the two-dimensional structure is no longer sufficient. Therefore, in order to provide a memory device with a higher storage capacity, there is still an urgent need to develop a three-dimensional inverter memory device with better electrical characteristics (for example, good data storage reliability and operating speed).

In this disclosure, a memory device and a manufacturing method thereof are provided, To solve at least part of the above problems.

According to an embodiment of the present invention, the memory device includes a substrate, a laminated structure, a plurality of channel structures, a memory layer, and a plurality of isolation structures. The substrate has an upper surface. The laminated structure is located on the upper surface of the substrate, wherein the laminated structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer sequentially stacked on the substrate Floor. The channel structure passes through the laminated structure and is electrically connected to the substrate. Each channel structure includes an upper portion and a lower portion. The upper portion corresponds to the second conductive layer, and the lower portion corresponds to the first conductive layer. The memory layer is located between the second conductive layer and the upper part. The isolation structure passes through the stacked structure to separate the stacked structure into a plurality of sub-stacks.

According to an embodiment of the present invention, the manufacturing method of the memory device includes the following steps. First, a substrate is provided, and the substrate has an upper surface; then, a laminated body is formed on the upper surface of the substrate, wherein the laminated body includes a first insulating layer and a first insulating layer sequentially stacked on the upper surface of the substrate. A conductive layer, a second insulating layer, an upper sacrificial layer, and a third insulating layer; forming a plurality of first openings passing through the laminated body; forming a plurality of channel structures in the first openings, and the channel structures are electrically connected On the substrate, each channel structure includes an upper part and a lower part, the lower part corresponds to the first conductive layer, and the upper part is located above the lower part; a memory layer corresponding to the upper part is formed; and a through-layer body is formed The upper sacrificial layer is removed and an upper opening is formed at the position where the upper sacrificial layer is removed; a conductive material is filled in the upper opening to form a second conductive layer, thus forming a first insulating layer Layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer; after that, a plurality of isolation structures are formed in the second opening, and the isolation structure divides the laminated structure into a plurality of Times stacked.

According to an embodiment of the present invention, the manufacturing method of the memory device includes the following steps. First, a substrate is provided, the substrate has an upper surface; then, a laminated body is formed on the upper surface of the substrate, wherein the laminated body includes a first insulating layer and a lower sacrificial layer sequentially stacked on the upper surface of the substrate , A second insulating layer, an upper sacrificial layer, and a third insulating layer; forming a plurality of first openings passing through the laminated body; forming a plurality of lower parts of a plurality of channel structures in the first opening; A memory layer corresponding to the upper sacrificial layer is formed in an opening; a plurality of upper parts forming a channel structure are in the first opening, and the upper part is located on the lower part; a plurality of second openings passing through the laminated body are formed; In addition to the upper sacrificial layer and the lower sacrificial layer, an upper opening and a lower opening are respectively formed at the positions where the upper sacrificial layer and the lower sacrificial layer are removed; a conductive material is filled in the upper opening and the lower opening to form a second A conductive layer and a first conductive layer, thus forming a laminated structure including a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer; after that, in the second opening A plurality of isolation structures are formed, and the isolation structure separates the laminated structure into a plurality of sub-stacks.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows. However, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100, 200, 300, 400, 500, 600, 700: memory components

110, 210, 310, 410, 510, 610, 710: substrate

110a, 210a, 310a, 410a, 510a, 610a, 710a: upper surface

112, 212, 312, 412, 512, 612, 712: channel structure

112a, 212a, 312a: lower part

112b, 212b, 312b: upper part

112c, 212c, 312c, 412c, 512c, 612c, 712c, 118, 218, 318, 418, 518, 618, 718: doped regions

112t, 172t: top surface

122, 222, 322, 422, 522, 622, 722: first insulating layer

124, 224, 324, 424, 524, 624, 724: second insulating layer

126, 226, 326, 426, 526, 626, 726: third insulating layer

128, 228, 328: cover layer

130, 230, 330, 430, 530, 630, 730: first conductive layer

132, 232, 332, 432, 532, 632, GO ₄ , GO ₅ , GO ₆ : thermal oxide layer

132’, 232’, 332’, 432’, 532’, 632’, 732’: oxide layer

140, 240, 340, 440, 540, 640, 740: upper sacrificial layer

152, 252, 352, 452, 552, 652, 752: first opening

154, 254, 354, 454, 554, 654, 754: second opening

156, 256, 356, 456, 556, 656, 756: upper opening

162, 262, 362, 462, 562, 662, 762: memory layer

164, 364, 664: protective layer

166, 266, 366, 566, 666, 766: dielectric materials

172, 272, 372, 472, 572, 672, 772: second conductive layer

172’, 272’, 372’, 472’, 572’, 672’, 772’: conductive material

174, 274, 374, 474, 574, 674, 774: isolation structure

176, 276, 376, 476, 576, 676, 776: conductive connection structure

211: Adulterants

342, 442, 642, 742: Lower sacrifice layer

259, 459, 559, 759: vertical opening

358, 458, 658: lower opening

472’: Conductive material

A, A’: End of section line

BL, BL0, BL1, BL2: bit lines

CL4, CL5, CL6, CL7: top conductive layer

CSL: Common Source Line

GSL0, GSL1, GSL2: Ground selection line

H ₁ : first height

H ₂ : second height

M, M ₁ , M ₂ , M ₃ , M ₄ , M ₅ , M ₆ , M ₇ : memory cell

OL4, OL5, OL6, OL7: top insulating layer

P1: Top opening

S1, S2, S3, S4, S5, S6, S7: laminated structure

S1’, S2’, S3’, S4’, S5’, S6’, S7’: laminated body

SLT1: The first groove

SLT2: second groove

SLT3: The third groove

SS1, SS2: secondary stack

T, T ₁ , T ₂ , T ₃ , T ₄ , T ₅ , T ₆ , T ₇ , TS ₄ , TS ₅ , TS ₆ , TS ₇ : Transistor

UN, UN ₁ , UN ₂ , UN ₃ , UN ₄ , UN ₅ , UN ₆ , UN ₇ , UN _t : unit cell

WL0, WL1, WL2: character line

FIG. 1A is a top view of a memory device according to an embodiment of the disclosure.

Figure 1B shows an embodiment according to the present disclosure along the line A-A' of Figure 1 The cross-sectional view of the memory device.

FIG. 1C is a cross-sectional view of a memory device according to another embodiment of the disclosure.

FIG. 1D is a cross-sectional view of a memory device according to another embodiment of the disclosure.

FIG. 1E is a cross-sectional view of a memory device according to another embodiment of the disclosure.

FIG. 1F is a cross-sectional view of a memory device according to another embodiment of the disclosure.

FIG. 1G is a cross-sectional view of a memory device according to another embodiment of the disclosure.

FIG. 1H is a cross-sectional view of a memory device according to another embodiment of the disclosure.

2A to 2N are cross-sectional views of a method of forming a memory device according to an embodiment of the disclosure.

3A to 3M are cross-sectional views of a method of forming a memory device according to another embodiment of the disclosure.

4A to 4L are cross-sectional views of a method of forming a memory device according to another embodiment of the disclosure.

FIG. 5 is an equivalent circuit diagram of a memory device according to an embodiment of the disclosure.

FIG. 6A is an equivalent circuit diagram of a memory device programmed by Fowler-Nordheim injection according to an embodiment of the present disclosure.

FIG. 6B is an equivalent circuit diagram of a memory device that performs a programming operation by channel-hot-electron injection according to an embodiment of the present disclosure.

FIG. 7A is an equivalent circuit diagram of a memory device that is erased by Fowler-Nordham injection according to an embodiment of the present disclosure.

FIG. 7B shows an equivalent circuit diagram of a memory device using a band-to-band tunneling induced hot hole injection operation according to an embodiment of the present disclosure.

FIG. 8 is an equivalent circuit diagram of a memory device in a read operation according to an embodiment of the disclosure.

9A to 9R are cross-sectional views illustrating a method of forming a memory device according to another embodiment of the disclosure.

10A to 10K are cross-sectional views of a method of forming a memory device according to another embodiment of the disclosure.

11A to 11M are cross-sectional views illustrating a method of forming a memory device according to another embodiment of the disclosure.

12A to 12K are cross-sectional views of a method of forming a memory device according to another embodiment of the disclosure.

FIG. 13 is an equivalent circuit diagram of a memory device programmed by Fowler-Nordheim injection according to an embodiment of the present disclosure.

FIG. 14A is an equivalent circuit diagram of a memory device that is erased by Fowler-Nordham injection according to an embodiment of the present disclosure.

FIG. 14B illustrates the induction by band-to-band tunneling according to an embodiment of the present disclosure The equivalent circuit diagram of the memory device in which the thermal hole performs the erase operation.

FIG. 15 is an equivalent circuit diagram of a memory device in a read operation according to an embodiment of the disclosure.

In the following detailed description, for the convenience of explanation, various specific details are provided to understand the embodiments of the present disclosure as a whole. However, it should be understood that one or more embodiments can be implemented without employing these specific details. In other cases, in order to simplify the drawings, the known structures and elements are shown in schematic diagrams.

FIG. 1A shows a top view of the memory device 100 according to an embodiment of the present disclosure; FIG. 1B shows the memory device 100 according to an embodiment of the present disclosure along the line A-A' of FIG. 1 Section view.

Please refer to FIG. 1A, a plurality of bit lines BL and a common source line CSL are located above the laminated structure S1, wherein the plurality of bit lines BL and the common source line CSL are parallel to the upper surface 110a of the substrate 110 ( (Shown in FIG. 1B) extending in a first direction (for example, the Y-axis direction), and a plurality of bit lines BL are arranged and separated along a second direction (for example, the X-axis direction) perpendicular to the first direction. The bit lines BL are electrically connected to the corresponding channel structures 112 respectively. The common source line CSL is electrically connected to the corresponding conductive connection structure 176.

Please refer to FIGS. 1A and 1B at the same time. The memory device 100 includes a substrate 110, a laminated structure S1, a cap layer 128, a plurality of channel structures 112, a thermal oxide layer 132, a memory layer 162, and a dielectric material. 166, a plurality of isolation structures 174, and a plurality of conductive connection structures 176. The stacked structure S1 is formed on the upper surface 110 a of the substrate 110. The laminated structure S1 includes a first insulating layer 122, a first conductive layer 130, a second insulating layer 124, a second conductive layer 172, and a The third insulating layer 126. The cap layer 128 may cover the laminated structure S1, that is, it is located on the third insulating layer 126. In some embodiments, the substrate 110 may be a silicon substrate or other suitable substrates. The first insulating layer 122, the second insulating layer 124, the third insulating layer 126, and the capping layer 128 may be formed of oxide, such as silicon dioxide (SiO ₂ ). The first conductive layer 130 and the second conductive layer 172 may be formed of a conductive material, such as tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), doped or not Doped poly-silicon or other suitable materials. In this embodiment, the first conductive layer 130 and the second conductive layer 172 are formed of different materials, such as n-type doped polysilicon and tungsten, respectively. However, the present invention is not limited thereto. The first conductive layer 130 and the second conductive layer 172 may be formed of the same material. In some embodiments, the thickness of the first conductive layer 130 can be 300 Å to 1000 Å, which can be used to adjust the threshold voltage (Vt).

The channel structure 112 passes through (for example, along the Z axis) the laminated structure S1 and is electrically connected to the substrate 110, wherein each channel structure 112 includes a lower portion 112a and an upper portion 112b. The upper portion 112b is located above the lower portion 112a, and the upper portion 112b is directly connected to the lower portion 112a. In other words, the upper portion 112b corresponds to the second conductive layer 172, and the lower portion 112a corresponds to the first conductive layer 130. The top region of the channel structure 112 may have a doped region 112c, such as an n-type semiconductor dopant, so that the channel structure 112 can be electrically connected to the bit line BL. In some embodiments, the channel structure 112 may be an epitaxial growth layer, such as a monocrystalline or polycrystalline silicon layer formed by an epitaxial growth process, or any combination of the above, and may be undoped or slightly P-type doped epitaxial growth layer. _{There is a first height H 1} between a top surface 112t of the channel structure 112 (that is, an epitaxial growth layer) and the upper surface 110a of the substrate 110, a top surface 172t of the second conductive layer 172 and the upper surface of the substrate 110 There is a second height H ₂ between 110 a, and the first height H ₁ may be greater than the second height H ₂ . Compared with the comparative example in which the channel structure only partially includes the epitaxial growth layer, since the channel structure 112 including the upper portion 112b and the lower portion 112a of the present invention is formed by an epitaxial growth process, the channel structure 112 may have a lower The resistor has better conductivity, and the memory device 100 can have a faster operating speed (for example, the operating speed of reading and writing).

The thermal oxide layer 132 is located between the first conductive layer 130 and the channel structure 112. For example, the thermal oxide layer 132 surrounds at least a portion of the lower portion 112 a of the channel structure 112. In some embodiments, the thermal oxide layer 132 is an oxide layer formed by directly performing an oxidation process on the first conductive layer 130, such as silicon dioxide (SiO ₂ ). Since the thermal oxide layer 132 is an oxide layer formed by directly oxidizing the conductive layer (for example, the first conductive layer 130), rather than by a deposition process (for example, chemical vapor deposition (CVD), physical vapor deposition ( For the oxide layer formed by PVD or other deposition processes), the purity of the oxide of the thermal oxide layer 132 is greater than that of the insulating layer formed by the deposition method (for example, the first insulating layer 122, the second insulating layer 124 or the third insulating layer). The purity of the oxide of layer 126). Compared with the comparative example in which the thermal oxide layer is an oxide layer formed by a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly oxidizing the conductive layer, the thermal oxide layer has a higher The purity and quality of the oxide can better control the threshold voltage (Vt), so it can have a lower threshold voltage in low-power applications, so that the memory device 100 can have better reliability.

The memory layer 162 is located between the second conductive layer 172 and the upper portion 112 b of the channel structure 112. For example, the memory layer 162 extends along the Z-axis direction and surrounds the upper portion 112b of the channel structure 112. The memory layer 162 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 162 may include a tunneling layer, a trapping layer, and a blocking layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials.

The dielectric material 166 is located between the memory layer 162 and the second conductive layer 172. Part of the dielectric material 166 may extend along the normal direction on the upper surface 110a of the substrate 110, part of the dielectric material 166 may extend in a direction parallel to the upper surface 110a of the substrate 110, and the dielectric material 166 may be covered The second conductive layer 172. In some embodiments, the dielectric material 166 may include a high k material, such as aluminum oxide (Al ₂ O ₃ ) or other suitable materials. The dielectric material 166 can also serve as a barrier layer to prevent lateral diffusion of charges. Compared with the comparative example that does not use high-permittivity material as the dielectric material, since the dielectric material 166 in this case can use high-permittivity material, the operation of the memory device can be performed without using too high voltage. (Such as erasing and writing), so the performance of the memory device can be improved.

The isolation structure 174 may pass through the stacked structure S1 and divide the stacked structure S1 into a plurality of sub-stacks SS1 and SS2. This embodiment only illustrates two sub-stacks, but the present invention is not limited to this, and the number of sub-stacks may be greater than two. The isolation structure 174 may be formed of an insulating material, such as oxide or other suitable materials. The second conductive layers 172 in the adjacent sub-stacks SS1 and SS2 can be physically and electrically isolated by the isolation structure 174. Therefore, the second conductive layers 172 in different sub-stacks can be operated independently, for example, by applying different Voltage.

The conductive connection structure 176 may pass through the stacked structure S1, and is electrically connected to the substrate 110 through the doped region 118, for example. The doped region 118 is doped with n-type semiconductor dopants, for example. The conductive connection structure 176 may be electrically connected to the common source line CSL.

In some embodiments, each overlap position (intersection) between the first conductive layer 130 and the thermal oxide layer 132 can form a transistor T ₁ , between the second conductive layer 172, the dielectric material 166 and the memory layer 162 Each overlapping position of, can form a memory cell M ₁ . The transistor T ₁ and the memory cell M _{1 are} connected in series through the channel structure 112 and can jointly form a unit cell UN ₁ . The first conductive layer 130 can be used as a ground select line, and the second conductive layer 172 can be used as a word line.

FIG. 1C is a cross-sectional view of a memory device 200 according to another embodiment of the present disclosure. The memory device 200 and the memory 100 have a similar top view (for example, FIG. 1A), so FIG. 1C is similar In the cross-sectional view along the line A-A' in Figure 1. The memory device 200 has a structure similar to that of the memory 100, except that the shape of the memory layer 262 is different.

1C, the memory device 200 includes a substrate 210, a stacked structure S2, a cap layer 228, a plurality of channel structures 212, a thermal oxide layer 232, a memory layer 262, a dielectric material 266, and more One isolation structure 274 and a plurality of conductive connection structures 276. The stacked structure S2 is formed on the upper surface 210 a of the substrate 210. The stacked structure S2 includes a first insulating layer 222, a first conductive layer 230, a second insulating layer 224, a second conductive layer 272, and a The third insulating layer 226. The cap layer 228 may cover the laminated structure S2, that is, it is located on the third insulating layer 226. In this embodiment, the first conductive layer 230 The second conductive layer 272 and the second conductive layer 272 are formed of different materials, such as n-type doped polysilicon and tungsten (W), respectively. However, the present invention is not limited to this. The first conductive layer 230 and the second conductive layer The layer 272 may be formed of the same material. In some embodiments, the thickness of the first conductive layer 230 can be 300 Å to 1000 A, which can be used to adjust the threshold voltage (Vt).

The channel structure 212 (for example, along the Z axis) passes through the laminated structure S2 and is electrically connected to the substrate 210, wherein each channel structure 212 includes an upper portion 212b and a lower portion 212a. The upper portion 212b corresponds to the second conductive layer 272, and the lower portion 212a corresponds to the first conductive layer 230. The top region of the channel structure 212 may have a doped region 212c, such as an n-type semiconductor dopant, so that the channel structure 212 can be electrically connected to the bit line BL. In some embodiments, the channel structure 212 may be an epitaxial growth layer, such as a monocrystalline or polycrystalline silicon layer formed by an epitaxial growth process or any combination of the above, and may be undoped or slightly P-type doped epitaxial growth layer. Compared with the comparative example in which the channel structure only partially includes the epitaxial growth layer, since the channel structure 212 including the upper portion 212b and the lower portion 212a of the present invention is formed by an epitaxial growth process, the channel structure 212 may have a lower The resistor has better conductivity, and the memory device 200 can have a faster operating speed (for example, the operating speed of reading and writing).

The thermal oxide layer 232 is located between the first conductive layer 230 and the channel structure 212. For example, the thermal oxide layer 232 surrounds at least a portion of the lower portion 212a of the channel structure 212. In some embodiments, the thermal oxide layer 232 is an oxide formed by directly performing an oxidation process on the first conductive layer 230, such as silicon dioxide (SiO ₂ ). Since the thermal oxide layer 232 is an oxide layer formed by directly oxidizing the conductive layer (for example, the first conductive layer 130), rather than by a deposition process (for example, chemical vapor deposition (CVD), physical vapor deposition ( For the oxide layer formed by PVD or other deposition processes), the purity of the oxide of the thermal oxide layer 232 is greater than that of the insulating layer formed by the deposition method (for example, the first insulating layer 222, the second insulating layer 224 or the third insulating layer) The purity of the oxide of layer 226). Compared with the comparative example in which the thermal oxide layer is an oxide layer formed by a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly oxidizing the conductive layer, the thermal oxide layer has a higher The purity and quality of the oxide can better control the threshold voltage (Vt), so it can have a lower threshold voltage in low-power applications, so that the memory device 200 can have better reliability.

The memory layer 262 is located between the second conductive layer 272 and the upper portion 212 b of the channel structure 212. For example, part of the memory layer 262 extends along the normal direction (for example, the Z-axis direction) of the upper surface 210 a of the substrate 210, and part of the memory layer 262 extends in a direction parallel to the upper surface 210 a of the substrate 210. The memory layer 262 may surround the upper portion 212 b of the channel structure 212 and cover the second conductive layer 272. The memory layer 262 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 262 may include a tunneling layer, a trapping layer, and a blocking layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials.

The dielectric material 266 is located between the memory layer 262 and the second conductive layer 272. Part of the dielectric material 266 may extend along the normal direction of the upper surface 210a of the substrate 210, part of the dielectric material 266 may extend in a direction parallel to the upper surface 210a of the substrate 210, and the dielectric material 266 may cover the first surface 210a. Two conductive layer 272. In some embodiments, the dielectric material 266 may include a high k material, such as aluminum oxide (Al ₂ O ₃ ) or other suitable materials. The dielectric material 266 can also serve as a barrier layer to prevent lateral diffusion of charges. Compared with the comparative example that does not use high-permittivity material as the dielectric material, since the dielectric material 266 in this case can use high-permittivity material, the operation of the memory device can be performed without using too high voltage. (Such as erasing and writing), so the performance of the memory device can be improved.

The isolation structure 274 may pass through the stacked structure S2, and divide the stacked structure S2 into a plurality of sub-stacks. The isolation structure 274 may be formed of an insulating material, such as oxide or other suitable materials. The second conductive layers 272 in adjacent sub-stacks can be physically and electrically separated by the isolation structure 274. Therefore, the second conductive layers 272 in different sub-stacks can operate independently, for example, by applying different voltages.

The conductive connection structure 276 may pass through the stacked structure S2, and is electrically connected to the substrate 210 through the doped region 218, for example. The doped region 218 is, for example, doped with n-type semiconductor dopants. The conductive connection structure 276 may be electrically connected to the common source line.

In some embodiments, each overlap position (intersection) between the first conductive layer 230 and the thermal oxide layer 232 can form a transistor T ₂ , between the second conductive layer 272, the dielectric material 266 and the memory layer 262 Each overlapping position of, can form a memory cell M ₂ . The transistor T ₂ and the memory cell M _{2 are} connected in series through the channel structure 212 and can jointly form a unit cell UN ₂ . The first conductive layer 230 may serve as a ground selection line, and the second conductive layer 272 may serve as a word line.

Compared with the memory device 100, the memory layer 262 of the memory device 200 partially extends along the normal direction of the upper surface 210a of the substrate 210, and the other portion extends along the direction parallel to the upper surface 210a of the substrate 210. Has a class The U-shaped appearance has better ability to prevent the lateral spread of charges and is less likely to affect the threshold voltage.

Figure 1D shows a cross-sectional view of a memory device 300 according to another embodiment of the present disclosure. The memory device 300 and the memory 100 have a similar top view (for example, Figure 1A), so Figure 1D is similar In the cross-sectional view along the line A-A' of Figure 1A. The memory device 300 has a structure similar to that of the memory 100, except that the material of the first conductive layer 330 is different, and the distribution position of the dielectric material 366 is different.

Referring to FIG. 1D, the memory device 300 includes a substrate 310, a stacked structure S3, a cap layer 328, a plurality of channel structures 312, a thermal oxide layer 332, a memory layer 362, a dielectric material 366, and more One isolation structure 374 and a plurality of conductive connection structures 376. The stacked structure S3 is formed on the upper surface 210 a of the substrate 210. The stacked structure S3 includes a first insulating layer 322, a first conductive layer 330, a second insulating layer 324, a second conductive layer 372, and a first insulating layer 322 stacked on the substrate 310 in sequence (for example, along the Z axis). The third insulating layer 326. The cap layer 328 can cover the laminated structure S3, that is, it is located on the third insulating layer 326. In some embodiments, the first conductive layer 330 and the second conductive layer 372 are formed of the same conductive material, such as tungsten (W), aluminum (Al), titanium nitride (TiN), and nitride. Tantalum (TaN), poly-silicon (poly-silicon) or other suitable materials. In this embodiment, both the first conductive layer 330 and the second conductive layer 372 are formed of tungsten. In some embodiments, the thickness of the first conductive layer 330 can be 300 Å to 1000 Å, which can be used to adjust the threshold voltage (Vt).

The channel structure 312 passes through (for example, along the Z axis) the stacked structure S3 and is electrically connected to the substrate 310, wherein each channel structure 312 includes an upper portion 312b and a lower portion 312a. The upper portion 312b corresponds to the second conductive layer 372, The lower portion 312a corresponds to the first conductive layer 330. The top region of the channel structure 312 may have a doped region 312c, such as an n-type semiconductor dopant, so that the channel structure 312 can be electrically connected to the bit line BL. In some embodiments, the channel structure 312 may be an epitaxial growth layer, such as a monocrystalline or polycrystalline silicon layer formed by an epitaxial growth process or any combination of the above, and may be undoped or slightly P-type doped epitaxial growth layer. Compared with the comparative example in which the channel structure only partially includes the epitaxial growth layer, since the channel structure 312 including the upper portion 312b and the lower portion 312a of the present invention is formed by an epitaxial growth process, the channel structure 312 may have a lower The resistor has better conductivity, and the memory device 300 can have a faster operating speed (for example, the operating speed of reading and writing).

The thermal oxide layer 332 is located between the first conductive layer 330 and the channel structure 312. For example, the thermal oxide layer 332 surrounds at least a portion of the lower portion 312a of the channel structure 312. In some embodiments, the thermal oxide layer 332 is an oxide formed by directly performing an oxidation process on the channel structure 312, such as silicon dioxide (SiO ₂ ). Since the thermal oxide layer 332 is an oxide layer formed by directly oxidizing the conductive layer (for example, the channel structure 312), rather than by a deposition process (for example, chemical vapor deposition (CVD), physical vapor deposition (PVD)) Or other deposition processes). The purity of the oxide of the thermal oxide layer 332 is greater than that of the insulating layer formed by the deposition method (for example, the first insulating layer 322, the second insulating layer 324, or the third insulating layer 326). ) The purity of the oxide. Compared with the comparative example in which the thermal oxide layer is an oxide layer formed by a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly oxidizing the conductive layer, the thermal oxide layer has a higher The purity and quality of the oxide can better control the threshold voltage (Vt), so it can have a lower threshold voltage in low-power applications, so that the memory device 300 can have better reliability.

The memory layer 362 is located between the second conductive layer 372 and the upper portion 312b of the channel structure 312. For example, the memory layer 362 extends along the normal direction (for example, the Z-axis direction) of the upper surface 210 a of the substrate 210 and may surround the upper portion 312 b of the channel structure 312. The memory layer 362 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 362 may include a tunnel layer, a capture layer, and a barrier layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials.

The dielectric material 366 is located between the memory layer 362 and the second conductive layer 372 and between the first conductive layer 330 and the thermal oxide layer 332. A part of the dielectric material 366 may extend along the normal direction of the upper surface 310a of the substrate 310, a part of the dielectric material 366 may extend in a direction parallel to the upper surface 310a of the substrate 310, and the dielectric material 366 may cover the first A conductive layer 330 and a second conductive layer 372. In some embodiments, the dielectric material 366 may include a high k material, such as aluminum oxide (Al ₂ O ₃ ) or other suitable materials. The dielectric material 366 can also serve as a barrier layer to prevent lateral diffusion of charges. Compared with the comparative example that does not use high-permittivity material as the dielectric material, since the dielectric material 366 in this case can use high-permittivity material, the operation of the memory device can be performed without using too high voltage. (For example, erasing and writing), so the performance of the memory device 300 can be improved.

The isolation structure 374 may pass through the stacked structure to separate the stacked structure into a plurality of sub-stacks. The isolation structure 374 may be formed of an insulating material, such as oxide Objects or other suitable materials. The second conductive layers 372 in adjacent sub-stacks can be physically and electrically separated by the isolation structure 374. Therefore, the second conductive layers 372 in different sub-stacks can operate independently, for example, by applying different voltages.

The conductive connection structure 376 can pass through the stacked structure, and is electrically connected to the substrate 310 through the doped region 318, for example. The doped region 318 is, for example, doped with n-type semiconductor dopants. The conductive connection structure 376 may be electrically connected to the common source line.

In some embodiments, the overlap between the first conductive layer 330 and the thermal oxide layer 332 can form a transistor T ₃ , and the overlap between the second conductive layer 372, the dielectric material 366 and the memory layer 362 The location can form a memory cell M ₃ . The transistor T ₃ and the memory cell M _{3 are} connected in series through the channel structure 312 and can jointly form a unit cell UN ₃ . The first conductive layer 330 may serve as a ground selection line, and the second conductive layer 372 may serve as a word line.

The above-mentioned embodiments of this case provide some memory devices 100-300 with two conductive layers, but the present invention is not limited to this, and the number of conductive layers can also be greater than two. Among them, some examples of memory devices 400-700 with three conductive layers are listed below. Among the memory devices 400-700, the components similar to the memory devices 100-300 are represented by similar component symbols. The same component names can have the same or similar materials.

FIG. 1E is a cross-sectional view of a memory device 400 according to another embodiment of the present disclosure. The memory device 400 and the memory 100 have a similar top view (for example, FIG. 1A), so FIG. 1E is similar. In the cross-sectional view along the line A-A' in Figure 1.

1E, the memory device 400 includes a substrate 410, a first insulating layer 422, a first conductive layer 430, a second insulating layer 424, a second conductive layer 472, a plurality of channel structures 412, thermal The oxide layer 432 and GO ₄ , a memory layer 462, a third insulating layer 426, a top conductive layer CL4, a top insulating layer OL4, a plurality of isolation structures 474 and a plurality of conductive connection structures 476.

In this embodiment, the first conductive layer 430 and the second conductive layer 472 are formed of different materials, such as n-type doped polysilicon and tungsten (W), respectively. However, the present invention is not based on this. However, the first conductive layer 430 and the second conductive layer 472 can be formed of the same material. In some embodiments, the thickness of the first conductive layer 430 can be 300 Å to 1000 A, which can be used to adjust the threshold voltage (Vt).

The channel structure 412 (for example, along the Z axis) passes through the laminated structure S4 and is electrically connected to the substrate 410. The top region of the channel structure 412 may have a doped region 412c, such as an n-type semiconductor dopant, so that the channel structure 412 can be electrically connected to the bit line BL. In some embodiments, the channel structure 412 may be an epitaxial growth layer, such as a monocrystalline or polycrystalline silicon layer formed by an epitaxial growth process or any combination of the above, and may be undoped or slightly P-doped Epitaxial growth layer.

The thermal oxide layer 432 and the GO ₄ are respectively located between the first conductive layer 430 and the channel structure 412, and between the top conductive layer CL4 and the channel structure 412. For example, the thermal oxide layer 432 surrounds at least a part of the lower part of the channel structure 412, and the thermal oxide layer GO ₄ surrounds at least a part of the upper part of the channel structure 412. In some embodiments, the thermal oxide layer 432 and GO ₄ are an oxide formed by directly performing an oxidation process on the channel structure 412, such as silicon dioxide (SiO ₂ ). Since the thermal oxide layer 432 and GO ₄ is an oxide layer formed by directly oxidizing the channel structure 412, instead of a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD)) or other deposition The purity of the oxide layer formed by the thermal oxide layer 432 and GO ₄ is greater than that of the insulating layer formed by the deposition method (for example, the first insulating layer 422, the second insulating layer 424, or the third insulating layer 426). ) The purity of the oxide. Compared with the comparative example in which the thermal oxide layer is an oxide layer formed by a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly oxidizing the conductive layer, the thermal oxide layer has a higher The purity and quality of the oxide can better control the threshold voltage (Vt), so it can have a lower threshold voltage in low-power applications, so that the memory device 400 can have better reliability.

The memory layer 462 is located between the second conductive layer 472 and the channel structure 412. For example, part of the memory layer 462 extends along the normal direction of the upper surface 410a of the substrate 410 (for example, the Z-axis direction), and part of the memory layer 462 extends in a direction parallel to the upper surface 410a of the substrate 410. The memory layer 462 may surround the channel structure 412 and cover the second conductive layer 472. The memory layer 462 may be composed of _{a composite layer (ie, AONO layer) including aluminum oxide (Al 2} O ₃ , silicon oxide), silicon oxide, silicon nitride, and silicon oxide. For example, the memory layer 462 may include a tunnel layer, a trap layer, and a barrier layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials.

The isolation structure 474 may pass through the stacked structure S4, and divide the stacked structure S4 into a plurality of sub-stacks. The isolation structure 474 may be formed of an insulating material, such as oxide or other suitable materials. The second conductive layers 472 in adjacent sub-stacks can be physically and electrically separated by the isolation structure 474, so the second conductive layers 472 in different sub-stacks can operate independently, for example, by applying different voltages.

The conductive connection structure 476 can pass through the laminated structure S4, and is, for example, transparent The over-doped region 418 is electrically connected to the substrate 410. The doped region 418 is, for example, doped with n-type semiconductor dopants. The conductive connection structure 476 may be electrically connected to the common source line.

In some embodiments, each overlap position (intersection) between the first conductive layer 430 and the thermal oxide layer 432 may form a transistor T ₄ , and each overlap position between the top conductive layer CL4 and the thermal oxide layer GO ₄ A transistor TS ₄ can be formed, and each overlapping position between the second conductive layer 472 and the memory layer 462 can form a memory cell M ₄ . The transistor T ₄ , the transistor TS ₄ and the memory cell M _{4 are} connected in series through the channel structure 412 and can jointly form a unit cell UN ₄ , which can also be referred to as a memory cell series. The first conductive layer 430 can be used as a ground selection line, the second conductive layer 472 can be used as a word line, and the top conductive layer CL4 can be used as a series selection line.

Figure 1F is a cross-sectional view of a memory device 500 according to another embodiment of the present disclosure. The memory device 500 and the memory 100 have a similar top view (for example, Figure 1A), so Figure 1F is similar In the cross-sectional view along the line A-A' in Figure 1.

1F, the memory device 500 includes a substrate 510, a first insulating layer 522, a first conductive layer 530, a second insulating layer 524, a second conductive layer 572, a plurality of channel structures 512, thermal Oxide layers 532 and GO ₅ , a memory layer 562, a third insulating layer 526, a top conductive layer CL5, a top insulating layer OL5, a plurality of isolation structures 574, and a plurality of conductive connection structures 576.

In this embodiment, the first conductive layer 530 and the second conductive layer 572 are formed of different materials, such as n-type doped polysilicon and tungsten (W), respectively. However, the present invention is not based on this. However, the first conductive layer 530 and the second conductive layer 572 can be formed of the same material. In some embodiments, the first conductive layer 530 The thickness can be 300Å~1000A, which can be used to adjust the threshold voltage (Vt).

The channel structure 512 (for example, along the Z axis) passes through the stacked structure S5 and is electrically connected to the substrate 510. The top region of the channel structure 512 may have a doped region 512c, such as an n-type semiconductor dopant, so that the channel structure 512 can be electrically connected to the bit line BL. In some embodiments, the channel structure 512 can be an epitaxial growth layer, such as a single crystal or polysilicon layer formed by an epitaxial growth process or any combination of the above, and can be undoped or slightly P-doped Epitaxial growth layer.

The thermal oxide layer 532 and the GO ₅ are located between the first conductive layer 530 and the channel structure 512, and between the top conductive layer CL5 and the channel structure 512, respectively. For example, the thermal oxide layer 532 surrounds at least a part of the lower part of the channel structure 512, and the thermal oxide layer GO ₅ surrounds at least a part of the upper part of the channel structure 512. In some embodiments, the thermal oxide layer 532 and the GO ₅ are oxides formed by directly oxidizing the channel structure 512, such as silicon dioxide (SiO ₂ ). Since the thermal oxide layer 532 and the GO ₅ are oxide layers formed by directly oxidizing the channel structure 512, rather than by a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD)) or other deposition The purity of the oxide layer formed by the thermal oxide layer 532 and GO ₅ is greater than that of the insulating layer formed by the deposition method (for example, the first insulating layer 522, the second insulating layer 524, or the third insulating layer 526). ) The purity of the oxide. Compared with the comparative example in which the thermal oxide layer is an oxide layer formed by a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly oxidizing the conductive layer, the thermal oxide layer has a higher The purity and quality of the oxide can better control the threshold voltage (Vt), so it can have a lower threshold voltage in low-power applications, so that the memory device 500 can have better reliability.

The memory layer 562 is located between the second conductive layer 572 and the channel structure 512. For example, part of the memory layer 562 extends along the normal direction of the upper surface 510a of the substrate 510 (for example, the Z-axis direction), and part of the memory layer 562 extends in a direction parallel to the upper surface 510a of the substrate 510. The memory layer 562 may surround the channel structure 512 and cover the second conductive layer 572. The memory layer 562 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 562 may include a tunnel layer, a trap layer, and a barrier layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials.

The isolation structure 574 may pass through the stacked structure S5, and divide the stacked structure S5 into a plurality of sub-stacks. The isolation structure 574 may be formed of an insulating material, such as oxide or other suitable materials. The second conductive layers 572 in adjacent sub-stacks can be physically and electrically separated by the isolation structure 574, so the second conductive layers 572 in different sub-stacks can operate independently, for example, by applying different voltages.

The conductive connection structure 576 may pass through the stacked structure S5, and is electrically connected to the substrate 410 through the doped region 518, for example. The doped region 518 is, for example, doped with n-type semiconductor dopants. The conductive connection structure 576 can be electrically connected to the common source line.

In some embodiments, each overlap position (intersection) between the first conductive layer 530 and the thermal oxide layer 532 can form a transistor T ₅ , and each overlap position between the top conductive layer CL5 and the thermal oxide layer GO ₅ A transistor TS ₅ can be formed, and each overlapping position between the second conductive layer 572 and the memory layer 562 can form a memory cell M ₅ . The transistor T ₅ , the transistor TS ₅ and the memory cell M _{5 are} connected in series through the channel structure 512 and can jointly form a unit cell UN ₅ , which can also be referred to as a memory cell series. The first conductive layer 530 can be used as a ground selection line, the second conductive layer 572 can be used as a word line, and the top conductive layer CL5 can be used as a series selection line.

FIG. 1G shows a cross-sectional view of a memory device 600 according to another embodiment of the present disclosure. The memory device 600 and the memory 100 have a similar top view (for example, FIG. 1A), so FIG. 1F is similar. In the cross-sectional view along the line A-A' in Figure 1.

Please refer to Figure 1G, the memory device 600 includes a substrate 610, a first insulating layer 622, a first conductive layer 630, a second insulating layer 624, a second conductive layer 672, a plurality of channel structures 612, thermal The oxide layers 632 and GO ₆ , a memory layer 662, a third insulating layer 626, a top conductive layer CL6, a top insulating layer OL6, a plurality of isolation structures 674 and a plurality of conductive connection structures 676.

The channel structure 612 (for example, along the Z axis) passes through the laminated structure S6 and is electrically connected to the substrate 610. The top region of the channel structure 612 may have a doped region 612c, such as an n-type semiconductor dopant, so that the channel structure 612 can be electrically connected to the bit line BL. In some embodiments, the channel structure 612 can be an epitaxial growth layer, such as a single crystal or polysilicon layer formed by an epitaxial growth process or any combination of the above, and can be undoped or slightly P-doped Epitaxial growth layer.

The thermal oxide layer 632 and the GO ₆ are located between the first conductive layer 630 and the channel structure 612, and between the top conductive layer CL6 and the channel structure 612, respectively. For example, the thermal oxide layer 632 surrounds at least a part of the lower part of the channel structure 612, and the thermal oxide layer GO ₆ surrounds at least a part of the upper part of the channel structure 612. In some embodiments, the thermal oxide layer 632 and GO ₆ are an oxide formed by directly performing an oxidation process on the channel structure 612, such as silicon dioxide (SiO ₂ ). Since the thermal oxide layer 632 and GO ₆ are oxide layers formed by directly oxidizing the channel structure 612, rather than by a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD)) or other deposition The purity of the oxide layer formed by the thermal oxide layer 632 and the GO ₆ oxide is greater than that of the insulating layer formed by the deposition method (for example, the first insulating layer 622, the second insulating layer 624, or the third insulating layer 626). ) The purity of the oxide. Compared with the comparative example in which the thermal oxide layer is an oxide layer formed by a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly oxidizing the conductive layer, the thermal oxide layer has a higher The purity and quality of the oxide can better control the threshold voltage (Vt), so it can have a lower threshold voltage in low-power applications, so that the memory device 600 can have better reliability.

The memory layer 662 is located between the second conductive layer 672 and the channel structure 612. For example, the memory layer 662 extends along the normal direction (for example, the Z-axis direction) of the upper surface 610a of the substrate 610. The memory layer 662 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 662 may include a tunnel layer, a trap layer, and a barrier layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials.

The isolation structure 674 may pass through the stacked structure S6 and divide the stacked structure S6 into a plurality of sub-stacks. The isolation structure 674 may be formed of an insulating material, such as oxide or other suitable materials. The second conductive layers 672 in adjacent sub-stacks can be physically and electrically separated by the isolation structure 674. Therefore, the second conductive layers 672 in different sub-stacks can operate independently, for example, by applying different voltages.

The conductive connection structure 676 can pass through the stacked structure S6, and is electrically connected to the substrate 610 through the doped region 618, for example. The doped region 618 is, for example, doped with n-type semiconductor dopants. The conductive connection structure 676 may be electrically connected to the common source line.

In some embodiments, each overlap position (intersection) between the first conductive layer 630 and the thermal oxide layer 632 can form a transistor T ₆ , and each overlap position between the top conductive layer CL6 and the thermal oxide layer GO ₆ A transistor TS ₆ can be formed, and each overlapping position between the second conductive layer 672 and the memory layer 662 can form a memory cell M ₆ . The transistor T ₆ , the transistor TS ₆ and the memory cell M _{6 are} connected in series through the channel structure 612 and can jointly form a unit cell UN ₆ , which can also be referred to as a memory cell series. The first conductive layer 630 can be used as a ground selection line, the second conductive layer 672 can be used as a word line, and the top conductive layer CL6 can be used as a series selection line.

Figure 1H shows a cross-sectional view of a memory device 700 according to another embodiment of the present disclosure. The memory device 700 and the memory 100 have a similar top view (for example, Figure 1A), so Figure 1H is similar In the cross-sectional view along the line A-A' in Figure 1.

1H, the memory device 700 includes a substrate 710, a first insulating layer 722, a first conductive layer 730, a second insulating layer 724, a second conductive layer 772, a plurality of channel structures 712, oxide The material layer 732 ′, a memory layer 762, a third insulating layer 726, a top conductive layer CL7, a top insulating layer OL7, a plurality of isolation structures 774, and a plurality of conductive connection structures 776. In some embodiments, the first insulating layer 722, the second insulating layer 724, the oxide layer 732', the third insulating layer 726, and the top insulating layer OL7 may be formed of the same material.

The channel structure 712 (e.g., along the Z axis) passes through the laminated structure S7 and It is electrically connected to the substrate 710. The top region of the channel structure 712 may have a doped region 712c, such as an n-type semiconductor dopant, so that the channel structure 712 can be electrically connected to the bit line BL. In some embodiments, the channel structure 712 may be an epitaxial growth layer, such as a monocrystalline or polycrystalline silicon layer formed by an epitaxial growth process or any combination of the above, and may be undoped or slightly P-doped Epitaxial growth layer.

The oxide layer 732' is located between the first conductive layer 730 and the channel structure 712, and between the top conductive layer CL7 and the channel structure 712.

The memory layer 762 is located between the second conductive layer 772 and the channel structure 712. For example, a part of the memory layer 762 extends along the normal direction (for example, the Z-axis direction) of the upper surface 710a of the substrate 710, and a part of the memory layer 762 extends in a direction parallel to the upper surface 710a of the substrate 710. The memory layer 762 may be composed of a composite layer including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 762 may include a tunneling layer, a trapping layer, and a barrier layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials.

The isolation structure 774 may pass through the stacked structure S7, and divide the stacked structure S7 into a plurality of sub-stacks. The isolation structure 774 may be formed of an insulating material, such as oxide or other suitable materials. The second conductive layers 772 in adjacent sub-stacks can be physically and electrically separated by the isolation structure 774. Therefore, the second conductive layers 772 in different sub-stacks can operate independently, for example, by applying different voltages.

The conductive connection structure 776 can pass through the stacked structure S7, and is electrically connected to the substrate 710 through the doped region 718, for example. The doped region 718 is, for example, an n-type Doped with semiconductor dopants. The conductive connection structure 776 can be electrically connected to the common source line.

Each of the first conductive layer 732 overlaps with the oxide layer 730 in some embodiments, the 'overlap of each position (intersection) between the can _7, CL7 top conductive layer and the oxide layer 732 is formed a transistor T' between the The position can form a transistor TS ₇ , and each overlapping position between the second conductive layer 772 and the memory layer 762 can form a memory cell M ₇ . The transistor T ₇ , the transistor TS ₇ and the memory cell M _{7 are} connected in series through the channel structure 712 and can jointly form a unit cell UN ₇ , which can also be referred to as a memory cell series. The first conductive layer 730 can be used as a ground selection line, the second conductive layer 772 can be used as a word line, and the top conductive layer CL7 can be used as a series selection line.

2A to 2N are cross-sectional views illustrating a method of forming the memory device 100 according to an embodiment of the disclosure.

Referring to FIG. 2A, a substrate 110 is provided, and a laminated body S1' is formed on the upper surface 110a of the substrate 110. The laminated body S1' includes sequentially (for example, by a deposition process) stacked on the substrate 110 A first insulating layer 122, a first conductive layer 130, a second insulating layer 124, an upper sacrificial layer 140, and a third insulating layer 126 on the surface 110a.

In some embodiments, the substrate 110 may be a silicon substrate or other suitable substrates. The first insulating layer 122, the second insulating layer 124, and the third insulating layer 126 may be formed of oxide, such as silicon dioxide. The first conductive layer 130 may be formed of a conductive material, such as tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), doped or undoped polysilicon (poly -silicon) or other suitable materials. In some embodiments, the first conductive layer 130 may be an n-type doped polysilicon layer. The upper sacrificial layer 140 may be formed of silicon nitride (SiN).

Referring to FIG. 2B, a plurality of first openings 152 are formed, and each first opening 152 passes through the laminated body S1' to expose a part of the substrate 110 to the outside. In some embodiments, the first opening 152 may be formed by an etching method, such as a dry etching method. In some embodiments, the substrate 110 may be overetched so that the bottom of the first opening 152 is lower than the upper surface 110 a of the substrate 110.

Referring to FIG. 2C, a part of the oxide layer 132' is formed on the side surface of the first conductive layer 130 exposed by the first opening 152 by an oxidation process, and the substrate 110 exposed by the first opening 152 A part of the oxide layer 132' is formed on the surface. In some embodiments, the first conductive layer 130 is an n-type doped polysilicon layer, and the substrate 110 is a silicon substrate. After an oxidation process and high temperature, the side surface of the first conductive layer 130 exposed by the first opening 152 is formed including An oxide layer 132' of silicon dioxide, and an oxide layer 132' including a silicon dioxide layer is formed on the surface of the substrate 110 exposed by the first opening 152.

Referring to FIG. 2D, the excess oxide layer 132' in the first opening 152 is removed to form a thermal oxide layer 132 directly in contact with the first conductive layer 130, and the substrate 110 is exposed. In some embodiments, the excess oxide layer 132' in the first opening 152 is removed by soaking in a solvent, such as hydrofluoric acid (HF). Since the thermal oxide layer 132 is an oxide layer formed by directly oxidizing a conductive layer (for example, the first conductive layer 130), rather than by a deposition process (for example, chemical vapor deposition (CVD), physical vapor deposition ( For the oxide layer formed by PVD or other deposition processes), the purity of the oxide of the thermal oxide layer 132 is greater than that of the insulating layer formed by the deposition method (for example, the first insulating layer 122, the second insulating layer 124 or the third insulating layer). The purity of the oxide of layer 126).

Please refer to Figure 2E, the coating is formed by a first epitaxial growth process The thermal oxide layer 132 covers the lower portion 112a of the channel structure, and the thermal oxide layer 132 is located between the first conductive layer 130 and the lower portion 112a of the channel structure. That is, the lower portion 112a of the channel structure is an epitaxial growth layer of silicon. The height of the top surface of the lower portion 112 a of the channel structure is greater than the height of the top surface of the first conductive layer 130.

Thereafter, the P-type dopant is implanted into the lower portion 112a of the channel structure by an ion implantation. This P-type dopant helps to adjust the threshold voltage.

Referring to FIG. 2F, a memory layer 162 is formed to cover part of the sidewall of the first opening 152 and the lower portion 112a of the channel structure. The memory layer 162 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 162 may include a tunneling layer, a trapping layer, and a blocking layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials.

Then, a protective layer 164 is formed on the memory layer 162 by a deposition process. The protective layer 164 can prevent the memory layer 162 from being damaged in the subsequent manufacturing process. The protective layer 164 is, for example, silicon nitride, polysilicon or other suitable materials.

Referring to FIG. 2G, a portion of the memory layer 162 and the protective layer 164 are removed by an etching process to expose the lower portion 112a of the channel structure. The etching process can be a dry etching process or a wet etching process.

Referring to FIG. 2H, the protective layer 164 is removed by soaking in a solvent, so that the memory layer 162 is exposed. The solvent is, for example, hot phosphoric acid (H ₃ PO ₄ ), but the present invention is not limited to this, as long as it is a solvent that can remove the protective layer 164 but does not damage the memory layer 162.

Referring to FIG. 21, the upper portion 112b of the channel structure is formed by a second epitaxial growth process, and thus the channel structure 112 including the lower portion 112a and the upper portion 112b is deformed. In this embodiment, the channel structure 112 is an epitaxial growth layer of silicon.

Thereafter, an ion implantation is used to form a doped region 112c on the top of the channel structure 112. The doped region 112c is, for example, a heavily doped region of an n-type semiconductor. The doped region 112c can be used to form a contact structure in a subsequent process to be electrically connected to the bit line.

Referring to FIG. 2J, a cover layer 128 covering the laminated body S1' is formed by a deposition process, that is, the cover layer 128 covers the third insulating layer 126 and the channel structure 112.

Thereafter, a second opening 154 passing through the laminated body S1' is formed by an etching process. The etching process is, for example, a dry etching process. After that, an ion implantation can be used to form the doped region 118 on the substrate 110 corresponding to the second opening 154. The doped region 118 includes, for example, a heavily doped n-type semiconductor. Alternatively, the step of forming the doped region 118 may be performed after the upper sacrificial layer 140 is removed.

Referring to FIG. 2K, the upper sacrificial layer 140 is removed from the second opening 154 by an etching process to form an upper opening 156 where the upper sacrificial layer 140 is removed. The etching process may be isotropic etching (for example, wet etching), and may be a highly selective etching, for example, selective etching of silicon nitride instead of silicon dioxide and polysilicon.

Then, by a deposition process, a dielectric material 166 extending along the sidewalls of the second opening 154 and the upper opening 156 and covering the cover layer 128 is formed. In some embodiments, the dielectric material 166 may include a high k material, such as aluminum oxide (Al ₂ O ₃ ) or other suitable materials. The dielectric material 166 can also serve as a barrier layer to prevent lateral diffusion of charges.

Referring to FIG. 2L, the conductive material 172' is filled in the second opening 154 and the upper opening 156 by a deposition process. The conductive material 172' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable materials.

Referring to FIG. 2M, the conductive material 172' in the second opening 154 is removed by an etching process to form the second conductive layer 172 in the upper opening 156. The etching process is, for example, a dry etching process. In some embodiments, the etching process can remove part of the conductive material in the upper opening 156 at the same time. The second conductive layer 172 may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable conductive materials. In this embodiment, the second conductive layer 172 includes tungsten (W). Thereby, a stacked structure S1 including the first insulating layer 122, the first conductive layer 130, the second insulating layer 124, the second conductive layer 172, and the third insulating layer 126 is formed.

Referring to FIG. 2N, an insulating material is filled in the second opening 154 through a deposition process to form a plurality of isolation structures 174. The isolation structure 174 may include oxide or other suitable insulating materials.

Thereafter, referring back to Figure 1B, a plurality of vertical openings passing through the isolation structure 174 and extending along the normal direction of the upper surface 110a of the substrate 110 are formed, and then a conductive material is filled in the vertical openings by a deposition process , To form a plurality of conductive connection structures 176. The conductive connection structure 176 may include tungsten (W), aluminum (Al), titanium nitride (TiN), or other suitable conductive materials. In this way, the memory device 100 as shown in FIG. 1B is formed.

3A to 3M are cross-sectional views illustrating a method of forming the memory device 200 according to an embodiment of the disclosure.

Referring to FIG. 3A, a substrate 210 is provided, and a laminated body S2' is formed on the upper surface 210a of the substrate 210. The laminated body S2' includes sequentially (for example, by a deposition process) stacked on the substrate 210 A first insulating layer 222, a first conductive layer 230, a second insulating layer 224, an upper sacrificial layer 240, and a third insulating layer 226 on the surface 210a.

In some embodiments, the substrate 202 may be a silicon substrate or other suitable substrates. The first insulating layer 222, the second insulating layer 224, and the third insulating layer 226 may be formed of oxide, such as silicon dioxide. The first conductive layer 230 may be formed of a conductive material, such as tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), doped or undoped polysilicon (poly -silicon) or other suitable materials. In some embodiments, the first conductive layer 230 may be an n-type doped polysilicon layer. The upper sacrificial layer 240 may be formed of silicon nitride (SiN).

Referring to FIG. 3B, a plurality of first openings 252 are formed, and each first opening 252 passes through the laminated body S2' to expose a part of the substrate 210 to the outside. In some embodiments, the first opening 252 may be formed by an etching method, such as a dry etching method. In some embodiments, the substrate 210 may be overetched, so that the bottom of the first opening 252 is lower than the upper surface 210 a of the substrate 210.

Referring to FIG. 3C, a dopant 211 is implanted in the substrate 210 corresponding to the first opening 252 by an ion implantation. The dopant 211 is, for example, a P-type dopant. The dopant 211 helps to adjust the threshold voltage.

Referring to FIG. 3D, a portion of the oxide layer 232' is formed on the side surface of the first conductive layer 230 exposed by the first opening 252 by an oxidation process, and the substrate 210 exposed by the first opening 252 A part of the oxide layer 232' is formed on the surface. In some embodiments, the first conductive layer 230 is n-type doped The substrate 210 is a silicon substrate. After an oxidation process and high temperature, the side surface of the first conductive layer 230 exposed by the first opening 252 forms an oxide layer 232' including silicon dioxide. An oxide layer 232' including silicon dioxide is formed on the surface of the substrate 210 exposed by 252.

Referring to FIG. 3E, the excess oxide layer 232' in the first opening 252 is removed to form a thermal oxide layer 232 directly in contact with the first conductive layer 230, and the substrate 210 is exposed. In some embodiments, the excess oxide layer 232' in the first opening 252 is removed by soaking in a solvent, such as hydrofluoric acid (HF). Since the thermal oxide layer 232 is an oxide layer formed by directly oxidizing the conductive layer (for example, the first conductive layer 230), rather than by a deposition process (for example, chemical vapor deposition (CVD), physical vapor deposition ( For the oxide layer formed by PVD or other deposition processes), the purity of the oxide of the thermal oxide layer 232 is greater than that of the insulating layer formed by the deposition method (for example, the first insulating layer 222, the second insulating layer 224 or the third insulating layer). The purity of the oxide of layer 226).

Referring to FIG. 3F, the lower portion 212a and the upper portion 212b of the channel structure 212 are formed by the same first epitaxial growth process. The lower portion 212 a of the channel structure 212 corresponds to the first conductive layer 230. The upper portion 212 b of the channel structure 212 corresponds to the upper sacrificial layer 240. The lower portion 212 a of the channel structure 212 covers the thermal oxide layer 232, and the thermal oxide layer 232 is located between the first conductive layer 230 and the lower portion 212 a of the channel structure 212. In this embodiment, the entire channel structure 212 is an epitaxial growth layer of silicon.

Thereafter, a doped region 212c is formed on the top surface of the channel structure 212 by an ion implantation. The doped region 212c is, for example, a heavily doped region of an n-type semiconductor. The doped region 212c can be used to form a contact structure in a subsequent process to be electrically connected to the bit line.

Referring to FIG. 3G, a cover layer 228 covering the stacked body S2' is formed by a deposition process, that is, the cover layer 228 covers the third insulating layer 226 and the channel structure 212. In this embodiment, the dopant 211 can be dispersed to the lower portion 212a of the channel layer 212 by a thermal process. The thermal process can activate the dopant 211.

Referring to FIG. 3H, the second opening 254 passing through the laminated body S2' is formed by an etching process. The etching process is, for example, a dry etching process. After that, a doped region 218 can be formed on the substrate 210 through the second opening 254. The doped region 218 includes, for example, a heavily doped n-type semiconductor. Alternatively, the step of forming the doped region 218 may be performed after the upper sacrificial layer 240 is removed.

Referring to FIG. 31, the upper sacrificial layer 240 is removed from the second opening 254 by an etching process to form an upper opening 256 where the upper sacrificial layer 240 is removed. The etching process can be isotropic etching (for example, wet etching), and can be a highly selective etching, for example, selective etching of silicon nitride (SiN) without etching silicon dioxide (SiO ₂ ).

Then, by a deposition process, a memory layer 262 and a dielectric material 266 extending along the sidewalls of the second opening 254, the sidewalls of the upper opening 256, and part of the sidewalls of the channel structure 212 and covering the capping layer 128 are sequentially formed. The memory layer 262 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 162 may include a tunneling layer, a trapping layer, and a blocking layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials. In some embodiments, the dielectric material 266 may include a high k material, such as aluminum oxide (Al ₂ O ₃ ) or other suitable materials. The dielectric material 166 can also serve as a barrier layer to prevent lateral diffusion of charges.

Referring to FIG. 3J, the conductive material 272' is filled in the second opening 254 and the upper opening 256 by a deposition process. The conductive material 272' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable materials.

Referring to FIG. 3K, the conductive material 272' in the second opening 254 is removed by an etching process to form the second conductive layer 272 in the upper opening 256. The etching process is, for example, a dry etching process. In some embodiments, the etching process can remove part of the conductive material in the upper opening 256 at the same time. The second conductive layer 272 may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable conductive materials. In this embodiment, the second conductive layer 272 includes tungsten (W). Thereby, a stacked structure S2 including the first insulating layer 222, the first conductive layer 230, the second insulating layer 224, the second conductive layer 272, and the third insulating layer 226 is formed.

Referring to FIG. 3L, an insulating material is filled in the second opening 254 by a deposition process to form a plurality of isolation structures 274. The isolation structure 274 may include oxide or other suitable insulating materials.

Referring to FIG. 3M, a plurality of vertical openings 259 passing through the isolation structure 274 and extending along the normal direction of the upper surface 210a of the substrate 210 are formed.

Thereafter, referring back to FIG. 1C, a conductive material is filled in the vertical openings 259 by a deposition process to form a plurality of conductive connection structures 276. The conductive connection structure 276 may include tungsten (W), aluminum (Al), titanium nitride (TiN), or other suitable conductive materials. In this way, the memory device 200 as shown in FIG. 1C is formed.

4A to 4L are cross-sectional views of a method of forming the memory device 300 according to an embodiment of the disclosure.

Referring to FIG. 4A, a substrate 310 is provided, and a laminated body S3' is formed on the upper surface 310a of the substrate 310. The laminated body S3' includes stacking on the substrate 310 in sequence (for example, by a deposition process) A first insulating layer 322, a lower sacrificial layer 342, a second insulating layer 324, an upper sacrificial layer 340, and a third insulating layer 326 on the surface 310a.

In some embodiments, the substrate 310 may be a silicon substrate or other suitable substrates. The first insulating layer 322, the second insulating layer 324, and the third insulating layer 326 may be formed of oxide, such as silicon dioxide. The lower sacrificial layer 342 and the upper sacrificial layer 340 may be formed of silicon nitride (SiN).

Referring to FIG. 4B, a plurality of first openings 352 are formed, and each first opening 352 passes through the laminated body S3' to expose a part of the substrate 310 to the outside. In some embodiments, the first opening 352 may be formed by an etching process, such as a dry etching process. In some embodiments, the substrate 310 may be overetched so that the bottom of the first opening 352 is lower than the upper surface 310 a of the substrate 310.

Referring to FIG. 4C, the lower portion 312a of the channel structure is formed by a first epitaxial growth process. That is, the lower part 312a of the channel structure is an epitaxial growth layer of silicon. The height of the top surface of the lower part 312 a of the channel structure is greater than the height of the top surface of the lower sacrificial layer 342.

Thereafter, the P-type dopant is implanted into the lower portion 312a of the channel structure by an ion implantation. This P-type dopant helps to adjust the threshold voltage.

Referring to FIG. 4D, a memory layer 362 is formed to cover part of the sidewall of the first opening 352 and the lower part 312a of the channel structure. The memory layer 362 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 362 may include a tunnel layer, a capture layer, and a barrier layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials.

Then, a protective layer 364 is formed on the memory layer 362 by a deposition process. The protective layer 364 can prevent the memory layer 362 from being damaged in the subsequent manufacturing process. The protective layer 364 is, for example, silicon nitride, polysilicon or other suitable materials.

Referring to FIG. 4E, a portion of the memory layer 362 and the protective layer 364 are removed by an etching process to expose the lower portion 312a of the channel structure. The etching process can be a dry etching process or a wet etching process.

Referring to FIG. 4F, the protective layer 364 is removed by soaking in a solvent, so that the memory layer 362 is exposed. The solvent is, for example, hot phosphoric acid (H ₃ PO ₄ ), but the present invention is not limited to this, as long as it is a solvent that can remove the protective layer 364 but does not damage the memory layer 362.

Referring to FIG. 4G, the upper portion 312b of the channel structure is formed by a second epitaxial growth process, and thus the channel structure 312 including the lower portion 312a and the upper portion 312b is deformed. In this embodiment, the channel structure 312 is an epitaxial growth layer of silicon.

Thereafter, an ion implantation is used to form a doped region 312c on the top of the channel structure 312. The doped region 312c is, for example, a heavily doped region of an n-type semiconductor. The doped region 312c can be used to form a contact structure in a subsequent process to be electrically connected to the bit line.

Then, a covering layer 328 covering the laminated body S3' is formed by a deposition process, that is, the covering layer 328 covers the third insulating layer 326 and the channel structure 312.

Referring to FIG. 4H, the second opening 354 passing through the laminated body S3' is formed by an etching process. The etching process is, for example, a dry etching process. After that, an ion implantation can be used to form a doped region 318 on the substrate 310 corresponding to the second opening 354. The doped region 318 includes, for example, a heavily doped n-type semiconductor. Alternatively, the step of forming the doped region 318 may be performed after the upper sacrificial layer 340 and the lower sacrificial layer 342 are removed.

Referring to FIG. 4I, the upper sacrificial layer 340 and the lower sacrificial layer 342 are removed from the second opening 354 by an etching process to form upper openings 356 and 342 at the positions where the upper sacrificial layer 340 and the lower sacrificial layer 342 are removed, respectively Lower opening 358. The etching process may be isotropic etching (for example, wet etching), and may be a highly selective etching, for example, selective etching of silicon nitride instead of silicon dioxide.

Then, a thermal oxide layer 332 is formed on the side surface of the channel structure 312 exposed by the lower opening 358 by an oxidation process. In some embodiments, the channel structure 312 is an epitaxial growth layer of silicon. After an oxidation process and high temperature, the side surface of the channel structure 312 exposed by the lower opening 358 forms a thermal oxide layer 332 including silicon dioxide.

Thereafter, by a deposition process, a dielectric material 366 extending along the sidewalls of the second opening 354, the lower opening 358 and the upper opening 356 and covering the cover layer 328 is formed. In some embodiments, the dielectric material 366 may include a high k material, such as aluminum oxide (Al ₂ O ₃ ) or other suitable materials. The dielectric material 366 can also serve as a barrier layer to prevent lateral diffusion of charges.

Referring to FIG. 4J, the conductive material 372' is filled in the second opening 354, the lower opening 358, and the upper opening 356 by a deposition process. The conductive material 372' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable materials.

Referring to FIG. 4K, the conductive material 372' in the second opening 354 is removed by an etching process to form the first conductive layer 330 in the lower opening 358 and the second conductive layer in the upper opening 356 372. The etching process is, for example, a dry etching process. In some embodiments, the etching process can remove part of the conductive material 372' located in the upper opening 356 and the lower opening 358 at the same time. The first conductive layer 330 and the second conductive layer 372 may respectively include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable conductive materials. In this embodiment, the first conductive layer 330 and the second conductive layer 372 may include the same conductive material, such as tungsten (W). Thereby, a stacked structure S3 including the first insulating layer 322, the first conductive layer 330, the second insulating layer 324, the second conductive layer 372, and the third insulating layer 326 is formed.

Referring to FIG. 4L, an insulating material is filled in the second opening 354 by a deposition process to form a plurality of isolation structures 374. The isolation structure 374 may include oxide or other suitable insulating materials.

After that, please refer back to Figure 1D to form a plurality of vertical openings passing through the isolation structure 374 and extending along the normal direction of the upper surface 310a of the substrate 310, and then a conductive material is filled in the vertical openings by a deposition process , To form a plurality of conductive connection structures 376. The conductive connection structure 376 may include tungsten (W), aluminum (Al), Titanium nitride (TiN) or other suitable conductive materials. In this way, the memory device 300 as shown in FIG. 1D is formed.

FIG. 5 is an equivalent circuit diagram of the memory device 100, 200 or 300 according to an embodiment of the disclosure.

The memory device 100, 200, or 300 may be a three-dimensional NOR type memory device. In the array area of the memory device 100, 200, or 300, three word lines WL0, WL1, WL2, three bit lines BL0, BL1, BL2, and three ground selection lines GSL0, GSL1, GSL2 are exemplarily shown. However, the present invention is not limited to this, and the number of word lines, bit lines, and ground selection lines may be greater than three, respectively. The overlapping position of each character line and the channel structure forms a memory cell M, and the overlapping position of each ground selection line and the channel structure forms a transistor T. The memory cell M is located above the transistor T, and the channel structure connects the memory cell M and the transistor T in series. A memory cell M and a transistor T can jointly form a unit cell UN. Each transistor T is electrically connected to the common source line CSL. The word lines (such as WL0, WL1, WL2) can be electrically isolated by the isolation structure.

FIG. 6A is an equivalent circuit diagram of a memory device programmed by Fowler-Nordheim injection according to an embodiment of the present disclosure.

Please refer to FIG. 6A. To _{perform a programming operation on the target cell memory cell UN t} , the word line WL0 and the ground selection line GSL0 are selected, the word line WL0 is applied with the programming voltage Vpgm1, and the ground selection line GSL0 is applied with 0V. The word line WL1 and the ground selection line GSL1 are not selected, and 0 volt (V) is applied. The common source line applies a common source voltage V _CSL . 0V is applied to the bit line BL0. The bit line BL1 applies the inhibit voltage V _inhibit . The cell memory cell coupled to the bit line BL1 is inhibited.

FIG. 6B is an equivalent circuit diagram of a memory device that performs a programming operation by channel-hot-electron injection according to an embodiment of the present disclosure.

Please refer to FIG. 6B. To program the target cell UN _t , the word line WL0 and the ground selection line GSL0 are selected. The word line WL0 is applied with the programming voltage Vpgm1, and the ground selection line GSL0 is applied with the programming voltage Vpgm2. The word line WL1 and the ground selection line GSL1 are not selected, and 0 volt (V) is applied. 0V is applied to the common source line CSL. The bit line BL0 applies the drain programming voltage Vdpgm. 0V is applied to the bit line BL1. The programming voltage Vpgm2 may be less than the programming voltage Vpgm1. In some embodiments, the programming voltage Vpgm1 may be 5-10V. The drain programming voltage Vdpgm can be 4-10V.

FIG. 7A is an equivalent circuit diagram of a memory device that is erased by Fowler-Nordham injection according to an embodiment of the present disclosure.

Please refer to FIG. 7A. To _{erase the target cell UN t} (for example, including 2 memory cells and 2 transistors), the word line WL0 and the ground selection line GSL0 are selected. 0V is applied to the word line WL0. The ground selection line GSL0 applies the erase voltage Vers2. The word line WL1 and the ground selection line GSL1 are not selected, and both are floating (that is, no voltage is applied). The common source line applies a common source voltage V _CSL . P-type well (p well) applies a P-type well voltage V _PWI . An erase voltage Vers1 is applied to the peripheral circuit. The bit lines BL0 and BL1 are floating. The common source voltage V _CSL may be the same as the erase voltage Vers1 and the P-well voltage V _PWI .

FIG. 7B shows an equivalent circuit diagram of a memory device using a band-to-band tunneling induced hot hole injection operation according to an embodiment of the present disclosure.

Please refer to FIG. 7B. To _{perform an erase operation on the target cell UN t} , the word line WL0 and the ground selection line GSL0 are selected. 0V is applied to the ground selection line GSL0. The word line WL0 is applied with a ground erase voltage Vgers. The ground erase voltage Vgers can be less than zero. The word line WL1 and the ground selection line GSL1 are not selected, and 0 volt (V) is applied. The bit line BL0 can be applied with a drain erase voltage Vders. The drain erase voltage Vders can be greater than zero. 0V can be applied to the bit line BL1. The common source line applies a common source voltage V _CSL . Use bit line bias (BL bias) (erase/inhibit) (+Vders is used for erasing, 0V is not used for suppression) to apply Fowler-Nordheim erase (Fowler-Nordheim erase) to perform bit Replacement of element line erasing operation (all GSL (such as GSL0, GSL1...)=0V, CSL=+Vcs1).

FIG. 8 is an equivalent circuit diagram of a memory device in a read operation according to an embodiment of the disclosure.

Please refer to FIG. 8. To _{perform a read operation on the target cell UN t} (for example, including 2 memory cells and 2 transistors), the word line WL0 and the ground selection line GSL0 are selected. The word line WL0 can be applied with 0V. _{A power supply voltage V CC} can be applied to the ground selection line GSL0. The word line WL1 and the ground selection line GSL1 are not selected, and 0 volt (V) is applied. The bit lines BL0 and BL1 can be applied with a bit line read voltage Vblr. The common source line applies a common source voltage V _CSL . When performing a read operation in the memory device of the present invention, all voltages applied to the bit line, word line, and ground selection line can be equal to or less than the power supply voltage V _CC , so power consumption can be reduced.

9A to 9R are cross-sectional views illustrating a method of forming a memory device 400 according to an embodiment of the present disclosure.

Please refer to FIG. 9A, a substrate 410 is provided, and a laminated body S4' is formed on the upper surface 410a of the substrate 410, and the laminated body S4' includes sequential (for example (By a deposition process), a lower sacrificial layer 442, a second insulating layer 424, an upper sacrificial layer 440, a third insulating layer 426, a top sacrificial layer SF4, and a top insulating layer are stacked on the upper surface 410a of the substrate 410 Layer OL4.

In some embodiments, the substrate 410 may be a silicon substrate or other suitable substrates. The second insulating layer 424, the third insulating layer 426, and the top insulating layer OL4 may be formed of oxide, such as silicon dioxide. The lower sacrificial layer 442, the upper sacrificial layer 440, and the top sacrificial layer SF4 may be formed of silicon nitride (SiN).

Referring to FIG. 9B, a plurality of first openings 452 are formed, and each of the first openings 452 passes through the laminated body S4' to expose a part of the substrate 410 to the outside. In some embodiments, the first opening 452 may be formed by an etching process, such as a dry etching process. In some embodiments, the substrate 410 may be overetched so that the bottom of the first opening 452 is lower than the upper surface 410a of the substrate 410.

Referring to FIG. 9C, the channel structure 412 is formed by a first epitaxial growth process. That is, in this embodiment, the entire channel structure 412 (including the lower part and the upper part) is an epitaxial growth layer of silicon.

Referring to FIG. 9D, a plurality of first trenches SLT1 passing through the top sacrificial layer SF4 and the top insulating layer OL4 are formed by an etching process.

Referring to FIG. 9E, the top sacrificial layer SF4 is removed through the first trench SLT1. The space where the top sacrificial layer SF4 is removed forms a top opening 460. _{Then, a thermal oxide layer GO 4} is formed on one side surface of the upper portion of the exposed channel structure 412 by an oxidation process. In some embodiments, the channel structure 412 is a P-type doped polysilicon epitaxial growth layer. After an oxidation process and high temperature, the exposed side surface of the channel structure 412 forms a thermal oxide layer GO ₄ including silicon dioxide.

Please refer to Fig. 9F, through a deposition process in the top opening 460 And a conductive material CL4' is deposited in the first trench SLT1. The conductive material CL4' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), doped or undoped poly-silicon (poly-silicon) or other suitable materials.

Referring to FIG. 9G, a portion of the conductive material CL4' is removed by an etching process to form a top opening P1, and a top conductive layer CL4 is formed between the third insulating layer 426 and the top insulating layer OL4.

Referring to FIG. 9H, an insulating material is filled in the top opening P1 through a deposition process.

Referring to FIG. 9I, a second trench SLT2 passing through the top insulating layer OL4 and the third insulating layer 426 is formed by an etching process, and then the upper sacrificial layer 440 is removed to form an upper opening 456. Thereafter, by a deposition process, a memory layer 462 extending along the second trench SLT2 and the upper opening 456 is formed. The memory layer 462 may be made of aluminum oxide (Al ₂ O ₃ , aluminum oxide), silicon oxide (silicon oxide) Layer, a composite layer of a silicon nitride layer and a silicon oxide layer (ie, an AONO layer).

Referring to FIG. 9J, a conductive material 472' is deposited on the memory layer 462 through a deposition process. The conductive material 472' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable conductive materials. That is, the conductive material 472' is filled in the second trench SLT2 and the upper opening 456.

Referring to FIG. 9K, a portion of the conductive material 472' and the memory layer 462 are removed by an etching process to form the third trench SLT3, and the third trench SLT3 is left between the second insulating layer 424 and the third insulating layer 426 Two conductive layers 472 and a memory layer 462.

Referring to FIG. 9L, an insulating material is filled in the third trench SLT3 through a deposition process.

Referring to FIG. 9M, a second opening 454 is formed through the lower sacrificial layer 442, the second insulating layer 424, the third insulating layer 426, and the top insulating layer OL4 through an etching process. Thereafter, the lower sacrificial layer 442 is removed from the second opening 454 by an etching process, and a lower opening 458 is formed where the lower sacrificial layer 442 is removed.

Referring to FIG. 9N, a thermal oxide layer 432 is formed on one side surface of the channel structure 412 exposed by the lower opening 458 by an oxidation process, and a first insulating layer 422 is formed on the upper surface exposed by the substrate 410. For example, the thermal oxide layer 432 and the first insulating layer 422 may each include silicon dioxide.

Referring to FIG. 90, the conductive material 430' is filled in the second opening 454 and the lower opening 458 by a deposition process. The conductive material 430' may include polysilicon or other suitable materials.

Referring to FIG. 9P, the conductive material 430' in the second opening 454 is removed by an etching process to form the first conductive layer 430 in the lower opening 458. In some embodiments, the etching process can remove part of the conductive material in the lower opening 458 at the same time. The first conductive layer 430 may include polysilicon or other suitable conductive materials. Thereby, a laminated structure including the first insulating layer 422, the first conductive layer 430, the second insulating layer 424, the second conductive layer 472, the third insulating layer 426, the top conductive layer CL4, and the top insulating layer OL ₄ is formed S4. In some embodiments, doped regions 412c and 418 can be formed by implanting an ion on the top of the channel structure 412 and the surface of the substrate 410 exposed to the second opening 454, respectively. The doped regions 412c and 418 are, for example, n-type Heavily doped regions of semiconductors. The dopants 412c and 418 can be used to form contact structures in subsequent processes to be electrically connected to the bit line and the common source line, respectively.

Referring to FIG. 9Q, through a deposition process, an insulating material is filled in the second opening 454 to form a plurality of isolation structures 474. Isolation structure 474 It may include oxide or other suitable insulating materials.

Referring to FIG. 9R, a plurality of vertical openings 459 passing through the isolation structure 474 and extending along the normal direction of the upper surface 410a of the substrate 410 are formed.

Thereafter, referring back to FIG. 1E, a conductive material is filled in the vertical openings 459 by a deposition process to form a plurality of conductive connection structures 476. The conductive connection structure 476 may include tungsten (W), aluminum (Al), titanium nitride (TiN), or other suitable conductive materials. In this way, a memory device 400 as shown in FIG. 1E is formed.

10A to 10K are cross-sectional views illustrating a method of forming a memory device 500 according to an embodiment of the disclosure.

Referring to FIG. 10A, a substrate 510 is provided, and a laminated body S5' is formed on the upper surface 510a of the substrate 510. The laminated body S5' includes sequentially (for example, by a deposition process) stacked on the substrate 510 A first insulating layer 522, a first conductive layer 530, a second insulating layer 524, an upper sacrificial layer 540, a third insulating layer 526, a top conductive layer CL5, and a top insulating layer OL5 on the surface 510a.

In some embodiments, the substrate 510 may be a silicon substrate or other suitable substrates. A first insulating layer 522, a second insulating layer 524, a third insulating layer 526, and a top insulating layer OL5 may be formed of oxide, such as silicon dioxide. The upper sacrificial layer 540 may be formed of silicon nitride (SiN).

Referring to FIG. 10B, a plurality of first openings 552 are formed, and each first opening 552 passes through the laminated body S5' to expose a part of the substrate 510 to the outside. In some embodiments, the first opening 552 may be formed by an etching process, such as a dry etching process. In some embodiments, the substrate 510 may be overetched so that the bottom of the first opening 552 is lower than the upper surface 510a of the substrate 510.

Referring to FIG. 10C, a portion of the oxide layer 532' is formed on the side surface of the first conductive layer 530 exposed by the first opening 552 by an oxidation process, and the substrate 510 exposed by the first opening 552 forming a portion of a surface of an oxide layer 532 ', and the side surface of the top conductive layer is formed of a CL5 oxide layer GO _5. In some embodiments, the first conductive layer 530 and the top conductive layer CL5 are respectively n-type doped polysilicon layers, and the substrate 510 is a silicon substrate. After an oxidation process and high temperature, the first conductive layer exposed by the first opening 552 An oxide layer 532' including silicon dioxide is formed on the side surface of 530, and an oxide layer 532' including a silicon dioxide layer is formed on the surface of the substrate 510 exposed by the first opening 552.

Referring to FIG. 10D, the excess oxide layer 532' in the first opening 552 is removed to form a thermal oxide layer 532 directly in contact with the first conductive layer 530, and the substrate 510 is exposed. Since the thermal oxide layer 532 is an oxide layer formed by directly oxidizing the conductive layer (for example, the first conductive layer 530), rather than by a deposition process (for example, chemical vapor deposition (CVD), physical vapor deposition ( For the oxide layer formed by PVD or other deposition processes), the purity of the oxide of the thermal oxide layer 532 is greater than that of the insulating layer formed by the deposition method (for example, the first insulating layer 522, the second insulating layer 524, or the third insulating layer). The purity of the oxide of layer 526). In some embodiments, the P-type dopant is implanted into the substrate 510 by an ion implantation. This P-type dopant helps to adjust the threshold voltage.

Referring to FIG. 10E, the channel structure 512 covering the thermal oxide layer 532 and GO ₅ is formed by a first epitaxial growth process. The thermal oxide layer 532 is located between the first conductive layer 530 and the channel structure 512, and the thermal oxide layer GO ₅ is located between the top conductive layer CL5 and the channel structure 512.

Please refer to Figure 10F, through an etching process to form through the first insulation The edge layer 522, the first conductive layer 530, the second insulating layer 524, the upper sacrificial layer 540, the third insulating layer 526, the top conductive layer CL5, and the second opening 554 of the top insulating layer OL5. Next, the upper sacrificial layer 540 is removed to form an upper opening 556 where the upper sacrificial layer 540 is removed. Then, an ion is implanted on the top of the channel structure 512 and the surface of the substrate 510 exposed to the second opening 554 to form doped regions 512c and 518, respectively. The doped regions 512c and 518 are, for example, heavily doped n-type semiconductors. Area. The doping 512c and 518 can be used to form a contact structure in the subsequent process to be electrically connected to the bit line and the common source line, respectively.

Referring to FIG. 10G, by a deposition process, a memory layer 562 and a dielectric material 566 extending along the sidewalls of the second opening 554 and the upper opening 556 and covering the top insulating layer OL5 are sequentially formed. The memory layer 562 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 562 may include a tunnel layer, a trap layer, and a barrier layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials. In some embodiments, the dielectric material 566 may include a high k material, such as aluminum oxide (Al ₂ O ₃ ) or other suitable materials. The dielectric material 566 can also be used as a barrier layer to prevent lateral diffusion of charges.

Referring to FIG. 10H, the conductive material 572' is filled in the second opening 554 and the upper opening 556 by a deposition process. The conductive material 572' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable materials.

Please refer to Figure 10I, by an etching process to remove the second opening The conductive material 572' in the opening 554 forms the second conductive layer 572 in the upper opening 556. The etching process is, for example, a dry etching process. In some embodiments, the etching process can also remove part of the conductive material located in the upper opening 556. The second conductive layer 572 may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable conductive materials. In this embodiment, the second conductive layer 572 includes tungsten (W). Thereby, a laminated structure S5 including the first insulating layer 522, the first conductive layer 530, the second insulating layer 524, the second conductive layer 572, the third insulating layer 526, the top conductive layer CL5, and the top insulating layer OL5 is formed. .

Referring to FIG. 10J, through a deposition process, an insulating material is filled in the second opening 554 to form a plurality of isolation structures 574. The isolation structure 574 may include oxide or other suitable insulating materials.

Referring to FIG. 10K, a plurality of vertical openings 559 passing through the isolation structure 574 and extending along the normal direction of the upper surface 510a of the substrate 510 are formed.

Thereafter, referring back to FIG. 1F, a conductive material is filled in the vertical openings 559 by a deposition process to form a plurality of conductive connection structures 576. The conductive connection structure 576 may include tungsten (W), aluminum (Al), titanium nitride (TiN), or other suitable conductive materials. In this way, a memory device 500 as shown in FIG. 1F is formed.

11A to 11M are cross-sectional views illustrating a method of forming the memory device 600 according to an embodiment of the disclosure.

Referring to FIG. 11A, a substrate 610 is provided, and a laminated body S6' is formed on the upper surface 610a of the substrate 610. The laminated body S6' includes sequentially (for example, by a deposition process) stacked on the substrate 610 On the surface 610a, a lower sacrificial layer 642, a second insulating layer 624, an upper sacrificial layer 640, a third insulating layer 626, A top sacrificial layer SF6 and a top insulating layer OL6.

In some embodiments, the substrate 610 may be a silicon substrate or other suitable substrates. The second insulating layer 624, the third insulating layer 626, and the top insulating layer OL6 may be formed of oxide, such as silicon dioxide. The lower sacrificial layer 642, the upper sacrificial layer 640, and the top sacrificial SF6 may be formed of silicon nitride (SiN).

Referring to FIG. 11B, a plurality of first openings 652 are formed, and each of the first openings 652 passes through the laminated body S6' to expose a part of the substrate 610 to the outside. In some embodiments, the first opening 652 may be formed by an etching process, such as a dry etching process. In some embodiments, the substrate 610 may be overetched so that the bottom of the first opening 652 is lower than the upper surface 610a of the substrate 610.

Referring to FIG. 11C, the lower portion 612a of the channel structure is formed by a first epitaxial growth process. That is, the lower part 612a of the channel structure is an epitaxial growth layer of silicon. The height of the top surface of the lower part 612 a of the channel structure is greater than the height of the top surface of the lower sacrificial layer 642.

Thereafter, the P-type dopant is implanted into the lower portion 612a of the channel structure by an ion implantation. This P-type dopant helps to adjust the threshold voltage.

Referring to FIG. 11D, a memory layer 662 covering part of the sidewall of the first opening 652 and the lower part 612a of the channel structure is formed. The memory layer 662 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 662 may include a tunnel layer, a trap layer, and a barrier layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials.

Then, a protective layer 664 is formed on the memory layer 662 by a deposition process. The protective layer 664 can prevent the memory layer 662 from being damaged in the subsequent manufacturing process. The protective layer 664 is, for example, silicon nitride, polysilicon or other suitable materials.

Referring to FIG. 11E, a portion of the memory layer 662 and the protective layer 664 are removed by an etching process to expose the lower portion 612a of the channel structure. The etching process can be a dry etching process or a wet etching process.

Referring to FIG. 11F, the protective layer 664 is removed by soaking in a solvent, so that the memory layer 662 is exposed. The solvent is, for example, hot phosphoric acid (H ₃ PO ₄ ), but the present invention is not limited to this, as long as it is a solvent that can remove the protective layer 664 but does not damage the memory layer 662.

Referring to FIG. 11G, the upper portion 612b' of the channel structure is formed by a second epitaxial growth process.

Referring to FIG. 11H, a portion of the upper portion 612b' and the memory layer 662 are removed to form a vertical opening through the top insulating layer OL6, the top sacrificial layer SF6, and a portion of the third insulating layer 626. The width of this vertical opening may be greater than the width of the lower portion 612a of the channel structure. Next, the upper portion 612b of the channel structure is formed by a third epitaxial growth process.

Referring to FIG. 11I, the second opening 654 passing through the laminated body S6' is formed by an etching process. The etching process is, for example, a dry etching process. Afterwards, a doped region 618 can be formed on the substrate 610 corresponding to the second opening 654 by an ion implantation, and a doped region 612c can be formed on the top of the channel structure 612. The doped regions 612c and 618 include, for example, heavily doped n-type semiconductors. Alternatively, the step of forming the doped regions 612c and 618 may be performed after the upper sacrificial layer 640 and the lower sacrificial layer 642 are removed.

Please refer to FIG. 11J, through an etching process from the second opening 654 The top sacrificial layer SF6, the upper sacrificial layer 640, and the lower sacrificial layer 642 are removed to form a top opening 660, an upper opening 656, and a lower opening at the positions where the top sacrificial layer SF6, the upper sacrificial layer 640, and the lower sacrificial layer 642 are removed, respectively 658. The etching process may be isotropic etching (for example, wet etching), and may be a highly selective etching, for example, selective etching of silicon nitride instead of silicon dioxide.

Next, a thermal oxidation layer 632 is formed on the side surface of the channel structure 612 exposed by the lower opening 658 by an oxidation process, and a first insulating layer 622 is formed on the upper surface 610a of the substrate 610 exposed by the lower opening 658, and _{A thermal oxide layer GO 6} is formed on the surface of one side of the channel structure 612 exposed by the top opening 660. In some embodiments, the channel structure 612 is an epitaxial growth layer of silicon. After an oxidation process and high temperature, the side surface of the channel structure 612 exposed by the top opening 660 and the side surface of the channel structure 612 exposed by the lower opening 658 _{Thermal oxide layers GO 6} and 632 including silicon dioxide are formed respectively.

Thereafter, by a deposition process, a dielectric material 666 extending along the sidewalls of the second opening 654, the lower opening 658, the upper opening 656 and the top opening 660 and covering the top insulating layer OL6 is formed. In some embodiments, the dielectric material 666 may include a high k material, such as aluminum oxide (Al ₂ O ₃ ) or other suitable materials. The dielectric material 666 can also be used as a barrier layer to prevent lateral diffusion of charges.

Referring to FIG. 11K, the conductive material 672' is filled in the second opening 654, the top opening 660, the lower opening 658, and the upper opening 656 by a deposition process. The conductive material 672' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable materials.

Please refer to Figure 11L, by an etching process to remove the second opening The conductive material 672' in the opening 654 forms the first conductive layer 630 in the lower opening 658, the second conductive layer 672 in the upper opening 656, and the top conductive layer CL6 in the top opening 660. The etching process is, for example, a dry etching process. In some embodiments, the etching process can remove part of the conductive material 672' in the top opening 660, the upper opening 656, and the lower opening 658 at the same time. The first conductive layer 630, the second conductive layer 672, and the top conductive layer CL6 may respectively include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable conductive materials. In this embodiment, the first conductive layer 630, the second conductive layer 672, and the top conductive layer CL6 may include the same conductive material, such as tungsten (W). Thereby, a stacked structure S6 including the first insulating layer 622, the first conductive layer 630, the second insulating layer 624, the second conductive layer 672, the third insulating layer 626, the top conductive layer CL6, and the top insulating layer OL6 is formed. .

Referring to FIG. 11M, an insulating material is filled in the second opening 654 by a deposition process to form a plurality of isolation structures 674. The isolation structure 674 may include oxide or other suitable insulating materials.

After that, please refer back to Figure 1G to form a plurality of vertical openings passing through the isolation structure 674 and extending along the normal direction of the upper surface 610a of the substrate 610, and then a conductive material is filled in the vertical openings by a deposition process , To form a plurality of conductive connection structures 676. The conductive connection structure 676 may include tungsten (W), aluminum (Al), titanium nitride (TiN), or other suitable conductive materials. In this way, a memory device 600 as shown in FIG. 1G is formed.

12A to 12K are cross-sectional views illustrating a method of forming a memory device 700 according to an embodiment of the disclosure.

Please refer to FIG. 12A, a substrate 710 is provided, and a laminated body S7' is formed on the upper surface 710a of the substrate 710. The laminated body S7' includes sequential (for example (Such as by a deposition process) stacked on the upper surface 710a of the substrate 710, a first insulating layer 722, a first conductive layer 730, a second insulating layer 724, an upper sacrificial layer 740, a third insulating layer 726, A top conductive layer CL7 and a top insulating layer OL7.

In some embodiments, the substrate 710 may be a silicon substrate or other suitable substrates. A first insulating layer 722, a second insulating layer 724, a third insulating layer 726, and a top insulating layer OL7 may be formed of oxide, such as silicon dioxide. The lower sacrificial layer 742, the upper sacrificial layer 740, and the top insulating layer OL7 may be formed of silicon nitride (SiN).

Referring to FIG. 12B, a plurality of first openings 752 are formed, and each of the first openings 752 passes through the laminated body S7' to expose a part of the substrate 710 to the outside. In some embodiments, the first opening 752 may be formed by an etching process, such as a dry etching process. In some embodiments, the substrate 710 may be overetched so that the bottom of the first opening 752 is lower than the upper surface 710a of the substrate 710.

Referring to FIG. 12C, an oxide layer 732' is formed on the sidewall and bottom of the first opening 752 by a deposition process. In some embodiments, the first insulating layer 722, the second insulating layer 724, the oxide layer 732', the third insulating layer 726, and the top insulating layer OL7 may be formed of the same material.

Referring to FIG. 12D, the excess oxide layer 732' in the first opening 752 is removed, and the substrate 510 is exposed. In some embodiments, the P-type dopant is implanted into the substrate 710 by an ion implantation. This P-type dopant helps to adjust the threshold voltage.

Referring to FIG. 12E, the channel structure 712 covering the oxide layer 732' is formed by a first epitaxial growth process.

Referring to FIG. 12F, the first insulating layer 722, the first conductive layer 730, the second insulating layer 724, the upper sacrificial layer 740, and the first insulating layer 722 are formed through an etching process. The third insulating layer 726, the top conductive layer CL7, and the second opening 754 of the top insulating layer OL7. Next, the upper sacrificial layer 740 is removed to form an upper opening 756 where the upper sacrificial layer 740 is removed. Then, an ion is implanted on the top of the channel structure 712 and the surface of the substrate 710 exposed to the second opening 754 to form doped regions 712c and 718, respectively. The doped regions 712c and 718 are, for example, heavily doped n-type semiconductors. Area. The dopants 712c and 718 can be used to form contact structures in the subsequent process to be electrically connected to the bit line and the common source line, respectively.

Please refer to Figure 12G, remove the oxide layer 732' corresponding to the upper opening 756 (that is, remove the middle part of the oxide layer 732'), and then through a deposition process, sequentially form along the second opening The sidewalls of 754 and the upper opening 756 extend and cover a memory layer 762 and a dielectric material 766 of the top insulating layer OL7. The memory layer 762 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the memory layer 762 may include a tunneling layer, a trapping layer, and a barrier layer. The tunnel layer may include _{silicon dioxide (SiO 2} ), _{a double-layer structure formed of silicon dioxide (SiO 2} )/silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials. In some embodiments, the dielectric material 766 may include a high k material, such as aluminum oxide (Al ₂ O ₃ ) or other suitable materials. The dielectric material 766 can also serve as a barrier layer to prevent lateral diffusion of charges.

Referring to FIG. 12H, the conductive material 772' is filled in the second opening 754 and the upper opening 756 by a deposition process. The conductive material 772' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable materials.

Please refer to Figure 12I, the second opening is removed by an etching process The conductive material 772' in the opening 754 forms the second conductive layer 772 in the upper opening 756. The etching process is, for example, a dry etching process. In some embodiments, the etching process can remove part of the conductive material in the upper opening 756 at the same time. The second conductive layer 772 may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable conductive materials. In this embodiment, the second conductive layer 772 includes tungsten (W). Thereby, a laminated structure S7 including the first insulating layer 722, the first conductive layer 730, the second insulating layer 724, the second conductive layer 772, the third insulating layer 726, the top conductive layer CL7, and the top insulating layer OL7 is formed. .

Referring to FIG. 12J, through a deposition process, an insulating material is filled in the second opening 754 to form a plurality of isolation structures 774. The isolation structure 774 may include oxide or other suitable insulating materials.

Referring to FIG. 12K, a plurality of vertical openings 759 passing through the isolation structure 774 and extending along the normal direction of the upper surface 710a of the substrate 710 are formed.

After that, please refer back to FIG. 1H, and a conductive material is filled in the vertical openings 759 by a deposition process to form a plurality of conductive connection structures 776. The conductive connection structure 776 may include tungsten (W), aluminum (Al), titanium nitride (TiN), or other suitable conductive materials. In this way, a memory device 700 as shown in FIG. 1H is formed.

13 to 15 are equivalent circuit diagrams of operating memory devices 400, 500, 600, or 700 according to an embodiment of the present disclosure.

The memory device 400, 500, 600, or 700 may be a three-dimensional NOR-type memory device. In Figures 13-15, two serial selection lines SSL0, SSL1, two word lines WL0, WL1, and two bit lines are illustrated in the array area of the memory element 400, 500, 600, or 700. BL0, BL1 and 2 grounding options Select the lines GSL0, GSL1. However, the present invention is not limited to this, and the number of serial selection lines, word lines, bit lines, and ground selection lines may be greater than two, respectively. The overlapping position of each word line and the channel structure forms a memory cell M, the overlapping position of each ground selection line and the channel structure forms a transistor T, and the overlapping position of each serial selection line and the channel structure forms a transistor TS. The memory cell M is located above the transistor T, the transistor TS is located above the memory cell M, and the channel structure is connected in series with the transistor TS, the memory cell M, and the transistor T. A transistor TS, a memory cell M and a transistor T can jointly form a unit cell UN. Each transistor T is electrically connected to the common source line CSL. The word lines (such as WL0 and WL1) can be electrically isolated by the isolation structure.

FIG. 13 is an equivalent circuit diagram of a memory device programmed by Fowler-Nordheim injection according to an embodiment of the present disclosure.

Please refer to Figure 13. To program the target cell UN _t , the serial selection line SSL0, the word line WL0 and the ground selection line GSL0 are selected, the serial selection line SSL0 is applied with the turn-on voltage Vpass, and the word line WL0 The programming voltage Vpgm1 is applied, and 0V is applied to the ground selection line GSL0. The serial selection line SSL1, the word line WL1, and the ground selection line GSL1 are not selected, and 0 volt (V) is applied. The common source line applies a common source voltage V _CSL . 0V is applied to the bit line BL0. The bit line BL1 applies the inhibit voltage V _inhibit . The cell memory cell coupled to the bit line BL1 is inhibited. In one embodiment, the turn-on voltage Vpass is greater than the inhibiting voltage V _inhibit to transmit the inhibiting voltage V _inhibit to the unit cell. In one embodiment, the turn-on voltage Vpass is equal to the inhibiting voltage V _inhibit , which is used for self-boosting and can reduce programming interference.

FIG. 14A is an equivalent circuit diagram of a memory device that is erased by Fowler-Nordham injection according to an embodiment of the present disclosure.

Please refer to Figure 14A. To _{erase the target cell UN t} (for example, 2 memory cells and 4 transistors in different series), serial selection line SSL0, word line WL0 and ground selection The line GSL0 is selected. The serial selection line SSL0 applies the erase voltage Vers3 or is floating. 0V is applied to the word line WL0. The ground selection line GSL0 applies the erase voltage Vers2. The serial selection line SSL1, the word line WL1, and the ground selection line GSL1 are unselected and all floating. The common source line applies a common source voltage V _CSL . P-type well (p well) applies a P-type well voltage V _PWI . An erase voltage Vers1 is applied to the peripheral circuit. The bit lines BL0 and BL1 are floating. The common source voltage V _CSL may be the same as the erase voltage Vers1 and the P-well voltage V _PWI .

FIG. 14B is an equivalent circuit diagram of a memory device in which the thermal holes induced by band tunneling are erased by band tunneling according to an embodiment of the present disclosure.

Please refer to FIG. 14B. To _{perform an erase operation on the target cell UN t} , the serial selection line SSL0, the word line WL0, and the ground selection line GSL0 are selected. The serial selection line SSL0 applies a turn-on voltage Vpass. 0V is applied to the ground selection line GSL0. The word line WL0 is applied with a ground erase voltage Vgers. The ground erase voltage Vgers can be less than zero. The serial selection line SSL1, the word line WL1, and the ground selection line GSL1 are not selected, and 0 volt (V) is applied. The bit line BL0 can be applied with a drain erase voltage Vders. The drain erase voltage Vders can be greater than zero. 0V can be applied to the bit line BL1. The common source line applies a common source voltage V _CSL .

FIG. 15 is an equivalent circuit diagram of a memory device in a read operation according to an embodiment of the disclosure.

Please refer to Figure 15. To _{perform a read operation on the target cell UN t} (for example, 2 memory cells and 4 transistors including different memory series), the serial select line SSL0, the word line WL0 and The ground selection line GSL0 is selected. _{A power supply voltage V CC} can be applied to the serial selection line SSL0. The word line WL0 can be applied with 0V. _{A power supply voltage V CC} can be applied to the ground selection line GSL0. The serial selection line SSL1, the word line WL1, and the ground selection line GSL1 are not selected, and 0 volt (V) is applied. The bit lines BL0 and BL1 can be applied with a bit line read voltage Vblr. The common source line applies a common source voltage V _CSL . When performing a read operation in the memory device of the present invention, all voltages applied to the bit line, word line, and ground selection line can be equal to or less than the power supply voltage V _CC , so power consumption can be reduced.

This case provides a memory device, its manufacturing method and its operation method. Since the memory device of the present application has a three-dimensional structure, it can be applied to an inverted or gate memory device, and has a smaller unit memory cell area than a general two-dimensional inverted or gate memory device. Furthermore, the memory device of the present application can use a high dielectric constant material as the dielectric material, and the operation of the memory device (such as erasing, writing, and programming) can be performed without too high voltage. Moreover, according to an embodiment of the present case, the channel structure is an epitaxial growth layer, which has better electrical characteristics than the comparative example where the channel structure only partially includes an epitaxial growth layer or is mainly formed by a polysilicon layer, so that The ground selection line can obtain better control ability, the critical voltage can be smaller and the distribution is more concentrated (tight distribution). In addition, the thermal oxide layer in this case is an oxide formed by directly oxidizing the first conductive layer or the channel structure. Compared with the thermal oxide layer formed by the general deposition method, it can have higher oxidation. The purity of the material is beneficial to the regulation of the threshold voltage, and it can have a smaller threshold voltage. Therefore, the memory device of the present application can have lower energy consumption, better reliability, and performance can be improved.

To sum up, although the present invention has been disclosed as above by embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100: memory components

110: substrate

110a: upper surface

112: Channel structure

112a: lower part

112b: upper part

112c, 118: doped area

112t, 172t: top surface

122: first insulating layer

124: second insulating layer

126: third insulating layer

128: cap layer

130: first conductive layer

132: Thermal oxide layer

162: Memory Layer

166: Dielectric materials

172: second conductive layer

174: Isolation structure

176: Conductive connection structure

A, A’: End of section line

H ₁ : first height

H ₂ : second height

M ₁ : memory cell

S1: laminated structure

T ₁ : Transistor

UN ₁ : unit memory cell

Claims (10)

A memory device includes: a substrate having an upper surface; a laminated structure located on the upper surface of the substrate, wherein the laminated structure includes a first insulating layer and a first insulating layer sequentially stacked on the substrate A first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer; a plurality of channel structures passing through the laminated structure and electrically connected to the substrate, wherein each channel structure includes an upper portion Part and a lower part, the upper part corresponds to the second conductive layer, the lower part corresponds to the first conductive layer; a memory layer located between the second conductive layer and the upper part; and a plurality of isolation structures , Passing through the stacked structure to separate the stacked structure into a plurality of sub-stacks; wherein the isolation structures are formed of insulating materials; wherein each of the isolation structures has a first side and a side opposite to the first side A second side, the first side is connected to a first one of the sub-stacks, and the second side is connected to a second one of the sub-stacks, wherein a top surface of the channel structure and There is a first height between the upper surfaces of the substrate, a second height is between a top surface of the second conductive layer and the upper surface of the substrate, and the first height is greater than the second height. In the memory device described in claim 1, wherein each of the channel structures is an epitaxial growth layer. The memory device described in item 1 of the scope of patent application includes a The thermal oxide layer is located between the first conductive layer and each of the channel structures, wherein the purity of the oxide of the thermal oxide layer is higher than the purity of the oxide of the first insulating layer. A method for manufacturing a memory device includes: providing a substrate, the substrate having an upper surface; forming a laminated body on the upper surface of the substrate, wherein the laminated body includes the upper surface of the substrate sequentially stacked A first insulating layer, a first conductive layer, a second insulating layer, an upper sacrificial layer, and a third insulating layer on the surface; forming a plurality of first openings through the laminated body; forming a plurality of channels The structure is in the first openings, and the channel structures are electrically connected to the substrate. Each channel structure includes an upper portion and a lower portion. The lower portion corresponds to the first conductive layer, and the upper portion is located at Above the lower portion; forming a memory layer corresponding to the upper portion; forming a plurality of second openings through the laminated body; removing the upper sacrificial layer and forming a memory layer at the position where the upper sacrificial layer is removed Upper opening; filling a conductive material in the upper opening to form a second conductive layer, thus forming a first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer and the first A stacked structure of three insulating layers; and a plurality of isolation structures are formed in the second openings, and the isolation structures separate the stacked structure into a plurality of sub-stacks. The manufacturing method of the memory device as described in item 4 of the scope of patent application, It further includes: forming a thermal oxide layer on one side surface of the first conductive layer by an oxidation process; forming the lower portion of each channel structure covering the thermal oxide layer by a first epitaxial growth process, the The thermal oxide layer is located between the first conductive layer and the lower portion of each of the channel structures, and the purity of the oxide of the thermal oxide layer is higher than the purity of the oxide of the first insulating layer. According to the method for fabricating a memory device as described in claim 5, the upper part and the lower part of each of the channel structures are formed by the first epitaxial growth process. The method for fabricating a memory device as described in claim 5, wherein after the step of forming the lower portion, the memory layer is formed on the sidewall of each of the first openings before forming the upper portion, and The upper part is formed by a second epitaxial growth process. A method for manufacturing a memory device includes: providing a substrate, the substrate having an upper surface; forming a laminated body on the upper surface of the substrate, wherein the laminated body includes the upper surface of the substrate sequentially stacked A first insulating layer, a lower sacrificial layer, a second insulating layer, an upper sacrificial layer, and a third insulating layer on the surface; forming a plurality of first openings through the laminated body; forming a plurality of channel structures A plurality of lower parts are in the first openings; A memory layer corresponding to the upper sacrificial layer is formed in each of the first openings; a plurality of upper parts forming the channel structures are in the first openings, and the upper parts are located on the lower parts; forming A plurality of second openings passing through the laminated body; removing the upper sacrificial layer and the lower sacrificial layer, and respectively forming an upper opening and a lower opening at the positions where the upper sacrificial layer and the lower sacrificial layer are removed ; Fill a conductive material in the upper opening and the lower opening to respectively form a second conductive layer and a first conductive layer, thus forming the first insulating layer, the first conductive layer, and the second insulating layer , A stacked structure of the second conductive layer and the third insulating layer; and a plurality of isolation structures are formed in the second openings, and the isolation structures separate the stacked structure into a plurality of sub-stacks. The manufacturing method of the memory device as described in claim 8, wherein after forming the first openings, it further comprises: forming the lower portions of the channel structures by a first epitaxial growth process; and After forming the memory layer on the lower part, the upper parts of the channel structures are formed by a second epitaxial growth process. The method for manufacturing a memory device as described in claim 8, wherein after the step of forming the second openings, it further comprises: performing an oxidation process to form a thermal oxidation on part of the side surfaces of the lower parts Layer, wherein the purity of the oxide of the thermal oxide layer is higher than that of the first insulating layer The purity of the material; and depositing a dielectric material on a side wall of the upper opening and a side wall of the lower opening.

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