KR100878347B1 - Silicon Oxide Nitride Oxide Semiconductor memory device and Manufacturing method thereof - Google Patents

Abstract

The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a SONOS memory device and a method for manufacturing the same. According to the present invention, the method comprises: doping a first diffusion region in a lower portion of a substrate, selectively etching the substrate to form a silicon pillar having a predetermined depth, doping a second diffusion region in an upper portion of the silicon pillar, and Forming a trap layer stack on one side of the pillar, forming an upper insulating film to cover the silicon pillar and the trap layer stack, and forming a gate between the silicon pillars to contact the upper insulating film A memory device manufacturing method is provided. The present invention has the effect of providing a sonos memory device and a method of manufacturing the same that can maximize the degree of integration.

SONOS, source, drain, gate

Description

SONOS memory device and method for manufacturing same {Silicon Oxide Nitride Oxide Semiconductor memory device and Manufacturing method}

1 is a plan view of a conventional Sonos memory device.

2A is a first cross-sectional view of a conventional Sonos memory element.

2B is a second cross-sectional view of a conventional Sonos memory element.

3 is a plan view schematically illustrating a part of a memory cell array of a sonos memory device according to an exemplary embodiment of the present invention.

4A to 9, 10A and 11A are cross-sectional views illustrating a method of manufacturing a sonos memory device according to an embodiment of the present invention.

10B and 11B are perspective views illustrating a method of manufacturing a sonos memory device according to an embodiment of the present invention.

12 is a cross-sectional view of a portion of a sonos memory element in accordance with an embodiment of the present invention.

FIG. 13 is a graph illustrating a distribution of electrons trapped in a trap layer after completion of a write operation of a Sonos memory device according to the present invention; FIG.

FIG. 14 is a graph illustrating a change in a threshold voltage after completion of a write operation of a sonos memory device according to the present invention. FIG.

15 is a graph illustrating a change in a threshold voltage during an erase operation of a sonos memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

410: P-type substrate

420: first N-type diffusion region

510: gate insulating film

520: Silicon Pillar

610: second N-type diffusion region

711 to 714: trap layer stack

810: upper insulating film

910: Gate

1010: bit line insulating film

1110 bit line

The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a SONOS memory device and a method for manufacturing the same.

Recently, with the spread of the Internet and the development of information technology, the amount of information available to users is increasing rapidly compared with the past. Accordingly, a user has no choice but to store information in order to efficiently use a large amount of information, and in order to store the information for a long time, a nonvolatile memory device that does not erase stored information even after power is removed is required.

Currently, the main types of nonvolatile memory devices are flash memory devices, but various kinds of nonvolatile memory devices are being developed, and one of them is a silicon oxide nitride memory device (SONOS). Hereinafter, a general configuration of a conventional sonos memory device will be briefly described with reference to FIGS. 1, 2A, and 2B.

1 is a plan view of a conventional Sonos memory device, FIG. 2A is a first cross-sectional view of a conventional Sonos memory device, and FIG. 2B is a second cross-sectional view of a conventional Sonos memory device.

1, 2A and 2B, FIG. 2A is a cross-sectional view taken along the line II ′ of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line II-II ′ of FIG. 1.

As shown in FIGS. 2A and 2B, the conventional Sonos memory device 100 may include a substrate 210, an isolation layer 215, a source region 220, a drain region 230, The lower insulating layer 240, the trap layer 250, the upper insulating layer 260, and the gate electrode gate 270 are included.

That is, the device isolation layer 215 is formed between the devices to separate them, and the common source region 220 and the common drain region 230 are formed on the substrate 210 so as to be spaced apart from each other. The lower insulating layer 240 is present on the substrate 210 between the common source region 220 and the common drain region 230.

)이 일반적으로 사용된다. 즉, 데이터 쓰기(write) 동작에서는 트랩층(250)에 전자가 트랩될 수 있다. In addition, a trap layer 250 is present on the lower insulating layer 240. The trap layer 250 is a storage node layer in which actual bit data is recorded.

) Is commonly used. That is, in the data write operation, electrons may be trapped in the trap layer 250.

In addition, an upper insulating layer 260 may be disposed on the trap layer 250 to prevent electrons from entering the gate 270 while being trapped in the trap layer 250. In this case, the upper insulating layer 260 may be a silicon oxide layer.

In addition, a gate electrode 270 is present on the upper insulating layer 260. Here, a side surface of the gate stack including the lower insulating layer 240, the trap layer 250, the upper insulating layer 260, and the gate electrode 270 may be covered with an isolation layer 215 made of an insulating material.

As described above, the conventional Sonos memory device 100 has a planar structure. That is, the conventional sonos memory device 100 is a stack including a gate stack (ie, a lower insulating film 240, a trap layer 250, an upper insulating film 260, and a gate electrode 270) on the substrate 210. Water) is laminated.

However, the planar stacked structure of the conventional Sonos memory device 100 has a problem that it is difficult to maximize the degree of integration. That is, since the conventional Sonos memory device 100 has a planar structure, the interval between the bits must be narrowed to increase the degree of integration. In this case, the length of the channel is shortened. At this time, the electric field (that is, the value obtained by dividing the difference between the source voltage and the drain voltage by the channel length) becomes large, and thus a carrier having a high electric field becomes too mobile.

In addition, the manufacture of multi-bit memory cells (cells having more than 2 bits per cell) is being actively researched, and among them, Sonos memory devices have received much attention and research. That is, two bits may be implemented by locally trapping electrons only near the drain by using the property that electrons trapped in the nitride layer of the multi-bit sonos memory device do not diffuse to the surroundings.

However, in the case of the conventional multi-bit sonos memory device, the shorter the channel length is formed, each bit interferes with each other, and thus there is still a problem that a satisfactory characteristic cannot be obtained.

Accordingly, the present invention is to propose a sonos memory device and a method of manufacturing the same that can maximize the degree of integration.

In addition, the present invention is to propose a sonos memory device and a method of manufacturing the same that can increase the degree of integration without reducing the length of the channel to be formed.

According to an embodiment of the present invention for solving the above-mentioned problems, the method comprises: doping a first diffusion region under a substrate; Selectively etching the substrate to form a silicon pillar of a predetermined depth; Doping a second diffusion region over the silicon pillar; Forming a trap layer stack on one side of the silicon pillar; Forming an upper insulating film to cover the silicon pillar and the trap layer stack; And forming a gate between the silicon pillars so as to contact the upper insulating layer.

The method of manufacturing the above-described sonos memory device may further include forming a gate insulating layer for preventing contact between the first diffusion region and the gate.

In addition, one of the first diffusion region and the second diffusion region may be a source region, and the other may be a drain region.

In addition, the forming of the trap layer stack may include stacking a lower insulating film, which is a tunneling insulating film, on one side of the silicon pillar; And laminating a trap layer to which electrons are trapped in a write operation on one side of the lower insulating layer.

The silicon pillar may be a P-type substrate, and the doping of the first diffusion region may include doping N-type impurities under the P-type substrate, and the doping of the second diffusion region may include: Doping an N-type impurity on the upper portion of the silicon pillar included in the substrate.

The forming of the silicon pillar may include forming a first etching portion by etching the substrate to a predetermined depth; And forming a second etching portion by etching the bottom surface of the first etching portion to a predetermined depth, wherein the silicon pillar may have an iron shape.

The forming of the second etching portion may include etching the bottom surface of the first etching portion to expose a portion of the first diffusion region, wherein a portion of a bottom surface of the second etching portion and a side surface of the second etching portion is exposed. May be the first diffusion region.

The etching may be anisotropic etching, and the anisotropic etching may be any one of a laser etching method, a plasma etching method, an anisotropic dry etching method, or an etching method using a mask.

In addition, the forming of the trap layer stack may include forming the trap layer stack on one side of the silicon pillar and being deposited on the side of the first etching portion or the side of the second etching portion. have.

The forming of the trap layer stack may include covering the predetermined portion of one side of the silicon pillar and one side of any one of the first diffusion region and the second diffusion region. It may comprise the step of forming.

The method may further include forming a bit line for applying a voltage to the second diffusion region on the second diffusion region.

The method may further include forming a bit line insulating layer between the gate and the bit line to prevent the bit line and the gate from contacting each other.

The method may further include etching the bit line insulating layer to etch a bit line connection hole for connecting the bit line and the second diffusion region.

The forming of the bit line may include forming a plurality of bit lines in accordance with the bit line connecting hole, and etching the bit line connecting hole may include the bit line connecting hole adjacent to the bit line connecting hole. And cross etching so as not to share the same silicon pillar as other bit lines.

According to another embodiment of the present invention for solving the above problems, a substrate including a silicon pillar formed by selectively etching; A first diffusion region formed under the silicon pillar; A second diffusion region formed on the silicon pillar; A trap layer stack formed on one side of the silicon pillar; An upper insulating film formed to cover the silicon pillar and the trap layer stack; And a gate formed between the silicon pillars and in contact with the adjacent upper insulating layer, wherein a channel formed according to a voltage applied to the gate, the first diffusion region, and the second diffusion region is the silicon pillar. Provided is a sonos memory element, characterized in that formed along the side of.

here, The sonos memory device may further include a gate insulating layer for preventing contact between the first diffusion region and the gate.

In addition, one of the first diffusion region and the second diffusion region may be a source region, and the other may be a drain region.

In addition , the trap layer stack is a lower insulating film which is a tunneling insulating film deposited on one side of the silicon pillar; And a trap layer in which electrons are trapped in a write operation and stacked on one side of the lower insulating layer, wherein the trap layer may be a nitride layer.

Also, The silicon pillar is a P-type substrate, and the first diffusion region is formed by doping N-type impurities under the P-type substrate, and the second diffusion region is formed by doping N-type impurities on the silicon pillar. Can be.

Also, The silicon pillar may include a side surface of the first etching part formed by etching the substrate to a predetermined depth; And a side surface of the second etching portion formed by etching the bottom surface of the first etching portion to a predetermined depth, wherein the silicon pillar may have an iron shape.

The second etching portion may be formed by etching the bottom surface of the first etching portion to expose a portion of the first diffusion region, and a portion of a bottom surface of the second etching portion and a side surface of the second etching portion may be formed in the first diffusion region. Can be.

The etching may be anisotropic etching, and the anisotropic etching may be any one of a laser etching method, a plasma etching method, an anisotropic dry etching method, or an etching method using a mask.

In addition, the trap layer stack is formed on one side of the silicon pillar, it may be formed to be deposited on the side of the first etching portion or the side of the second etching portion.

The trap layer stack may be formed to cover a predetermined portion of one side of the silicon pillar and a predetermined portion of one side of the first diffusion region or the second diffusion region.

In addition, the sonos memory device may be formed on the second diffusion region, and may further include a bit line for applying a voltage to the second diffusion region.

In addition, the sonos memory device may further include a bit line insulating layer formed between the gate and the bit line to prevent the bit line and the gate contact.

The sonos memory device may further include a bit line connection hole for connecting the bit line and the second diffusion region, and the bit line connection hole may be formed by etching the bit line insulating layer.

In addition, a plurality of bit lines may be formed along the bit line connection holes, and the bit line connection holes may be crossed and etched so that the bit lines do not share the same silicon pillar as other adjacent bit lines.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

3 is a plan view schematically illustrating a part of a memory cell array of a sonos memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a sonos memory device according to an embodiment of the present invention may include a plurality of word lines 310-1, 310-2, 310-3, 310-4,... N is a natural number) and a plurality of bit lines 320-1, 320-2, 320-3, 320-4, 320-5, 320-6, 320-7, 320-8,... ... 320-n, where n is a natural number, to form a memory cell array.

Here, the hatched portion in the region A 340 may be a silicon pillar, and the trap layers 350-1 and 350-2 may be stacked on the side of the silicon pillar.

Hereinafter, a structure and a manufacturing method of a sonos memory device according to an embodiment of the present invention will be described with reference to FIGS. 4A to 11B. 4A to 9, 10A and 11A are cross-sectional views taken along the cutting line A-A 'shown in FIG. 3, and FIGS. 10B and 11B are taken along the region B 330 shown in FIG. It is a perspective view cut away.

4A through 9, 10A, and 11A are cross-sectional views illustrating a method of manufacturing a sonos memory device according to an exemplary embodiment of the present invention. 10B and 11B are perspective views illustrating a method of manufacturing a sonos memory device according to an embodiment of the present invention.

Referring to FIG. 4A, a cross-sectional view of a Sonos memory device having a first N-type diffusion region 420 doped under a P-type substrate 410 is illustrated, and the P-type substrate 410 includes one or more silicon pillars 520. (Three silicon pillars 520 are shown in FIG. 4A). Here, the first N-type diffusion region 420 may be formed by doping (or implanting) electrons under the P-type substrate 410. In addition, each silicon pillar 520 of the planar P-type substrate 410 may have a thickness of 20 nm and a depth of 70 nm. In this case, the method of forming the silicon pillar may vary.

For example, the P-type substrate 410 is a planar P-type substrate on which an oxide film (eg, Nitride, Oxide, Carbon, etc.) 430 is deposited is patterned by a photoresist (PR) process. Afterwards, the first etching unit 415 may be formed as shown in FIG. 4B by an anisotropy etching process (hereinafter, referred to as 'first etching'). Here, the etching portion may be a hole formed in the P-type substrate 410 by etching, and the etching portion may include both side surfaces of the hole and / or the bottom surface of the hole.

In this case, a laser etching method, a plasma etching method, an anisotropic dry etching method or an etching method using a mask (or spacer) may be used for the first etching process. In addition, when the first etching process is completed, the oxide layer 430 may be removed as shown in FIG. 4B.

In addition, after a mask (or spacer) having a thickness of 5 nm is formed on both sides of the silicon pillar 520, an anisotropic etching (hereinafter referred to as a “secondary etching”) process is performed, as shown in FIG. 5A. As described above, the second etching portion 515 may be formed, and thus, the silicon pillar 520 having the shape illustrated in FIG. 5B may be formed. That is, the silicon pillar 520 formed after the second etching process may be an iron-shaped silicon pillar, and may include a step 440 on the side surface thereof.

In this case, as shown in FIG. 5B, a portion of the first N-type diffusion region 420 may also be anisotropically etched. That is, the second etching portion 515 may be formed by etching the bottom surface of the first etching portion 415 so that a part of the first diffusion region is exposed. Accordingly, the bottom surface of the second etching portion 515 may be formed. It may be a first N-type diffusion region 420. Thus, the bottom of silicon pillar 520 (ie, bottom of step 440 in FIG. 5B) may have a thickness of 30 nm, and the top of silicon pillar 520 (ie in FIG. 5B, step 440. ) May have a thickness of 20 nm.

In addition, between the silicon pillars 520 may be 55nm. Here, in the second etching process, the same or similar method as the first etching process (laser etching method, plasma etching method, anisotropic dry etching method or etching method using a mask) may be used.

In addition, after the silicon pillars 520 are formed, a gate insulating layer 510 may be formed between the silicon pillars 520 as shown in FIG. 5B. In this case, the gate insulating layer 510 may be formed to have a depth of 150 nm from the upper portion of the silicon pillar 520 to the upper portion of the gate insulating layer 510. The gate insulating layer 510 may be an insulating layer for preventing contact between the first N-type diffusion region 420 and the gate to be described later.

Here, since the thickness and depth of the silicon pillar 520 is only an example, it is obvious that the numerical value does not limit the scope of the present invention.

Referring to FIG. 6, a second N-type diffusion region 610 may be formed on the silicon pillar 520. Here, the second N-type diffusion region 610 may be formed by electrons doped (or implanted) on the silicon pillar 520.

Referring to FIG. 7, one or more trap layer stacks (four trap layer stacks are shown in FIG. 7) on both sides of each silicon pillar 520 doped with a second N-type diffusion region 610 ( 711, 712, 713, 714, hereinafter referred to collectively as '710' may be stacked. Here, the trap layer stack 710 may be stacked to be deposited on the side of the first etching unit 415 of the side of the silicon pillar 520 (711, 713), the side of the second etching unit 515 It may be stacked (712, 714) to be deposited. In this case, the bottom surface 530 of the step 440 and / or the second etching unit 515 may prevent the stacked trap layer stack 710 from sliding on the side of the silicon pillar 520. In addition, the thickness of the trap layer stack 710 may be 5 nm.

In this case, as illustrated in FIG. 7, the trap layer stack 710 may include a predetermined portion of one side of the silicon pillar 520 and one of the first N-type diffusion region 420 or the second N-type diffusion region 410. One portion of one side may be formed to be covered. That is, the trap layer stack 710 may be stacked to be seated on the step 440 and / or the bottom surface 530 of the second etching unit 515, and a part of the trap layer stack 710 may be a silicon pillar ( 520, and the other portion may cover any one of the first N-type diffusion region 420 or the second N-type diffusion region 610.

That is, according to the voltage applied to the first N-type diffusion region 420, the second N-type diffusion region 610, and / or a gate (not shown), the first N-type diffusion region 420 may be a source or a drain. It may operate as one, and a channel (not shown) may be formed in the silicon pillar 520 (more details will be described later). In this case, assuming that the first N-type diffusion region 420 operates as a source and the second N-type diffusion region 610 operates as a drain, the second N of electrons present in the channel (not shown) may be used. Electrons present near the diffusion region 610 may become hot carriers and may be trapped in the trap layer 710 (a detailed description will be described later). Therefore, each trap layer stack 710 must be located near the first N-type diffusion region 420 or the second N-type diffusion region 610 (ie, near the drain) so that a certain level of electrons can be trapped. .

In addition, the electrons trapped in the trap layer stack 710 (particularly the trap layer 730) are drained (ie, either the first N-type diffusion region 420 or the second N-type diffusion region 610) and Each trap layer stack 710 may cover a portion of the first N-type diffusion region 420 or the second N-type diffusion region 610 so as to be erased by the silicon pillar 520. .

Of course, the trap layer stack 710 may be formed on the side of the silicon pillar 520 without covering the portion of the first N-type diffusion region 420 or the second N-type diffusion region 610. Do. However, even in this case, it may be more preferable that each trap layer stack 710 is formed near the first N-type diffusion region 420 or the second N-type diffusion region 610. This is to allow each trap layer stack 710 to trap electrons independently.

)이 사용될 수 있다. 즉, 데이터 쓰기 동작에서는 트랩층(730)에 전자가 트랩될 수 있다. 또한, 하부 절연막(720)은 터널링 전류가 흐를 수 있도록 얇게(대략 10nm 이하) 증착될 수 있다.In addition, each trap layer stack 710 may include a lower insulating layer 720 and a trap layer 730. Here, the lower insulating layer 720 may be a tunneling insulating layer, and the trap layer 730 may be a nitride layer (storage node layer) in which actual bit data is recorded.

) Can be used. That is, in the data write operation, electrons may be trapped in the trap layer 730. In addition, the lower insulating layer 720 may be deposited thinly (about 10 nm or less) so that the tunneling current flows.

In addition, the manner in which the trap layer stack 710 is stacked may vary. For example, when the lower insulating film 720 and the trap layer 730 are stacked on both sides of each silicon pillar 520 doped with the second N-type diffusion region 610, the stacked lower insulating film 720 and The trap layer 730 may be anisotropically etched to form four trap layer stacks 710 as shown in FIG. 7.

Referring to FIG. 8, after one or more trap layer stacks 710 are formed on each silicon pillar 520, an upper insulating layer 810 may be deposited. That is, the upper insulating layer 810 may be formed to cover both the silicon pillar 520 and the one trap layer stack 710 formed on the side surfaces of the silicon pillar 520. The upper insulating layer 810 may be a silicon oxide layer. The lower insulating film 720 and the upper insulating film 810 described above are formed to allow the electrons stored in the trap layer 830 to be trapped for a long time.

Referring to FIG. 9, a gate 910 may be formed between the silicon pillars 520. That is, after the gate material is deposited between the silicon pillars 520 on which the upper insulating film 810 is deposited, the gate 910 may be formed when the upper portion of the deposited gate material is planarized by a chemical mechanical polishing (CMP) process. have. In this case, the gate material may be polysilicon (Poly-SI).

As shown in FIG. 10A, a bit line insulating layer 1010 for forming a bit line (not shown) may be deposited on the formed gate 910. In this case, the bit line insulating film 1010 may be an oxide film. In addition, the bit line connection hole may be etched in the formed bit line insulating layer 1010 so that a bit line (not shown) to be formed later may be connected to the second N-type diffusion region 610. Referring to FIG. 10B, the bit line connecting hole 1020 is etched in the bit line insulating layer 1010 so that a predetermined region of the second N-type diffusion region 610 is formed.

In this case, the bit line connection hole 1020 may be etched at a predetermined interval and / or size, and the bit line to be formed later and the second N-type diffusion region 610 may be connected through the bit line connection hole 1020. have.

For example, as shown in FIGS. 10A and 10B, the bit line contact hole 1020 is etched for each second N-type diffusion region 610 formed on each silicon pillar 520. Each adjacent bitline that is not (or perforated) may be crossed and etched so as not to share the same silicon pillar 520. That is, five bit line connection holes 1020 are illustrated in FIG. 10B, and these may be located at the front and the rear of the region B 1000, respectively, and one may be positioned at the center thereof. This is to allow the plurality of trap layers 710 deposited on one silicon pillar 520 to operate independently. This will be described later.

In addition, as illustrated in FIG. 11A, a bit line 1110 may be formed on the formed bit line insulating layer 1010. In this case, the bit line 1010 may be connected to the second N-type diffusion region 610 through the bit line connection hole 1020. Therefore, a voltage may be applied to the second N-type diffusion region 610 through the bit line 1010.

In addition, as illustrated in FIG. 11B, the bit lines 1110 may be formed at predetermined predetermined intervals. In this case, one bit line 1110 does not share the same silicon pillar 520 as the adjacent bit line 1110. As a result, the four trap layer stacks 710 deposited on one silicon pillar 520 may operate as one bit of memory. Detailed description thereof will be described later with reference to FIG. 12.

12 is a cross-sectional view of a portion of a sonos memory device according to an embodiment of the present invention.

Hereinafter, an operation of the sonos memory device 1100 according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 12.

First, a write operation in which data is stored in the first trap layer stack 711 of the four trap layer stacks 710 illustrated in FIG. 12 will be described. At this time, the gate 910 connected to the first trap layer stack 711 has a voltage of 4V, a voltage of 1V in the first N-type diffusion region 420, and a voltage of 4V in the second N-type diffusion region 610. Assume the authorized case. In this case, the first N-type diffusion region 420 may operate as a source, and the second N-type diffusion region 610 may operate as a drain.

Accordingly, a channel 1210 may be formed in the silicon pillar 520 (that is, the P-type substrate) between the first N-type diffusion region 420 and the second N-type diffusion region 610. In addition, electrons may move from the first N-type diffusion region 420 to the second N-type diffusion region 610 through the formed channel 1210. In this case, the energy of the electrons is increased near the second N-type diffusion region 610, and the electrons having the increased energy may be injected into the first trap layer 730 beyond the energy barrier of the first lower insulating layer 720.

Next, a read operation in which data written to the first trap layer 730 is read will be described. At this time, the gate 910 connected to the first trap layer stack 711 has a read voltage of 1.6V, a voltage of 0V in the second N-type diffusion region 610, and a voltage of 2V in the first N-type diffusion region 420. Assume a case where a voltage is applied. In this case, the second N-type diffusion region 610 may operate as a source, and the first N-type diffusion region 420 may operate as a drain, in the same manner as described above.

In this case, when a current flows between the second N-type diffusion region 610 and the first N-type diffusion region 420, electrons are not trapped in the first trap layer 730. This may mean that electrons are trapped in the layer. That is, after the read voltage is applied to the gate 910, the current sensed in the first N-type diffusion region 420 may be analyzed to determine whether electrons are trapped in the first trap layer 730.

Next, an erase operation for erasing data written to the first trap layer 730 will be described. In this case, when the voltage of -4V, the first N-type diffusion region 420, and the second N-type diffusion region 610 are applied to the gate 910 connected to the first trap layer stack 711, 5V is applied. Assume

In this case, a negative voltage of 9V may be applied to the first trap layer 730 and the second N-type diffusion region 610. Accordingly, electrons trapped in the first trap layer 730 obtain energy due to the erase voltage, and thus, an F-N tunnel current flows from the first trap layer 730 to the second N-type diffusion region 610. In this case, electrons trapped in the first trap layer 730 may exit to the second N-type diffusion region 610.

In addition, when an erase voltage of −9 V is applied to the first trap layer 730 and the second N-type diffusion region 610 by the above-described method, a voltage of about 4 V may be applied to the silicon pillar 520, which is a P-type substrate. (4.3V is applied as a result of the simulation). Accordingly, electrons that do not escape to the second N-type diffusion region 610 may obtain energy by an erase voltage of −8 V applied between the first trap layer 730 and the silicon pillar 520, and the first The FN tunnel current flowing from the trap layer 730 to the silicon pillar 520 may escape to the silicon pillar 520.

In this case, as described above, since one bit line 1110 does not share the same silicon pillar 520 as the adjacent bit line 1110, the adjacent silicon pillar 520 even if a voltage is applied to one bit line 1110. The voltage is not applied to all of the second N-type diffusion regions 610 formed at When a voltage is applied to one bit line 1110 and all the second N-type diffusion regions 610 are applied, the plurality of trap layer stacks affected by the same gate 910 perform the same operation. to be.

That is, in order for the plurality of trap layers 710 to operate independently of each other, as described above, one bit line 1110 does not share the same silicon pillar 520 as the adjacent bit line 1110. Hole 1020 should be etched.

Here, various voltages applied during the write operation, the read operation, and / or the erase operation of the sonos memory device 1100 according to the exemplary embodiment of the present invention described with reference to FIG. It is obvious that the scope of the invention is not limited. Therefore, 5V in the gate 910, 1V in the first N-type diffusion region 420 and / or 5V in the second N-type diffusion region 610 during the write operation of the sonos memory device 1100 according to the present invention. May be applied.

In addition, data is stored in another trap layer stack deposited on the same silicon pillar 520, that is, the second trap layer stack 712, the third trap layer stack 713, and the fourth trap layer stack 714. The same or similar to the above-described method is also apparent when stored or when stored data is read and / or erased. For example, if data is to be stored in the second trap layer stack 712, the first N-type diffusion region 420 will operate as a drain, and the second N-type diffusion region 610 may serve as a source. Will work. Therefore, in this case, a voltage of 4V may be applied to the first N-type diffusion region 420 and a voltage of 1V may be applied to the second N-type diffusion region 610.

By the above-described method, different data may be stored in one or more trap layers 730 deposited on the same silicon pillar 520, thereby maximizing the integration of the sonos memory device 1100.

13 is a graph illustrating a distribution of electrons trapped in a trap layer after completion of a write operation of a sonos memory device according to the present invention.

Referring to FIG. 13, the length of the channel 1210 formed on the silicon pillar 520 during the write operation of the sonos memory device 1100 according to the present invention is indicated on the X axis, and the channel 1210 is indicated on the Y axis. A graph showing the density of electrons present is shown. Here, the hatched region shown is an area where the channel 1210 overlaps with the trap layer 730. Of course, the hatched region does not physically overlap the channel 1210 and the trap layer 730, and the lower insulating layer 720 may exist between the channel 1210 and the trap layer 730 as described above.

In this case, the triangle-shaped portion has a voltage applied to the gate 910 (ie, Vg) of 5V, a voltage applied to the drain (ie, Vd) of 5V, and a voltage applied to the source (ie, Vs) of 1V. May mean a result value for (hereinafter, referred to as 'first case'). In addition, the portion displayed in a square shape may mean a result value when Vg is 4V, Vd is 4V, and Vs is 1V (hereinafter, referred to as 'second case'). Also, if the first N-type diffusion region 420 is a drain, the second N-type diffusion region 610 may be a source, and if the first N-type diffusion region 420 is a source, the second N-type diffusion region 610 may be a source. The drain may be the same as described above.

As shown in FIG. 13, it can be seen that electrons trapped in the trap layer 710 are evenly distributed over the entire range of the channel 1210 in the first case. In contrast, in the second case, the density increases toward the drain portion of the channel 1210 (that is, the right side of the X-axis).

Therefore, in the write operation of the sonos memory device 1100 according to the present invention, the second case is applied more accurately than the case where the first case is applied. In other words, a voltage of 4V for Vg, 4V for Vd, and / or 1V for Vs may be applied during the write operation of the sonos memory device 1100 according to the present invention.

FIG. 14 is a graph illustrating a change in a threshold voltage after a write operation is finished in a sonos memory device according to the present invention.

Referring to FIG. 14, the magnitude of the gate voltage Vg applied to the gate 910 during the read operation of the Sonos memory device 1100 according to the present invention is indicated on the X axis, and the channel 1210 is indicated on the Y axis. A graph is shown showing the current flowing through it (ie, drain current, Id).

Here, the line marked with a square is the gate voltage Vg and the drain current Id in the initial state of the Sonos memory device 1100 according to the present invention (that is, the electrons are not trapped in the trap layer 730). ) Is shown. In addition, the line indicated by the triangle is the gate voltage Vg and the drain current Id after the write operation of the sonos memory device 1100 according to the present invention (that is, the electrons are trapped in the trap layer 730). ) Is shown. At this time, 2V (ie, Vd = 2V) may be applied to the drain and 0V (ie, Vs = 0V) to the source (ie, Vds = 2V).

In this case, as shown in FIG. 14, when 1.6 V is applied to the gate 910 as the read voltage Vg, a drain current of 1 uA may be sensed in the initial state. On the other hand, a current of 0.1nA may be sensed after the write state progresses. In addition, a voltage of 2.6V or more must be applied to the gate 910 in order to detect a drain current of an initial state or more after the write state progresses. That is, after the write operation of the sonos memory device 1100 according to the present invention, the threshold voltage V _th for detecting a drain current having a predetermined value (that is, for conducting the source and the drain) may be shifted. . In the above example, it can be seen that the gate voltage (that is, the threshold voltage V _th ) for detecting the drain current of 1 uA is increased from 1.6V to 2.6V.

Therefore, in order to determine whether electrons are trapped in the trap layer 730, a read voltage of 1.6V is applied to the gate 910, a voltage of 0V to the source, and a voltage of 2V to the drain, and the drain current Id is applied. You can check whether it is 1uA.

15 is a graph illustrating a change in a threshold voltage during an erase operation of a sonos memory device according to the present invention.

Referring to FIG. 15, an erase time is displayed on the X axis during an erase operation of the Sonos memory device 1100, and a graph on which a shift value of the threshold voltage Vth is displayed is displayed on the Y axis. In addition, the correlation between the erase time and the shift value of the threshold voltage when the erase voltage Verase is applied at −10 V, −9 V, −8 V, −7 V, and −6 V, respectively, is shown. In this case, the erase voltage may be a value obtained by subtracting the drain voltage Vd from the gate voltage Vg (ie, Verase = Vg−Vd). In addition, the erase operation of the sonos memory device 1100 according to the present invention may be erased by the method described above with reference to FIG. 12.

By the way, the most important point in the erase operation of the semiconductor memory device is the correlation between the erase time and the erase voltage. That is, if the erase voltage is too large, the erase time may be short, but a high voltage may be applied. If the erase voltage is too small, the high voltage may not be applied, but the erase time may be long. For example, if the erase time is too long, the use of the memory device is inconvenient. If the erase voltage is too high to shorten the erase time, the size of the semiconductor memory device may be increased to apply a high voltage.

Therefore, when the sonos memory device 1100 according to the present invention completes the write operation and the threshold voltage is 2V and the threshold voltage is 0.5V or less, the charges trapped in the trap layer 730 are removed. Assume that it is considered to be. At this time, it can be seen that the erase voltage is less than -9V to indicate a fast erase time (for example, 1 ms).

Therefore, in order to make the erase voltage less than -9V, -4V as the gate voltage, 5V as the drain voltage and the source voltage can be applied. Of course, it is obvious that -5V can be applied as the gate voltage, and 4V can be applied as the drain voltage and the source voltage. In this case, since the erase voltage is a value obtained by subtracting the drain voltage from the gate voltage, the erase voltage may be −9V. In addition, the reason for applying the source voltage is to prevent the channel 1210 from being formed between the source and the drain. This is because electrons may be trapped again in the trap layer 730 when the channel 1210 is formed.

That is, the channel is not formed by applying the same voltage as the drain to the source, and electrons trapped in the trap layer 730 receive energy due to the erase voltage, and thus drain and / or silicon pillars (ie, P-type substrates) 520. And the erase operation may proceed.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.

As described above, according to the present invention, there is an effect of providing a sonos memory device and a method of manufacturing the same, which can maximize the degree of integration.

In addition, there is an effect that can provide a sonos memory device and a method of manufacturing the same that can increase the degree of integration without reducing the length of the channel to be formed.

Claims (28)

Doping the first diffusion region under the substrate; Selectively etching the substrate to form a silicon pillar of a predetermined depth; Doping a second diffusion region over the silicon pillar; Forming a trap layer stack on one side of the silicon pillar; Forming an upper insulating film to cover the silicon pillar and the trap layer stack; And Forming a gate between the silicon pillars so as to contact the upper insulating layer. The method of claim 1, And forming a gate insulating film for preventing contact between the first diffusion region and the gate. The method of claim 1, At least one of the first diffusion region and the second diffusion region is a source region, and the other is a drain region. The method of claim 1, Forming the trap layer stack includes: Stacking a lower insulating film, which is a tunneling insulating film, on one side of the silicon pillar; And And stacking a trap layer in which electrons are trapped in a write operation, on one side of the lower insulating layer. The method of claim 1, The silicon pillar is a P-type substrate, Doping the first diffusion region is a step of doping the N-type impurities in the lower portion of the P-type substrate, And doping the second diffusion region comprises doping an N-type impurity on an upper portion of the silicon pillar included in the P-type substrate. The method of claim 1, Forming the silicon pillar, Etching the substrate to a predetermined depth to form a first etching portion; And Forming a second etching portion by etching the bottom surface of the first etching portion to a predetermined depth; The silicon pillar is a method of manufacturing a sonos memory device, characterized in that the iron (凸) shape. The method of claim 6, Forming the second etching portion, Etching the bottom surface of the first etching portion to expose a portion of the first diffusion region, And a portion of a bottom surface of the second etching portion and a side surface of the second etching portion is the first diffusion region. The method of claim 6, The etching is anisotropic etching, The anisotropic etching may be any one of a laser etching method, a plasma etching method, an anisotropic dry etching method or an etching method using a mask. The method of claim 6, Forming the trap layer stack, And forming the trap layer stack on one side of the silicon pillar, wherein the trap layer stack is formed on the side of the first etched portion or the side of the second etched portion. The method of claim 1, Forming the trap layer stack, And forming the trap layer stack to cover a predetermined portion of one side of the silicon pillar and a predetermined portion of one side of the first diffusion region or the second diffusion region. METHOD DEVICE MANUFACTURING METHOD. The method of claim 1, And forming a bit line on the second diffusion region to apply a voltage to the second diffusion region. The method of claim 11, And forming a bit line insulating layer between the gate and the bit line to prevent the bit line and the gate from contacting the bit line. The method of claim 12, Etching the bit line insulating layer to etch a bit line connection hole for connecting the bit line and the second diffusion region. The method of claim 13, Forming the bit line, Forming a plurality of bit lines according to the bit line connection holes, Etching the bit line connection hole, And etching the bit line connection hole by crossing the bit line connection hole so that the bit line does not share the same silicon pillar as another bit line adjacent to the bit line connection hole. delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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