CN1881559A - Low inductance via structures - Google Patents
Low inductance via structures Download PDFInfo
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- CN1881559A CN1881559A CNA2006101054748A CN200610105474A CN1881559A CN 1881559 A CN1881559 A CN 1881559A CN A2006101054748 A CNA2006101054748 A CN A2006101054748A CN 200610105474 A CN200610105474 A CN 200610105474A CN 1881559 A CN1881559 A CN 1881559A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
In one embodiment, a method for forming a semiconductor device, comprises forming a first aperture and a second aperture in a first surface of the substrate, the first and second apertures being coaxial; forming, in the first aperture, a first conductive path between the first surface of the substrate and a second surface of the substrate; and forming, in the second aperture, a second conductive path between the first surface of the substrate and a second surface of the substrate.
Description
Background technology
Between conductor on the ground floor of semiconductor device and the conductor on the second layer, provide a kind of electrical connection by through-silicon via structure.The ground floor of semiconductor device and the second layer can be separated by insulating material and/or backing material.Semiconductor device with through-hole structure can use in many application, comprises radio frequency (RF) application.
Description of drawings
Give detailed description with reference to the accompanying drawings.
Fig. 1 is a flow chart, shows the method operation that is used to make a semiconductor device that contains low inductance via structures according to an embodiment.
Fig. 2 A-2G is a sectional view, shows the method that contains the semiconductor device of low inductance via structures of manufacturing according to an embodiment.
Fig. 3 A is a schematic plan view that contains the semiconductor device of low inductance via structures according to an embodiment.
Fig. 3 B is the schematic sectional view of the semiconductor device among Fig. 3 A.
Fig. 4 A is a schematic plan view that contains the semiconductor device of low inductance via structures according to an embodiment.
Fig. 4 B is the schematic sectional view of the semiconductor device among Fig. 4 A.
Fig. 5 illustrate schematicallys the radio telephone according to an embodiment.
Embodiment
Described here is the example of low inductance via structures and the technology of making through-hole structure, and this through-hole structure for example is used in the semiconductor device.In the following description, many concrete details are suggested to provide understanding completely to various embodiment.Yet, it should be appreciated by those skilled in the art that even without these concrete details, various embodiment still can be implemented.Under other situation, well-known method, process, element and circuit are not described in detail, so that specific embodiment is clearer.
In the following description, term " semiconductor device " is used for definite discontinuity layer that forms the material of active semiconductor component.Device can be individually and is formed many structures integratedly, such as but be not limited to, diode, transistor, field effect transistor (FET), comprise the device in electronics and the photoelectronic device.A device also can refer to one or more passive electric circuit elements, as inductance, electric capacity, resistance or microelectromechanical systems (MEMS) device, as cantilever switch.
" embodiment " who mentions in specification or " embodiment " are meant that concrete feature, structure or the characteristic relevant with this embodiment are comprised at least one enforcement.The phrase " at an embodiment " that occurs everywhere at specification can be or not be meant same embodiment.
The A-2G that sees figures.1.and.2 has described an embodiment who forms the technology of low inductance via structures.Fig. 1 is a flow chart, shows the operation of method that is used to make a semiconductor device according to an embodiment, and this semiconductor device comprises a low inductance via structures.Fig. 2 A-2G is a cross-sectional view, shows each stage according to the method for the semiconductor device of manufacturing of an embodiment, and this semiconductor device comprises a low inductance via structures.
Fig. 2 A is the end view of Semiconductor substrate 240.In operation 110, on the first surface of Semiconductor substrate 240, form groove 242a, the 242b (seeing Fig. 2 B) of two vicinities.Various methods can be used for forming groove 242a, 242b.In one embodiment, groove 242a, 242b are to use etching method to form, as mechanical engraving method, method for chemially etching, electric paste etching method, photochemical engraving method or the like.
The size of groove 242a, 242b is not very important.In one embodiment, the depth dimensions of groove 242a, 242b and has similar size greatly between 200 microns and 500 microns on width.
In operation 115, at insulator of surface deposition of the substrate 240 that forms groove 242a, 242b.With reference to Fig. 2 C, deposition one deck insulating material 230 comprises the surface of groove 242a, 242b with the surface of coated substrates 230.Various methods can be used for depositing this layer insulating material 230.In one embodiment, this layer insulating material 230 uses a depositing operation to deposit, as chemical vapor deposition (CVD), plating, crystal extension, thermal oxidation, physical vapor deposition (PVD) casting, evaporation, sputter coating or the like.
The size of insulating barrier 230 is not very important.In one embodiment, the gauge of insulating barrier is greatly between 5 microns and 100 microns.
In operation 120, one deck conductor material is deposited on the insulation material layer 230, and is patterned to form the first conductor 220a and the second conductor 220b.With reference to Fig. 2 D, the first conductor 220a cover part insulating barrier 230, and filled at least a portion of groove 242a.Equally, the first conductor 220b cover part insulating barrier 230, and filled at least a portion of groove 242b.The thickness of conductor material layer is not very important.In one embodiment, the gauge of conductor material layer is greatly between 5 microns and 100 microns.Certainly, the conductor layer of filling groove 242a, 242b part is much thicker than other parts.
Various methods can be used for depositing this layer conductor material.Conductor material layer can use above-mentioned any deposition technique to deposit.Equally, the whole bag of tricks that is used for forming conductor 220a, 220b is not conclusive.In one embodiment, this layer conductor material can use the engraving method of above-mentioned any selection to form.
In operation 125, material is removed from the rear surface of substrate 240.Term " rear surface " refers to the substrate surface facing surfaces that forms with groove 242a, 242b as used herein.This term is arbitrarily.In one embodiment, wide variety of materials is removed by the rear surface from substrate 240, and conductor 220a, the 220b of filling groove 242a, 242b expose thereby make respectively.With reference to Fig. 2 D, in one embodiment, corresponding quantity of material is removed in frame of broken lines 244.In the embodiment that Fig. 2 E describes, the SI semi-insulation material is removed for 230 layers, thereby obtains the electricity isolated layer of 3 insulating material, is marked as 230a, 230b and 230c.
The whole bag of tricks that material is removed from the rear surface of substrate 240 is not conclusive.In one embodiment, use a kind of suitable Ginding process that material is removed.Optionally, can use one or more above-mentioned engraving methods that material is removed from the rear surface of substrate 240.
In operation 130, insulating material is deposited upon the rear surface, and is patterned so that conductor 220a, the 220b of filling groove 242a, 242b expose respectively.With reference to Fig. 2 F, deposition and etching operation form the isolated layer of electricity of 3 insulating material, are marked as 230a, 230b and 230c.Any above-mentioned deposition and patterning techniques can be used in operation 130.
In operation 135, conductive material layer is deposited to insulator 230a, 230b and the 230c (Fig. 2 F) on the rear surface of substrate 240 and is used for respectively on the surface of exposing of conductor 220a, 220b of filling groove 242a, 242b.With reference to Fig. 2 G, conductive material layer is patterned so that keep between conductor 220a and the 220b isolating.In the described embodiment of Fig. 2 G, conductive layer is patterned so that insulator 230c exposes.In an alternative embodiment, SI semi-insulation body 230c can be continued to cover by conductive material layer.Any above-mentioned deposition and patterning techniques can be used in operation 135.
Operation 110-135 can make conductive path, and this path passes the front surface of substrate 240, passes the cross section of substrate 240, and passes the rear surface of substrate 240.The partially conductive path that passes substrate 240 cross sections is referred to as through hole.Therefore, operation 110-135 can construct the multilayer semiconductor structure that is connected by through hole.
Operation 110-135 has described the structure of the through hole between substrate 240 front surfaces and rear surface.Technology among the operation 110-135 can be used to be configured in any amount of through hole between substrate 240 front surfaces and the rear surface.In addition, the technology of describing among the 110-135 in operation can further be used for constructing multi-level semiconductor device.
Various materials can be used to make semiconductor device.Semiconductor substrate can comprise silicon, SiGe, germanium, glass or the like.Insulating material can comprise various oxides, nitride, polymer or the like.Conductor can comprise copper, gold, aluminium and their various alloys or the like.
The described technology of Fig. 1 and 2 A-2G can be used for constructing low inductance via structures.Fig. 3 A is a schematic plan view that contains the semiconductor device 300 of low inductance via structures according to an embodiment.In one embodiment, the described semiconductor device of Fig. 3 A can comprise a co-planar waveguide.Fig. 3 B is the schematic partial cross section figure of the described semiconductor device 300 of Fig. 3 A.In one embodiment, this semiconductor device 300 can comprise a co-planar waveguide.In another embodiment, semiconductor device 300 can comprise planed signal and the earth connection that is connected by through-hole structure.
With reference to Fig. 3 A and 3B, semiconductor device 300 comprises a signal conductor 320a, and this signal conductor 320a passes the part front surface and the part rear surface of substrate 340, and passes the cross section of substrate 340 by through hole 350.Equally, semiconductor device 300 comprises an earthing conductor 320b, and this earthing conductor 320b passes the part front surface and the part rear surface of substrate 340, and passes the cross section of substrate 340 by through hole 352.Insulator 330c among Fig. 3 B is corresponding to the 330 visible parts of insulating barrier among Fig. 3 A.
In the embodiment described in Fig. 3 A-3B, through hole 350 and 352 is coaxial along axis basically, extends through to this axis normal substrate 340.Term " coaxial " should not be configured to satisfy the accurate aligning of the longitudinal axis of through hole 350 and 352 on the geometric meaning of strictness as used herein.On the contrary, term " coaxial " should be configured to allow between the longitudinal axis of through hole 350 and 352 deviation is arranged, and this may be because the defective in restriction in the design and/or the production produces.Because signal conductor 320a and the basic coplane of earthing conductor 320b are so through hole 352 can not fully surround through hole 350.However, still between the front surface of substrate 340 and rear surface, produced a low inductance path by through hole 350 and 352 determined coaxial through-hole structures.
Fig. 4 A is a schematic plan view that contains the semiconductor device 400 of low inductance via structures according to an embodiment.In one embodiment, the described semiconductor device of Fig. 3 A can comprise a co-planar waveguide.Fig. 4 B is the schematic partial cross section figure of the described semiconductor device 400 of Fig. 4 A.In one embodiment, this semiconductor device 400 can comprise a co-planar waveguide.In another embodiment, semiconductor device 400 can comprise planed signal and the earth connection that is connected by through-hole structure.
With reference to Fig. 4 A and 4B, semiconductor device 400 comprises a signal conductor 420a, and this signal conductor 420a passes the part front surface and the part rear surface of substrate 440, and passes the cross section of substrate 440 by through hole 450.Equally, semiconductor device 400 comprises an earthing conductor 420b, and this earthing conductor 420b passes the part front surface and the part rear surface of substrate 440, and passes the cross section of substrate 440 by through hole 452.Insulator 430c among Fig. 4 B is corresponding to the 430 visible parts of insulating barrier among Fig. 4 A.
In the embodiment described in Fig. 4 A-4B, through hole 450 and 452 is coaxial along axis basically, extends through to this axis normal substrate 440.Term " coaxial " should not be configured to satisfy the accurate aligning of the longitudinal axis of through hole 450 and 452 on the geometric meaning of strictness as used herein.On the contrary, term " coaxial " should be configured to allow between the longitudinal axis of through hole 450 and 452 deviation is arranged, and for example this may be because the defective in restriction in the design and/or the production produces.With reference to Fig. 4 B, because the residing plane of signal conductor 420a is higher than the residing plane of earthing conductor 420b, so through hole 452 can fully surround through hole 450.Between the front surface of substrate 440 and rear surface, produced a low inductance path by through hole 450 and 452 determined coaxial through-hole structures.
The semiconductor device that contains low inductance via described here can be used as the circuit element in radio frequency (RF) transceiver application, as the wireless network adapter in radio telephone and the calculation element.Fig. 5 illustrate schematicallys a radio telephone 500 according to an embodiment.With reference to Fig. 5, radio telephone 500 comprises a display 510, keyboard 515, radio-circuit 520, voicefrequency circuit 525 and processor 530.Processor 530 links to each other with memory module 535.Radio-circuit 520 links to each other with an antenna 555 through suitable connector 560.
Handled by radio-circuit 520 by antenna 555 received wireless signals, this is the same with the operation in the wireless set.Radio-circuit 520 can comprise a receiving filter, down converter, baseband filter, analog to digital converter (ADC), local oscillator circuit etc.Radio-circuit 520 can also comprise a reflector with power amplifier (PA) circuit, is used for being amplified to certain level transmitting and is fit to emission from antenna 555 afterwards.Radio-circuit 520 is supported one or more frequency ranges.Such as, the tranmitting frequency of unlicensed wireless signal be 900MHz or at 2.4GHz to the frequency range between the 5GHz.
Treatment circuit 530 comprises baseband processor, one or more support circuit, and be used for storing one or more memories required or instruction that requires and calibration data etc.Wherein, baseband processor can comprise one or more microprocessors, application-specific integrated circuit (ASIC) (ASIC), field programmable gate array (FPGA) or other electronic logic devices; Support that circuit for example is clock/timing control circuit, I/O (IO) interface circuit; Memory for example is electrically erasable programmable ROM (EEPROM) or flash memory.
Processed wireless signal converts audio signal to by voicefrequency circuit 525.Audio signal offers the user by audio interface 532, and wherein audio interface comprises loud speaker, microphone and/or other devices.Handle by processor 530, voicefrequency circuit 525 and radio-circuit 520 by the audio signal that audio interface 532 receives.Wireless signal is sent to antenna 555 then, is played as the RF signal thus.
Memory module 535 comprises the logical order that realizes various feature or functions.Such as, memory module 535 comprises that is delivered a module 540, is used for handling the task of delivering between the cellular network base station.Memory module 535 also comprises a position tracking module 545, is used for determining the current location of radio telephone 500.In addition, memory module 535 comprises authentication module 550, is used for coordinating an authentication procedure, makes radio telephone 500 be registered use in network.
Therefore, though with concrete language description the architectural feature of embodiment and/or method action, should be appreciated that theme required for protection should not be defined in concrete feature or said process.More properly, the exemplary forms implemented by theme required for protection of concrete feature and action is disclosed.
Claims (20)
1, a kind of method comprises:
On the substrate first surface, form first and second through holes, and first and second through holes are coaxial;
In first through hole, between the first surface of substrate and second surface, form first conductive path;
In second through hole, between the first surface of substrate and second surface, form second conductive path.
2, the process of claim 1 wherein that forming first and second through holes on substrate comprises:
On the first surface of substrate, form first and second grooves, and first and second grooves are coaxial; Partly remove with second surface substrate.
3, the process of claim 1 wherein that in first through hole forming first conductive path between the first surface of substrate and second surface comprises:
On the first surface of substrate, form first groove;
On first surface, form first conductive material layer, and this conductive material layer is filled first groove;
Patterning first conductive material layer is to form first conductor on first surface; With
The second surface of substrate is partly removed, the electric conducting material in the groove of winning is exposed.
4, the method for claim 3 also comprises:
On second surface, form second conductive material layer, it is electrically connected with electric conducting material in first groove;
Patterning second conductive material layer is to form second conductor on second surface.
5, the process of claim 1 wherein that in second through hole forming second conductive path between the first surface of substrate and second surface comprises:
On the first surface of substrate, form second groove;
On first surface, form first conductive material layer, and this conductive material layer is filled second groove;
Patterning first conductive material layer is to form the 3rd conductor on first surface; With
The second surface of substrate is partly removed, made that the electric conducting material in second groove exposes.
6, the method for claim 5 also comprises:
On second surface, form second conductive material layer, it is electrically connected with electric conducting material in second groove;
Patterning second conductive material layer is to form the 4th conductor on second surface.
7, a kind of method comprises:
On the first surface of substrate, form coaxial groove;
On the first surface of substrate, form first insulation material layer;
On first insulation material layer, form first conductive material layer;
Patterning first conductive material layer is to form first conductor and second conductor;
The second surface of substrate is partly removed, made part first insulation material layer and first conductive material layer expose.
On the second surface of substrate, form second insulation material layer;
On second insulation material layer, form second conductive material layer;
Patterning second conductive material layer with isolate with the second layer part of the first conductor telecommunication and with the second layer part of the second conductor telecommunication.
8, the method for claim 7 wherein forms contiguous groove and comprises the etching part backing material on the first surface of a substrate.
9, the method for claim 7 wherein is included in deposition of insulative material on the first surface of substrate at formation first insulation material layer on the first surface of substrate.
10, the method for claim 7 wherein is included in deposits conductive material on the first surface of substrate at formation first conductive material layer on first insulation material layer.
11, the method for claim 7, wherein patterning first conductive material layer comprises optionally etching part electric conducting material to form first conductor and second conductor.
12, the method for claim 7 is wherein partly removed the second surface of substrate with expose portion first insulation material layer and first conductive material layer and is comprised: the part second surface that grinds substrate.
13, a kind of semiconductor device comprises:
Substrate;
First through hole makes to be connected with source conductor on the substrate second surface at the source conductor on the substrate first surface; With
Second through hole, coaxial with first through hole, make to be connected with earthing conductor on the substrate second surface at the earthing conductor on the substrate first surface.
14, the semiconductor device in the claim 13 is a coplane at source conductor on the first surface and the earthing conductor on first surface wherein.
15, the semiconductor device in the claim 13, wherein the source conductor on first surface is on first plane, and the earthing conductor on first surface is positioned at second plane.
16, the semiconductor device in the claim 13 is a coplane at source conductor on the second surface and the earthing conductor on second surface wherein.
17, the semiconductor device in the claim 13, wherein the source conductor on second surface is positioned at the 3rd plane, and the earthing conductor on second surface is positioned at Siping City's face.
18, a kind of radio telephone comprises:
Audio interface;
Be used to receive the circuit of wireless communication signal, its wireless communication signal is given audio interface after converting audio signal to, and this circuit comprises the semiconductor device, and this semiconductor device comprises:
Substrate;
First through hole makes to be connected with source conductor on the substrate second surface at the source conductor on the substrate first surface; With
Second through hole, coaxial with first through hole, make to be connected with earthing conductor on the substrate second surface at the earthing conductor on the substrate first surface.
19, the radio telephone of claim 18, wherein semiconductor device comprises radio-frequency (RF) transceiver, receiving filter, down conversion circuit, baseband filter, analog to digital converter, local oscillator circuit or power amplifier circuit.
20, the radio telephone of claim 18, wherein semiconductor device comprises shaft through-hole altogether.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/135,112 US20060264029A1 (en) | 2005-05-23 | 2005-05-23 | Low inductance via structures |
| US11/135,112 | 2005-05-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1881559A true CN1881559A (en) | 2006-12-20 |
Family
ID=36945145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101054748A Pending CN1881559A (en) | 2005-05-23 | 2006-05-23 | Low inductance via structures |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20060264029A1 (en) |
| CN (1) | CN1881559A (en) |
| WO (1) | WO2006127988A1 (en) |
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| US9269485B2 (en) | 2007-11-29 | 2016-02-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of creating spiral inductor having high Q value |
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-
2005
- 2005-05-23 US US11/135,112 patent/US20060264029A1/en not_active Abandoned
-
2006
- 2006-05-23 CN CNA2006101054748A patent/CN1881559A/en active Pending
- 2006-05-23 WO PCT/US2006/020407 patent/WO2006127988A1/en active Application Filing
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9269485B2 (en) | 2007-11-29 | 2016-02-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of creating spiral inductor having high Q value |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2006127988A1 (en) | 2006-11-30 |
| US20060264029A1 (en) | 2006-11-23 |
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