CN1881058A - Display device - Google Patents

Abstract

The present invention provides a display device wherein a first public line and a first strobe down-lead wiring are installed together in the frame. Compared with the first strobe down-lead wiring, the first public line is configured much nearer in the side of a number of pixels. The strobe wiring design, which is composed of a number of strobe lines, the first and the second strobe down-lead wirings, while the memory wiring design is composed of a number of memory lines, the first and the second public lines. These two designs above form a non-cross wiring pattern.

Description

Display device and liquid crystal display device

This application is a divisional application of application No. 200410083181.5, filed on 9/27/2002, entitled "display device".

Technical Field

The present invention relates to a display device, and more particularly, to an active matrix display device having gate lines and data lines alternately arranged on one of 2 substrates and having storage lines constituting storage capacitors for maintaining light emission of pixels.

Background

Liquid crystal display devices are often used as display devices for personal computers, various monitors, and various information devices. In particular, a liquid crystal display device having small size, light weight, and power saving characteristics is used for display of a mobile phone and a mobile information terminal called a PDA. Therefore, it is a mainstream to directly mount the driving circuit chip on a part of the substrate to reduce the overall size.

In many cases, the liquid crystal display device used in such a portable information terminal is configured to supply display data and a driving voltage from one side of a 2-piece bonded substrate, in order to reduce a mounting space and facilitate mounting of a control circuit. In particular, in a liquid crystal display device for a mobile phone, a flexible printed circuit board is mounted on one side of 2 substrates to supply display data and a driving voltage in many cases in order to be easily accommodated in a limited mounting space.

Liquid crystal display devices have various types depending on the electrode configuration and the driving method, and a liquid crystal display device generally referred to as a TH type will be described as an example. In this TN liquid crystal display device, a liquid crystal formation display region is sealed in a bonding gap between a 1 st substrate and a 2 nd substrate constituting a pair of substrates. In the display region of the 1 st substrate, for example, a matrix is formed by a plurality of data lines (also referred to as drain lines, signal lines, and the like) extending in the vertical direction (hereinafter referred to as the 1 st direction) and arranged in parallel in the horizontal direction (hereinafter referred to as the 2 nd direction) and a plurality of gate lines (also referred to as scan lines and the like) extending in the vertical direction and arranged in parallel in the horizontal direction and perpendicular to the data lines, and a region surrounded by 1 pair of each of the data lines and the scan lines forms a pixel.

A counter electrode for applying an electric field to liquid crystals of the pixel is provided on the No. 2 substrate so as to be opposed to the pixel electrode, and a 3-color filter is provided in color display. Each pixel is formed of liquid crystal sandwiched between a 1 st substrate having a pixel electrode and a 2 nd substrate having a counter electrode, and light emission/non-light emission is controlled by on/off of a switching element (usually, a thin film transistor: TFT, hereinafter described as a thin film transistor) provided at one corner of the pixel.

In order to maintain the voltage of display data for a certain time when thin film transistors constituting the pixels are turned on, a storage capacitor (Cstg) is provided in each pixel. There are many methods of supplying power to the storage capacitor (that is, storing and holding charges of display data supplied to pixels for a predetermined period), and there is also a method of providing a wiring called a storage line in a display region. The storage line is generally formed on the 1 st substrate adjacent to each gate line and in parallel.

In a display region, the scanning lines are arranged alternately between the scanning lines in a plane, extend in parallel to the extending direction of the scanning lines, and are connected at one end by a common line to a predetermined terminal provided on one side of the substrate. The gate lines and the storage lines of such a liquid crystal display device are laid as follows. It is assumed here that a liquid crystal display device is described in which a 1 st substrate has a driver circuit mounting region, i.e., a region on which a driver circuit chip is mounted, and a 2 nd substrate is stacked on a portion other than the driver circuit mounting region, and the periphery of the stacked portion is sealed with a sealing material. The following describes the driving circuit mounting region as being set to the lower side (lower side) in the vertical direction of the liquid crystal display device. Therefore, the lower side and the adjacent two sides of the 1 st substrate having this driving circuit mounting area are referred to as left and right sides.

When data lines are formed in the 1 st direction (for example, the vertical direction) of one substrate (the 1 st substrate described above, also referred to as a thin film transistor substrate) of a liquid crystal display device configured by laminating 2 substrates, gate lines are formed in the 2 nd direction (for example, the horizontal direction) orthogonal to the data lines. The gate line is led to the above-mentioned driving circuit mounting region along the left side of the substrate at one side (e.g., the left side) in the lateral direction. Then, a memory line is formed between the gate lines, and is led to the driver circuit mounting region along the right side on the other lateral side (for example, the right side) via a common line.

However, when the gate line is led out only on one side (for example, only on the frame region on the left side) as in the conventional technique, the width of the frame region on the left side and the width of the frame region on the right side are different, and the display region is arranged on the substrate at a position laterally shifted to the right from the center.

Here, the gate lines may be drawn downward from the frame region on the left side and the gate lines may be drawn downward from the frame region on the right side, or the display region may be arranged at a central position in the lateral direction by drawing from both the frame regions on the left and right sides. However, in such an arrangement, in a configuration in which a common line connecting a plurality of memory lines is provided only on one side (for example, only in a frame region on the right side) as in the prior art, the gate lines and the lead lines thereof are arranged alternately. Among them, the wiring needs to be bridged over when formed in another layer, and a disconnection defect is likely to occur in such a bridged portion, which is a factor of hindering improvement of reliability.

Further, aluminum is used for the gate line and the storage line, and when the gate line and the storage line are anodized (anodized), they are formed separately for crossing, which is one of the causes of increasing the manufacturing cost due to the increase of the number of steps.

Disclosure of Invention

The invention provides a display device with high display quality, which improves reliability by means of a gate line wiring pattern composed of a gate line and a gate line guide wire and a wiring pattern without crossing between storage line patterns composed of storage lines and wires connecting the storage lines even when the gate line is guided in frame regions on both left and right sides.

To achieve the above object, the present invention is characterized in that a gate line wiring pattern composed of a gate line and a gate line lead wiring and a storage line wiring pattern composed of a storage line and a common line are formed so as not to intersect each other by forming the common line connecting respective storage lines in the frame regions on both sides while guiding the gate line in the frame regions on both sides with the gate line lead wiring. The present invention is characterized by including an auxiliary common line for reducing a voltage difference between the storage lines divided into the upper and lower groups when the storage lines are divided into the upper and lower groups of the display area and the common lines connecting the storage lines are formed in the frame areas on both the left and right sides. The present invention is typically configured as follows.

The present invention provides a display device, characterized by comprising: a substrate having a display region and a frame region surrounding the display region outside the display region; a plurality of data lines extending in a 1 st direction and arranged in parallel in a 2 nd direction intersecting the 1 st direction in the display region of the substrate; a plurality of gate lines extending in the 2 nd direction and arranged in parallel in the 1 st direction in the display region of the substrate; a switching element disposed near an intersection of the data line and the gate line; a pixel electrode formed in a region surrounded by the adjacent data line and the adjacent gate line; and a plurality of storage lines extending in the 2 nd direction in the display region of the substrate, arranged alternately in parallel with the gate lines in the 1 st direction, and forming storage capacitors with the pixel electrodes, wherein the substrate includes: a plurality of connection terminals arranged on the 1 st side and connected with an external circuit; 1 st and 2 nd gate line lead wirings respectively provided on the frame regions on the 2 nd and 3 rd sides adjacent to the 1 st side and for leading out the gate lines in the 1 st direction; and 1 st and 2 nd common lines respectively provided in frame regions on the 2 nd and 3 rd sides and connecting the plurality of storage lines to each other, wherein the storage lines are divided into a near group near the 1 st side and a far group far from the 1 st side, the near group near the 1 st side is connected to the 1 st common line, the far group far from the 1 st side is connected to the 2 nd common line, a gate wiring pattern including the plurality of gate lines and the 1 st and 2 nd gate line lead wirings, and a storage wiring pattern including the plurality of storage lines and the 1 st and 2 nd common lines form a wiring pattern which does not cross each other.

It is needless to say that the present invention is not limited to the above configuration and the examples described below, and various modifications may be made without departing from the technical idea of the present invention.

Drawings

Fig. 1 is a schematic plan view illustrating a 1 st embodiment of a liquid crystal display device of the present invention.

Fig. 2 is a schematic plan view illustrating embodiment 2 of the liquid crystal display device of the present invention.

Fig. 3 is a schematic plan view illustrating embodiment 3 of the liquid crystal display device of the present invention.

Fig. 4 is a schematic plan view illustrating a 4 th embodiment of a liquid crystal display device of the present invention.

Fig. 5 is a schematic diagram illustrating a wiring configuration of a 5 th embodiment of a liquid crystal display device of the present invention.

Fig. 6 is a schematic diagram illustrating a wiring configuration of embodiment 6 of the liquid crystal display device of the present invention.

Fig. 7 is a schematic diagram illustrating a wiring configuration of embodiment 7 of the liquid crystal display device of the present invention.

Fig. 8 is a schematic diagram illustrating a wiring configuration of an 8 th embodiment of a liquid crystal display device of the present invention.

Fig. 9 is a schematic diagram illustrating a wiring configuration of a 9 th embodiment of a liquid crystal display device of the present invention.

Fig. 10 is a schematic diagram illustrating a wiring configuration of a 10 th embodiment of a liquid crystal display device according to the present invention.

Fig. 11 is a schematic plan view illustrating an 11 th embodiment of a liquid crystal display device of the present invention.

Fig. 12 is a sectional view of an auxiliary common line portion taken along line B-B' of fig. 11.

Fig. 13 is a schematic plan view illustrating a 12 th embodiment of a liquid crystal display device of the present invention.

Fig. 14 is a schematic plan view illustrating an example of the configuration of the vicinity of one pixel of the 1 st substrate of the liquid crystal display device of the present invention.

Fig. 15 is a sectional view of the 1 st substrate taken along line a-a' of fig. 14.

Fig. 16 is a cross-sectional view of the 1 st substrate taken along the line a-a' in fig. 14 when the present invention is applied to a liquid crystal display device having another structure.

Fig. 17 is a schematic plan view illustrating another configuration example of the vicinity of one pixel of the 1 st substrate of the liquid crystal display device of the present invention.

Fig. 18 is a sectional view of the 1 st substrate taken along line a-a' of fig. 17.

FIG. 19 is a cross-sectional view of a 1 st substrate taken along the line A-A' in FIG. 17, when the present invention is applied to a liquid crystal display device having another structure.

Detailed Description

The embodiments of the present invention will be described in detail below with reference to the drawings of the embodiments.

Fig. 1 is a schematic plan view illustrating a 1 st embodiment of a liquid crystal display device of the present invention. In this liquid crystal display device, a 1 st substrate SUB1 and a 2 nd substrate SUB2 are bonded to each other, a liquid crystal (not shown) is sealed between the substrates to form a display region AR, and the periphery thereof is sealed with a sealing material. The symbol INJ denotes a liquid crystal seal port, and the liquid crystal is sealed between the two substrates and then sealed with a sealing material. The region other than the display region AR is referred to as a frame region. Further, one side (lower side in fig. 1) of the 1 st substrate SUB1 is exposed from the 2 nd substrate SUB 2.

On this portion adjacent to the display area AR, there are provided a data line drive circuit (data drive circuit: semiconductor integrated circuit or chip) DDR and a gate line drive circuit (gate drive circuit: semiconductor integrated circuit or chip) GDR1, GDR2, input terminals DDM, GDM1, GDM2, and various power supply PADs P-PAD1, P-PAD2, P-PAD3 thereof. This portion is referred to as a drive circuit mounting region BR. The input terminals DDM, GDM1, GDM2 and the various power supply PADs P-PAD1, P-PAD2, P-PAD3 of the driver circuit mounting region BR are connected to output terminals of a flexible printed circuit board not shown in the figure. The data line driving circuit and the gate line driving circuit are so-called integrated circuits, but are not limited to chips, and include those directly formed on a substrate. The same applies to the following examples.

The display region of the 1 st substrate SUB1 has a plurality of data lines DL extending in the vertical direction (1 st direction) of the substrate and arranged in parallel in the horizontal direction (2 nd direction), and is connected to output terminals of a data line driving circuit DDR mounted on the driving circuit mounting region BR. In addition, the display region of the 1 st substrate SUB1 also has a plurality of gate lines GL extending in the lateral direction (2 nd direction) of the substrate and arranged in parallel in the longitudinal direction (1 st direction). The gate line GL is divided into two groups GL1 and GL2, which are connected to output terminals of gate line driving circuits GDR1 and GDR2 installed in the driving circuit installation region BR for driving the two gate line groups, respectively, by gate line lead lines GLL1 and GLL2 passing through the left and right frame regions, respectively, with respect to the display region AR.

By thus dividing the wiring between the two groups, the display area AR can be disposed substantially at the center in the left-right direction of the 1 st substrate SUB1, i.e., at the center of the screen.

In addition, in the display region AR, a plurality of thin film transistors as switching elements provided at each pixel formed at a crossing portion of the data line DL and the gate line GL are omitted in the drawing. In addition, a pixel formed of each thin film transistor has a pixel electrode, which is not shown in the drawing.

An opposite electrode facing the pixel electrode is formed on the inner surface of the 2 nd substrate SUB 2. In the case of color display, a plurality of color filters are provided on the upper layer or the lower layer of the counter electrode, and are not shown together with the counter electrode. The counter electrodes are connected to power supply PADs P-PAD1, P-PAD2, and P-PAD3 provided in the driving circuit mounting region BR via counter electrode connection PADs C-PAD1 and C-PAD2 provided at upper corners of the 1 st substrate SUB1 and common lines B1 and B2.

The storage line STL is formed between the gate lines GL (GL1, GL2) of the 1 st substrate SUB 1. The storage line STL is divided into two groups, i.e., an upper group and a lower group with respect to the display region of the 1 st substrate SUB1, the lower group is connected to the power supply PAD P-PAD2 in the driving circuit mounting region BR by the common line B3 provided on the left side, and the upper group is connected to the power supply PAD P-PAD3 in the driving circuit mounting region BR by the common line B2 provided on the right side.

The power supply to the storage line STL is performed by power supply PADs P-PAD2, P-PAD 3. In addition, since the counter electrode connection PADs C-PAD1 and C-PAD2 are connected to the counter electrode, it can also be said that the storage line STL is supplied with power from the counter electrode connection PADs C-PAD1 and C-PAD2 and the power supply PAD P-PAD 1. Even if the common lines B1 and B2 are disconnected due to a fault or the resistance increases, the power supply to the storage line STL can be sufficient.

With the constitution as in the present embodiment, the storage line wiring pattern (storage line and common line) and the gate line wiring pattern (gate line and gate line lead wiring) do not cross at a place on the substrate plane. Accordingly, the storage line STL and the gate line GL may be formed in the same layer. In addition, even when the wiring layer is formed in another layer, since there is no portion crossing each other, there is no need to consider the problem of occurrence of disconnection defect. In addition, since the storage line STL and the gate line GL are formed in the same layer, in the case of patterning them with an aluminum material, anodic oxidation for preventing hillocks from occurring can be performed in one process without increasing the manufacturing process. Since the wirings, including the lead wirings, are arranged in the display region AR in a bilaterally symmetrical manner, the display region AR can be arranged at the center of the liquid crystal display device.

In addition, a power supply PAD P-PAD2 applying a voltage to the storage line wiring pattern is formed between a connection terminal (GDM1) associated with the gate line and a connection terminal (DDM) associated with the data line, and power can be supplied from this power supply PAD P-PAD 2. Therefore, even when the storage line wiring patterns are formed so as to be separated into 2 pieces as in the present embodiment, power can be supplied. In addition, the gate line driving circuit GDR1, GDR2, and the data line driving circuit DDR may be formed as one circuit on one chip. The same applies to the following embodiments.

As described above, according to the present embodiment, a highly reliable liquid crystal display device of a storage line system can be provided without increasing the number of manufacturing steps.

Fig. 2 is a schematic plan view illustrating embodiment 2 of the liquid crystal display device of the present invention. The same reference numerals as in fig. 1 denote the same functional parts. In this embodiment, only the data line driving circuit DDR is mounted in the driving circuit mounting region BR of embodiment 1, and the gate line driving circuit is mounted on the flexible printed circuit board side not shown in the figure. The configurations of the data lines DL, the gate lines GL and the storage lines STL disposed on the display area AR are the same as those of embodiment 1, and a description thereof will not be repeated.

In the present embodiment, the gate line lead wirings GLL1, GLL2 are directly connected to the gate line terminals GTM1, GTM2 at the driving circuit mounting region BR. The gate line terminals GTM1 and GTM2 are connected to output terminals of a gate line driving circuit (similar to GDR1 and GDR2 in fig. 1) mounted on a flexible printed circuit board (not shown) and supply power to the gate lines GL1 and GL 2. Therefore, the area of the various wirings and pads provided in the driver circuit mounting region BR can be increased.

With the constitution like this embodiment, the storage line STL and the gate line GL can be formed in the same layer as in embodiment 1 where the storage line wiring pattern and the gate line wiring pattern do not cross on the substrate plane. In addition, even when the wiring layer is formed in another layer, since there is no portion crossing each other, there is no need to consider the problem of occurrence of disconnection defect. In addition, since the storage line STL and the gate line GL are formed in the same layer, in the case of patterning them with an aluminum material, anodic oxidation for preventing hillocks from occurring can be performed in one process without increasing the manufacturing process. Since the wirings, including the lead wirings, are arranged in the display region AR in a bilaterally symmetrical manner, the display region AR can be arranged at the center of the liquid crystal display device.

In addition, a power supply PAD P-PAD2 for applying a voltage to the storage line wiring pattern is formed between a connection terminal (here, GTM1 unlike fig. 1) associated with the gate line and a connection terminal (DDM) associated with the data line, and power can be supplied from this power supply PAD P-PAD 2. In addition, the data line driving circuit may be provided on a portion other than the 1 st substrate SUB1, and a data terminal for supplying a data line driving voltage to the data line DL may be provided on the 1 st substrate SUB1 as a connection terminal associated with the data line, and may be connected to an output of the data line driving circuit. The same applies to the following embodiments.

As described above, according to this embodiment, as in embodiment 1, a highly reliable liquid crystal display device of a storage line system can be provided without increasing the number of manufacturing steps.

Fig. 3 is a schematic plan view illustrating embodiment 3 of the liquid crystal display device of the present invention. The same reference numerals as in fig. 1 and 2 denote the same functional parts. This liquid crystal display device is a device in which the gate lines shown in fig. 1 or fig. 2 are replaced with groups of gate lines driven by gate line driving circuits GDR1 and GDR2, which alternately extend from the left and right sides to the display area AR. With this arrangement of the gate lines, the storage lines STL are divided into two groups, one above the other, and are connected to the common line B2 or B3 with one gate line interposed therebetween.

That is, the upper group is supplied with power from the power supply PAD P-PAD3 through the counter electrode connection PAD C-PAD2 with the common line B2, and the lower group is supplied with power from the power supply PAD P-PAD2 with the common line B3. In addition, the common line B2 may be connected to the power supply PAD P-PAD3 without passing through the counter electrode connection PAD C-PAD 2.

As in the present embodiment, at least a part of the plurality of storage lines STL is connected to the common line of the frame region on the left side and the common line of the frame region on the right side, so that a pattern without crossing of the wirings can be formed. In addition, in the present embodiment, the storage line pattern forms a curved pattern between the common lines on the left and right sides. In the present embodiment, the storage line STL is formed by bending two lines in a set, but a pattern of bending 3 lines or more may be formed in a set. The same applies to the following embodiments.

With the configuration like this embodiment, the storage line STL and the gate line GL can be formed in the same layer where the storage line wiring pattern and the gate line wiring pattern do not cross on the substrate plane, as in the 1 st embodiment and the 2 nd embodiment. In addition, even when the wiring layer is formed in another layer, since there is no portion crossing each other, there is no need to consider the problem of occurrence of disconnection defect. In addition, since the storage line STL and the gate line GL are formed in the same layer, in the case of patterning them with an aluminum material, anodic oxidation for preventing hillocks from occurring can be performed in one process without increasing the manufacturing process. Since the wirings, including the lead wirings, are arranged in the display region AR in a bilaterally symmetrical manner, the display region AR can be arranged at the center of the liquid crystal display device.

As described above, according to this embodiment, as in embodiment 1 and embodiment 2, a highly reliable storage line type liquid crystal display device can be provided without increasing the number of manufacturing steps.

Fig. 4 is a schematic plan view illustrating a 4 th embodiment of a liquid crystal display device of the present invention. The same reference numerals as in fig. 3 denote the same functional parts. This embodiment is a configuration example in the case where only the data line driving circuit DDR is mounted in the driving circuit mounting region BR of embodiment 3 and the gate line driving circuit is mounted on the flexible printed circuit board side not shown in the figure. Since the configurations of the data lines DL, the gate lines GL and the storage lines STL disposed in the display area AR are the same as those of embodiment 3, the description thereof will not be repeated.

In the present embodiment, the gate line lead wirings GLL1, GLL2 are directly connected to the gate line terminals GTM1, GTM2 provided in the driving circuit mounting region BR. The gate line terminals GTM1 and GTM2 are connected to output terminals of a gate line driving circuit (the same as GDR1 and GDR2 in fig. 1) mounted on a flexible printed circuit board (not shown), and supply a driving voltage to the gate lines GL1 and GL 2. Therefore, the area of the various wirings and pads provided in the driver circuit mounting region BR can be increased.

With the constitution like this embodiment, the storage line STL and the gate line GL can be formed in the same layer as in embodiment 3 where the storage line wiring pattern and the gate line wiring pattern do not cross on the substrate plane. In addition, even when the wiring layer is formed in another layer, since there is no portion crossing each other, there is no need to consider the problem of occurrence of disconnection defect. In addition, since the storage line STL and the gate line GL are formed in the same layer, in the case of patterning them with an aluminum material, anodic oxidation for preventing hillocks from occurring can be performed in one process without increasing the manufacturing process. Since the wirings, including the lead wirings, are arranged in the display region AR in a bilaterally symmetrical manner, the display region AR can be arranged at the center of the liquid crystal display device.

As described above, according to this embodiment, as in embodiments 1 to 3, a highly reliable storage line type liquid crystal display device can be provided without increasing the number of manufacturing steps.

Fig. 5 is a schematic diagram illustrating a wiring configuration of a 5 th embodiment of a liquid crystal display device of the present invention. The same reference numerals as in fig. 1 and 2 correspond to the same functional portions. In the liquid crystal display devices according to embodiment 1 and embodiment 2, the storage lines STL are divided into a plurality of groups in the upper and lower portions of the display area AR, and are physically independent in the display area AR. In the present embodiment, the common line B4 of the group of storage lines STL divided corresponding to the gate line GL1 of the 1 st group and the common line B3 of the group of storage lines STL divided corresponding to the gate line GL2 of the 2 nd group are connected and physically connected at both ends of the storage lines STL in the display area AR. The common line B4 may be replaced with a common line B2. However, the wirings cannot intersect. The same is true of the following examples.

By connecting the storage lines STL of the groups thus divided, in addition to the effects of the above-described embodiments, it is possible to ensure power supply when a connection failure occurs in one of the power supply circuits, and to suppress blunting of the voltage waveform supplied to the storage lines STL by supplying power from both ends. Thus, a highly reliable liquid crystal display device of a storage line system can be provided.

As in the present embodiment, at least a part of the plurality of storage lines STL is connected to the common line in the frame region on the left side and the common line in the frame region on the right side, so that a pattern without crossover can be formed. In addition, when the storage line wiring pattern is integrally formed as in the present embodiment, power supply from both ends is not necessary, and power supply from only the power supply PAD P-PAD2 may be used, for example. The same applies to the following embodiments.

Fig. 6 is a schematic diagram illustrating a wiring configuration of embodiment 6 of the liquid crystal display device of the present invention. The same reference numerals as in fig. 5 correspond to the same functional parts. In the present embodiment, the storage line storage lines STL of the liquid crystal display devices of the above-described embodiments 1 and 2 are divided into a plurality of groups in the upper and lower portions of the display area AR, and are physically independent in the display area AR, and in the present embodiment, like in embodiment 5, the common line B4 of the group of storage lines STL divided corresponding to the gate line GL1 of the group 1 and the common line B3 of the group of storage lines STL divided corresponding to the gate line GL2 of the group 2 are connected at both ends of the storage line STL in the display area AR and physically connected. Accordingly, the supply pad is not provided to the common line B3 of the group of storage lines STL divided corresponding to the gate line GL2 of the 2 nd group. Therefore, power is supplied to these storage lines STL from the power supply PAD P-PAD3 as well.

According to the present embodiment, the number of pads provided in the driving circuit mounting region BR can be reduced, and a highly reliable storage line type liquid crystal display device can be provided by effectively utilizing the space of the driving circuit mounting region BR.

Fig. 7 is a schematic diagram illustrating a wiring configuration of embodiment 7 of the liquid crystal display device of the present invention. The same reference numerals as in fig. 5 and 6 correspond to the same functional portions. In the liquid crystal display devices according to embodiments 3 and 4 described above, the storage line storage lines STL are divided into a plurality of groups in the upper and lower portions of the display area AR, and physically independent in the display area AR, and in the present embodiment, they are physically connected.

By connecting the thus divided groups of storage lines STL, similarly to the above-described embodiment 5, power supply can be secured when a connection failure occurs in one of the power supply circuits, and power supply from both ends can suppress blunting of the voltage waveform supplied to the storage lines STL, whereby a highly reliable storage line type liquid crystal display device can be provided.

Fig. 8 is a schematic diagram illustrating a wiring configuration of an 8 th embodiment of a liquid crystal display device of the present invention. The same reference numerals as in fig. 7 correspond to the same functional parts. In the present embodiment, the bridge lines BCL1 and BCL2 connected to the common lines B3 and B4 of the storage line STL in fig. 7, respectively, are provided. The bridge lines BCL1 and BCL2 are disposed on the gate line GL and the storage line STL via an insulating layer. Contact holes are provided in the insulating layer at the positions of the common lines B3 and B4. Therefore, although the number of steps for forming the bridge lines BCL1 and BCL2 is increased, power can be reliably supplied to the storage line STL, and a liquid crystal display device with further increased reliability can be provided. The number of processes is not increased even when the data line DL is formed in the same layer.

Fig. 9 is a schematic diagram illustrating a wiring configuration of a 9 th embodiment of a liquid crystal display device of the present invention. This embodiment is a configuration in which power is supplied to the storage line STL via the power supply PAD P-PAD3 as in the 6 th embodiment except for the power supply PAD P-PAD2 of the 7 th embodiment described above.

According to the present embodiment, the number of pads provided in the driving circuit mounting region BR can be reduced, and a highly reliable storage line type liquid crystal display device can be provided by effectively utilizing the space of the driving circuit mounting region BR.

Fig. 10 is a schematic diagram illustrating a wiring configuration of a 10 th embodiment of a liquid crystal display device according to the present invention. This embodiment is an embodiment in which the bridge winding BCL1, BCL2 described in embodiment 8 is provided in embodiment 9 described above. The bridge lines BCL1 and BCL2 are disposed on the gate line GL and the storage line STL via an insulating layer, as in fig. 8. Contact holes are provided in the insulating layer at the positions of the common lines B3 and B4. Therefore, although the number of steps for forming the bridge lines BCL1 and BCL2 is increased, power can be reliably supplied to the storage line STL, and a liquid crystal display device with further increased reliability can be provided. The number of processes is not increased even when the data line DL is formed in the same layer. Other configurations and effects are the same as those of embodiment 9.

Fig. 11 is a schematic plan view illustrating an 11 th embodiment of a liquid crystal display device of the present invention. Corresponding to a modification of the embodiment of fig. 1, a data line driving circuit DDR and two gate line driving circuits GDR1 and GDR2 are mounted in the driving circuit mounting region BR. In the drawings, the same reference numerals as those in the above embodiments correspond to the same functions. In the liquid crystal display device having the configuration of fig. 1, 2, 5, and 6, i.e., the configuration in which the storage lines are divided into 2 groups in the upper and lower portions of the effective region, there may be a difference in the power supply resistance of the lines. For example, when a part of the wiring connecting the power supply PAD P-PAD2 and the common line B3 is thin. The voltage difference caused by the resistance difference causes a difference in luminance between the upper and lower pixels of the screen connected to the upper and lower storage lines, resulting in deterioration of image quality,

the basic wiring of fig. 11 is the same as that of fig. 1. In this liquid crystal display device, in a frame region on the left side of the display region AR when facing fig. 11, there are a plurality of gate line lead wirings, and wirings on both sides thereof are a common line B1 connecting the counter electrode connection PAD C-PAD1 to the power supply PAD P-PAD1 and a common line B3 commonly connecting the storage line STL on the lower side. Therefore, it is difficult to secure a sufficient wiring width of the common line B3 as compared with the common line B2 provided in the frame region on the right side of the display region AR in fig. 11. As a result, the above-described difference in luminance between the upper and lower pixels of the screen is generated.

In the present embodiment, the common line B1 connecting the counter electrode connection PAD C-PAD1 to the power supply PAD P-PAD1 and the common line B3 commonly connecting the storage line STL on the lower side are electrically connected by the auxiliary common line CBL. In this case, the common line B1 may be referred to as a power supply line. The counter electrode connection PAD C-PAD1 is connected to the power supply PAD P-PAD3 on the right side of the display area AR via a counter electrode on the 2 nd substrate SUB 2. Thereby, the potential of the lower storage line STL connected to the common line B1 becomes the same as the potential of the upper storage line STL. The auxiliary common line CBL is defined as a component not included in the storage line wiring pattern. Therefore, the wiring pattern does not intersect with the storage line wiring pattern.

Fig. 12 is a sectional view of an auxiliary common line portion taken along line B-B' of fig. 11. The auxiliary common line CBL is electrically connected to the common lines B1 and B3 across the gate line lead wiring GLL 1. Insulated from the gate line lead wiring GLL1 by a gate line insulating layer GI. The auxiliary common line CBL may be formed of a separate semiconductor, or may be formed of the same conductive material as the data line DL, and may be formed simultaneously in the patterning process of the data line DL. That is, after the gate line lead wiring GLL1 is formed, a contact hole is formed on the gate line insulating layer GI at the connection portion of the common lines B1 and B3 to cover the gate line insulating layer GI, and an auxiliary common line CBL as a bridge of the common lines B1 and B3 is formed at the time of patterning the data line DL. The gate line wiring pattern and the storage line wiring pattern are preferably formed in the same layer with the same material as each other.

According to this embodiment, the voltage difference due to the resistance difference between the common lines B1 and B3 for supplying power to the upper and lower storage lines can be reduced, and the luminance difference between the pixels connected to these upper and lower storage lines can be reduced, thereby improving the image quality. Alternatively, the upper storage line and the lower storage line may be connected at a point B in the drawing. In addition, with such a configuration, the power supply PAD P-PAD2 provided in the driver circuit mounting region can be omitted, and the margin of arrangement of the terminal space used for connecting the external circuit can be made larger.

Fig. 13 is a schematic plan view illustrating a 12 th embodiment of a liquid crystal display device according to the present invention, which corresponds to a modification of fig. 2, and can solve the same problems as those in fig. 11. In the drawings, the same reference numerals as those in the above embodiments correspond to the same functions.

The basic wiring of fig. 13 is the same as that of fig. 2. As in fig. 2, the liquid crystal display device has a structure in which only the data line driving circuit DDR is mounted. Also in this liquid crystal display device, in a frame region on the left side of the display region AR when facing fig. 13, there are a plurality of gate line lead wirings GLL1, and wirings on both sides thereof are a common line B1 connecting the counter electrode connection PAD C-PAD1 to the power supply PAD P-PAD1 and a common line B3 commonly connecting the storage line STL on the lower side. Therefore, it is difficult to secure a sufficient wiring width of the common line B3 as compared with the common line B2 provided in the frame region on the right side of the display region AR in fig. 13. As a result, the above-described difference in luminance between the upper and lower pixels of the screen is generated.

In the present embodiment, the common line B1 connecting the counter electrode connection PAD C-PAD1 to the power supply PAD P-PAD1 and the common line B3 commonly connecting the storage line STL on the lower side are electrically connected by the auxiliary common line CBL. The counter electrode connection PAD C-PAD1 is connected to the power supply PAD P-PAD3 on the right side of the display area AR via a counter electrode on the 2 nd substrate SUB 2. Thereby, the potential of the lower storage line STL connected to the common line B1 becomes the same as the potential of the upper storage line STL. In addition, the sectional structure along the line B-B' of the auxiliary common line CBL of fig. 13 is the same as that of fig. 12. Other configurations and effects are the same as those of fig. 11.

Fig. 14 is a schematic plan view illustrating an example of the configuration of the vicinity of one pixel of the 1 st substrate of the liquid crystal display device of the present invention. In the drawing, reference numeral DL denotes a data line, GL denotes a gate line, STL denotes a storage line, ITO denotes a pixel electrode, TFT denotes a thin film transistor, and Cstg denotes a storage capacitor. The region surrounded by the two data lines DL and the two gate lines GL constitutes a pixel. The pixel includes the pixel electrode ITO driven by the thin film transistor TFT and a counter electrode not shown in the figure and provided on the 2 nd substrate.

The storage line STL is formed adjacent to the gate line GL in parallel, where a portion where the storage line STL and the pixel electrode ITO overlap forms a storage capacitor Cstg. In fig. 14, the width of the storage line STL for forming the storage capacitor Cstg is enlarged within the pixel, and such enlargement is not necessarily required, and the storage line STL may be formed in a straight line according to the characteristics of a dielectric (insulating layer) between the storage line STL and the pixel electrode ITO.

The storage capacitor Cstg is not limited to the illustrated portion, and may be formed so that the storage line passes through the center of the pixel in a device that does not require consideration of the aperture ratio required for a transmissive liquid crystal display device, such as a reflective, partially transmissive, or semi-transmissive liquid crystal display device. The storage line STL is formed in the arrangement as described above with reference to fig. 1 to 13. In fig. 14, the semiconductor layer SI and the like are not illustrated.

Fig. 15 is a sectional view of the 1 st substrate taken along line a-a' of fig. 14. The same reference numerals as in fig. 14 correspond to the same functional parts. In the drawing, SUB1 is a 1 st substrate, and on this 1 st substrate SUB1, a gate electrode G and a storage line STL extending from a gate line are formed. The gate electrode G and the storage line STL are covered with a gate line insulating layer GI (e.g., SiN), and a thin film transistor TFT composed of a semiconductor layer SI, a drain electrode SD1, and a source electrode SD2 is formed on the gate electrode G. In addition, the surfaces of the gate electrode G including the gate line and the storage line STL have an oxide film AO formed through anodic oxidation. The semiconductor layer SI may be amorphous silicon (a-SI) or polycrystalline silicon (p-SI), and a structure of a thin film transistor is assumed according to its characteristics.

On the gate line insulating layer GI including the thin film transistor TFT, there is a passivation layer PAS on the entire pixel region, and a pixel electrode ITO is formed on the passivation layer PAS. This structure is a so-called transmissive liquid crystal display device, and a transparent conductive film is used as a pixel electrode. The pixel electrode ITO is connected to the source electrode SD2 through a via hole formed in the passivation layer PAS. In addition, the pixel electrode ITO extends on the storage line STL to form a storage capacitor Cstg together with the storage line STL.

Fig. 16 is a cross-sectional view of the 1 st substrate taken along the line a-a' in fig. 14 when the present invention is applied to a liquid crystal display device having another structure. The same reference numerals as in fig. 15 correspond to the same functional portions. In fig. 16, the passivation layer PAS and the via hole are not formed in the pixel region. The other constitution and effect are the same as those of fig. 15.

Fig. 17 is a schematic plan view illustrating another configuration example of the vicinity of one pixel of the 1 st substrate of the liquid crystal display device of the present invention. In fig. 17, illustration of the semiconductor layer SI and the like is also omitted. Fig. 18 is a cross-sectional view of the 1 st substrate taken along line a-a' of fig. 17. In the structure illustrated in fig. 14 to 16, the passivation layer PAS covering the gate line insulating layer GI is the 1 st passivation layer PAS1, and the reflective electrode RF is formed on the pixel electrode through the 2 nd passivation layer PAS 2. In addition, the 2 nd passivation layer PAS2 may not be present.

The reflective electrode RF is preferably a metal thin film, and a portion of the pixel region is removed together with the underlying 2 nd passivation layer PAS2 to form an opening TP on the reflective electrode RF. When the liquid crystal display device operates as a transmission type, light (external light or so-called front light) from the back surface side of the 1 st substrate SUB1 is reflected by the reflective electrode RF and emitted to the 2 nd substrate side to display an image.

When the substrate works as a transmission type and a reflection type, light from the back side of the 1 st substrate SUB1 is reflected by the opening TP of the reflection electrode RF and emitted to the 2 nd substrate side, and light incident from the 2 nd substrate side is reflected by the reflection electrode RF and emitted in the 2 nd substrate direction.

As shown in fig. 17 and 18, the reflective electrode RF has a slit S between the reflective electrode of the adjacent pixel and the storage line STL. There is also a slit S on the drain line DL and between the reflective electrodes of the adjacent pixels. With this arrangement, light leakage from the backlight at the interface between adjacent pixels in transmissive display can be prevented, and good contrast can be obtained.

FIG. 19 is a cross-sectional view of a 1 st substrate taken along the line A-A' in FIG. 17, when the present invention is applied to a liquid crystal display device having another structure. The same reference numerals as in fig. 17 correspond to the same functions. In fig. 19, in the pixel region, the passivation layer PAS is not present, and the pixel electrode ITO is formed adhered on the 1 st substrate SUB 1. The passivation layer PAS formed under the reflective electrode RF is removed at the pixel region. The other structures and effects are the same as those of fig. 17 and 18 except that the passivation layer PAS2 is not present.

In addition to the liquid crystal display devices of the various forms described above, a reflective liquid crystal display device can be produced by using a reflective electrode RF formed of a metal thin film or the like instead of the pixel electrode ITO formed of a transparent conductive film in fig. 14 to 16. In addition, a transflective liquid crystal display device may be configured by forming pixel electrodes with semitransparent reflective electrodes. The present invention is not limited to the relatively small liquid crystal display device used in the portable terminal described above, and may be applied to a liquid crystal display device used as a display screen for a notebook computer or other monitor. The present invention is not limited to the liquid crystal display device, and can be applied to other types of display devices such as an organic EL display.

As described in detail in the above embodiments, according to the present invention, a pattern in which the gate line wiring pattern and the storage line wiring pattern do not overlap and the wirings do not cross can be formed. Thus, even when the storage lines are divided into upper and lower groups in the display area, a display device can be provided which can reduce the luminance difference in the entire display area and obtain high-quality display.

Claims (24)

1. A display device, characterized in that: has the advantages of

A substrate;

a plurality of pixels arranged in a matrix in the display region and having a storage capacitor;

a plurality of gate lines arranged in the display region;

a plurality of data lines disposed in the display region and intersecting the plurality of gate lines;

a plurality of storage lines arranged in the display region and supplying power to the storage capacitors,

wherein,

the substrate has a 1 st side having a plurality of connection terminals connected to an external circuit, a 2 nd side and a 3 rd side adjacent to the 1 st side and facing each other with the display region interposed therebetween,

the plurality of gate lines include a 1 st gate line, a 2 nd gate line disposed at a position closer to the 1 st side than the 1 st gate line, a 3 rd gate line disposed at a position closer to the 1 st side than the 2 nd gate line, a 4 th gate line disposed at a position closer to the 1 st side than the 3 rd gate line, and a 5 th gate line disposed at a position closer to the 1 st side than the 4 th gate line,

the 1 st, 3 rd and 5 th gate lines are respectively led to the 1 st direction through the 1 st, 3 rd and 5 th gate line lead wires arranged at the 2 nd side,

the 2 nd and 4 th gate lines are respectively led to the 1 st direction through the 2 nd and 4 th gate line lead wires arranged at the 3 rd side,

the plurality of storage lines have a 1 st storage line disposed between the 1 st gate line and the 2 nd gate line, a 2 nd storage line disposed between the 2 nd gate line and the 3 rd gate line, a 3 rd storage line disposed between the 3 rd gate line and the 4 th gate line, and a 4 th storage line disposed between the 4 th gate line and the 5 th gate line,

the 1 st storage line and the 2 nd storage line are connected to each other by a 1 st common line designed at the 2 nd side,

the 2 nd storage line and the 3 rd storage line are connected to each other by a 2 nd common line designed at the 3 rd side,

the 3 rd storage line and the 4 th storage line are connected to each other by a 3 rd common line designed at the 2 nd side.

2. The display device of claim 1, wherein:

the 1 st common line and the 3 rd common line are electrically connected by a 1 st bridge line provided on a layer different from a layer on which the 1 st and 3 rd common lines are provided.

3. The display device of claim 2, wherein:

the 1 st bridge winding is designed on the 2 nd side.

4. A display device as claimed in claim 3, characterized in that:

the gate lines have a 6 th gate line disposed at a position closer to the 1 st edge than the 5 th gate line,

the 6 th gate line is led to the 1 st direction through the 6 th gate line lead wiring designed at the 3 rd side,

the plurality of storage lines have a 5 th storage line disposed between the 5 th gate line and the 6 th gate line,

the 4 th storage line and the 5 th storage line are connected to each other by a 4 th common line designed at the 3 rd side.

5. The display device of claim 4, wherein:

the 2 nd common line and the 4 th common line are electrically connected by a 2 nd bridge line designed on a layer different from a layer in which the 2 nd and 4 th common lines are designed.

6. The display device of claim 5, wherein:

the 2 nd bridge is designed on the 3 rd side.

7. The display device of claim 1, wherein:

the 1 st common line and the 3 rd common line are disposed between the display region and the 1 st gate line lead line,

the 2 nd common line is disposed between the display region and the 2 nd gate line lead line.

8. The display device of claim 1, wherein:

at least one driving circuit is disposed on the 1 st side.

9. The display device according to any one of claims 1 to 8, wherein:

the plurality of connection terminals have power supply pads for applying a voltage to the storage lines.

10. The display device according to any one of claims 1 to 8, wherein:

the plurality of gate lines and the plurality of storage lines are formed on the same layer with the same material.

11. The display device according to any one of claims 1 to 8, wherein:

the 1 st gate line and the 2 nd gate line are gate lines adjacent to each other,

the 2 nd gate line and the 3 rd gate line are gate lines adjacent to each other,

the above-mentioned 3 rd gate line and the above-mentioned 4 th gate line are gate lines adjacent to each other,

the 4 th gate line and the 5 th gate line are gate lines adjacent to each other.

12. The display device according to any one of claims 1 to 8, wherein: has the advantages of

A counter substrate facing the substrate, and a liquid crystal layer interposed between the substrate and the counter substrate.

13. The display device according to claim 12, wherein:

the substrate has a pixel electrode formed thereon,

the counter substrate has a counter electrode,

the liquid crystal layer applies an electric field through the pixel electrode and the counter electrode.

14. A liquid crystal display device, characterized in that: has the advantages of

A 1 st substrate with a pixel electrode;

a 2 nd substrate having a counter electrode and facing the 1 st substrate;

a liquid crystal layer interposed between the 1 st substrate and the 2 nd substrate and applying an electric field to the liquid crystal layer through the pixel electrode and the counter electrode;

a plurality of pixels arranged in the display region in a matrix and having a storage capacitor;

a plurality of gate lines arranged in the display region;

a plurality of data lines disposed in the display region and intersecting the plurality of gate lines;

a plurality of storage lines arranged in the display region and supplying power to the storage capacitors,

wherein,

the 1 st substrate has a 1 st side having a plurality of connection terminals connected to an external circuit, a 2 nd side and a 3 rd side adjacent to the 1 st side and facing each other with the display region interposed therebetween,

the plurality of gate lines include a 1 st gate line, a 2 nd gate line disposed at a position closer to the 1 st side than the 1 st gate line, a 3 rd gate line disposed at a position closer to the 1 st side than the 2 nd gate line, a 4 th gate line disposed at a position closer to the 1 st side than the 3 rd gate line, and a 5 th gate line disposed at a position closer to the 1 st side than the 4 th gate line,

the 1 st, 3 rd and 5 th gate lines are respectively led to the 1 st direction through the 1 st, 3 rd and 5 th gate line lead wires arranged at the 2 nd side,

the 2 nd and 4 th gate lines are respectively led to the 1 st direction through the 2 nd and 4 th gate line lead wires arranged at the 3 rd side,

the plurality of storage lines have a 1 st storage line disposed between the 1 st gate line and the 2 nd gate line, a 2 nd storage line disposed between the 2 nd gate line and the 3 rd gate line, a 3 rd storage line disposed between the 3 rd gate line and the 4 th gate line, and a 4 th storage line disposed between the 4 th gate line and the 5 th gate line,

the 1 st storage line and the 2 nd storage line are connected to each other by a 1 st common line designed at the 2 nd side,

the 2 nd storage line and the 3 rd storage line are connected to each other by a 2 nd common line designed at the 3 rd side,

the 3 rd storage line and the 4 th storage line are connected to each other by a 3 rd common line designed at the 2 nd side.

15. The liquid crystal display device according to claim 14, wherein:

the 1 st common line and the 3 rd common line are electrically connected by a 1 st bridge line provided on a layer different from a layer on which the 1 st and 3 rd common lines are provided.

16. The liquid crystal display device according to claim 15, wherein:

the 1 st bridge winding is designed on the 2 nd side.

17. The liquid crystal display device according to claim 16, wherein:

the gate lines have a 6 th gate line disposed at a position closer to the 1 st edge than the 5 th gate line,

the 6 th gate line is led to the 1 st direction through the 6 th gate line lead wiring designed at the 3 rd side,

the plurality of storage lines have a 5 th storage line disposed between the 5 th gate line and the 6 th gate line,

the 4 th storage line and the 5 th storage line are connected to each other by a 4 th common line designed at the 3 rd side.

18. The liquid crystal display device according to claim 17, wherein:

the 2 nd common line and the 4 th common line are electrically connected by a 2 nd bridge line designed on a layer different from a layer in which the 2 nd and 4 th common lines are designed.

19. The liquid crystal display device according to claim 18, wherein:

the 2 nd bridge is designed on the 3 rd side.

20. The liquid crystal display device according to claim 14, wherein:

the 1 st common line and the 3 rd common line are disposed between the display region and the 1 st gate line lead line,

the 2 nd common line is disposed between the display region and the 2 nd gate line lead line.

21. The liquid crystal display device according to claim 14, wherein:

at least one driving circuit is disposed on the 1 st side.

22. The liquid crystal display device according to any one of claims 14 to 21, wherein:

the plurality of connection terminals have power supply pads for applying a voltage to the storage lines.

23. The liquid crystal display device according to any one of claims 14 to 21, wherein:

the plurality of gate lines and the plurality of storage lines are formed on the same layer with the same material.

24. The liquid crystal display device according to any one of claims 14 to 21, wherein:

the 1 st gate line and the 2 nd gate line are gate lines adjacent to each other,

the 2 nd gate line and the 3 rd gate line are gate lines adjacent to each other,

the above-mentioned 3 rd gate line and the above-mentioned 4 th gate line are gate lines adjacent to each other,

the 4 th gate line and the 5 th gate line are gate lines adjacent to each other.

Images