CN1879054A

CN1879054A - Thin film transistor array panel and method of manufacturing the same

Info

Publication number: CN1879054A
Application number: CNA2004800332711A
Authority: CN
Inventors: 金湘甲; 李帝珉; 赵宽英; 郑钟台; 宋仁虎; 崔熙焕; 姜圣哲; 妻镐民; 崔凡洛; 崔埈厚
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2003-09-18
Filing date: 2004-09-16
Publication date: 2006-12-13
Anticipated expiration: 2024-09-16
Also published as: CN100590499C; KR20050028531A

Abstract

The present invention relates to a thin film transistor array panel, a liquid crystal display, and a manufacturing method of the same. A TFT array for a LCD or an EL display is used as a circuit board for driving the respective pixels in an independent manner. The present invention provides pixel electrodes and contact assistants, which connect expansions of gate lines and data lines to an external circuit, having a structure of double layers including IZO layer and ITO layer. The ITO layer is disposed on the IZO layer. In the present invention, the pixel electrodes are formed to have double layers of IZO layer and ITO layer to avoid wires from getting damage by the ITO etchant and to prevent prove pins from having accumulation of foreign body during the gross test. In the present invention, the contact assistants may only be formed to have double layers of IZO layer and ITO layer to prevent prove pins from having accumulation of foreign body during the gross test. Since the consumption of ITO is reduced, manufacturing cost decreases.

Description

Thin-film transistor display panel and manufacture method thereof

Technical field

The present invention relates to a kind of cloth wire structures, have the thin-film transistor display panel and the manufacture method thereof of this wire structures.

Background technology

Usually, be used for thin film transistor (TFT) (" the TFT ") arraying bread board of LCD (" LCD ") or electroluminescence (" EL ") display as the circuit board that drives each pixel with independent mode.The tft array panel comprise the scan signal line that transmits sweep signal or gate line, the image signal line or the data line of transmitted image signal, the TFT that is connected to gate line and data line, the pixel electrode that is connected to TFT, covering gate polar curve with the gate insulator of insulation, cover TFT and data line passivation layer with insulation.TFT comprises as the gate electrode of a gate line part, forms the semiconductor of raceway groove, as source electrode and drain electrode, gate insulator and the passivation layer of a data line part.TFT is used to respond the on-off element that picture signal is sent to pixel electrode from data line from the sweep signal of gate line.

The tft array panel has been widely used for LCD.LCD uses arbitrary source.Especially, transmission-type LCD and transmission-reflection (trans-reflection) type LCD have the pixel electrode of being made by conductive material such as the tin indium oxide (ITO) and the indium zinc oxide (IZO) of transmissive (transmittable).

ITO and IZO have shortcoming.

ITO needs strong acid as etchant.Strong etchant may pollute (smear) and corrosion data line or gate line by the pin hole of insulation course.

IZO does not have such problem, but its easy tested probe is delineated and glued thereon.These characteristics of IZO are owing to the contact resistance that has increased test probe has been upset overall test (gross test), and this test was carried out before drive IC is installed.

Summary of the invention

Target of the present invention provides a kind of thin-film transistor display panel that does not have this problem.

The invention provides the pixel electrode that forms by the bilayer that comprises IZO and ITO, or it is auxiliary to be connected to contacting of external circuit by the expansion gate line and data line that the bilayer that comprises IZO and ITO forms.

Description of drawings

Fig. 1 is the layout according to the tft array panel that is used for LCD of the embodiment of the invention;

Fig. 2 is the sectional view that tft array panel II-II along the line shown in Figure 1 is got;

Fig. 3 A, 4A, 5A and 6A show the layout of manufacturing according to the intermediate steps of the manufacture method of the tft array panel that is used for LCD of the embodiment of the invention successively;

Fig. 3 B is the sectional view that the tft array panel IIIb-IIIb ' along the line shown in Fig. 3 A is got;

Fig. 4 B is the sectional view that the tft array panel IVb-IVb ' along the line shown in Fig. 4 A is got in the step after the step shown in Fig. 3 B;

Fig. 5 B is the sectional view that the tft array panel Vb-Vb ' along the line shown in Fig. 5 A is got in the step after the step shown in Fig. 4 B;

Fig. 6 B is the sectional view that the tft array panel VIb-VIb ' along the line shown in Fig. 6 A is got in the step after the step shown in Fig. 5 B;

Fig. 7 is the layout that is used for the tft array panel of LCD according to another embodiment of the present invention;

Fig. 8 and 9 is respectively the sectional view that tft array panel VIII-VIII ' along the line shown in Figure 7 and line IX-IX ' are got;

Figure 10 A is the layout of the tft array panel shown in Fig. 7 to 9 in according to the first step of the manufacture method of the embodiment of the invention;

Figure 10 B and 10C are respectively the sectional views that tft array panel Xb-Xb ' along the line shown in Figure 10 A and line Xc-Xc ' are got;

Figure 11 A and 11B are respectively the sectional views that the tft array panel Xb-Xb ' along the line shown in Figure 10 A and line Xc-Xc ' are got in the step after the step shown in Figure 10 B and the 10C;

Figure 12 A is the layout of tft array panel in the step after the step shown in Figure 11 A and the 11B;

Figure 12 B and 12C are respectively the sectional views that tft array panel XIIb-XIIb ' along the line shown in Figure 12 A and line XIIc-XIIc ' are got;

Figure 13 A, 14A and 15A and Figure 13 B, 14B and 15B are respectively the sectional views that tft array panel XIIb-XIIb ' along the line shown in Figure 12 A and line XIIc-XIIc ' are got, and illustrate the step afterwards of the step shown in Figure 12 B and the 12C successively;

Figure 16 A and 16B are the sectional views of tft array panel in the step after the step shown in Figure 15 A and the 15B;

Figure 17 A is the sectional view of tft array panel in the step after the step shown in Figure 16 A and the 16B;

Figure 17 B and 17C are respectively the sectional views that tft array panel XVIIb-XVIIb ' along the line shown in Figure 17 A and line XVIIc-XVIIc ' are got;

Figure 18 is the layout that is used for the tft array panel of LCD according to another embodiment of the present invention;

Figure 19 is the sectional view that the tft array panel XIX-XIX ' along the line of Figure 18 is got;

Figure 20 A is the layout according to the tft array panel of manufacture method in its first step of the embodiment of the invention;

Figure 20 B is the sectional view that the tft array panel XXb-XXb ' along the line shown in Figure 20 A is got;

Figure 21 A is the layout of the tft array panel in the step after the step shown in Figure 20 A;

Figure 21 B is the sectional view that the tft array panel XXIb-XXIb ' along the line shown in Figure 21 A is got;

Figure 22 A is the layout of the tft array panel in the step afterwards of the step shown in Figure 21 A;

Figure 22 B is the sectional view that the tft array panel XXIIb-XXIIb ' along the line shown in Figure 22 A is got;

Figure 23 A is the layout of the tft array panel in the step after the step shown in Figure 22 A;

Figure 23 B is the sectional view that the tft array panel XXIIIb-XXIIIb ' along the line shown in Figure 23 A is got;

Figure 24 A is the layout of the tft array panel in the step after the step shown in Figure 23 A;

Figure 24 B is the sectional view that the tft array panel XXIVb-XXIVb ' along the line shown in Figure 24 A is got;

Figure 25 is the layout that is used for the tft array panel of LCD according to another embodiment of the present invention;

Figure 26 and 27 is sectional views that tft array panel XXVI-XXVI ' along the line shown in Figure 25 and line XXVII-XXVII ' are got;

Figure 28 A is the layout according to the tft array panel in the first step of its manufacture method of fourth embodiment of the invention;

Figure 28 B and 28C are respectively the sectional views that tft array panel XXVIIIb-XXVIIIb ' along the line shown in Figure 28 A and line XXVIIIc-XXVIIIc ' are got;

Figure 29 A and 29B are respectively the sectional views that the tft array panel XXVIIIb-XXVIIIb ' along the line shown in Figure 28 A and line XXVIIIc-XXVIIIc ' are got in the step after the step shown in Figure 28 B and the 28C;

Figure 30 A is the layout of tft array panel in the step after the step shown in Figure 29 A and the 29B;

Figure 30 B and 30C are respectively the sectional views that tft array panel XXXb-XXXb ' along the line shown in Figure 30 A and line XXXc-XXXc ' are got;

Figure 31 A, 32A and 33A and Figure 31 B, 32B and 33B are respectively the sectional views that tft array panel XXXb-XXXb ' along the line shown in Figure 30 A and line XXXc-XXXc ' are got, and illustrate the described step of Figure 30 B and 30C step afterwards successively;

Figure 34 A is the sectional view of tft array panel in the step after the step shown in Figure 33 A and the 33B;

Figure 34 B and 34C are respectively the sectional views that tft array panel XXXIVb-XXXIVb ' along the line shown in Figure 34 A and line XXXIVc-XXXIVc ' are got;

Figure 35 A is the sectional view of the tft array panel in the step after the step shown in Figure 33 A-33C;

Figure 35 B and 35C are respectively the sectional views that tft array panel XXXVb-XXXVb ' along the line shown in Figure 35 A and line XXXVc-XXXVc ' are got;

Figure 36 is the layout that is used for the tft array panel of LCD according to another embodiment of the present invention;

Figure 37 is the sectional view that tft array panel XXXVII-XXXVII ' along the line shown in Figure 36 is got;

Figure 38 A, 39A, 40A and 41A are the layouts that illustrates the intermediate steps of the tft array method for producing panel shown in Figure 36 and 37 successively;

Figure 38 B is the sectional view that the tft array panel XXXVIIIb-XXXVIIIb ' along the line shown in Figure 38 A is got;

Figure 39 B is the sectional view that the tft array panel XXXIXb-XXXIXb ' along the line shown in Figure 39 A is got in the step after the step shown in Figure 38 B;

Figure 40 B is the sectional view that the tft array panel XLb-XLb ' along the line shown in Figure 40 A is got in the step after the step shown in Figure 39 B;

Figure 41 B is the sectional view that the tft array panel XLIb-XLIb ' along the line shown in Figure 41 A is got in the step after the step shown in Figure 40 B;

Figure 42 is the sectional view that the tft array panel XLIb-XLIb ' along the line shown in Figure 41 A is got in the step after the step shown in Figure 41 B;

Figure 43 is the sectional view that uses the LCD XLIb-XLIb ' along the line of the tft array panel shown in Figure 41 A to be got in the step after step shown in Figure 42;

Figure 44 is the sectional view that uses the LCD XLIb-XLIb ' along the line of the tft array panel shown in Figure 41 A to be got in the step after step shown in Figure 43;

Figure 45 is the layout that is used to make the shadow mask of LCD shown in Figure 44;

Figure 46 is the layout that is used for the tft array panel of electroluminescence (" EL ") display according to the embodiment of the invention;

Figure 47 and 48 is respectively the sectional view of the tft array panel got of XLVIIb-XLVIIb ' along the line shown in Figure 46 and line XLVIII-XLVIII ';

Figure 49 and 50 is respectively the sectional view of the tft array panel got of XLI-XLI ' along the line shown in Figure 46 and line L-L ';

Figure 51,53,55,57,59 and 61 is the layouts of intermediate steps that illustrate the manufacture method of the tft array panel shown in Figure 46 to 50 successively;

Figure 52 A, 52B and 52C are respectively the sectional views that tft array panel LIIa-LIIa ', LIIb-LIIb ' and the LIIc-LIIc ' along the line shown in Figure 51 got;

Figure 54 A, 54B and 54C are respectively the sectional views that tft array panel LIVa-LIVa ', LIVb-LIVb ' and the LIVc-LIVc ' along the line shown in Figure 53 got;

Figure 56 A, 56B, 56C and 56D are respectively the sectional views that tft array panel LVIa-LVIa ', LVIb-LVIb ', LVIc-LVIc ' and the LVId-LVId ' along the line shown in Figure 55 got;

Figure 58 A, 58B, 58C and 58D are respectively the sectional views that tft array panel LVIIIa-LVIIIa ', LVIIIb-LVIIIb ', LVIIIc-LVIIIc ' and the LVIIId-LVIIId ' along the line shown in Figure 57 got;

Figure 60 A, 60B, 60C and 60D are respectively the sectional views that tft array panel LXa-LXa ', LXb-LXb ', LXc-LXc ' and the LXd-LXd ' along the line shown in Figure 59 got;

Figure 62 A and 62B are respectively the sectional views that tft array panel LXIIa-LXIIa ' along the line shown in Figure 61 and line LXIIb-LXIIb ' are got;

Figure 63 is the layout that is used for the tft array panel of electroluminescence (" EL ") display according to another embodiment of the present invention;

Figure 64 and 65 is respectively the sectional view that tft array panel LXIV-LXIV ' along the line shown in Figure 63 and line LXV-LXV ' are got;

Figure 66 and 67 is respectively the sectional view that tft array panel LXVI-LXVI ' along the line shown in Figure 63 and line LXVII-LXVII ' are got;

Figure 68 is the layout that uses the tft array panel of polysilicon according to the embodiment of the invention;

Figure 69,70 and 71 is respectively the sectional view that tft array panel LXIX-LXIX ', LXX-LXX ' and the LXXI-LXXI ' along the line shown in Figure 68 got;

Reference number explanation among the figure

110: dielectric substrate 124: gate electrode

131: storage electrode line 140: gate insulator

150: amorphous silicon layer 160: doped amorphous silicon layer

170: conductive layer 173: the source electrode

175: drain electrode 177: the storage conductor

180: passivation layer 182,85,187,189: contact hole

901: pixel electrode 906,908: contact is auxiliary

Embodiment

With reference to the accompanying drawing that wherein shows the preferred embodiment of the present invention, the preferred embodiments of the present invention are described more fully hereinafter.Yet form that the present invention can be much different realizes and should not be construed as the embodiment that is limited to here to be set forth.On the contrary, for those skilled in the art, provide these embodiment to make that the disclosure is comprehensive and complete, and passed on scope of the present invention fully.

For clear, exaggerated the thickness in layer, film and zone in the accompanying drawings.All similar reference numbers are represented similar element.Be understandable that when the element such as layer, film, zone or substrate be called as another element " on " time, it can be directly on other element or can have intermediary element.

Now with reference to accompanying drawing, describe tft array panel and manufacture method thereof in detail, so that those of ordinary skills implement according to the embodiment of the invention.

As shown in fig. 1, the tft array panel according to embodiment comprises thin film transistor (TFT), pixel electrode, is arranged on the signal wire of viewing area and is arranged on the expansion of the signal wire of frontier district.

Fig. 1 is the layout according to the tft array panel that is used for LCD of the embodiment of the invention, and Fig. 2 is the sectional view that tft array panel II-II along the line shown in Figure 1 is got.

Many the gate lines 121 that are used to transmit signal are formed on dielectric substrate 110.

Every gate line 121 comprise a plurality of downward protrusions with the part that forms a plurality of gate electrodes 124 with have the large-area expansion 125 that is used to contact another layer or external devices.The major part of gate line 121 is arranged on the viewing area, and the expansion 125 of gate line 121 is arranged on the frontier district of viewing area.

Gate line 121 comprises two films with different physical characteristicss, following film 121p and last film 121q.In order to reduce signal delay or the pressure drop in the gate line 121, last film 121q is preferably by comprising that the low resistivity metal that contains the Al metal such as Al and Al alloy makes.On the other hand, following film 121p is preferably by such as Cr, Mo, make such as the material of Mo alloy, Ta and the Ti of MoW, and these materials have and good physics, chemistry and contact characteristics such as other material of tin indium oxide (ITO) and indium zinc oxide (IZO).The good example of the combination of following film 121p and last film 121q is Cr layer and Al-Nd alloy-layer.In Fig. 2, the following film of gate electrode 124, go up film and represent by

reference number

124p and 124q respectively, and the following film of expansion 125, go up film and represent by

reference number

125p and 125q respectively.

In addition, the surface tilt of the relative substrate 110 in side of

film

121q and 121p, and the scope at its inclination angle up and down is about 30-80 degree.

Preferably the gate insulator of being made by silicon nitride (SiNx) 140 is formed on the gate line 121.

Preferably a plurality of semiconductors 150 of being made by amorphous silicon hydride (being abbreviated as " a-Si ") are formed on the gate insulator 140.Each semiconductor 150 is arranged on the gate electrode 124, and the frontier district of covering grid electrode 124 and gate electrode 124.

Preferably a plurality of

Ohmic contact island

163 and 165 that has the n+ hydrogenation a-Si of n type impurity to make by silicide or heavy doping is formed on the semiconductor island 150.

Ohmic contact island

163 and 165 is arranged on the semiconductor island 150 in couples.

The surface tilt of relative with 165 the side substrate 110 of semiconductor striped 151 with Ohmic contact 163, and its pitch angle is preferably in the scope between the 30-80 degree.

Many data lines 171 and a plurality of drain electrode 175 be formed on

Ohmic contact

163 and 165 and gate insulator 140 on.

The data line 171 that is used to transmit data voltage extends substantially in the vertical and intersects with gate line 121.Every data line 171 comprises having than large tracts of land and is used for the expansion 179 that contacts with other layer or external devices.The major part of data line 171 is arranged on the viewing area, but expansion 179 is arranged on the borderline region.

A plurality of branches of every the data line 171 that protrudes to drain electrode 175 form multiple source electrode 173.The every pair of source electrode 173 and drain electrode 175 are separated from one another, and about gate electrode 124 toward each other.Gate electrode 124, source electrode 173 and drain electrode 175 and semiconductor island 150 form TFT, and this TFT has the raceway groove that is formed in the semiconductor island 150 that is arranged between source electrode 173 and the drain electrode 175.

Data line 171 and drain electrode 175 comprise following film 171p and the 175p that is preferably made by Mo, Mo alloy and Cr, and disposed thereon and preferably by containing the Al metal or containing metal film 171q of going up of Ag and 175q.The expansion 179 of data line 171 also comprises film 179q and following film 179p.

Similar gate line 121, last film 171q, the 175q of data line 171 and drain electrode 175 has the tapered side on relative substrate 110 surfaces with following

film

171q, 175q, and the scope at its pitch angle is about 30-80 degree.

Ohmic contact

163 and 165 are inserted between following semiconductor 150 and the top source electrode 173 and between the drain electrode above the electrode of source 175 and reduce therebetween contact resistance.Semiconductor 150 comprises not the expose portion that is covered by source electrode 173 and drain electrode 175.

Passivation layer 180 is formed on data line 171 and the drain electrode 175 and on the expose portion of semiconductor 150.Passivation layer 180 is preferred by the photosensitive organic material with good flat characteristic, by making such as the low dielectric insulation material of a-Si:C:O and a-Si:O:F or such as the inorganic material of silicon nitride and monox that plasma enhanced CVD (PECVD) forms.

Passivation layer 180 has a plurality of

contact holes

185 and 189 of the expansion 179 that exposes drain electrode 175 and data line 171 respectively.Passivation layer 180 and gate insulator 140 have a plurality of contact holes 182 of the expansion 125 that exposes gate line 121.

A plurality of pixel electrodes 901

assist

906 and 908 to be formed on the passivation layer 180 with a plurality of the contact.

Pixel electrode 901 has the bilayer of following film 901p and last film 901q.Here, following film 901p is made by IZO, and last film 901q is made by ITO.

Pixel electrode 901 is by contact hole 185 physical connections and be electrically connected to drain electrode 175, makes pixel electrode 901 receive data voltage from drain electrode 175.

The pixel electrode 901 that provides data voltage produces electric field with the common electrode (not shown) on another panel (not shown), and this electric field redirects the liquid crystal molecule that is arranged in the liquid crystal layer therebetween (not shown).

Pixel electrode 901 and common electrode form liquid crystal capacitor, and it stores the voltage that is applied after TFT closes.The building-out condenser that is called " holding capacitor " that is parallel to liquid crystal capacitor can be provided, be used to improve the store voltages ability.

Contact auxiliary 906 and 908 is connected to the expansion 179 of the exposure of the expansion 125 of exposure of gate line 121 and data line 171 respectively by contact hole 182 and 189.The auxiliary 906 and 908

protection expansions

125 and 179 of contact, and

additional expansion

125 and 179 and external devices between adhesion.The auxiliary 906 and 908 optional elements of contact.So they can save.

Contact auxiliary 906 and 908 has following

film

906p and 908p and goes up the bilayer of film 906q and 908q.Here, following

film

906p and 908p are made by IZO, and

last film

906q and 908q are made by ITO.

Here,

IZO layer

901p, 906p and 908p have at 500  to the thickness between 1500 , and

ITO layer

901q, 906q and 908q have at 50  to the thickness between 250 .Especially,

IZO layer

901p, 906p and 908p preferably have the thickness of 900 , and

ITO layer

901q, 906q and 908q have the thickness of 200 .

By considering such as the process conditions of etching period, the ITO layer can not be destroyed by probe during overall test condition, the ability of deposition apparatus and the thickness that light transmission determines IZO layer and ITO layer.

About etching period, approximately to spend 130 seconds by the ITO layer of ITO etchant etching 400 , and approximately will spend 45 seconds by the IZO layer of IZO etchant etching 900 .Approximately to spend 60 seconds by the IZO layer of IZO etchant etching 900  and the ITO layer of 200 .Etching period is elongated with the thickness thickening of IZO layer and ITO layer.When the thickness of ITO exceeded certain value, the ITO layer was not by the IZO etchant etching.When IZO layer and ITO layer had excessive thickness, light transmission descended.When etching and transmittance were all considered, preferred IZO layer had the following thickness of 1500 , and the ITO layer has the following thickness of 250 .

Secondly, the ITO layer preferably has the thickness that exceeds a certain value and is destroyed by probe during overall test avoiding.The deposition apparatus of ITO layer has the restriction of deposit ability.When considering these things, preferred ITO layer has the thickness that exceeds 50 .When the resistance of considered pixel electrode, the IZO layer preferably has the thickness that surpasses 500 .

Now describe the manufacture method of tft array panel in detail to 6B and Fig. 1 and 2 with reference to Fig. 3 A.

Fig. 3 A, 4A, 5A and 6A illustrate the layout of manufacturing according to the intermediate steps of the manufacture method of the tft array panel that is used for LCD of the embodiment of the invention successively.Fig. 3 B is the sectional view that the tft array panel IIIb-IIIb ' along the line shown in Fig. 3 A is got.Fig. 4 B is the sectional view that the tft array panel IVb-IVb ' along the line shown in Fig. 4 A is got in the step after the step shown in Fig. 3 B.Fig. 5 B is the sectional view that the tft array panel Vb-Vb ' along the line shown in Fig. 5 A is got in the step after the step shown in Fig. 4 B.Fig. 6 B is the sectional view that the tft array panel VIb-VIb ' along the line shown in Fig. 6 A is got in the step after the step shown in Fig. 5 B.

Two conducting films, i.e. lower conductive film and upper conductive film sputter on such as the dielectric substrate 110 of clear glass successively.The thickness of about 2500  is preferably made and preferably had to upper conductive film by aluminiferous metals.The Al-Nd target preferably includes the Nd of 2atm%.

With reference to Fig. 3 A and 3B, use photoresist pattern successively to upper conductive film and lower conductive film composition, comprises many gate lines 121 of a plurality of gate electrodes 124 by photoetching with formation.

With reference to Fig. 4 A and 4B, after deposit gate insulator 140, intrinsic a-Si layer and doping a-Si layer successively, doping a-Si layer and intrinsic a-Si layer by photoetching to form a plurality of doped semiconductors 160 and a plurality of intrinsic semiconductor 150.Gate insulator 140 is preferably made to the silicon nitride of the thickness of 5000  by having about 2000 , and deposition temperature is preferably in the scope between about 250 ℃ and about 500 ℃.

With reference to Fig. 5 A and 5B, two conducting films of sputter successively: lower conductive film and upper conductive film.Lower conductive film is preferably by the thickness of making and preferably having about 500  such as the metal of Cr, Mo and Mo alloy.Upper conductive film preferably has the thickness of about 2500 .The target that is used for film is preferably made by Al or the Al-Nd that contains the Nd of 2atomic%.Preferably about 150 ℃ of sputter temperature.

Then, the upper and lower conducting film of etching comprises many data lines 171 of multiple source electrode 173 and a plurality of drain electrode 175 with formation.At this moment, last film and following film can perhaps be gone up film and be descended film by the dry etching etching by the wet etching etching by wet etching etching simultaneously.When film 171p is made by Mo or Mo alloy instantly, it can be under etching condition with on film 171q etching.

Then, do not removed to finish also expose portion intrinsic semiconductor 150 of a plurality of

Ohmic contact

163 and 165 by etching by the part of the doped semiconductor 160 of data line 171 and drain electrode 175 coverings.For the exposed surface of stabilization of semiconductor 150, can carry out oxygen plasma treatment subsequently.

With reference to Fig. 6 A and 6B, deposit passivation layer 180 and with gate insulator 140 dry etchings to form a plurality of contact holes 182,185 and 189.Gate insulator 140 and passivation layer 180 be etching under the etching condition that has with gate insulator 140 and passivation layer 180 essentially identical rate of etch preferably.

At last, as illustrated in fig. 1 and 2,, form a plurality of pixel electrodes 901 that comprise bilayer and contact auxiliary 906 and 908 with a plurality of by sputter and photoetching IZO layer and ITO layer.

Here, the IZO etchant is used for etching IZO layer and ITO layer.The IZO etchant comprises HCL, CH ₃COOH, deionized water and surfactant.In order to prevent on by contact hole 182,185 and 189 metal levels 125,175 that expose and 179 parts, to form metal oxide, at N ₂Be used for the preheating of deposit IZO layer and ITO layer in the atmosphere.

As mentioned above, when pixel electrode 901 was formed by the bilayer on the upper strata of lower floor that comprises IZO and ITO, the etchant that can adopt Cr, Al etc. to be forming pixel electrode 901, thereby prevented that the lower floor (under layer) such as metal wire from damaging.This external overall test process middle probe contact ITO layer makes probe not have foreign matter to pile up.

With reference to Fig. 7-17C in detail, the tft array panel that is used for LCD according to another embodiment of the present invention will be described.

Fig. 7 is the layout that is used for the tft array panel of LCD according to another embodiment of the present invention.Fig. 8 and 9 is respectively the sectional view that tft array panel VIII-VIII ' along the line shown in Figure 7 and line IX-IX ' are got.

With reference to Fig. 7 to 9, comprise many gate lines 121 of a plurality of gate electrodes 124 and the expansion 125 that is used to contact external circuit and be formed on substrate 110 with many storage electrode lines 131 that gate line 121 electricity are isolated.

Gate line 121 comprises two films with different physical characteristicss with storage electrode line 131, and following

film

121p and 131p reach and go up film 121q and 131q.In order to reduce signal delay or the pressure drop in the gate line 121, the last film 121q of gate line 121 is preferably by comprising that the low resistivity metal that contains the Al metal such as Al and Al alloy makes.On the other hand, following film 121p is preferably by such as Cr, Mo, make such as the material of Mo alloy, Ta and the Ti of MoW, and these materials have and good physics, chemistry and contact characteristics such as other material of tin indium oxide (ITO) and indium zinc oxide (IZO).The good example of the combination of following film 121p material and last film 121q material is Cr and Al-Nd alloy.

Storage electrode line 131 also has following film 131p and last film 131q, and provides the predetermined voltage such as common voltage.If the holding capacitor that overlapping produced by gate line 121 and pixel electrode 901 is enough, storage electrode line 131 can save so.In this situation, storage capacitor conductors 177 also can be saved.

In addition, the surface tilt of following film 121p and the relative substrate 110 in side of 131p and

last film

121q and 131q, and its pitch angle is about 30-80 degree.

Preferably a plurality of semiconductor stripeds 151 of being made by amorphous silicon hydride (being abbreviated as " a-Si ") are formed on the gate insulator 140.Each semiconductor striped 151 extends substantially in the vertical and has a plurality of protrusions 154 of telling to gate electrode 124.Form a plurality of semiconductor sections (segment) 157 with cover part storage electrode line 131.

Preferably a plurality of Ohmic contact stripeds 163, island 165 and the section 167 that has the n+ hydrogenation a-Si of n type impurity to make by silicide or heavy doping is formed on the semiconductor striped 151.Each Ohmic contact striped 161 has a plurality of protrusions 163, and protrude 163 and Ohmic contact island 165 be arranged in pairs on the protrusion 154 of semiconductor striped 151.Ohmic contact section 167 is formed on the semiconductor section 157.

Semiconductor 151 with 157 with the surface tilt of Ohmic contact 161,165 relative substrates 110 with 167 side, and its pitch angle is preferably in the scope between about 30-80 degree.

Many data lines 171, a plurality of drain electrode 175 and a plurality of storage capacitor conductors 177 be formed on Ohmic contact 161,165 and 167 and gate insulator 140 on.

The data line 171 that is used to transmit data voltage extends substantially in the vertical and intersects with gate line 121.Every data line 171 comprises that having larger area is used for the expansion 179 that contacts with other layer or external devices.The major part of data line 171 is arranged on the viewing area, but the expansion 179 of data line 171 is arranged on borderline region.

A plurality of branches of every the data line 171 that protrudes to drain electrode 175 form multiple source electrode 173.The every pair of source electrode 173 and drain electrode 175 are separated from one another and about gate electrode 124 toward each other.The protrusion 154 of gate electrode 124, source electrode 173 and drain electrode 175 and semiconductor striped 151 forms TFT together, and this TFT has the raceway groove that is formed in the protrusion 154 that is arranged between source electrode 173 and the drain electrode 175.

Storage capacitor conductors 177 overlaps with part storage electrode line 131, and storage capacitor conductors 177 is formed on Ohmic contact section 167 and the semiconductor section 157.

Data line 171, drain electrode 175 and storage capacitor conductors 177 comprise following

film

171p, 175p and the 177p that is made by Mo, Mo alloy or Cr, and are provided with on it and by containing the Al metal or containing

metal film

171q, 175q and the 177q of going up of Ag.The expansion 179 of data line 171 also comprises film 179q and following film 179p.

Similar gate line 121 and storage electrode line 131, last film 171q, the 175q of data line 171 has the surperficial tapered side of relative substrate 110 with 177q and following film 171p with 175p, drain electrode 175 and storage capacitor conductors 177, and the scope at its pitch angle is about 30-80 degree.

161,165 and 167 of Ohmic contact are inserted in following

semiconductor

151 and 157 and reach between top data line 171, drain electrode 175 and the storage capacitor conductors 177, and reduce contact resistance therebetween.Semiconductor striped 151 comprises not by a plurality of expose portions of data line 171 and drain electrode 175 coverings, such as the part that is arranged between source electrode 173 and the drain electrode 175.Semiconductor section 157 is arranged on below the Ohmic contact section 167 that is formed on below the storage capacitor conductors 177.

Passivation layer 180 be formed on data line 171, drain electrode 175, storage electrode capacitor 177 and the expose portion of the semiconductor striped 151 that do not covered by data line 171 and drain electrode 175 on.Passivation layer 180 preferably by photosensitive organic material with good flat characteristic, by making less than 4.0 low dielectric insulation material or such as the inorganic material of silicon nitride and monox that plasma enhanced CVD (PECVD) forms such as the specific inductive capacity of a-Si:C:O and a-Si:O:F.

Passivation layer 180 has a plurality of contact holes 185,187 and 189 of the expansion 179 that exposes drain electrode 175, the 177p of lower floor that stores conductor 177 and data line 171 respectively.Passivation layer 180 and gate insulator 140 have a plurality of contact holes 181 of the expansion 125 that exposes gate line 121.

A plurality of pixel electrodes 901

assist

Pixel electrode 901 makes pixel electrode 901 receive data voltages and the data voltage that is received is sent to storage capacitor conductors 177 from drain electrode 175 by contact hole 185 physical connections and be electrically connected to drain electrode 175 and be connected to storage capacitor conductors 177 by contact hole 187.

The pixel electrode 901 that provides data voltage produces electric field with the common electrode (not shown) on another panel (not shown), and electric field redirects the liquid crystal molecule that is arranged in the liquid crystal layer therebetween (not shown).

Pixel electrode 901 and common electrode form liquid crystal capacitor, and it stores the voltage that is applied after TFT closes.The building-out condenser that is called " holding capacitor " is parallel to liquid crystal capacitor.Realize holding capacitor by overlapping pixels electrode 190 and storage line 131.It is following to reduce the distance between storage electrode line 131 and the pixel electrode 901 that storage capacitor conductors 177 is arranged on passivation layer 180.

Pixel electrode 901 overlapping gate polar curves 121 and data line 171 are with the raising aperture opening ratio, but this is optional.

Contact auxiliary 906 and 908 is connected to the expansion 179 of the exposure of the expansion 125 of exposure of gate line 121 and data line 171 respectively by contact hole 182 and 189.The auxiliary 906 and 908 protection expansions 125 of contact and 179 and replenish

expansions

125 and 179 and external devices between adhesion.

Contact auxiliary 906 and 908 has following

film

906p and 908p and goes up the bilayer of film 906q and 908q.Here, following

film

906p and 908p are made by IZO, and

last film

906q and 908q are made by ITO.

Here,

IZO layer

901p, 906p and 908p have at 500  to the thickness between 1500 , and

ITO layer

901q, 906q and 908q have at 50  to the thickness between 250 .Especially,

IZO layer

901p, 906p and 908p preferably have the thickness of 900 , and

ITO layer

901q, 906q and 908q have the thickness of 200 .

To 17C and Fig. 8 and 9 in detail, the manufacture method of the tft array panel shown in Fig. 7,8 and 9 will be described with reference to Figure 10 A.

Figure 10 A is at the layout according to the tft array panel shown in the Fig. 7 to 9 in the first step of the manufacture method of the embodiment of the invention.Figure 10 B and 10C are respectively the sectional views that tft array panel Xb-Xb ' along the line shown in Figure 10 A and line Xc-Xc ' are got.Figure 11 A and 11B are respectively the sectional views that the tft array panel Xb-Xb ' along the line shown in Figure 10 A and line Xc-Xc ' are got in the step after the step shown in Figure 10 B and the 10C.Figure 12 A is the layout of tft array panel in the step after the step shown in Figure 11 A and the 11B.Figure 12 B and 12C are respectively the sectional views that tft array panel XIIb-XIIb ' along the line shown in Figure 12 A and line XIIc-XIIc ' are got.Figure 13 A, 14A and 15A and Figure 13 B, 14B and 15B are respectively the sectional views that tft array panel XIIb-XIIb ' along the line shown in Figure 12 A and line XIIc-XIIc ' are got, and illustrate the step afterwards of the step shown in Figure 12 B and the 12C successively.Figure 16 A and 16B are the sectional views of the tft array panel in the step after the step shown in Figure 15 A and the 15B.Figure 17 A is the sectional view of the tft array panel in the step after the step shown in Figure 16 A and the 16B.Figure 17 B and 17C are respectively the sectional views that tft array panel XVIIb-XVIIb ' along the line shown in Figure 17 A and line XVIIc-XVIIc ' are got.

Two conducting films, i.e. lower conductive film and upper conductive film sputter on such as the dielectric substrate 110 of clear glass successively.Upper conductive film is preferably by the thickness that about 2500  were made and preferably had to the Al metal that contains such as Al-Nd.The Al-Nd target preferably includes the Nd of 2atm%.

With reference to Figure 10 A and 10C, use photoresist pattern successively to upper conductive film and lower conductive film composition, comprises many gate lines 121 and many storage electrode lines 131 of a plurality of gate electrodes 124 by photoetching with formation.

With reference to Figure 11 A and 11B, gate insulator 140, intrinsic a-Si layer and the doping a-Si layer made by SiNx of deposit successively.Comprise the down conductor layer of film and last film by the sputter deposit, and photoresist film 210 is covered on the conductive layer.

Shown in Figure 12 B and 12C, photoresist film 210 makes that by exposure of exposed mask (not shown) and development the photoresist after developing has the thickness that depends on the position.The photoresist that develops comprises a plurality of first to third part 214 and 212.First 214 is arranged on the channel region C, and second portion 212 is arranged on the A of data line zone, and not have to the third part designated reference label that is arranged on the remaining area B, is 0 thickness substantially because they have.Here, rely on the thickness ratio that process conditions in subsequently the processing step are regulated first 214 and second portion 212.The thickness of preferred first 214 is equal to or less than half of thickness of second portion 212.

The thickness that photoresist depends on the position can obtain by several technology, for example, and by translucent area and transparent region and resistance light zone of opacity are provided on exposed mask.Translucent area can have slit pattern, grid pattern, have the film of medium transmissivity or intermediate gauge.When using slit pattern, the width of preferred slit or the distance between the slit are less than the resolution of the exposer that is used for photoetching.Another example is to use the photoresist that can reflux.Particularly, when in case but the photoresist pattern of being made by reflow materials has only transparent region and zone of opacity by using common exposed mask to form, it is carried out reflux technique flowing on the zone that does not have photoresist, thereby form thin part.

Then, the layer below

etching photoresist film

212 and 214 reaches makes data line and following layer stay on the A of data area, have only intrinsic semiconductor layer to stay on the channel region C, and gate insulator 140 is exposed on the remaining area B.

At first, shown in Figure 13 A and 13B, remove the part of expose portion below exposure doping semiconductor layer 160 of the conductive layer on other area B.In this step, optionally use dry etching and wet etching, and preferably be easy to etching and

photoresist pattern

212 and 214 is difficult to implement under the etched condition at conductive layer.Yet, because be difficult to determine above-mentioned condition for dry etching, thus dry etching can photoresist

pattern

212 and 214 and conductive layer implement under the etched condition simultaneously.In this situation, the first 214 that is used for dry etching preferably makes and is thicker than the part that is used for wet etching, with removal that prevents first 214 and the exposure that therefore prevents the conductive layer lower part.

The result, shown in Figure 13 A and 13B, conductive layer part on channel region C and data area A, that is (" S/D ") conductor 178 of source/leakage, and the part that storage capacitor conductors 177 is left and the conductive layer on remaining area B stays are removed the part below exposure doped semiconductor 160.Here, S/D conductor 178 has and the source shown in Fig. 7 to 9 and

drain electrode

173 and 175 essentially identical flat shapes, except source electrode 173 and drain electrode 175 are not to disconnect but being connected each other.

Then, shown in Figure 14 A and Figure 14 B, the expose portion of the doping semiconductor layer 160 on area B and the part below the intrinsic semiconductor layer 150, and the first 214 of

photoresist pattern

212 and 214 removes by dry etching.Be easy to etching and gate insulator 140 is difficult to implement etching under the etched condition in

photoresist pattern

212 and 214, doping semiconductor layer 160 and intrinsic semiconductor layer 150.Especially, preferred photoresist pattern 212 is approaching identical with the rate of etch of intrinsic semiconductor layer 150 with 214.For example, by using SF ₆Gaseous mixture or SF with HCl ₆And O ₂Gaseous mixture, photoresist pattern 212 with 214 and the etched thickness of semiconductor layer 150 can be near identical.When photoresist pattern 212 was identical with the rate of etch of intrinsic semiconductor layer 150 with 214, the original depth of first 214 was equal to or less than the summation of the thickness of the thickness of intrinsic semiconductor layer 150 and doping semiconductor layer 160.

Therefore, shown in Figure 14 A and 14B, remove the part of first 214 below exposure S/D conductor 178 on channel region C.Simultaneously, the second portion on the A of data area 212 is also etched with attenuation.

Then, remove the S/D conductor 178 lip-deep photoresist residues of staying on the channel region C by ashing.

Then, shown in Figure 15 A and 15B, the part of the S/D conductor 178 on channel region C and the etched removal of part below the doping semiconductor layer 160.Here, the etching of S/D conductor 178 and doping semiconductor layer 160 can only use dry etching to finish.Perhaps, S/D conductor 178 is by the wet etching etching, and doping semiconductor layer 160 is by the dry etching etching.In the former situation, preferably under the high condition of the etching selectivity between S/D conductor 178 and the doping semiconductor layer 160, implement etching.This is because low etching selectivity makes etching finish judgement difficulty a little, thereby the adjusting that causes staying the thickness of the semiconductor pattern part on the channel region C becomes difficult.Situation in the back is alternately used wet etching and dry etching, and dry etching is difficult to the side of etching impurity semiconductor layer 160 owing to the side of wet etch etches S/D conductor 178, therefore forms stepped transverse side.The example that is used for the etching gas of etching doping semiconductor layer 160 is CF ₄Gaseous mixture and CF with HCl ₄And O ₂Gaseous mixture.Use CF ₄And O ₂Gaseous mixture make the uniform thickness of the etching part can obtain intrinsic semiconductor 150.In this, shown in Figure 15 B, the expose portion of semiconductor 154 can be etched to have the thickness that reduces.Preferred photoresist 212 and 214 is enough thick to expose following data line to prevent second portion 212 to be removed.

Therefore, source electrode 173 and drain electrode 175 are separated from one another, and finish data line and the Ohmic contact under it 163 and 165 simultaneously.

At last, remove the photoresist pattern 212 stayed on the A of data field and 214 residual second portion 212.Perhaps, second portion 212 can be after the part of the S/D conductor 178 on removing channel region C and remove part below the doping semiconductor layer 160 before be removed.

As mentioned above, can carry out wet etching and dry etching in succession, but can only adopt dry etching.The latter is simple relatively but compare with the former and to be not easy to find suitable etching condition.On the contrary, the former finds suitable etching condition easily, but the former with the latter is compared relative complex.

After this, shown in Figure 16 A and 16B, by silicon nitride, the CVD of a-Si:C:O or a-Si:O:F, or by the coating organic insulation form passivation layer 180.

To shown in the 17C, passivation layer 180 is respectively exposed the expansion 125 of drain electrode 175, gate line 121, the expansion 179 of data line 171 and a plurality of contact holes 182,185,187 and 189 of storage capacitor conductors 177 by photoetching to form with gate insulator 140 as Figure 17 A.

At last, shown in Fig. 7 to 9, deposit and photoetching IZO layer and ITO layer are connected to a plurality of pixel electrodes 901 of drain electrode 175 and storage capacitor conductors 177, expansion 125 a plurality of that are connected to gate line 121 with formation and contact auxiliary 906 and contact auxiliary 908 with a plurality of of the expansion 179 that is connected to data line 171.

Pixel electrode 901 with

contact auxiliary

906 and 908 have following

film

901p, 906p and 908p and on the bilayer of

film

901q, 906q and 908q.Here, following

film

901p, 906p and 908p are made and go up

film

901q, 906q and 908q is made by ITO by IZO.

Here the IZO etchant is used for etching IZO layer and ITO layer.The IZO etchant comprises HCl, CH ₃COOH, deionized water and surfactant.At N ₂Carry out the deposit preheating of IZO layer and ITO layer under the atmosphere, to prevent on part, forming metal oxide layer by contact hole 182,185 and 189 metal levels 125,175 that expose and 179.

Because data line 171,173,175,177 and 179, the Ohmic contact it under 163,165 and 167 and semiconductor 151 down and the single mask formation of 157 uses in this technology, and source electrode 173 and drain electrode 175 are separated from one another, and the embodiment shown in Fig. 7,8 and 9 provides the given advantage of the embodiment shown in simple manufacturing method and Fig. 1 and 2.

To describe the tft array panel that is used for LCD according to another embodiment of the present invention in detail with reference to figure 18-24B.

Figure 18 is the layout that is used for the tft array panel of LCD according to another embodiment of the present invention.Figure 19 is the sectional view of the tft array panel got of the line XIX-XIX ' along Figure 18.

Many the gate lines 121 that are used to transmit signal are formed on dielectric substrate 110.Every gate line 121 is substantially along horizontal expansion, and a plurality of parts of every gate line 121 form a plurality of gate electrodes 124.A plurality of protrusions 127 that every gate line 121 comprises a plurality of downward protrusions with have the large-area expansion 129 that is used to contact another layer or external devices.

In addition, the side of gate line 121 is about the surface tilt of substrate 110, and its angle of inclination changes from about 30-80 degree.

Preferably a plurality of semiconductor stripeds 151 of being made by amorphous silicon hydride (being abbreviated as " a-Si ") are formed on the gate insulator 140.Each semiconductor striped 151 extends longitudinally substantially and has a plurality of a plurality of protrusions 154 of telling towards gate electrode 124.Each semiconductor striped 151 becomes big at the width near gate line 121 places, thus the large tracts of land of semiconductor striped 151 covering gate polar curves 121.

Preferably a plurality of Ohmic contact stripeds 161 and the island 165 of being made by the n+ hydrogenation a-Si of silicide or heavy doping n type impurity is formed on the semiconductor striped 151.Each Ohmic contact striped 161 has a plurality of protrusions 163, and protrude 163 and Ohmic contact island 165 be arranged in couples on the protrusion 154 of semiconductor striped 151.

The side of semiconductor striped 151 and

Ohmic contact

161 and 165 tilts about substrate 110, and its angle of inclination is preferably in about 30-80 degree scope.

Many data lines 171, a plurality of drain electrode 175 and a plurality of storage capacitor conductors 177 are formed on

Ohmic contact

161 and 165 and reach on the gate insulator 140.

The data line 171 that is used to transmit data voltage extends longitudinally substantially and intersects with data line 121.Every data line 171 comprises having the large-area expansion 179 that is used to contact another layer or external devices.The major part of data line 171 is arranged on the viewing area, but expansion 179 is arranged on the frontier district.

Every data line 171 towards drain electrode 175 protrude a plurality of branches form multiple source electrode 173.The every pair of source electrode 173 and drain electrode 175 are separated from one another and about gate electrode 124 toward each other.Gate electrode 124, source electrode 173 and drain electrode 175 form TFT with the protrusion 154 of semiconductor striped 151, and this TFT has the raceway groove that is formed in the protrusion 154 that is arranged between source electrode 124 and the drain electrode 175.

The protrusion 127 of storage capacitor conductors 177 overlapping gate polar curves 121.

Be similar to gate line 121, data line 171, drain electrode 175 and storage capacitor conductors 177 have tapered side with respect to substrate 110 surfaces, and its angle of inclination changes at about 30-80 degree.

Ohmic contact

161 and 165 only is arranged between following semiconductor striped 151 and top data line 171 and the drain electrode 175 above the data line 171, and reduces contact resistance therebetween.Semiconductor striped 151 comprises a plurality of not by the expose portion of data line 171 and drain electrode 175 coverings, for example part between source electrode 173 and drain electrode 175.Though semiconductor striped 151 is narrower than data line 171 in most of position, as mentioned above, the width of semiconductor striped 151 is becoming big near gate line 121 places, thereby makes the smooth-shaped on surface, therefore prevents the disconnection of data line 171.

On the expose portion of the semiconductor striped 151 that a plurality of colored filter R, G and B be formed on data line 171, drain electrode 175, storage capacitor conductors 177, do not covered by data line 171 and drain electrode 175 and the gate insulator 140 that do not covered by their.Colored filter R, G and B have open C 1 and the C2 that exposes drain electrode 175 and storage capacitor conductors 177.

Passivation layer 180 is formed on colored filter R, G and the B.The low dielectric insulation material that passivation layer 180 preferably forms by the photosensitive organic material with good flat characteristic, by plasma-reinforced chemical vapor deposition (PECVD) is a-Si:C:O and a-Si:O:F for example, or for example inorganic material formation of silicon nitride and monox.

Passivation layer 180 has a plurality of contact holes 185,187 and 189 of the expansion 179 that exposes drain electrode 175, storage capacitor conductors 177 and data line 171 respectively.Passivation layer 180 and gate insulator 140 have a plurality of contact holes 182 of the expansion 129 that exposes gate line 121.

A plurality of pixel electrodes 901

assist

Pixel electrode 901 with

contact auxiliary

906 and 908 have following

film

901p, 906p and 908p and on the bilayer of

film

901q, 906q and 908q.Here, following

film

901p, 906p and 908p are made by IZO, and go up

film

901q, 906q and 908q is made by ITO.

Here,

IZO layer

901p, 906p and 908p have the thickness of 500  to 1500 , and

ITO layer

901q, 906q and 908q have the thickness of 50  to 250 .Especially,

IZO layer

901p, 906p and 908p preferably have the thickness of 900 , and

ITO layer

901q, 906q and 908q preferably have the thickness of 200 .

Pixel electrode 901 is by contact hole 185 physical connections and be electrically connected to drain electrode 175, and by contact hole 187 physical connections and be electrically connected to storage capacitor conductors 177, thereby pixel electrode 901 receives data voltages and transmits the data voltage that receives to storage capacitor conductors 177 from drain electrode 175.

The common electrode (not shown) of pixel electrode 901 on another panel (not shown) that is supplied with data voltage produces electric field, and this electric field redirects the liquid crystal molecule that is arranged in the liquid crystal layer therebetween (not shown).

Pixel electrode 901 and common electrode form liquid crystal capacitor, and it stores the voltage that is applied after TFT closes.Can provide the building-out condenser that is called " holding capacitor " that is parallel to liquid crystal capacitor to be used to improve the store voltages capacity.Implement holding capacitor by the pixel electrode 901 and the overlapping of adjacent gate lines 121.Protrusion 127 by being provided for increasing the overlapping area at gate line 121 also protrudes 127 storage capacitor conductors 177 to reduce the distance between the terminal by providing for 901 times at pixel electrode to be connected to pixel electrode 901 and to overlap, thereby increase the electric capacity of holding capacitor, i.e. memory capacitance.

Pixel electrode 901 overlapping gate polar curves 121 and data line 171 are with the increase aperture opening ratio, but this is optional.

expansions

125 and 179 and external devices between adhesion.

To describe the method for the manufacturing tft array panel shown in Figure 18 and 19 with reference to figure 20A in detail to 24B and Figure 18 and 19.

Figure 20 A is the layout according to the tft array panel of manufacture method in its first step of the embodiment of the invention.Figure 20 B is the sectional view that the tft array panel XXb-XXb ' along the line shown in Figure 20 A is got.Figure 21 A is the layout of the tft array panel in the step after the step shown in Figure 20 A.Figure 21 B is the sectional view that the tft array panel XXIb-XXIb ' along the line shown in Figure 21 A is got.Figure 22 A is the layout of the tft array panel in the step afterwards of the step shown in Figure 21 A.Figure 22 B is the sectional view that the tft array panel XXIIb-XXIIb ' along the line shown in Figure 22 A is got.Figure 23 A is the layout of the tft array panel in the step after the step shown in Figure 22 A.Figure 23 B is the sectional view that the tft array panel XXIIIb-XXIIIb ' along the line shown in Figure 23 A is got.Figure 24 A is the layout of the tft array panel in the step after the step shown in Figure 23 A.Figure 24 B is the sectional view that the tft array panel XXIVb-XXIVb ' along the line shown in Figure 24 A is got.

At first, sputter conducting film on the dielectric substrate 110 of for example clear glass.

With reference to figure 20A and 20B, this conducting film is patterned to be comprised a plurality of gate electrodes 124 and protrudes 127 many gate lines 121 with formation.

With reference to figure 21A and 21B, after sequential deposit gate insulator 140, intrinsic a-Si layer and doping a-Si layer, doping a-Si layer and intrinsic a-Si layer by photoetching to form a plurality of doped semiconductors 160 and a plurality of intrinsic semiconductor 150.Gate insulator 140 is preferably made to the silicon nitride of about 5000  thickness by about 2000 , and deposition temperature is preferably in about 250 ℃ and about 500 ℃ of scopes.

With reference to figure 22A and 22B, sputter and patterning conductive layer comprise many data lines 171, a plurality of drain electrode 175 and a plurality of storage capacitor conductors 177 of multiple source electrode 173 with formation.

Then, the part of removing not the doped semiconductor 160 that is covered by data line 171 and drain electrode 175 by etching is to finish a plurality of

Ohmic contact

163 and 165 and expose the part of intrinsic semiconductor 151.Can carry out oxygen plasma subsequently and play the exposed surface of processing with stabilization of semiconductor 151.

Then, shown in Figure 23 A and 23B, apply the organic photo anti-corrosion agent material that comprises red, green and blue pigment respectively, form a plurality of colored filter R, G and B with order by light technology.At this moment, form open C 1 and the C2 that exposes drain electrode 175 and storage capacitor conductors 177 simultaneously.Form open C 1 and C2 and have good profile so that expose the contact hole of the passivation layer 180 of drain electrode 175 and storage capacitor conductors 177.

With reference to figure 24A and 24B, the organic insulating film that has the flat characteristic that low-k becomes reconciled by coating, or by specific inductive capacity be lower than about 4.0 low dielectric insulation material for example the PECVD of a-Si:C:O and a-Si:O:F form passivation layer 180.After this, photoetching passivation layer 180 and gate insulator 140 are to form a plurality of contact holes 182,185,187 and 189.

Here, the

contact hole

185 and 187 of exposure drain electrode 175 and storage capacitor conductors 177 is formed in the open C 1 and C2 of colored filter R, G and B.In the present invention, colored filter R, G and B form has open C 1 and C2, and passivation layer 180 is patterned forming the

contact hole

185 and 187 that exposes drain electrode 175 and storage capacitor conductors 177 respectively, thereby contact

hole

185 and 187 has good profile.

At last, shown in Figure 18 and 19, form a plurality of pixel electrodes 901 that comprise bilayer by sputter and photoetching IZO layer and ITO layer and contact auxiliary 906 and 908 with a plurality of.

Here, use the IZO etchant with etching IZO layer and ITO layer.The IZO etchant comprises HCl, CH ₃COOH, deionized water and surfactant.

To describe the tft array panel that is used for LCD in accordance with another embodiment of the present invention in detail to 35C with reference to Figure 25.

Figure 25 is the layout that is used for the tft array panel of LCD in accordance with another embodiment of the present invention.Figure 26 and 27 is sectional views that tft array panel XXVI-XXVI ' along the line shown in Figure 25 and line XXVII-XXVII ' are got.

With reference to Figure 25 to 27, on substrate 110, form comprise a plurality of gate electrodes 124 and be used to contact external circuit expansion 125 many gate lines 121 and with many storage electrode lines 131 of gate line 121 electricity isolation.

Storage electrode line 131 has been supplied predetermined voltage, for example common voltage.If the memory capacitance that is produced by overlapping gate polar curve 121 and pixel electrode 901 is enough, can omit storage electrode line 131 so.In this situation, can also omit storage capacitor conductors 177.

In addition, the side of gate line 121 and storage electrode line 131 is about the surface tilt of substrate 110, and its angle of inclination is about 30-80 degree scope.

Preferably a plurality of semiconductor stripeds 151 of being made by amorphous silicon hydride (being abbreviated as " a-Si ") are formed on the gate insulator 140.Each semiconductor striped 151 extends substantially in the vertical and has a plurality of protrusions 154 of telling to gate electrode 124.Form a plurality of semiconductor sections 157 with cover part storage electrode line 131 and be connected to and protrude 154.

Preferably a plurality of Ohmic contact stripeds 163, island 165 and the section 167 that has the n+ hydrogenation a-Si of n type impurity to make by silicide or heavy doping is formed on the semiconductor striped 151.Each Ohmic contact striped 161 has a plurality of protrusions 163, and protrude 163 and Ohmic contact island 165 be arranged in couples on the protrusion 154 of semiconductor striped 151.Ohmic contact section 167 is formed on the semiconductor section 157.Be similar to semiconductor section 157 and be connected to protrusion 154, Ohmic contact section 167 also is connected to Ohmic contact island 165.

Many data lines 171, a plurality of drain electrode 175 and a plurality of storage capacitor conductors 177 be formed on Ohmic contact 161,165 and 167 and gate insulator 140 on.Drain electrode 175 and storage capacitor conductors 177 are connected to each other.

A plurality of branches of every the data line 171 that protrudes to drain electrode 175 form multiple source electrode 173.The every pair of source electrode 173 and drain electrode 175 are separated from one another and about gate electrode 124 toward each other.The protrusion 154 of gate electrode 124, source electrode 173 and drain electrode 175 and semiconductor striped 151 forms TFT together, and this TFT has the raceway groove that is formed in the protrusion 154 that is arranged between source electrode 173 and the drain electrode 175.The far-end of drain electrode 175 distance sources electrodes 173 is connected to storage capacitor conductors 177.

Similar gate line 121 and storage electrode line 131, data line 171, drain electrode 175 and storage capacitor conductors 177 have the surperficial tapered side of relative substrate 110, and the scope at its pitch angle is about 30-80 degree.

161,165 and 167 of Ohmic contact are inserted in following

semiconductor

Passivation layer 180 be formed on data line 171, drain electrode 175, the storage electrode capacitor 177 and the expose portion of the semiconductor striped 151 that do not covered by data line 171 and drain electrode 175 on.The specific inductive capacity such as a-Si:C:O and a-Si:O:F that passivation layer 180 preferably forms by the photosensitive organic material with good flat characteristic, by plasma enhanced CVD (PECVD) is lower than 4.0 low dielectric insulation material or makes such as the inorganic material of silicon nitride and monox.

Passivation layer 180 has a plurality of contact holes 185,187 and 189 of the expansion 179 that exposes drain electrode 175, storage conductor 177 and data line 171 respectively.Passivation layer 180 and gate insulator 140 have a plurality of contact holes 181 of the expansion 125 that exposes gate line 121.

A plurality of pixel electrodes 901

assist

Pixel electrode 901 is by

contact hole

185 and 187 physical connections and be electrically connected to drain electrode 175 and storage capacitor conductors 177, makes pixel electrode 901 receive data voltage and the data voltage that is received is sent to storage capacitor conductors 177 from drain electrode 175.

Pixel electrode 901 and common electrode form liquid crystal capacitor, and it stores the voltage that is applied after TFT closes.The building-out condenser that is called " holding capacitor " can be parallel to liquid crystal capacitor.Realize this holding capacitor by overlapping pixels electrode 190 and storage line 131.

expansions

125 and 179 and external devices between adhesion.

Contact auxiliary 906 and 908 has following

film

906p and 908p and goes up the bilayer of film 906q and 908q.Here, following

film

906p and 908p are made by IZO, and

last film

906q and 908q are made by ITO.

Here,

IZO layer

901p, 906p and 908p have at 500  to the thickness between 1500 , and

ITO layer

901q, 906q and 908q have at 50  to the thickness between 250 .Especially,

IZO layer

901p, 906p and 908p preferably have the thickness of 900 , and

ITO layer

901q, 906q and 908q have the thickness of 200 .

To describe the manufacture method of the tft array panel shown in Figure 25,26 and 27 with reference to figure 28A in detail to 35A and Figure 25,26,27.

Figure 28 A is the layout according to the tft array panel in the first step of its manufacture method of fourth embodiment of the invention.Figure 28 B and 28C are respectively the sectional views that tft array panel XXVIIIb-XXVIIIb ' along the line shown in Figure 28 A and line XXVIIIc-XXVIIIc ' are got.Figure 29 A and 29B are respectively the sectional views that the tft array panel XXVIIIb-XXVIIIb ' along the line shown in Figure 28 A and line XXVIIIc-XXVIIIc ' are got in the step after the step shown in Figure 28 B and the 28C.Figure 30 A is the layout of tft array panel in the step after the step shown in Figure 29 A and the 29B.Figure 30 B and 30C are respectively the sectional views that tft array panel XXXb-XXXb ' along the line shown in Figure 30 A and line XXXc-XXXc ' are got.Figure 31 A, 32A and 33A and Figure 31 B, 32B and 33B are respectively the sectional views that tft array panel XXXb-XXXb ' along the line shown in Figure 30 A and line XXXc-XXXc ' are got, and illustrate the described step of Figure 30 B and 30C step afterwards successively.Figure 34 A is the sectional view of tft array panel in the step after the step shown in Figure 33 A and the 33B.Figure 34 B and 34C are respectively the sectional views that tft array panel XXXIVb-XXXIVb ' along the line shown in Figure 34 A and line XXXIVc-XXXIVc ' are got.Figure 35 A is the sectional view of the tft array panel in the step after the step shown in Figure 33 A-33C.

With reference to figure 28A to 28C, patterned many gate lines 121 and many storage electrode lines 131 that comprise a plurality of gate electrodes 124 with formation of conducting film.

With reference to figure 29A and 29B, the gate insulator 140 that sequential deposit is made by SiNx, intrinsic a-Si layer 150 and doping a-Si layer 160.Comprise the down conductive layer of film and last film by the sputter deposit, and photoresist film 210 is coated on the conducting film.

Photoresist film 210 is exposed to light by the exposed mask (not shown) and develops, and makes the photoresist that develops have the thickness that depends on the position shown in Figure 30 B and the 30C.The photoresist that develops comprises a plurality of first to third part 214 and 212.First 214 is arranged on that channel region C goes up and second portion 212 is arranged on the A of data line zone, and not have to the third part designated reference label that is arranged on the remaining area B, is 0 thickness substantially because they have.Here, rely on the thickness ratio that process conditions in subsequently the processing step are regulated first 214 and second portion 212.The thickness of preferred first 214 is equal to or less than half of thickness of second portion 212.

The thickness that depends on the position of photoresist can obtain by several technology, for example, and by translucent area, transparent region and resistance light zone of opacity are provided on exposed mask.Translucent area can have slit pattern, grid pattern, have the film of medium transmissivity or intermediate gauge.When using slit pattern, the width of preferred slit or the distance between the slit are less than the resolution of the exposer that is used for photoetching.

When photoresist film is exposed to the light time by for example such mask, the polymkeric substance that directly is exposed to the part of light almost completely decomposes, and is not decomposed fully by the part that slit pattern or semi-transparent film are exposed to light, because the illumination total amount is little.The polymkeric substance that is set at the part photoresist film of the light blocking film obstruct on the mask is difficult to decompose.After the photoresist film development, stay the part that comprises Undec polymkeric substance.At this moment, be thinner than the thickness of unexposed portion by the thickness of the part of less exposure.Because the long time shutter can be decomposed all molecules, so need to adjust the time shutter.

Another example that the formation glimmer causes resist layer 214 is to use the photoresist that can reflux.Particularly, when in case but the photoresist pattern of being made by reflow materials has only transparent region and zone of opacity by using common exposed mask to form, it is carried out reflux technique flowing on the zone that does not have photoresist, thereby form thin part.

Then, the layer below

etching photoresist film

At first, shown in Figure 31 A and 31B, remove the part of expose portion below exposure doping semiconductor layer 160 of the conductive layer on other area B.In this step, optionally use dry etching and wet etching, and preferably be easy to etching and

photoresist pattern

212 and 214 is difficult to implement under the etched condition at conductive layer.Yet, because be difficult to determine above-mentioned condition for dry etching, dry etching can photoresist

pattern

212 and 214 and conductive layer implement under the etched condition simultaneously.In this situation, the first 214 that is used for dry etching preferably makes and is thicker than the part that is used for wet etching, thereby with removal that prevents first 214 and the exposure that prevents the conductive layer lower part.

The result, shown in Figure 31 A and 31B, conductive layer part on channel region C and data area A, promptly, data line 171, source/leakage (" S/D ") conductor 178 and storage capacitor conductors 177 are left, and the remainder of the conductive layer on remaining area B is removed the part below exposure doped semiconductor 160.Here, S/D conductor 178 have with Fig. 7 to source and

drain electrode

173 and 175 essentially identical flat shapes shown in Figure 9, except source electrode 173 and drain electrode 175 are not to disconnect but being connected each other.

Then, shown in Figure 32 A and Figure 32 B, the expose portion of the doping semiconductor layer 160 on area B and the part below the intrinsic semiconductor layer 150, and the first 214 of

photoresist pattern

Therefore, shown in Figure 32 A and 32B, remove the part of first 214 below exposure S/D conductor 178 on channel region C.Simultaneously, the second portion on the A of data area 212 is also etched with attenuation.

Then, the part of the S/D conductor 178 on channel region C and the etched removal of part below the doping semiconductor layer 160.Here, the etching of S/D conductor 178 and doping semiconductor layer 160 can only use dry etching to carry out.Perhaps, come 178 etchings of etching S/D conductor, come etching doping semiconductor layer 160 by dry etching by wet etching.In the former situation, preferably under the high condition of the etching selectivity between S/D conductor 178 and the doping semiconductor layer 160, implement etching.This is because low etching selectivity makes etching finish judgement difficulty a little, thereby the adjusting that causes staying the thickness of the semiconductor pattern part on the channel region C becomes difficult.Situation in the back is alternately used wet etching and dry etching, and dry etching is difficult to the side of etching impurity semiconductor layer 160 owing to the side of wet etch etches S/D conductor 178, therefore forms stepped sides.The example that is used for the etching gas of etching impurity semiconductor layer 160 is CF ₄Gaseous mixture and CF with HCl ₄And O ₂Gaseous mixture.Use CF ₄And O ₂Gaseous mixture make the uniform thickness of the etching part can obtain intrinsic semiconductor 150.In this, shown in Figure 33 B, the expose portion of semiconductor 154 can be etched to have the thickness that reduces.Preferred photoresist 212 and 214 is enough thick to expose following data line to prevent second portion 212 to be removed.

Therefore shown in Figure 33 A and 33B, source electrode 173 and drain electrode 175 are separated from one another, and finish data line and the Ohmic contact 161,163 and 165 under it simultaneously.

At last, remove the photoresist pattern 212 stayed on the A of data field and 214 residual second portion 212.Perhaps, after the part of the S/D conductor 178 on removing channel region C and remove before the part below the doping semiconductor layer 160, can remove second portion 212.

As mentioned above, can carry out wet etching and dry etching in succession, but can only adopt dry etching.The latter is simple relatively but compare with the former and to be not easy to obtain suitable etching condition.On the contrary, the former finds suitable etching condition easily, but the former with the latter is compared relative complex.

By above-mentioned technology, realized the structure shown in Figure 33 A and the 33B.

Then, shown in Figure 34 A and 34C, coating comprises the organic photosensitive material of red, green and blue pigment respectively and forms a plurality of colored filter R, G and B by light technology composition with order.At this moment, form open C 1 and the C2 that exposes drain electrode 175 and storage capacitor conductors 177 simultaneously.

At this moment, the shading layer that is formed by red or green colored filter can be set on the channel region C of thin film transistor (TFT), to intercept light with short wavelength by absorbing.

Then, the insulating material that is lower than about 4.0 low-k by coating acrylic acid organic insulating film or have forms passivation layer 180.After this, passivation layer 180 and gate insulator 140 are by a plurality of contact holes 182,185,187 and 189 of photoetching with the expansion 179 that forms expansion 125, storage capacitor conductors 177 and the data line expose drain electrode 175, gate line respectively.

Here, expose the expansion 179 of data line and the

contact hole

189 and 187 of storage capacitor conductors 177 and be formed in the open C 1 and C2 of colored filter R, G and B, make

contact hole

187 and 189 have good profile.

To describe the tft array panel that is used for LCD in accordance with another embodiment of the present invention in detail with reference to Figure 36 to 45.

Figure 36 is the layout that is used for the tft array panel of LCD in accordance with another embodiment of the present invention.Figure 37 is the sectional view that tft array panel XXXVII-XXXVII ' along the line shown in Figure 36 is got.

When the embodiment of present embodiment and Fig. 1 and 2 compared, the pixel electrode 901 that is formed by individual layer was special features of present embodiment.Yet, contact auxiliary 906 and 908 and the similar bilayer of Fig. 1 and Fig. 2 with IZO and ITO.

After this, will provide detailed description.

Every gate line 121 comprises that the part of a plurality of downward protrusions is to form a plurality of gate electrodes 124 and to have the large-area expansion 125 that is used to contact another layer or external devices.The major part of gate line 121 is arranged on the viewing area, and the expansion 125 of gate line 121 is arranged on the frontier district of viewing area.

Gate line 121 comprises two films with different physical characteristicss, promptly descends film 121p and last film 121q.In order to reduce signal delay or the pressure drop in the gate line 121, last film 121q is preferably by comprising that the low resistivity metal that contains the Al metal such as Al and Al alloy makes.On the other hand, following film 121p is preferably by such as Cr, Mo, make such as the material of Mo alloy, Ta and the Ti of MoW, and these materials have and good physics, chemistry and contact characteristics such as other material of tin indium oxide (ITO) and indium zinc oxide (IZO).The good example of the combination of following film 121p material and last film 121q material is Cr layer and Al-Nd alloy-layer.In Figure 37, the upper and lower film of gate electrode 124 is represented by

reference number

124p and 124q respectively, and the upper and lower film of expansion 125 is represented by

reference number

125p and 125q respectively.

In addition, the surface tilt of the relative substrate 110 in side of upper and

lower film

121q and 121p, and the scope at its inclination angle is about 30-80 degree.

Preferably a plurality of semiconductors 150 of being made by amorphous silicon hydride (being abbreviated as " a-Si ") are formed on the gate insulator 140.Each semiconductor 150 is arranged on the gate electrode 124 and the frontier district of covering grid electrode 124 and gate electrode 124.

Preferably a plurality of

Ohmic contact island

163 and 165 is arranged in pairs on the semiconductor island 150.

Many data lines 171 and a plurality of drain electrode 175 be formed on

Ohmic contact

163 and 165 and gate insulator 140 on.

The data line 171 that is used to transmit data voltage extends substantially in the vertical and intersects with gate line 121.Every data line 171 comprises having than large tracts of land and is used for the expansion 179 that contacts with other layer or external devices.The major part of data line 171 is arranged on the viewing area, but expansion 179 is arranged on borderline region.

A plurality of branches of every the data line 171 that protrudes to drain electrode 175 form multiple source electrode 173.The every pair of source electrode 173 and drain electrode 175 are separated from one another and about gate electrode 124 toward each other.Gate electrode 124, source electrode 173 and drain electrode 175 and semiconductor island 150 form TFT, and this TFT has the raceway groove that is formed in the semiconductor island 150 that is arranged between source electrode and the drain electrode.

Data line 171 and drain electrode 175 comprise following film 171p and the 175p that is preferably made by Mo, Mo alloy and Cr, and disposed thereon preferably by containing the Al metal or containing metal film 171q of going up of Ag and 175q.The expansion 179 of data line 171 also comprises film 179q and following film 179p.

film

171q, 175q, and the scope at its pitch angle is about 30-80 degree.

Ohmic contact

163 and 165 are inserted between following semiconductor 150 and the top source electrode 173 and between the drain electrode above the electrode of source 175 and reduce therebetween contact resistance.Semiconductor 150 comprises not by the expose portion of source electrode 173 and drain electrode 175 coverings, for example part between source electrode 173 and the drain electrode 175.

Passivation layer 180 has a plurality of

contact holes

A plurality of pixel electrodes 901

assist

Pixel electrode 901 has the individual layer of IZO.Yet contact auxiliary 906 and 908 has the bilayer of IZO and ITO.

Pixel electrode 901 and common electrode form liquid crystal capacitor, and it stores the voltage that is applied after TFT closes.The building-out condenser that is called " holding capacitor " that is parallel to liquid crystal capacitor can be provided, be used to improve the store voltages capacity.

expansions

125 and 179 and external devices between

adhesion.Contact auxiliary

906 and 908 is not essential element.So they can save.

Contact auxiliary 906 and 908 has following

film

906p and 908p and goes up the bilayer of film 906q and 908q.Here, following

film

906p and 908p are made by IZO, and

last film

906q and 908q are made by ITO.

To describe the manufacture method of Figure 36 and tft array panel shown in Figure 37 with reference to figure 38A in detail to Figure 45 and Figure 36,37.

Figure 38 A, 39A, 40A and 41A are the layouts that illustrates the intermediate steps of the tft array method for producing panel shown in Figure 36 and 37 successively.Figure 38 B is the sectional view that the tft array panel XXXVIIIb-XXXVIIIb ' along the line shown in Figure 38 A is got.Figure 39 B is the sectional view that the tft array panel XXXIXb-XXXIXb ' along the line shown in Figure 39 A is got in the step after the step shown in Figure 38 B.Figure 40 B is the sectional view that the tft array panel XLb-XLb ' along the line shown in Figure 40 A is got in the step after the step shown in Figure 39 B.Figure 41 B is the sectional view that the tft array panel XLIb-XLIb ' along the line shown in Figure 41 A is got in the step after the step shown in Figure 40 B.Figure 42 is the sectional view that the tft array panel XLIb-XLIb ' along the line shown in Figure 41 A is got in the step after the step shown in Figure 41 B.Figure 43 is the sectional view that uses the LCD XLIb-XLIb ' along the line of the tft array panel shown in Figure 41 A to be got in the step after step shown in Figure 42.Figure 44 is the sectional view that uses the LCD XLIb-XLIb ' along the line of the tft array panel shown in Figure 41 A to be got in the step after step shown in Figure 43.Figure 45 is the layout that is used to make the shadow mask of LCD shown in Figure 44.

Two conducting films, i.e. lower conductive film and upper conductive film, sputter is on the dielectric substrate 110 such as clear glass successively.The thickness of about 2500  is preferably made and preferably had to upper conductive film by aluminiferous metals.The Al-Nd target preferably includes the Nd of 2atm%.

With reference to Figure 38 A and Figure 38 B, composition upper conductive film and lower conductive film comprise many gate lines 121 of a plurality of gate electrodes 124 with formation successively to use the photoresist pattern.

With reference to Figure 39 A and 39B, after deposit gate insulator 140, intrinsic a-Si layer and doping a-Si layer successively, doping a-Si layer and intrinsic a-Si layer by photoetching to form a plurality of doped semiconductors 160 and a plurality of intrinsic semiconductor 150.Gate insulator 140 is preferably made to the silicon nitride of the thickness of 5000  by having about 2000 , and deposition temperature is preferably in the scope between about 250 ℃ and about 500 ℃.

With reference to Figure 40 A and 40B, two conducting films of sputter, i.e. lower conductive film and upper conductive film successively.Lower conductive film is preferably by the thickness of making and preferably having about 500  such as the metal of Cr, Mo and Mo alloy.Upper conductive film preferably has the thickness of about 2500 .The target that is used for film is preferably made by Al or the Al-Nd that contains the Nd of 2atomic%.Preferably about 150 ℃ of sputter temperature.

Then, the upper and lower conducting film of etching comprises many data lines 171 and a plurality of drain electrode 175 of multiple source electrode 173 with formation.At this moment, upper and lower film can perhaps be gone up film and be descended film by the dry etching etching by the wet etching etching by wet etching etching simultaneously.When film 171p is made by Mo or Mo alloy instantly, it can be under etching condition with on film 171q etching.

Then, the part of the doped semiconductor 160 that is covered by data line 171 and drain electrode 175 is not removed finishing a plurality of

Ohmic contact

163 and 165 by etching, and expose portion intrinsic semiconductor 150.For the exposed surface of stabilization of semiconductor 150, can carry out oxygen plasma treatment subsequently.

With reference to Figure 41 A and 41B, deposit passivation layer 180 and with its with gate insulator 140 dry etchings to form a plurality of contact holes 182,185 and 189.Preferably have etching grid insulation course 140 and passivation layer 180 under the etching condition of essentially identical rate of etch at gate insulator 140 and passivation layer 180.

Then, shown in Figure 36 and 42, deposit and photoetching IZO layer are connected to the contacting of expansion 179 of a plurality of pixel electrodes 901 of drain electrode 175, the expansion 125 that is connected to gate line and data line and assist 906 and 908 a plurality of 906p of lower floor and 908p by contact hole 185 with formation.

At N ₂Carry out the deposit preheating of IZO layer and ITO layer under the atmosphere, to prevent on part, forming metal oxide layer by contact hole 182,185 and 189 metal levels 125,175 that expose and 179.

When pixel electrode 901 was formed by IZO, the etchant that can use Cr or Al was with photoetching IZO layer, thus prevent by under wiring destroyed.Yet if

contact auxiliary

906 and 908 is made by IZO, in overall test (GT), the Elements C and the Si of

contact auxiliary

906 and 908 adhere on the probe, carry out suitable test thereby disturbed so.

For fear of such problem, shown in Figure 36 and 37, deposit ITO layer on 906p of lower floor that makes by IZO and 908p.

The other method that forms the ITO layer on auxiliary 906p of lower floor of the contact of making by IZO and 908p will only be described in detail.

Figure 43 shows the LCD that has the thin-film transistor display panel shown in Figure 36 and 42 and face the colorful optical filter array panel of this thin-film transistor display panel, this thin-film transistor display panel has the pixel electrode of being made by IZO 901 and

assists

906p and 908p with contacting, and this colorful optical filter array panel has black matrix 220, colored filter 230 and common electrode 270.

With reference to Figure 43, both alignment layers 11 is formed on pixel electrode 901 and the passivation layer 180.Then, the separator 320 that is used for the holding unit spacing is formed on both alignment layers 11.Then, sealant 310 is formed on the frontier district of thin-film transistor display panel.When forming liquid crystal layer by drippage (dropping), sealant 310 forms and obtains closed curve.When passing through to inject the formation liquid crystal layer after component film transistor display panel and manufacturing method thereof and colorful optical filter array panel, sealant 310 forms and causes open curve to have filling orifice.

In dropping method, the dropping liquid crystal material is also filled the space that is centered on by sealant 310.After this, the colorful optical filter array panel sets is contained on the thin-film transistor display panel.

In method for implanting, component film transistor display panel and manufacturing method thereof and colored filter panel are to form the space, and after this, liquid crystal material is injected in this space.After injection, seal filling orifice.

In sealant 310 outsides, be formed for common electrode 270 is connected to wiring that is formed on the thin-film transistor display panel and the short circuit ball 60 that transmits common voltage.

Then, as shown in figure 44, in contacting auxiliary 906p of lower floor and 908p,

form ITO layer

906q and 908q.

ITO layer 906q contacting on the auxiliary 906p of lower floor and 908p by sheltering with evaporation deposition with 908q.Shadow mask shown in Figure 45 is used to cover.

Evaporation is a kind of deposition process, and wherein evaporation is used for the material of deposit and is deposited on substrate.Material is heated by heat or electron beam is heated evaporates.

When the sputter of evaporation relatively and the ionic bombardment that uses plasmoid, evaporation has the advantage that does not need high energy or high vacuum.In addition, when adopting evaporation, can select deposit by using shadow mask.

ITO layer deposit by evaporation is preferably at component film transistor display panel 100 and colored filter panel 200, carry out after injecting liquid crystal material and motherboard being cut into all technologies of unit.That is, the deposit of ITO layer was preferably carried out before visual test, and this visual test was carried out before module process.

Owing to after motherboard is cut into the unit, carry out, and by using shadow mask in the auxiliary lower floor of contact, to select deposit ITO layer, so evaporation method can easily be applicable to large size panel by evaporation deposit ITO layer in the auxiliary lower floor of contact.

Shadow mask 5 has and is used to expose auxiliary 906p of lower floor of contact and the opening of 908p.Promptly, shadow mask 5 has gate openings 5b and data opening 5a, gate openings 5b is used to expose the auxiliary 906p of lower floor of contact of the expansion 125 that is connected to gate line, and data opening 5a is used to expose the auxiliary 908p of lower floor of contact of the expansion 179 that is connected to data line.

Therefore, contact auxiliary 906 and 908 comprises the 906p of lower floor of IZO and upper strata 906q and the 908q of 908p and ITO.Owing to contact with 908q with the upper strata 906q of ITO at overall test process middle probe, make probe not have foreign matter to pile up.

The present invention can be applied to electroluminescence (EL) display.

To describe EL display below in detail according to the embodiment of the invention.

To two embodiment of EL display be described.One at Figure 46 shown in Figure 62 b, and another at Figure 63 to shown in Figure 67.

The embodiment of EL display comprises the semi-conductive thin-film transistor display panel of use amorphous silicon as thin film transistor (TFT).

Figure 46 is the layout according to the tft array panel that is used for electroluminescence (" EL ") display of the embodiment of the invention.Figure 47 and 48 is respectively the sectional view of the tft array panel got of XLVIIb-XLVIIb ' along the line shown in Figure 46 and line XLVIII-XLVIII '.Figure 49 and 50 is respectively the sectional view of the tft array panel got of XLI-XLI ' along the line shown in Figure 46 and line L-L '.

Many the gate lines 121 that are used to transmit signal are formed on dielectric substrate 110.Every gate line 121 is substantially along horizontal expansion, and a plurality of parts of every gate line 121 form a plurality of first grid electrode 124a.A plurality of second gate electrode 124b are formed on the layer identical with gate line 121, and each second gate electrode 124b is connected to the storage electrode 133 that extends longitudinally.

Gate line 121, the first and

second gate electrode

124a and 124b, storage electrode 133 can comprise the two membranes that physical characteristics is different.A skim is preferably by comprising that the low resistivity metal that contains the Al metal such as Al and Al alloy makes, to reduce signal delay or the pressure drop in the gate line 121.Another tunic is preferably by such as Cr, Mo, make such as the material of the Mo alloy of MoW, and these materials have and good physics, chemistry and contact characteristics such as other material of tin indium oxide (ITO) and indium zinc oxide (IZO).The good example of the combination of this two membranes is Cr layer and Al-Nd alloy-layer.

The side of gate line 121 and storage electrode 133 is about the surface tilt of substrate 110, and its angle of inclination changes from about 30-80 degree.

Preferably a plurality of semiconductor stripeds 151 and the island 154b that is made by amorphous silicon hydride (being abbreviated as " a-Si ") is formed on the gate insulator 140.Each semiconductor striped 151 extends longitudinally substantially and has to what first grid electrode 124a told and a plurality of first protrudes 154a.The width of semiconductor striped 151 is becoming big near gate line 121 places.Semiconductor island 154b comprises second protrusion that intersects with the second gate electrode 124b.

Preferably a plurality of Ohmic contact stripeds and island 161,165a, 163b and the 165b that is made by the n+ hydrogenation a-Si of silicide or heavy doping n type impurity is formed on semiconductor striped 151 and the island 154b.Each Ohmic contact striped 161 has a plurality of protrusion 163a, and protrudes 163a and Ohmic contact island 165a and be arranged on first of semiconductor striped 151 in couples and protrude on the 154a.

Ohmic contact island

163b and 165b are arranged on the semiconductor island 154b in couples about the second gate electrode 124b.

The side of

semiconductor

151 and 154b and Ohmic contact 161,165a, 163b and 165b tilts about substrate 110, and its angle of inclination is preferably in about 30-80 degree scope.

Many data lines 171, the first drain electrode 175a, line of electric force (power line) the 172 and second drain electrode 175b be formed on that Ohmic contact 161,165a, 163b and 165b go up and gate insulator 140 on.

Be used for transmitting respectively the data line 171 of data voltage and voltage of power and line of electric force 172 extends longitudinally substantially and intersect with data line 121.

Every data line 171 comprises having the large-area expansion 179 that is used to contact another layer or external devices.The major part of data line 171 is arranged on the viewing area but expansion 179 is arranged on the frontier district.

Every data line 171 towards the first drain electrode 175a protrude a plurality of branches form a plurality of first source electrode 173a.Every line of electric force 172 forms a plurality of second source electrode 173b towards a plurality of branches that the second drain electrode 175b protrudes.Every couple first and second source electrode 173a and the 173b and the first and

second drain electrode

175a and 175b is separated from one another and about the first and

second gate electrode

124a and 124b toward each other.

First grid electrode 124a, the first source electrode 173a and the first drain electrode 175a protrude 154a with first of semiconductor striped 151 and form switching TFT, and the second gate electrode 124b, the second source electrode 173b and the second drain electrode 175b form drive TFT with semiconductor island 154b.Every line of electric force 172 overlapping semiconductor island 154b and storage electrode part 157.

Data line 171, the first and

second drain electrode

175a and 175b and line of electric force 172 comprise Mo or Mo alloy.When they have bilayer or three-decker, can comprise Al or Al alloy.When they had double-decker, Al and Al alloy-layer be deposit below Mo or Mo alloy-layer preferably.When they had three-decker, Al or Al alloy-layer advantageous applications were the middle layer.

Be similar to gate line 121, data line 171, the first and

second drain electrode

175a and 175b and line of electric force 172 have tapered side with respect to substrate 110 surfaces, and its angle of inclination is in the scope of about 30-80 degree.

Ohmic contact 161,163b, 165a and 165b only are arranged between following semiconductor 151,154b and top data line 171, the first and

second drain electrode

175a and 175b and the line of electric force 172, and reduce contact resistance therebetween.Semiconductor striped 151 comprises a plurality of not by the expose portion of data line 171 and first drain electrode 175a covering, for example part between the first source electrode 173a and the first drain electrode 175a.Though semiconductor striped 151 is narrower than data line 171 in most of position, as mentioned above, the width of semiconductor striped 151 is becoming big near gate line 121 places, thereby makes the smooth-shaped on surface, therefore prevents the disconnection of data line 171.

Passivation layer 180 is formed on the expose portion of data line 171, the first and

second drain electrode

175a and 175b, line of electric force 172 and semiconductor 151 and 154b.The low dielectric insulation material that passivation layer 180 preferably forms by the photosensitive organic material with good flat characteristic, by plasma-reinforced chemical vapor deposition (PECVD) is a-Si:C:O and a-Si:O:F for example, or for example inorganic material formation of silicon nitride and monox.

When passivation layer 180 is formed by organic insulation, can below organic insulator, form by the inorganic material extra insulation course made of silicon nitride or monox for example, with contacting of the expose portion that prevents organic layer and

semiconductor

151 and 154b.

Passivation layer 180 has a plurality of contact holes 185,183,181,182 and 189 of the expansion 179 of the expansion 125 that exposes the first drain electrode 175a, the second gate electrode 124b, the second drain electrode 175b, gate line respectively and data line 171.

The contact hole 182 of

passivation layer

180 and 189 exposes the expansion 125 of gate line 121 and the expansion 179 of data line 171.Expansion 125 contacts external drive circuit by contact hole 182 with 189 with 179.Here, asymmetric conducting film (ACF) is arranged between the outlet terminal and

expansion

125 and 179 of external drive circuit, connects and physical attachment with the circuit that improves them.Yet, when and driving circuit when on substrate 110, directly making, gate line 121 and data line 171 can not be connected to driving circuit by contact hole.Sometimes, gate driver circuit is directly made on substrate, and data drive circuit is encapsulated on the substrate 110 with chip form.At this moment, can only form contact hole 189 to expose the expansion 179 of data line 171.

Contact hole 185,183,181,182 and 189 exposes the

expansion

125 and 179 of the first and

second drain electrode

175a and 175b, the second gate electrode 124b and gate line 121 and data line 171.Preferred Al family conductive layer does not expose by contact hole 185,183,181,182 and 189, thereby guarantees to contact with the suitable of the last conductive layer that forms later.When Al family conductive layer exposed by contact hole 185,183,181,182 and 189, expose portion was preferably removed by covering etching (blanket etch).

A plurality of pixel electrodes 901, a plurality of connection auxiliary 902 and a plurality of the contact assist 906 and 908 to be formed on the passivation layer 180.

Pixel electrode 901 is by contact hole 185 physical connections and be electrically connected to the second drain electrode 175b.Each connection auxiliary 902 is passed through contact hole 181 and is connected the first drain electrode 175a and the second gate electrode 124b with 183.

Contact auxiliary

906 and 908 is connected to the expansion 179 of the exposure of expansion 125 that gate line 121 exposes and data line 171 respectively by

contact hole

182 and 189.

Pixel electrode 901, connect auxiliary 902 and contact auxiliary 906 and 908 and have following

film

901p, 902p, 906p and 908p and reach the upward bilayer of

film

901q, 906q and 908q.Here, following

film

901p, 906p and 908p are made by IZO, and

last film

901q, 906q and 908q are made by ITO.

The partition wall of being made by organic insulation or inorganic insulating material 803 is formed on the passivation layer 180 to isolate each organic light-emitting units.Partition wall 803 forms along the border of pixel electrode 901, also to separate the space of having filled luminous organic material 70 around pixel electrode 901.

Organic luminous layer 70 is formed on the pixel electrode 901 and fills the space of being separated by partition wall 803.

Each organic luminous layer 70 is made by the luminescent material of rubescent, green and blue light.The colour organic luminous layer 70 of red, green and blue sequentially and is repeatedly arranged.

Be formed on the partition wall 803 by the made auxiliary electrode 272 of the conductive material with low conductivity of for example metal, to have the pattern identical with partition wall 803.Auxiliary electrode 272 and the common electrode 270 on being formed on auxiliary electrode 272 contact and reduce the resistance of common electrode 270.

Common electrode 270 is formed on partition wall 803, organic luminous layer 70 and the auxiliary electrode 272.Common electrode 270 is made by the low-resistance conductive material of having of for example Al.In the present embodiment, EL display from back side illuminated has been described.But consideration is from the back side or from the luminous EL display in the back side and front, common electrode 270 is formed by the transparent conductive material of for example ITO or IZO.

To describe the manufacture method of Figure 46 in detail to Figure 62 B and Figure 46 and Figure 50 with reference to Figure 51 to tft array panel shown in Figure 50.

Figure 51,53,55,57,59 and 61 illustrates the layout of Figure 46 to the intermediate steps of the manufacture method of tft array panel shown in Figure 50 successively.Figure 52 A, 52B and 52C are respectively the sectional views that tft array panel LIIa-LIIa ', LIIb-LIIb ' and the LIIc-LIIc ' along the line shown in Figure 51 got.Figure 54 A, 54B and 54C are respectively the sectional views that tft array panel LIVa-LIVa ', LIVb-LIVb ' and the LIVc-LIVc ' along the line shown in Figure 53 got.Figure 56 A, 56B, 56C and 56D are respectively the sectional views that tft array panel LVIa-LVIa ', LVIb-LVIb ', LVIc-LVIc ' and the LVId-LVId ' along the line shown in Figure 55 got.Figure 58 A, 58B, 58C and 58D are respectively the sectional views that tft array panel LVIIIa-LVIIIa ', LVIIIb-LVIIIb ', LVIIIc-LVIIIc ' and the LVIIId-LVIIId ' along the line shown in Figure 57 got.Figure 60 A, 60B, 60C and 60D are respectively the sectional views that tft array panel LXa-LXa ', LXb-LXb ', LXc-LXc ' and the LXd-LXd ' along the line shown in Figure 59 got.Figure 62 A and 62B are respectively the sectional views that tft array panel LXIIa-LXIIa ' along the line shown in Figure 61 and line LXIIb-LXIIb ' are got.

At first, as Figure 51 to shown in the 52C, the conducting film sputter and comprises many gate lines 121 of a plurality of first grid electrode 124a, a plurality of second gate electrode 124b and a plurality of storage electrode 133 by this conducting film of photoetching composition with formation on the dielectric substrate 110 of for example clear glass.

Arrive 54C with reference to Figure 53, after sequential deposit gate insulator 140, intrinsic a-Si layer and doping a-Si layer, doping a-Si layer and intrinsic a-Si layer by photoetching to form a plurality of doped semiconductor stripeds 164 and to comprise that first protrudes a plurality of intrinsic semiconductor stripeds 151 of 154a and intrinsic semiconductor island 154b.Gate insulator 140 is preferably made to the silicon nitride of about 5000  by about 2000 , and deposition temperature preferably arrives about 500 ℃ of scopes at about 250 ℃.

Then, to shown in the 56D, deposit comprises the single or multiple lift of Al, Al alloy, Cr, Mo or Mo alloy as Figure 55, and forms the photoresist pattern on conductive layer.By using this photoresist pattern to come the etching conductive layer, comprise many data lines 171 of a plurality of first source electrode 173a, a plurality of first and

second drain electrode

175a and 175b and the many line of electric force 172 that comprise a plurality of second source electrode 173b with formation as etching mask.

Then, do not remove by the doped semiconductor 164 of data line 171, line of electric force 172 and the first and

second leakage deposit

175a and 175b covering by etching, finishing a plurality of Ohmic contact stripeds 161 and

island

165a, 165b and 163b, and expose the part of intrinsic semiconductor striped 151 and island 154b.

After this can carry out oxygen plasma treatment to stablize the exposed surface of

intrinsic semiconductor

151 and 154b.

Then, to shown in the 58D, form passivation layer 180 as Figure 57 by coating organic insulation or deposit inorganic insulating material.Passivation layer 180 by photoetching to form a plurality of contact holes 189,185,183,181 and 182.Contact hole 181,182,185,183 and 189 exposes the first and

second drain electrode

175a and 175b, the second gate electrode 124b, the expansion 125 of gate line and the expansion 179 of data line.

Then, to shown in the 60D, the 901p of lower floor, 902p, 906p and 908p by sputter and photoetching IZO and

upper strata

901q, 902q, 906q and the 908q of ITO form a plurality of pixel electrodes 901, a plurality ofly are connected auxiliary 902 and double-deck a plurality

ofly contact auxiliary

906 and 908 with comprising as Figure 59.

Then, to shown in the 62B, form partition wall 803 and auxiliary electrode 272 as Figure 61 by the photoetching process of using photomask.

Then shown in Figure 46 to 48, form a plurality of luminescent layers 70 and common electrode 270.

The pixel electrode 901 that the EL display can have a single layer structure be connected auxiliary 902 and have a double-deck Ohmic contact auxiliary 906 and 908.To such EL display be described.

Figure 63 is the layout that is used for the tft array panel of electroluminescence (" EL ") display according to another embodiment of the present invention.Figure 64 and 65 is respectively the sectional view that tft array panel LXIV-LXIV ' along the line shown in Figure 63 and line LXV-LXV ' are got.Figure 66 and 67 is respectively the sectional view that tft array panel LXVI-LXVI ' along the line shown in Figure 63 and line LXVII-LXVII ' are got.

When present embodiment was compared with the embodiment of Figure 63 and Figure 67, the pixel electrode 901 that is formed by individual layer was special characters of present embodiment with being connected auxiliary 902.

Figure 63 has individual layer rather than double-deck a plurality of pixel electrode 901 and is connected auxiliary 902 to the EL display shown in Figure 67.Therefore, pixel electrode 901 assists 902 to have the single layer structure of being made by ITO or IZO with being connected.

Pixel electrode 901 is by contact hole 185 physical connections and be electrically connected to the second drain electrode 175b.Connect auxiliary 902 and be connected to the first drain electrode 175a and the second gate electrode 124b.These features are identical with the EL display shown in Figure 46 to 50.

Shown in Figure 66 and 67, passivation layer 180 has the

contact hole

182 and 189 of the expansion 179 of the expansion 125 that exposes gate line respectively and data

line.Contact auxiliary

906 and 908 is connected to the expansion 179 of the exposure of the expansion 125 of exposure of gate line and data line respectively by contact hole 182 and 189.Contact auxiliary 906 and 908 has the bilayer of following

film

906p and 908p and last film 906q and 908q.Here, following

film

906p and 908p are made by IZO, and

last film

906q and 908q are made by ITO.

The present invention can be applied to and use the semi-conductive tft array panel of polysilicon as TFT.

Tft array panel according to the embodiment of the invention will be described below.

Figure 68 is the layout according to the tft array panel of the use polysilicon of the embodiment of the invention.Figure 69,70 and 71 is respectively the sectional view that tft array panel LXIX-LXIX ', LXX-LXX ' and the LXXI-LXXI ' along the line shown in Figure 68 got.

Preferably by monox (SiO ₂) or the barrier film 111 made of silicon nitride (SiNx) be formed on the transparent insulation substrate 110.

A plurality of polysilicon layers 150 are formed on the barrier film 111.This polysilicon layer 150 comprises channel region 154, source region 153 and drain region 155.

The adhesion that improve between dielectric substrate 110 and the polysilicon layer 150 on restraining barrier 111, and stop that the conductive impurity that is included in the dielectric substrate 110 is diffused into polysilicon layer 150.

Preferably the gate insulator of being made by silicon nitride (SiNx) 140 is formed on polysilicon layer 150 and the barrier film 111.

Many the gate lines 121 that extend along a direction are formed on the gate insulator 140.Gate line 121 comprises a plurality of gate electrodes 124 of downward protrusion, with the channel region 154 of overlapping polysilicon layer 150.Light doping section 152 is formed between source region 153 and the channel region 154, and is formed between drain region 155 and the channel region 154.

Many storage electrode lines 131 are formed on the layer identical with gate line 121 and by forming with gate line 121 identical materials.Storage electrode line 131 is parallel with gate line 121.

The part of the storage electrode line 131 of overlapping polysilicon layer 150 will become storage electrode 133.The part of polysilicon layer 150 overlapping storage electrodes 133 will become memory block 157.

Every gate line 121 can have expansion 125 with the contact external circuit.That is, the expansion 125 that forms gate line 121 is to guarantee and the contacting of external circuit.Therefore, when external circuit is made and directly be connected with gate line, do not form expansion 125 on substrate 110.

Interlayer insulating film 601 is formed on gate line 121 and the storage electrode line 131.Interlayer insulating film 601 has first and second contact holes 183 and 184 that expose source region 153 and drain region 155 respectively.

Many data line 171 is formed on the interlayer insulating film 601.Data line 171 intersects to limit pixel region with gate line 121.Every data line 171 comprises the multiple source electrode 173 that is connected to source region 153 by first contact hole 183.Data line 171 has the expansion 179 that is used to connect external circuit.

Drain electrode 175 is formed on the layer identical with source electrode 173 and goes up and separate with source electrode 173.Drain electrode 175 is connected to drain region 155 by second contact hole 184.

Second interlayer insulating film 602 is formed on the

data conductor

171 and 175 and first interlayer insulating film 601.Second interlayer insulating film 602 has a plurality of the 3rd contact holes 185 to expose drain electrode 175.

A plurality of pixel electrodes 901 are formed on second interlayer insulating film 602.

Pixel electrode 902 has the bilayer of following film 901p and last film 901q.Here, following film 901p is made by IZO, and last film 901q is made by ITO.

Shown in Figure 70 and 71, a plurality of contacts auxiliary 906 and 908 are formed on the expansion 179 of the expansion 125 of gate line 121 and data line 171.

The expansion 125 of gate line 121 is formed on the gate insulator 140, and this gate insulator 140 is formed on dielectric substrate 100 and the restraining barrier 111.First and second

interlayer insulating films

601 and 602 are stacked on the expansion 125.First and second

interlayer insulating films

601 and 602 have a plurality of the 4th contact holes 182 of the expansion 125 that exposes gate line 121.Contact auxiliary 906 is passed through the 4th contact hole 182 and is contacted with the expansion 125 of gate line 121.

The expansion 179 of data line 171 is formed on first interlayer insulating film 601 that is formed on the dielectric substrate 110, and on restraining barrier 111 and gate insulator 140.Second interlayer insulating film 602 is formed on the expansion 179.Second interlayer insulating film 602 has a plurality of the 5th contact holes 189 of the expansion 179 that exposes data line 171.Contact auxiliary 908 is passed through the 5th contact hole 189 and is contacted with the expansion of data line 171.

Contact auxiliary 906 and 908 has the bilayer of following

film

906p and 908p and last film 906q and 908q.Here, following

film

906p and 908p are made by IZO, and

last film

906q and 908q are made by ITO.

In the above-described embodiments, all pixel electrodes 901

assist

906 and 908 to have double-decker with contacting.The multi-crystal TFT panel can have double-deck pixel electrode 901 or double-

deck contact auxiliary

906 and 908.

When not forming expansion 125, the contact auxiliary 906 that is formed on the expansion 125 of gate line 121 can not be omitted.

Though described illustrative examples in conjunction with the accompanying drawings, should be appreciated that, the invention is not restricted to these embodiment, and those skilled in the art can carry out various changes and modifications and not break away from category of the present invention or spirit.All these changes and improvements all are included in the category of the present invention that is limited by claims.

In the present invention, pixel electrode forms the bilayer with IZO layer and ITO layer, is destroyed by the ITO etchant to avoid wiring in the overall test process, and prevents to pile up on the probe foreign matter.In the present invention, can only form contact auxiliary is the bilayer with IZO layer and ITO layer, to prevent piling up foreign matter on overall test process middle probe.Because reduced the consumption of ITO, manufacturing cost has reduced.

Claims

1. thin-film transistor display panel comprises:

Dielectric substrate;

First signal wire is formed on the described dielectric substrate and at first direction and extends;

First insulation course is formed on described first signal wire;

The secondary signal line is formed on described first insulation course and with described first signal wire and intersects;

Thin film transistor (TFT) is connected to described first signal wire and secondary signal line;

Second insulation course, first contact hole that is formed on the described thin film transistor (TFT) and has the terminal that exposes described thin film transistor (TFT); With

Pixel electrode is formed on described second insulation course, is connected to described thin film transistor (TFT) by described first contact hole, and has the double-decker that comprises indium zinc oxide layer and indium tin oxide layer.

2. thin-film transistor display panel according to claim 1, wherein said indium zinc oxide layer has the thickness of 500  to 1500 , and described indium tin oxide layer has the thickness of 50  to 250 .

3. thin-film transistor display panel according to claim 2, the thickness of wherein said indium zinc oxide layer are 900 , and the thickness of described indium tin oxide layer is 200 .

4. thin-film transistor display panel according to claim 1, the colored filter that also comprises in the pixel region that the intersection that is arranged on by described first signal wire and secondary signal line limits and cover by second insulation course.

5. thin-film transistor display panel according to claim 1, wherein said second insulation course have second contact hole of the expansion that exposes described first signal wire and expose the 3rd contact hole of the expansion of described secondary signal line, and also comprise:

First contact is auxiliary, is connected to the expansion of described first signal wire by described second contact hole; With

Second contact is auxiliary, is connected to the expansion of described secondary signal line by described the 3rd contact hole.

6. thin-film transistor display panel according to claim 5, wherein said first and second contacts are assisted has the double-decker that comprises indium zinc oxide layer and indium tin oxide layer.

7. thin-film transistor display panel comprises:

Gate line is formed on the dielectric substrate and comprises gate electrode;

Gate insulator is formed on the described gate line;

Semiconductor is formed on the described gate insulator;

Data line comprises the source electrode and intersects to limit pixel region with described gate line;

Drain electrode, towards described source electrode, gapped between described source electrode and the drain electrode on described semiconductor;

Passivation layer, have expose described drain electrode first contact hole;

Pixel electrode is formed on the described passivation layer, is connected to described drain electrode by described first contact hole, and has the double-decker that comprises indium zinc oxide layer and indium tin oxide layer.

8. thin-film transistor display panel according to claim 7 also comprises the storage capacitor conductors that overlaps with described gate line or is formed on storage electrode line on the identical layer with described gate line.

9. thin-film transistor display panel according to claim 8, wherein said storage capacitor conductors is connected with described drain electrode.

10. thin-film transistor display panel according to claim 7, wherein said passivation layer is made by having the chemical vapor deposition layer or the acrylic acid organic material that are lower than 4.0 specific inductive capacity.

11. thin-film transistor display panel according to claim 7, wherein the channel region between described source electrode and drain electrode, described semiconductor has and described data line and the essentially identical pattern of drain electrode.

12. thin-film transistor display panel according to claim 7 wherein also comprises the colored filter that is arranged in the pixel and is covered by described second insulation course.

13. thin-film transistor display panel according to claim 7, wherein said indium zinc oxide layer has the thickness of 500  to 1500 , and described indium tin oxide layer has the thickness of 50  to 250 .

14. thin-film transistor display panel according to claim 13, the thickness of wherein said indium zinc oxide layer are 900 , the thickness of described indium tin oxide layer is 200 .

15. thin-film transistor display panel according to claim 7, wherein said passivation layer have second contact hole of the expansion that exposes described gate line and expose the 3rd contact hole of the expansion of described data line, and also comprise:

First contact is auxiliary, is connected to the expansion of described gate line by described second contact hole; With

Second contact is auxiliary, is connected to the expansion of described data line by described the 3rd contact hole.

16. thin-film transistor display panel according to claim 15, wherein said first and second contacts are assisted has the double-decker that comprises indium zinc oxide layer and indium tin oxide layer.

17. the manufacture method of a thin-film transistor display panel comprises:

On dielectric substrate, form the gate line that comprises gate electrode;

Form the gate insulator that covers described gate line;

On described gate insulator, form semiconductor;

Formation comprise the source electrode and with described gate line data line crossing, with from described source electrode separation and with its about the relative drain electrode of described gate electrode;

The deposit passivation layer;

Described passivation layer of composition and described gate insulator expose described gate line and the expansion of data line and the contact hole of drain electrode to form;

Deposit indium zinc oxide layer and indium tin oxide layer successively; With

The described indium zinc oxide layer of photoetching is assisted with contacting with indium tin oxide layer is connected respectively to the described drain electrode and the expansion of described gate line and data line with formation pixel electrode,

Wherein, described indium zinc oxide layer and indium tin oxide layer are by the indium zinc oxide etchant etching that contains HCl.

18. method according to claim 17, wherein said indium zinc oxide etchant comprises HCl, CH ₃COOH, deionized water and surfactant.

19. method according to claim 17, wherein said data line and semiconductor by use have first, be thicker than the second portion of described first, the photoetching process of photoresist pattern that is thinner than the third part of described first forms.

20. method according to claim 19, wherein said first is arranged on the zone between described source electrode and the drain electrode, and described second portion is arranged on described data line and the drain electrode.

21. the manufacture method of a thin-film transistor display panel comprises:

On dielectric substrate, form the gate line that comprises gate electrode;

Form the gate insulator that covers described gate line;

On described gate insulator, form semiconductor;

On described gate insulator, form the data line comprise the source electrode with described source electrode separation and relative drain electrode;

Use comprises that the photo anti-corrosion agent material of red, green and blue pigment forms colored filter on described data line, and described colored filter has first opening that exposes the described drain electrode of at least a portion;

Deposit passivation layer on described colored filter;

The described passivation layer of composition is to form first contact hole to expose the described drain electrode of at least a portion in described first opening; With

Formation is connected to the pixel electrode of described drain electrode by described first contact hole,

The step that wherein forms described pixel electrode comprises in turn deposit indium zinc oxide layer and indium tin oxide layer and with the described indium zinc oxide layer of indium zinc oxide etchant photoetching and the indium tin oxide layer that comprise HCl.

22. method according to claim 21, the step that also is included in described formation colored filter forms the interlayer insulating film of silicon nitride or monox before.

23. method according to claim 21, wherein said indium zinc oxide etchant comprises HCl, CH ₃COOH, deionized water and surfactant.

24. a thin-film transistor display panel comprises:

Gate line is formed on the dielectric substrate and comprises gate electrode;

Gate insulator is formed on the described gate line;

Semiconductor is formed on the described gate insulator;

Drain electrode is formed on the layer identical with described data line, and towards described source electrode, gapped between described drain electrode and the source electrode;

Passivation layer has first contact hole that exposes described drain electrode;

Pixel electrode is formed on the described passivation layer, is connected to described drain electrode by first contact hole;

Contact is auxiliary, is used for the expansion of described gate line and data line is connected to external circuit,

Wherein said contact is assisted has the double-decker that comprises indium zinc oxide layer and indium tin oxide layer.

25. thin-film transistor display panel according to claim 24, wherein said indium tin oxide layer are arranged on the described indium zinc oxide layer.

26. a LCD comprises:

Thin-film transistor display panel comprises the gate line that is formed on the dielectric substrate and comprises gate electrode; Be formed on the gate insulator on the described gate line; Be formed on the semiconductor on the described gate insulator; Comprise the source electrode and intersect to limit the data line of pixel region with described gate line; Be formed on the identical layer with described data line and with the relative drain electrode of described source electrode, gapped between described source electrode and the described drain electrode; Passivation layer with first contact hole that exposes described drain electrode; Be formed on the pixel electrode on the described passivation layer, be connected to described drain electrode by described first contact hole; It is auxiliary to be used for that the expansion of described gate line and data line is connected to contacting of external circuit, and wherein said contact is assisted has the double-decker that comprises indium zinc oxide layer and indium tin oxide layer;

The colorful optical filter array panel is towards described thin-film transistor display panel and comprise common electrode; With

Liquid crystal layer is inserted between described thin-film transistor display panel and the described colored filter panel.

27. the manufacture method of a LCD comprises:

On first dielectric substrate, form the gate line that comprises gate electrode;

Form the gate insulator that covers described gate line;

On described gate insulator, form semiconductor;

Formation has the passivation layer of first contact hole that exposes described drain electrode;

Formation is connected to the pixel electrode of described drain electrode by described first contact hole, and contacting of external circuit is auxiliary with the expansion of described drain electrode and gate line and data line is connected to;

On second dielectric substrate, form common electrode;

Between described first substrate and second substrate, inject liquid crystal material and seal described liquid crystal material; With

On described contact is auxiliary, form indium tin oxide layer.

28. method according to claim 27, wherein said indium tin oxide layer by use have shadow mask corresponding to the auxiliary opening of described contact be formed on described contact auxiliary on.

29. method according to claim 27, wherein said indium tin oxide layer is formed on described contact by evaporation and assists.

30. method according to claim 27, wherein said evaporation are carried out at assembling described first substrate and second substrate, after injecting liquid crystal material and motherboard being cut into all technologies of unit.

31. a thin-film transistor display panel comprises:

First semiconductor and second semiconductor have first raceway groove and second channel part on the dielectric substrate of being formed on respectively;

Gate line comprises the first grid electrode of described first channel part that overlaps;

Second gate electrode covers described second channel part;

Gate insulator is arranged between described first semiconductor and second semiconductor and the described first grid electrode and second gate electrode;

Data line comprises the first source electrode that contacts with described first semiconductor;

First drain electrode, towards the described first source electrode and be connected to described second gate electrode, described first channel part is arranged between described first drain electrode and the described first source electrode;

The second source electrode adjoins described second channel part;

Second drain electrode, adjoin described second channel part and about described second channel part towards the described second source electrode;

Pixel electrode is connected to described second drain electrode and is arranged on the pixel region that is surrounded by described gate line and data line;

Partition wall has the described pixel electrode opening of exposure;

Auxiliary electrode is formed on the described partition wall and has and the essentially identical pattern of described partition wall;

Organic luminous layer is formed on the described pixel electrode and is filled in the opening of described partition wall;

Common electrode covers described auxiliary electrode and organic luminous layer; With

Contact is auxiliary, is connected to the expansion of described gate line and data line,

32. thin-film transistor display panel according to claim 31, wherein said indium tin oxide layer are arranged on the described indium zinc oxide layer.

33. thin-film transistor display panel according to claim 31, wherein said pixel electrode has the double-decker that comprises indium zinc oxide layer and indium tin oxide layer.

34. thin-film transistor display panel according to claim 33, the indium tin oxide layer of wherein said pixel electrode are arranged on the indium zinc oxide layer of described pixel electrode.

35. the manufacture method of a thin-film transistor display panel comprises:

On dielectric substrate, form first semiconductor and second semiconductor of making by polysilicon or amorphous silicon;

Formation comprises the gate line of the first grid electrode and second gate electrode;

Formation is arranged on the gate insulator between described first semiconductor and second semiconductor and the described first grid electrode and second gate electrode;

On described gate insulator, form the first and second source electrodes, data line, first and second drain electrodes and line of electric force;

Form the interlayer insulating film that covers the described first and second source electrodes, described data line, described first and second drain electrodes and described line of electric force;

It is auxiliary that formation is connected to contacting of the pixel electrode of described second drain electrode and the expansion that is connected to described gate line and data line on described interlayer insulating film;

Formation has the partition wall that is used to expose described pixel electrode opening;

On described partition wall, form auxiliary electrode;

On described pixel electrode, form organic luminous layer to fill the opening of described partition wall;

On described auxiliary electrode and organic luminous layer, form common electrode;

36. method according to claim 35, wherein said indium tin oxide layer are arranged on the described indium zinc oxide layer.

37. method according to claim 36, wherein said pixel electrode has the double-decker that comprises indium zinc oxide layer and indium tin oxide layer.

38. according to the described method of claim 37, the indium tin oxide layer of described pixel electrode is arranged on the indium zinc oxide layer of described pixel electrode.

39. a thin-film transistor display panel comprises:

Dielectric substrate;

The restraining barrier is formed on the described dielectric substrate;

Polysilicon layer is formed on the described restraining barrier;

Gate insulator is formed on the described polysilicon layer;

Gate line is formed on the described gate insulator;

First interlayer insulating film is formed on the described gate line;

First and second contact holes are formed in described first interlayer insulating film and expose the source region and the drain region of described polysilicon layer;

Data line comprises the source electrode that is connected to described source region by described first contact hole;

Drain electrode is connected to described drain region by second contact hole;

Second interlayer insulating film is formed on described data line and the drain electrode and has the 3rd contact hole that exposes described drain electrode;

Pixel electrode is formed on described second interlayer insulating film, is connected to described drain electrode by described the 3rd contact hole, and has the double-decker that comprises indium zinc oxide layer and indium tin oxide layer.

40. according to the described thin-film transistor display panel of claim 39, wherein said first and second interlayer insulating films have the 4th contact hole of the expansion that exposes described gate line, and second interlayer insulating film has the 5th contact hole of the expansion that exposes described data line, also comprises:

First contact is auxiliary, is connected to the expansion of described gate line and has the double-decker that comprises indium zinc oxide layer and indium tin oxide layer by the 4th contact hole; With

Second contact is auxiliary, is connected to the expansion of described data line and has the double-decker that comprises indium zinc oxide layer and indium tin oxide layer by the 5th contact hole.

41. according to claim 39 or 40 described thin-film transistor display panels, wherein said indium tin oxide layer is arranged on the described indium zinc oxide layer.