CN1877688B - Display device - Google Patents

Display device Download PDF

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Publication number
CN1877688B
CN1877688B CN2006100996319A CN200610099631A CN1877688B CN 1877688 B CN1877688 B CN 1877688B CN 2006100996319 A CN2006100996319 A CN 2006100996319A CN 200610099631 A CN200610099631 A CN 200610099631A CN 1877688 B CN1877688 B CN 1877688B
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CN
China
Prior art keywords
gate
display device
level
voltage
signal
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Expired - Fee Related
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CN2006100996319A
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Chinese (zh)
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CN1877688A (en
Inventor
朴大真
张在爀
全亨一
李钟焕
林都基
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Samsung Display Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020050074963A external-priority patent/KR20070020746A/en
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Publication of CN1877688A publication Critical patent/CN1877688A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Abstract

The present invention relates to a display device, and more particularly to a display device in which gate lines and a main gate driver can be repaired. The display device includes a plurality of pixels respectively including a switching element, a gate line connected to the switching element, and first and second gate drivers respectively including a plurality of stages that are interconnected and sequentially generate output signals. Any one of the stages of the first gate driver and any one of the stages of the second gate driver are connected to the same gate line. In this manner, gate drivers that generate the same output are disposed in one gate line on the left and right sides. It is therefore possible to repair disconnected gate lines without using a laser.

Description

Display device
The cross reference of related application
The application requires respectively on June 7th, 2005 and on August 16th, 2005 right of priority to the korean patent application of korean industrial property office submission 10-2005-0048299 number and 10-2005-0074963 number, and its content comprises with way of reference at this.
Technical field
The present invention relates to a kind of display device.
Prior art
Develop the flat-panel monitor such as Organic Light Emitting Diode (OLED) display, plasma display panel (PDP) and LCD (LCD) effectively, be used for substituting heavy and bulky cathode ray tube (CRT).PDP is by adopting Plasma Display character and/or the image that is produced by gas discharge.The OLED display comes character display and area image by adopting the electric field by specific organism or condensate emission.Thereby LCD is come display image by applying liquid crystal layer between electric field to two display board and the control electric field intensity control transmittance by liquid crystal layer.
The dual screen that is used for mobile phone or the like does not comprise inner main display board unit and the outside secondary display board of installing fully.Flexible print circuit (FPC) film receives external input signal, and secondary FPC connects main display board and the secondary display board unit of being controlled by integrated chip.Each aforesaid equipment all comprises display board, a large amount of pixel, gate drivers and data driver, and wherein each pixel all has on-off element and display signal line.Be used for controlling the gate drivers of main display board unit and secondary display board unit and the integrated chip of data driver is installed in the main display board unit with glass-based chip (COG) form usually.A plurality of shift register stage that gate drivers comprises interconnection and becomes a row to be provided with.
In order to proofread and correct manufacturing defect such as signal wire that disconnects or the like, repair line for many and be set at the outer peripheral areas viewing area outside, wherein these patch cords are connected to the left side and the right side of the gate line of a plurality of disconnections, and signal is applied in to the reparation line.Must use amplifying lens to seek the line that disconnects, afterwards, use laser to repair the part of disconnection.In addition, the quantity that may be arranged in the reparation line of outer peripheral areas is restricted, and this makes can not repair a plurality of breaking parts.But the defective in any transistor all is not easy to repair.
Summary of the invention
The invention provides a kind of demonstration and be not equipped with, wherein can not use laser to repair gate line, and can utilize the assistant grid driver to repair the main grid driver.The second level of the first order of first grid driver and second grid driver is connected to identical gate line, and on-off element is between the first order and the second level, therefore, then produce output by the second level that is connected to failure level through identical gate line if any one first order breaks down and makes and can not produce output.
Description of drawings
According to the description of reading in conjunction with the accompanying drawings subsequently, it is more obvious that aforesaid purpose and feature will become, wherein:
Fig. 1 is the synoptic diagram according to the LCD of one exemplary embodiment of the present invention.
Fig. 2 is the calcspar according to the LCD of one exemplary embodiment of the present invention.
Fig. 3 is the equivalent circuit diagram that illustrates according to a pixel of the LCD of one exemplary embodiment of the present invention.
Fig. 4 is the calcspar according to the gate drivers of one exemplary embodiment of the present invention.
Fig. 5 is the exemplary circuit diagram of j level that is used for the shift register of gate drivers shown in Figure 4.
Fig. 6 is the signal waveforms of gate drivers shown in Figure 4.
Fig. 7 is the calcspar according to the gate drivers of another exemplary embodiment of the present invention.
Fig. 8 is illustrated in the view of repairing an example of gate drivers in the calcspar shown in Figure 7.
Embodiment
The thickness of layer is exaggerated in the accompanying drawings.In whole instructions, identical reference marker is represented components identical.When being described to that for example any part of layer, film, zone or plate is positioned on another part, then represent this part be located immediately on another part or above another part and the centre accompany at least one pars intermedia.On the other hand, be located immediately on another part if be described to any part, then being illustrated between these two parts does not have center section.
In Fig. 1, except as otherwise noted, otherwise gate drivers 400 can be gate drivers 400RM, gate drivers 400LM or gate drivers 400S.This display device comprises main display board unit 300M, secondary display board unit 300S, is attached to the FPC 650 of main display board unit 300M, between main display board unit 300M and secondary display board unit 300S attached secondary FPC 680, and be installed in integrated chip 700 on the display board unit 300M.
FPC 650 is attached near the side of main display board unit 300M.And FPC 650 has opening 690, and when FPC650 was folded, this opening can expose the part of main display board unit 300M.Importation 660 is positioned at opening 690 belows, and wherein external signal is input to importation 660.FPC 650 also comprises a plurality of signal wire (not shown), and these signal wires are used to be electrically connected other parts and the integrated chip 700 of importation 660, and is electrically connected integrated chip 700 and main display board unit 300M.These signal wires are connected to the point of integrated chip 700 and some place that they are attached to main display board unit 300M has wide width at them, thereby form the pad (not shown).
Secondary FPC 680 is attached between the side of the opposite side of main display board unit 300M and secondary display board unit 300S, and comprises signal wire SL2 and the DL that is used to be electrically connected integrated chip 700 and secondary display board unit 300S.Display board unit 300M comprises viewing area 310M and the outer peripheral areas 320M that forms screen.Outer peripheral areas 320M can comprise the light shielding layer (not shown) (" black matrix" ") that is used for shielded from light.And display board unit 300S comprises viewing area 310S and the outer peripheral areas 320S that forms screen.Outer peripheral areas 320S can comprise the light shielding layer (not shown) (" black matrix" ") that is used for shielded from light.FPC 650 and secondary FPC 680 are attached to outer peripheral areas 320M and 320S.
As shown in Figure 2, each display board unit 300M and 300S comprise having a plurality of gate lines G 1-G nAnd a plurality of data line D 1-D mA plurality of display signal lines, be connected to gate line and data line and show a plurality of pixel PX that matrix form arranges greatly and provide signal to gate lines G 1-G nGate drivers 400.Most pixel PX and display signal line G 1-G nAnd D 1-D mAll be positioned at viewing area 310M and 310S.Gate drivers 400M and 400S are arranged in outer peripheral areas 320M and 320S.Outer peripheral areas 320M and 320S on that side that gate drivers 400M and 400S are positioned at have more bigger width.
As shown in Figure 1, the data line D of main display board unit 300M 1-D mA part be connected to secondary display board unit 300S by secondary FPC 680.Just, two display board unit 300M and 300S shared data line D 1-D mA part.In Fig. 1, one of data line is illustrated as DL.Upper board 200 is less than lower panel 100, so outside a part of zone of lower panel 100 is exposed to.Data line D 1-D mExtend up to this zone, be connected to data driver 500 then.Gate lines G 1-G nAlso extend up to the zone that is coated with outer peripheral areas 320M and 320S, be connected to gate drivers 400RM, 400LM and 400S then.
Display signal line G 1-G nAnd D 1-D mThe point that is connected to FPC 650 and 680 at them has wide width, thereby forms the pad (not shown).Display board unit 300M and 300S and FPC 650 and 680 are adhered to by the anisotropic conductive layer (not shown), to be electrically connected pad.Each pixel PX (for example, be connected to i (i=1,2 ..., n) gate lines G iAnd j (j=1,2 ..., m) data line D jPixel PX) all comprise and be connected to signal wire G iAnd D jOn-off element Q, and the liquid crystal capacitor Clc and the holding capacitor Cst that are connected to on-off element Q.If suitable, can save holding capacitor Cst.
On-off element Q can be the three-terminal element that provides in the lower panel 100, for example thin film transistor (TFT).On-off element Q has the gate lines G of being connected to iControl end, be connected to data line D jInput end and be connected to liquid crystal capacitor Clc and the output terminal of holding capacitor Cst.The pixel electrode 191 of liquid crystal capacitor Clc use lower panel 100 and the common electrode 270 of upper board 200 are as two terminals.Liquid crystal layer 3 between two electrodes 191 and 270 is as dielectric material.Pixel electrode 191 is connected to on-off element Q.Common electrode 270 is formed on the whole surface of upper board 200 and receives common voltage Vcom.With shown in Figure 2 different, common electrode 270 can be arranged in lower panel 100.In this case, at least one in two electrodes 191 and 270 can have linear or shaft-like shape.
Be used for assisting the holding capacitor Cst of liquid crystal capacitor Clc that additional signal lines (not shown) and the pixel electrode 191 that provides in the lower panel 100 is provided, wherein overlapping between lower panel and pixel electrode have an insulator.Common voltage Vcom is applied to this additional signal lines.But in holding capacitor Cst, pixel electrode 191 can be overlapping with that gate line directly over the previous gate line by effect in the middle of the insulator.
In order to realize colored the demonstration, each pixel PX can a kind of primary colours of unique demonstration (spatial division), perhaps each pixel PX can be according to time-interleaved ground display primary (time division), and the summation of room and time that therefore can be by primary colours is discerned needed color.An example of primary colours can comprise for example three kinds of primary colours of red, green and blue look.As an example of spatial division, Fig. 3 shows the example that each pixel PX has color filter 230, and wherein color filter demonstrates a kind of primary colours on the zone corresponding to the upper board 200 of pixel electrode 191.Different with Fig. 3, color filter 230 can be formed on the pixel electrode 191 of lower panel 100 or down.At least one polariscope (not shown) of polarized light is attached to the outside of liquid crystal board assembly 300.
Grey scale voltage generator 800 produces two groups of gray-scale voltages (perhaps reference gray level step voltage), and wherein these two groups of gray-scale voltages are relevant with the transmittance of pixel PX.In two groups one group have about common voltage Vcom on the occasion of, and another group in two groups has the negative value about common voltage Vcom.
Gate drivers 400RM, 400LM and 400S are connected to gate lines G 1-G n, and applying signal, this signal is the gate turn-on voltage Von that can connect on-off element Q and the combining of gate off voltage Voff that can stopcock element Q.Gate drivers 400RM, 400LM and 400S utilize the technology identical with the on-off element Q of pixel and formation and integrated easily, and are connected to integrated chip 700 by signal wire SL1 and SL2.Gate drivers 400RM and 400LM lay respectively at right side and the left side of main display board unit 300M, and are connected to identical gate lines G 1-Gn.Gate drivers 400RM carries out identical operations with 400LM according to the identical signal that comes self integrated chip 700.In secondary display board 300S, gate drivers 400S also can be positioned on the right side.
Data driver 500 is connected to the data line D of liquid crystal board assembly 300 1-D mData driver 500 is selected from the gray-scale voltage of grey scale voltage generator 800 outputs, and it is applied to data line D 1-D mAs data-signal.But, do not provide the voltage of whole gray level at grey scale voltage generator 800 and only provide under the situation of reference gray level step voltage of predetermined quantity, data driver 500 splits the reference gray level step voltage, producing the gray-scale voltage of all gray levels, and from the gray-scale voltage that produces, select data-signal.
Signal controller 600 control gate drivers 400, data driver 500 or the like.Integrated chip 700 receives external signal by the signal wire that provides among importation 660 and the FPC 650, and the wiring that provides among outer peripheral areas 320M by main display board voltage 300M and the secondary FPC 680, the signal of handling is offered main display board unit 300M and secondary display board unit 300S, thus control main display board unit 300M and secondary display board unit 300S.Integrated chip 700 comprises the grey scale voltage generator 800 shown in Fig. 2, data driver 500, signal controller 600 or the like.
To describe the display operation that makes up the LCD that forms according to top description below in detail.Signal controller 600 receives received image signal R, G and B from the external graphics controller (not shown), and receives the input control signal of the demonstration that is used to control these signals.The example of input control signal can comprise vertical synchronizing signal Vsync, horizontal-drive signal Hsync, master clock signal MCLK and data enable signal DE or the like.Signal controller 600 is handled received image signal R, G and B according to received image signal R, G and B and input control signal in the mode of the operating conditions that is suitable for liquid crystal board assembly 300, and generation grid control signal CONT1, data controlling signal CONT2 or the like, grid control signal CONT1 is transferred to gate drivers 400, and data controlling signal CONT2 and processed images signal DAT are transferred to data driver 500.
Grid control signal CONT1 comprises the scan start signal STV that beacon scanning starts, and at least one clock signal in the output cycle of control gate turn-on voltage Von.Grid control signal CONT1 can also comprise that output enable signal (OE) is to limit keeping the cycle of gate turn-on voltage Von.Data controlling signal CONT2 comprises horizontal synchronization enabling signal STH, be written into signal LOAD and data clock signal HCLK offers data line D with the designation data signal 1-D m, wherein horizontal synchronization enabling signal is informed one-row pixels PX with the startup of image data transmission.Data controlling signal CONT2 can also comprise the reverse reverse signal RVS of the polarity of voltage of the data-signal that is used to be used in common voltage Vcom (below, " polarity of voltage that is used for the data-signal of common voltage " will be reduced to " polarity of data-signal ").
Data driver 500 is in response to from the data controlling signal CONT2 of signal controller 600 and receive data image signal DAT about one-row pixels PX, selection is corresponding to the gray-scale voltage of each data image signal DAT, DAT converts analog data signal to data image signal, then the signal that is converted is imposed on corresponding data line D 1-D mGate drivers 400 is in response to from the grid control signal CONT1 of signal controller 600 and gate turn-on voltage Von is imposed on gate lines G 1-G nThereby, connect and be connected to gate lines G 1-G nOn-off element Q.Therefore, impose on data line D 1-D mData-signal be applied to corresponding pixel PX by the on-off element Q that connects.
Be applied to voltage and the charging voltage that the difference between the common voltage Vcom shows as liquid crystal capacitor Clc, the just pixel voltage of the data-signal of pixel PX.Liquid crystal molecule comes directed according to the pixel voltage amount, therefore correspondingly change the polarity by the light of liquid crystal layer 3.Variation in this polarity by the polariscope that is attached to display plate component 300 show as optical transmission than in variation.
Repeat these processes at each horizontal cycle (this is also referred to as " 1H ", and is identical with the one-period of horizontal-drive signal Hsync and data enable signal DE), gate turn-on voltage Von is applied to all gate lines G subsequently 1-G n, and data-signal is applied in to all pixel PX, thus show the image of a frame.When finishing a frame, next frame begins, and is applied to the state Be Controlled (image is anti-phase) of the inversion signal RVS of data driver 500, and therefore, the polarity that offers the data-signal of each pixel PX becomes opposite with the former frame image.At this moment, flow through a data line data-signal polarity can according in addition a frame in the characteristic of inversion signal RVS be changed that (for example: row is anti-phase, point is anti-phase), perhaps be applied to a pixel column data-signal polarity can according in addition a frame in the characteristic of inversion signal RVS and difference (for example: be listed as anti-phasely, point is anti-phase).
With the display device of describing in detail according to exemplary embodiment of the present invention with reference to figure 4 to 6 below.Gate drivers 400L shown in Figure 4 and 400R series connection are arranged on left side and right side, and are the shift registers that comprises a plurality of grades of 410L and 410R respectively, and wherein these a plurality of levels are connected to gate lines G 1-G nScan start signal STV, a plurality of clock signal clk 1 and CLK2 and gate off voltage Voff are input to gate drivers 400L and 400R respectively.Each grade 410L and 410R have set terminal S, grid voltage terminal GV, a pair of clock terminal CK1 and CK2, reseting terminal R, grid lead-out terminal OUT1 and carry lead-out terminal OUT2.These two lead-out terminal OUT1 and OUT2 are connected respectively to impact damper BF1 and BF2.
To this set terminal S of each grade (for example, being positioned at the left side or the j level STj on right side) the carry output of input previous stage ST (j-1) is (just, last advanced potential output Cout (j-1)), carry to its reseting terminal R input back one-level ST (j+1) is exported (just, back one carry output Cout (j+1)), to its clock terminal CK1 and CK2 input clock signal CLK1 and CLK2, and to grid voltage end GV input gate off voltage Voff.Two output terminal OUT1 and OUT2 export Gout (N) and carry output Cout (N) respectively by grid impact damper BUF and carry impact damper CARRY.Grid output Gout (j) outputs to the gate lines G that is connected thereto 1-G nCarry output Cout (j) output to preceding and after level ST (j-1) and ST (j+1).
Grid output before scan start signal STV replaces is applied to the first order, ST1.If the clock end CK1 to j level ST (j) applies clock signal clk 1, and the clock end CK2 to it applies clock signal clk 2, then apply clock signal clk 2, and apply clock signal clk 1 to its clock end CK2 to clock end CK1 with (j-1) of j level ST (j) adjacency level and (j+1) level ST (j-1) and ST (j+1).When clock signal CLK1 and CLK2 have high voltage level, each clock signal clk 1 can be preferably identical with gate turn-on voltage Von with CLK2, and when hour hands signal CLK1 and CLK2 have low voltage level, each clock signal clk 1 can be preferably identical with gate off voltage Voff with CLK2, thereby it can drive the on-off element Q of this pixel.As shown in Figure 6, each clock signal clk 1 and CLK2 can have 50% duty ratio, and the phase differential between two clock signal clks 1 and CLK2 can be 180 °.
With reference to figure 5, comprise a plurality of nmos pass transistor T1-T10 and capacitor C1-C3 according to each level (for example, j level) of the gate drivers 400 of one exemplary embodiment of the present invention.But, should be understood that the PMOS transistor can be used for shape for nmos pass transistor.And capacitor C1-C3 can be the stray capacitance between grid and the drain/source, and it can form in building process.
Transistor T 1 is connected between clock end CK1 and the output terminal OUT1, and has the control end that is connected to node J1.Transistor T 2 has input end and the control end that is connected to set terminal S jointly, and has the output terminal that is connected to node J1.Transistor T 3 and T4 are connected in parallel between node J1 and the grid voltage end GV.Transistor T 3 has the control end that is connected to reset terminal R, and transistor T 4 has the control end that is connected to node J2.Transistor T 5 and T6 are connected in parallel between output terminal OUT1 and the grid voltage end GV.Transistor T 5 has the control end that is connected to node J2, and transistor T 6 has the control end that is connected to clock end CK2.Transistor T 7 is connected between node J2 and the grid voltage end GV, and has the control end that is connected to node J1.Transistor T 8 is connected between clock end CK1 and the output terminal OUT2, and has the control end that is connected to node J1.Transistor T 9 and T10 are connected in parallel between output terminal OUT2 and grid voltage end GV.Transistor T 9 has the control end that is connected to clock end CK2, and transistor T 10 has the control end that is connected to node J2.
Capacitor C1 is connected between clock end CK1 and the node J2, and capacitor C2 is connected between node J1 and the output terminal OUT1, and capacitor C3 is connected between node J1 and the output terminal OUT2.
Below will by j level STj as an example describe according to foregoing constructed the level operation.For convenience of explanation, not high voltage with vacation corresponding to the clock signal clk 1 of high level and the voltage of CLK2, identical with gate off voltage Voff corresponding to the voltage of low level clock signal clk 1 and CLK2, wherein gate off voltage will be called as low-voltage.If clock signal clk 2 and the output Gout of grid before (j-1) are high, transistor T 2, T6 and T9 are switched on so.Transistor T 2 is sent to node J1 with high voltage, thereby connects transistor T 7.Transistor T 6 and T9 send low-voltage to output terminal OUT1 and OUT2 respectively.When connecting, transistor T 7 sends low-voltage to node J2.Transistor T 1 and T8 connect then, so clock signal clk 1 outputs to output terminal OUT1 and OUT2.At this moment, because clock signal clk 1 is low, so grid output Gout (j) and carry output Cout (j) become low.Simultaneously, why capacitor C1 is not recharged is because of identical at the voltage at its two ends, and capacitor C2 and C3 are charged to the voltage corresponding to the difference between this high low-voltage.At this moment, because clock signal clk 1 and the output Cout of carry afterwards (j+1) are low and node J2 also is low, so the transistor T 3 that its control end is connected thereto, T4, T5 and T10 keep turn-offing.
After this, if clock signal clk 2 and before carry output Cout (j-1) become low-voltage, transistor T 6 and T9 and transistor T 2 are turned off so.Therefore, two the capacitor C2 and the C3 that all have an end to be connected to node J2 float, and therefore transistor T 1 and T8 keep connecting.At this moment, clock signal clk 1 becomes height, and two output terminal OUT1 and OUT2 become height, the electromotive force of node J1 by capacitor C2 and C3 increase with this high voltage as many.Illustrate in Fig. 6, the electromotive force of node J1 is identical with voltage before.But in fact, this electromotive force increase and this high voltage are as many.
At this moment, because output Cout (j+1) of carry afterwards and node J2 are low, so transistor T 5, T6, T9 and T10 also keep turn-offing.Therefore, two output terminal OUT1 and OUT2 only are connected to clock signal clk 1 and isolate with low-voltage.Therefore, two output terminal OUT1 and OUT2 output HIGH voltage.On the other hand, capacitor C1 is charged to the voltage corresponding to the electric potential difference between the two ends.
After this, if carry afterwards output Cout (j+1) and clock signal clk 2 become height, and clock signal clk 1 become low, transistor T 3 shutoffs and send low-voltage to node J1 so.Therefore, the transistor T 7 that control end is connected to node J1 turn-offs, and capacitor C1 becomes and floats.And node J2 remains low-voltage (voltage before just).At this moment, because clock signal clk 1 is low, so become 0V at the voltage at capacitor C1 two ends.
Simultaneously, because transistor T 1 and T8 turn-off, thus two output terminal OUT1 and be connected disconnections of OUT2 to clock signal CLK1, and owing to transistor T 6 and T9 connection, so two output terminal OUT1 and OUT2 are connected to low-voltage, thus output LOW voltage.After this, if clock signal clk 1 becomes height, so when the voltage shift of the end of capacitor C1 during to high voltage, in the voltage shift of the other end (node J2 just) of capacitor C1 to high voltage.Therefore, the voltage at the two ends of capacitor C1 remains on OV.Therefore, because transistor T 4 connects and low-voltage is sent to node J1, so two transistor Ts 1 and T8 keep turn-offing.And, because two transistor Ts 5 and T10 connect and send low-voltage to two output terminal OUT1 and OUT2 respectively, so output terminal OUT1 and OUT2 continue output LOW voltage.
Then, the voltage of node J1 remains low-voltage, and the carry output Cout (j-1) up to before becomes height.The voltage of node J2 is synchronous with clock signal clk 1 because of capacitor C1, and therefore is changed.Therefore, when clock signal CLK1 is height and a clock signal clk 2 when low, output terminal OUT1 and OUT2 are connected to low-voltage by transistor T 5 and T10, and when clock signal CLK1 be low and clock signal clk 2 when high, output terminal OUT1 and OUT2 are connected to low-voltage by transistor T 6 and T9.In this way, each grade 410L and 410R export Cout (j+1) and synchronously produce grid output Gout (j) with clock signal clk 1 and CLK2 based on before carry output Cout (j-1) and carry afterwards.
Return Fig. 4, be positioned at the grid and the driver 400L in left side and be positioned at the gate drivers 400R on right side symmetrical.Be positioned at each grade 410L of gate drivers 400L on the left side all be connected to be positioned at the right side on the identical gate lines G of each grade 410R of gate drivers 400R 1-G J+1For example, as can be seen, if the 3rd gate lines G 3With (j+1) gate lines G J+1Be disconnected as shown in Figure 4, so the identical signal that provides from the left and right sides of breaking part op.Therefore, do not need to repair gate lines G 1-G nAdditional step (just, use laser repairing).Just because of this, although than the more gate lines G of repairing line 1-G nDisconnect (for example, all gate lines G 1-G nDisconnect), but they still can all be repaired.Therefore, saved and repaired required time and cost, and improved throughput rate.And, using glass material (for example, plastics) in addition to form under the situation of substrate, use laser emission is repaired normally inconvenient.One embodiment of the present of invention can address this problem.
Describe display device in detail below with reference to Fig. 7 and Fig. 8 according to another exemplary embodiment of the present invention.Fig. 7 is the calcspar according to the gate drivers of another exemplary embodiment of the present invention, and Fig. 8 is an example of gate drivers is repaired in explanation in a calcspar shown in Figure 7 view.Gate drivers 400L shown in Figure 7 and 400R are substantially the same with gate drivers 400L and 400R shown in Figure 4.In other words, gate drivers 400L and 400R lay respectively on left side and the right side, and are to comprise a plurality of gate lines G that are connected to respectively 1-G nThe shift register of level 410L and 410R.Apply scan start signal STV, a plurality of clock signal clk 1 and CLK2 to gate drivers 400L and 400R respectively, and gate off voltage Voff.But scan start signal STV is not input to the assistant grid driver 400R that is positioned on the right side, and this is different from gate drivers 400L and 400R shown in Figure 4.Switch element SW is arranged at each gate lines G near assistant grid driver 400R 1-G nIn.
Describe for example method of the failure level of j level STj of reparation in detail below with reference to Fig. 8.In order better to understand and to be convenient to not shown scan start signal STV, clock signal clk 1 and CLK2, and gate off voltage Voff are described.And, in Fig. 7, represent by " x " LC, and represent by " triangle " LS by the part that laser emission is shortened by the part of laser emission cutting.The assistant grid driver 400R that is positioned at the main grid driver 400L on the left side and is positioned on the right side is symmetrical.Each grade 410R of each grade 410L of main grid driver 400L and the gate drivers 400R relative with level 410L is connected to identical gate lines G J-2-G J+2As mentioned above, switch element SW is provided with near assistant grid driver 400R.Switch element SW keeps turn-offing during normal operations, and can connect when appropriate.Can apply the additional control signal of the operation that is used for switch element SW.With above-described difference, the gate lines G between main grid driver 400L and assistant grid driver 400R 1-G nCan in off-state, form, and can connect by utilizing the necessary part of laser emission.Each grade ST (j-2)-ST (j+2) comprises the first end line TL that is connected between switch element SW and the output terminal OUT1 1, be connected to the second end line TL of output terminal OUT2 2, and be connected respectively to the second end line TL 2And be also connected to before and afterwards the level signal wire SL J-1, SL jAnd SL J+1
At this moment, be positioned at (j-1) gate lines G J-1Switch element SW and be positioned at the j gate lines G jSwitch element SW connect, from the output terminal OUT1 of (j-1) level ST (j-1) of assistant grid driver 400R and the end line TL that OUT2 extends 1And TL 2Be cut off signal wire SL J-1And gate lines G J-1Shorten.Therefore, grid output Gout (j-1) is input to the j level STj of assistant grid driver 400R, and therefore moves this grade STj.By similar mode, the end line TL that extends from output terminal OUT1 and the OUT2 of the j level STj of main grid driver 400L 1And TL 2Can be cut off, and signal wire SLj and gate lines G jCan be shortened.If so, the grid output Gout (j) that produces from the j level STj of assistant grid driver 400L is input to the reset terminal R of (j-1) level ST (j-1) of main grid driver 400L and the set terminal S of (j+1) level ST (j+1) respectively.Simultaneously, owing to be connected to the end line TL of the output terminal OUT2 of assistant grid driver 400R 2Be cut off, so carry output Cout (j) is not input to end line TL 2Therefore, the level that comprises (j+1) level ST (j+1) is not subsequently moved.
As mentioned above, gate drivers 400L, 400R produce identical output and be connected to gate lines G on the left side of display board and right sides 1-G nTherefore, can not use laser to repair the gate lines G of disconnection 1-G nAnd, comprise switch element SW among main grid driver 400L and the assistant grid driver 400R, therefore the fault that takes place in the level 410L of main grid driver 400L can be repaired easily.Though described the present invention in conjunction with the current exemplary embodiment that is considered to put into practice, but, should be appreciated that the present invention is not restricted to the disclosed embodiments, on the contrary, the present invention will cover the structure of various modification included in the spirit and scope of appended claims and equivalence.

Claims (16)

1. display device comprises:
The a plurality of pixels that comprise on-off element respectively;
Be connected to the gate line of on-off element; And
Comprise a plurality of grades first and second gate drivers respectively, these level interconnection also produce output signal continuously,
Wherein the respective stages of the first grid driver level and second grid driver is connected to identical gate line and produces identical output.
2. display device as claimed in claim 1, the level that wherein is connected to first and second gate drivers of identical gate line produces output simultaneously.
3. display device as claimed in claim 2, wherein each level all comprises set terminal, reset terminal, grid voltage end, first and second output terminals and first and second clock end.
4. display device as claimed in claim 3, wherein each level all comprises:
Comprise first end that is connected to first clock end, first on-off element that is connected to second end of first node and is connected to the 3rd end of first output terminal;
Comprise first and second ends that are connected to set terminal jointly and the second switch element that is connected to the 3rd end of first node;
Comprise first end that is connected to first node, the 3rd on-off element that is connected to second end of reset terminal and is connected to the 3rd end of gate off voltage end;
Comprise first end that is connected to first node, the 4th on-off element that is connected to second end of Section Point and is connected to the 3rd end of gate off voltage end;
Comprise first end that is connected to first output terminal, the 5th on-off element that is connected to second end of Section Point and is connected to the 3rd end of gate off voltage end;
Comprise first end that is connected to first output terminal, the 6th on-off element that is connected to second end of second clock end and is connected to the 3rd end of gate off voltage end;
Comprise first end that is connected to Section Point, the minion pass element that is connected to second end of first node and is connected to the 3rd end of gate off voltage end;
Comprise first end that is connected to first clock end, the octavo pass element that is connected to second end of first node and is connected to the 3rd end of second output terminal;
Comprise first end that is connected to second output terminal, the 9th on-off element that is connected to second end of second clock end and is connected to the 3rd end of gate off voltage end;
Comprise first end that is connected to second output terminal, the tenth on-off element that is connected to second end of Section Point and is connected to the 3rd end of gate off voltage end;
First capacitor, it is connected between first clock end and the Section Point;
Second capacitor, it is connected between the first node and first output terminal; And
The 3rd capacitor, it is connected between the first node and second output terminal.
5. display device as claimed in claim 4, wherein first to the tenth on-off element is made by amorphous silicon.
6. display device as claimed in claim 5 also comprises:
The display board unit that comprises pixel and signal wire,
Wherein first and second gate drivers are integrated in the display board unit.
7. display device as claimed in claim 6 also comprises the drive circuit chip that is installed in the display board unit.
8. display device as claimed in claim 7 also comprises:
Be connected to the data line of pixel;
Produce data voltage and data voltage is applied to the data driver of data line; And
Generation is used for the signal controller of the control signal of control gate driver and data driver.
9. display device as claimed in claim 8, wherein drive circuit chip comprises data driver and signal controller.
10. display device as claimed in claim 9, wherein display device is a LCD.
11. a display device comprises:
The a plurality of pixels that comprise on-off element respectively;
Be connected respectively to the gate line of on-off element;
The first grid driver that comprises a plurality of first order, these a plurality of first order interconnection also produce output signal continuously; And
Comprise a plurality of partial second grid drivers, this a plurality of second level interconnection also produces output signal continuously,
Wherein the corresponding second level of the first grid driver first order and second grid driver is connected to identical gate line and produces identical output, and wherein on-off element is between them.
12. as the display device of claim 11, be can not produce under the situation of failure level of output in any first order wherein, the second level that is connected to this failure level by identical gate line produces output.
13. as the display device of claim 12, wherein be connected to the on-off element of the gate line between this failure level and the second level, and be connected to this gate line before the on-off element of gate line connect simultaneously.
14. as the display device of claim 13, wherein:
Each first and second grades all comprise first and second end lines, and are connected to second end line and before and the signal wire of each grade afterwards; And first and second end lines of this failure level disconnect, and the part of first end line of this failure level is shorted to signal wire, disconnect with first and second end lines of level before this failure level is connected to identical gate line partial, and be shorted to signal wire with the part of first end line of level before this failure level is connected to identical gate line partial.
15., wherein be connected to partial second end line disconnection of identical gate line with failure level as the display device of claim 14.
16. as the display device of claim 11, wherein display device is a LCD.
CN2006100996319A 2005-06-07 2006-06-07 Display device Expired - Fee Related CN1877688B (en)

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