CN1874512A - High performance pipeline system in use for AVS video decoder - Google Patents
High performance pipeline system in use for AVS video decoder Download PDFInfo
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Abstract
With the data dependence between the granularity of data processed in each module and the data, the invention adopts the three stages macro block-level pipeline and the two stages block-level pipeline. In macro case, the first stage in the three stages macro block-level pipeline is composed of the decoder of variable length code; the second stage of it is composed of the inverse quantization/inverse transformation module, intra-frame predication module and inter-frame predication module; the third stage of it is composed of the de-blocking filters. In micro case, the first stage of two stages block-level pipeline is composed of the variable length code modules; the second stage of two stages block-level pipeline is composed of the inverse quantization/inverse transformation module and the intra-frame module. The control module, reconstruction module, data Ping-pong RAM and head information storage FIFO are fitted together to ensure highly efficiency working of the two stage pipeline.
Description
Technical field
The present invention relates to a kind of method of digital video decoding technical field, specifically is a kind of high performance pipeline system of the AVS of being used for Video Decoder.
Background technology
The video section of the AVS audio/video encoding/decoding technical standard that digital audio/video encoding and decoding technique standard operation group (AVS working group) is formulated is the State Standard of the People's Republic of China on February 22nd, 2006 by promulgation, standard No. GB/T 20090.2-2006 was in enforcement on March 1 in 2006.
The data volume that video decoding system need be handled is very big, and its huge amount of calculation realizes having brought challenge for the VLSI of system.Under certain frequency requirement, how to guarantee the real-time of video decode, become problem that merits attention in the design process.
Streamline is a kind of technology that can make a plurality of task overlap operations.In decode system, the application of streamline just is embodied in whole system is divided into separate several tasks, according to the dependence of data the task reasonable distribution is arrived a certain stage of streamline then, as a whole, the data stand-by period reduces, whole efficiency improves greatly, and the performance of system also improves thereupon.Specifically, rationally dividing processing module and streamline level, is the key in the design of AVS Video Decoder pipeline organization.Reasonably design will effectively reduce the time redundancy of every level production line, reach the target of high-speed video decoding.
The main data processing module of AVS Video Decoder comprises decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module, inter prediction module, block-eliminating effect filtering module, wherein there are the data relevant issues between part of module, and each resume module time and inconsistent.Rationally dividing processing module and streamline level, is the committed step of AVS Video Decoder The pipeline design.
Find by prior art documents: (high definition that adopts mixed production line is the Video Decoder architecture design H.264/AVC) mentions a kind of streamline mechanism of Video Decoder that is used for H.264/AVC (owing to H.264/AVC have very strong similitude with AVS on hardware is realized in " Architecture design of is decoder withhybrid task pipelining for high definition videos H.264/AVC " that people such as To-Wei are delivered on 2005.ISCAS 2005.IEEEInternational Symposium on Circuits and Systems (IEEE Circuits and Systems international symposium in 2005), so the value of comparison is arranged), this method is considered the granularity difference of each resume module data, taked the thought of graded pipelining, but its shortcoming is: its macro-block level streamline only is divided into two-stage, the first order comprises the decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module and inter prediction module, the second level is made up of the block-eliminating effect filtering module.The first order is divided too coarse, causes existing serious data to wait for phenomenon.The header that intra-framed prediction module and inter prediction module will wait the decoding length changeable code module to separate this macro block could begin to carry out the prediction of this macro block; Inverse quantization/inverse transform block will wait the decoding length changeable code module to separate the header of this macro block and the residual error coefficient of a piece could carry out inverse quantization and inverse transformation to each piece in this macro block.The Video Decoder that uses this streamline mechanism to realize, the macro-block level flowing water first order is too huge, has bigger time redundancy, has restricted whole decoding speed.
Summary of the invention
The object of the present invention is to provide a kind of high performance pipeline system of the AVS of being used for Video Decoder.The present invention adopts mixed production line mechanism, according to the granularity and the data dependence relation of each resume module data, disparate modules is assigned in the different streamline ranks, and adopts suitable controlling mechanism to coordinate each module work.The decoding length changeable code module is ready to corresponding header or residual error coefficient before other module work, avoid the data of intermodule to wait for phenomenon, reduce time redundancy, under the prerequisite that does not enlarge markedly memory spending, reached the purpose of decoder high-speed decoding.
The present invention is achieved by the following technical solutions, the present invention includes important data processing modules such as decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module, inter prediction module, block-eliminating effect filtering module, and the control module, the reconstructed module that are used to control and coordinate pile line operation, wherein:
Described decoding length changeable code module is mainly used in resolves macro block header and residual error coefficient.The macro block header outputs to inverse quantization/inverse transform block, intra-framed prediction module, inter prediction module, block-eliminating effect filtering module; Residual error coefficient is that unit exports to inverse quantization/inverse transform block with the piece.
Described inverse quantization/inverse transform block is that unit carries out inverse quantization and inverse transformation to residual error coefficient with the piece, and result exports reconstructed module to.
Described intra-framed prediction module is that unit carries out intra-prediction process with the piece, and its input data are the reconstruction value of lastblock, and dateout is to reconstructed module.
Described inter prediction module is used to carry out inter prediction and handles, and its input data are the decoded picture behind block-eliminating effect filtering from former frame or two frames, and reconstructed module predicts the outcome between output frame.Though with the piece is processes data in units, because the reference data of adjacent block has very strong reusability, so be considered as the module of macro-block level.
Described block-eliminating effect filtering module is used for reconstruction value is carried out block-eliminating effect filtering, then the result is outputed to the external decoder buffering area, owing to being processes data in units with the macro block, so be considered as the macro-block level module.
Described control module, control decoding length changeable code flow process is also coordinated the macro-block level streamline, input is from the status signal of decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module and inter prediction module, and output enables and useful signal accordingly.
Described reconstructed module major function is to get reconstruction value according to the result of macro block (mb) type gating intra-framed prediction module or inter prediction module and the results added of inverse quantization/inverse transform block, exports to block-eliminating effect filtering module and intra-framed prediction module then.
For guaranteeing the streamline operate as normal, there is the data buffer zone in each intermodule, in order to data cached.The data buffer zone comprises two kinds of data ping-pong ram and header storage FIFO, and wherein, the data ping-pong ram is mainly used in the storage data, guarantee that the pipeline system of data is handled, and header storage FIFO is used to store the macro block header.Existing with the piece between decoding length changeable code module of the present invention and the inverse quantization/inverse transform block is the data ping-pong ram of unit; Existing with the piece between reconstructed module and the inverse quantization/inverse transform block is the unit data ping-pong ram; Existing with the macro block between reconstructed module and the inter prediction module is the unit data ping-pong ram; Existing with the macro block between reconstructed module and the block-eliminating effect filtering module is the data ping-pong ram of unit; There is header storage FIFO between decoding length changeable code module and the block-eliminating effect filtering module.Described data ping-pong ram is by being provided with two block RAMs, and the read-write operation that hockets has been realized seamless buffering of data and processing.
The present invention is directed to the granularity and the data dependence relation of each resume module data, adopt three grades of macro-block level streamlines and two-stage piece level production line.On macroscopic view, three grades of macro-block level streamline first order are made up of the decoding length changeable code module; Second level level is made up of inverse quantization/inverse transform block, intra-framed prediction module and inter prediction module; The third level is made up of the block-eliminating effect filtering module.From microcosmic, the two-stage piece level production line first order is made up of the decoding length changeable code module; The second level is made up of inverse quantization/inverse transform block, intra-framed prediction module.
On macroscopic view, the macro-block level streamline is all included the key data processing module interior as the core flow waterline of entire decoder.Though decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module are processes data in units with the piece, but in handling each macro block before the data of each piece, the decoding length changeable code module need be resolved the macro block header, and inverse quantization/inverse transform block, intra-framed prediction module need read the macro block header.So from the angle of overall control, decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module must be in the macro-block level streamline.Control module is coordinated control to the first order and the partial module of macro-block level streamline; The second level and third level module are according to the full co-ordination of sky of data ping-pong ram.
From microcosmic, in interior macroblocks, decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module are processes data in units with the piece, carry out piece level flowing water.Each module is according to the full co-ordination of sky of data ping-pong ram.
Under the coordination control of control module and data ping-pong ram, native system cooperatively interacts by macro-block level streamline and piece level production line, realizes high-efficient operation.Specifically, the operation principle of each module is as follows among the present invention:
Control module enables and useful signal through judging output accordingly according to macro block (mb) type with from the status signal of decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module and inter prediction module, and macro-block level flowing water is controlled.For the infra-frame prediction type of mb, after the decoding length changeable code module has been separated the macro block header, control module is drawn high header useful signal and infra-frame prediction enable signal, feed back header respectively until inverse quantization/inverse transform block and intra-framed prediction module and read signal, control module just drags down above-mentioned two signals, simultaneously the decoding length changeable code enable signal is drawn high; For the inter prediction type of mb, after the decoding length changeable code module has been separated the macro block header, control module is drawn high header useful signal and inter prediction enable signal, feed back header respectively until inverse quantization/inverse transform block and inter prediction module and read signal, control module just drags down above-mentioned two signals, simultaneously the decoding length changeable code enable signal is drawn high.
The decoding length changeable code module before the new macro block that begins to decode, the enable signal that the inquiry control module is sent, if effectively, then begin to resolve the macro block header, otherwise, continue inquiry; After having separated the macro block header, the sky of the data ping-pong ram between inquiry and inverse quantization/inverse transform block is full, if having a sky at least, then is unit decoded residual coefficient with the piece, otherwise continues inquiry.
Inverse quantization/inverse transform block is before beginning to handle a new macro block, and if the header useful signal sent of inquiry control module effectively, is read away header and fed back to header of control module simultaneously and read signal, otherwise, continue inquiry; After reading away header, inquiry and decoding length changeable code module and and reconstructed module between the sky of data ping-pong ram full, if the former has at least a full and latter to have a sky at least, then be that unit carries out inverse quantization/inverse transformation to residual error coefficient, otherwise continue to inquire about with the piece.
Intra-framed prediction module is before beginning to handle a new macro block, if inquiry control module header useful signal and the infra-frame prediction enable signal sent simultaneously effectively, are read away header and are fed back to header of control module simultaneously and read signal, otherwise, continue inquiry; Read away to begin behind the header to carry out the infra-frame prediction of each piece in the macro block.
The inter prediction module is before beginning to handle a new macro block, if inquiry control module header useful signal and the inter prediction enable signal sent simultaneously effectively, are read away header and are fed back to header of control module simultaneously and read signal, otherwise, continue inquiry; After reading away header, the sky of the data ping-pong ram between inquiry and reconstructed module is full, if having a sky at least, then begins calculating kinematical vector, gets reference value to the relevant position and carries out motion compensation; Otherwise continue inquiry.
Reconstructed module is to the infra-frame prediction type of mb, and the result of gating infra-frame prediction and the residual error data addition after inverse quantization/inverse transformation obtain reconstruction value; To the inter prediction type of mb, the result of gating inter prediction and the residual error data addition after inverse quantization/inverse transformation obtain reconstruction value.
The block-eliminating effect filtering module is before beginning to handle a new macro block, the sky of the data ping-pong ram between inquiry and reconstructed module is full, if have at least one to expire, then read corresponding macro block header from storing in the FIFO with the header of decoding length changeable code intermodule, begin the reconstruction value of this macro block is carried out block-eliminating effect filtering, otherwise continue inquiry.
Said system is mainly decoded towards high definition video, but is not limited to the decoding high definition video, and in the application of low resolution, frequency required for the present invention is corresponding to be reduced, and can greatly must reduce system power dissipation; Said system has very strong adaptability and flexibility, can be applicable at different demands in the AVS Video Decoder of software-hardware synergism, also can be applicable to the AVS Video Decoder that devices at full hardware realizes.
The present invention realizes a kind of high performance pipeline system of the AVS of being used for Video Decoder.The present invention is directed to the granularity of resume module data, adopt three grades of macro-block level streamlines and two-stage piece level production line, by cooperatively interacting of control module, reconstructed module, data ping-pong ram and header storage FIFO, guaranteed that two other streamlines of level work efficiently.All in all, the decoding length changeable code module is than inverse quantization/inverse transform block, intra-framed prediction module, macro block of inter prediction module advanced processing, than two macro blocks of block-eliminating effect filtering module advanced processing.Needn't wait for the header and the residual error coefficient of this macro block during the new macro block of back level resume module, significantly shorten the average time of each macro block of system handles.By effective controlling mechanism, reduced the expense of storage header, when improving system decodes speed, significantly do not increase taking of hardware resource.
Especially, the method that the people such as To-Wei that mentioned in the present invention and the preamble propose is compared, the macro-block level streamline is further segmented, and decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module and inter prediction module are divided into two-stage according to data dependence relation.Inverse quantization/inverse transform block, intra-framed prediction module and inter prediction module are after the data of handling n-1 macro block, and the decoding length changeable code module has been separated header and at least one piece residual error coefficient of n macro block.Inverse quantization/inverse transform block, intra-framed prediction module and inter prediction module need not to wait for header and residual error coefficient.Each module is more effective that flowing water gets up, and has greatly shortened decode time.According to checking, shortened 27% to 33% the average time of separating a macro block.
In sum, the invention enables decoding speed to improve greatly, and there is no remarkable increase memory, therefore, all have very big advantage aspect speed and the hardware resource.
Description of drawings
Fig. 1 is a system block diagram of the present invention;
Intermodular data buffering area schematic diagram among Fig. 2 the present invention;
Fig. 3 is three grades of macro-block level streamline schematic diagrames;
Fig. 4 is a two-stage piece level production line schematic diagram;
Fig. 5 is the mixed production line schematic diagram that people such as To-Wei proposes.
Specific implementation
Provide following examples in conjunction with technical solution of the present invention and accompanying drawing:
Fig. 1 has provided system block diagram of the present invention.The present invention includes important data processing modules such as decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module, inter prediction module, block-eliminating effect filtering module, and the control module and the reconstructed module that are used to control and coordinate pile line operation.
Decoding length changeable code module output macro build information is to inverse quantization/inverse transform block, intra-framed prediction module, inter prediction module, block-eliminating effect filtering module; With the piece is that unit exports to inverse quantization/inverse transform block with residual error coefficient.The data of inverse quantization/inverse transform block after with inverse transformation are that unit exports reconstructed module to the piece.Intra-framed prediction module input lastblock reconstruction value, prediction result is to reconstructed module in the output frame.The inter prediction mould is calculated to such an extent that motion vector obtains reference data to decoding buffer zone according to the macro block header, carries out motion compensation then, and the data after the motion compensation are outputed to reconstructed module.Macro block data after the block-eliminating effect filtering module input reconstruct outputs to the result external decoder buffering area then.
Control module control decoding length changeable code flow process is also carried out effective coordination to the streamline of macro-block level.The dateout of reconstructed module gating intra-framed prediction module or inter prediction module and the results added of inverse quantization/inverse transform block get reconstruction value, export to block-eliminating effect filtering module and intra-framed prediction module.
As Fig. 2, in order to guarantee normally carrying out of water operation, all there is the data buffer zone between the correlation module, comprise data ping-pong ram and header storage FIFO.The data ping-pong ram is mainly used in the storage data, guarantee that the pipeline system of data is handled, and header storage FIFO is used to store the macro block header.
The effect of data ping-pong ram in streamline: the sky that all will check its subordinate's ping-pong ram before higher level's module data is handled is full, if at least one be sky then can operate as normal, then need wait for as if full up; The sky that all will check its higher level's ping-pong ram before simultaneously subordinate's module data is handled is full, if at least one full then can operate as normal, if sky then need be waited for.Each module completely is fitted to each other according to the sky of data buffer zone, co-ordination, and then realize water operation.
For example among Fig. 2, after the decoding length changeable code module had been separated the macro block header, data query ping-pong ram 1 if having at least one then can begin the decoded residual coefficient for empty, otherwise needed to wait for.For inverse quantization/inverse transform block, after obtaining the macro block header, data query ping-pong ram 1 and RAM2 if having at least one completely and among the RAM2 to have a sky at least among the RAM1, then begin the residual error coefficient among the RAM1 is handled, otherwise need to wait for.
The effect of header storage FIFO in streamline: will work as the front module needed header of decoding by higher level's module and deposit FIFO in, and upgrade in time, and have only when data are conciliate the strict synchronism of harbour information, when front module ability read head information from FIFO.
For example among Fig. 2, the header what a macro block is the decoding length changeable code module whenever separate just deposits header storage FIFO in.Behind the intact macro block of block-eliminating effect filtering resume module, data query ping-pong ram 4, if having at least one full, then from the beginning take out the header of next macro block among the information stores FIFO, begin then next macro block is handled.
Below in conjunction with accompanying drawing 2, accompanying drawing 3 and accompanying drawing 4, in advanced audio/video encoding standard AVS, be applied as example with system of the present invention, technical scheme of the present invention is described in further detail.Wherein the macro block of black shows that this macro block is the macro block of infra-frame prediction type among the figure, and the macro block of white is the inter prediction macro block.
To the processing of inter prediction macro block, be that example describes with the flow process of each resume module macro block 3 in the macro-block level streamline.Idiographic flow is as follows:
As Fig. 3, after the decoding length changeable code module had been separated the header of macro block 3, control module was drawn high header useful signal and inter prediction enable signal.Afterwards, whether control module is inquired about this macro block header and is read away respectively by inter prediction module and inverse quantization/inverse transform block.When header was read away by two modules, control module just dragged down above-mentioned two signals, simultaneously the decoding length changeable code enable signal was drawn high, and signal decoding length changeable code module can be resolved the data of macro block 4.
As Fig. 3, before the data of inter prediction resume module macro block 3, the header useful signal and the inter prediction enable signal of the output of inquiry control module.When these two signals were effective simultaneously, the inter prediction module was read away header and feeds back to header of control module to read signal.Feedback signal shows that the inter prediction module read away the header of macro block 3, and the header of decoding length changeable code module parses macro block 4 can not exert an influence to this module.After the inter prediction module was read away header, the sky of data query ping-pong ram 3 was full, if having a sky at least, then began calculating kinematical vector, got reference value to the relevant position and carried out motion compensation; Otherwise continue inquiry.
As Fig. 3, inverse quantization/inverse transform block is carried out the data of macro block 3 before inverse quantization/inverse transformation, the header useful signal of inquiry control module output.When this signal was effective, inverse quantization/inverse transform block was read away header and is fed back to header of control module simultaneously and read signal.The sky of data query ping-pong ram 1 and RAM2 is full then, if data ping-pong ram 1 has at least a full and data ping-pong ram 2 to have a sky at least, then begins in the macro block 3 being that the residual error coefficient of unit carries out inverse quantization and inverse transformation with the piece.
As Fig. 3, the block-eliminating effect filtering module is processes data in units with the macro block.When the data reconstruct of macro block 2 finishes (have at least in the data ping-pong ram 4 one full) and the block-eliminating effect filtering module finishes to the data filtering of macro block 1, from the beginning the block-eliminating effect filtering module just reads the header of macro block 2 among the information stores FIFO, begins the data of macro block 2 are handled.The block-eliminating effect filtering module is finished a frame, and the signal of a frame end of feedback is given control module, so that carry out frame synchronization.
As Fig. 3, intra-framed prediction module is handled before the data of macro block 3, the header useful signal and the infra-frame prediction enable signal of the output of inquiry control module.Because macro block 3 is the inter prediction macro block, the infra-frame prediction enable signal is low always, so intra-framed prediction module is not handled macro block 3, is in query State always.
To the processing of infra-frame prediction macro block, be that example describes with the flow process of each resume module macro block 4 in the piece level production line.As seen from Figure 4, preceding 3 pieces are nonzero block in the macro block 4, and back 3 pieces are complete zero piece.Idiographic flow is as follows:
As Fig. 4, behind the header of the intact macro block 4 of decoding length changeable code module parses, if data ping-pong ram 1 has one for empty, then beginning to resolve in the macro block 4 with the piece is the residual error coefficient of unit; Otherwise, wait for.The decoding length changeable code module non-zero residual error data of only decoding, decoding order is piece 1, piece 2, piece 3; Do not handle back three complete zero pieces, to save processing time and power consumption.
As Fig. 4, after inverse quantization/inverse transform block obtains the header of macro block 4, learn that macro block 4 preceding 3 pieces are nonzero block, back 3 pieces are complete zero piece.If data ping-pong ram 1 has at least a full and data ping-pong ram 2 to have a sky at least, then begin in the macro block 4 being that the residual error coefficient of unit carries out inverse quantization/inverse transformation with the piece.After inverse quantization/inverse transform block is handled the non-zero of piece 1, piece 2, piece 3 successively, directly export 3 complete zero pieces and give reconstructed module.
Owing to all have the data ping-pong ram between inverse quantization/inverse transform block and decoding length changeable code module, reconstructed module, so in the piece level production line, the decoding length changeable code module shifts to an earlier date a more than piece than inverse quantization/inverse transform block.Thereby for inverse quantization/inverse transform block, can obtain required residual error coefficient at once and need not to wait for.
As Fig. 4, the data that intra-framed prediction module is handled also are to be unit with the piece.Its input data are the reconstruction value of a last piece, promptly go up result and infra-frame prediction result (or inter prediction result) sum after a piece inverse quantization and the inverse transformation.During first piece of intra-prediction process macro block 4, its input data are last piece reconstruction value of macro block 3; When handling second piece of macro block 4, the input data are first piece reconstruction value of macro block 4.
So far, realized being used for the high performance pipeline system of AVS Video Decoder.By cooperatively interacting of control module, reconstructed module, data ping-pong ram and header storage FIFO, guaranteed that two other streamlines of level work efficiently.The mixed production line that people such as To-Wei among streamline of the present invention and Fig. 5 among Fig. 3, Fig. 4 are proposed compares, and the macro-block level streamline is further segmented among visible the present invention.All in all, the decoding length changeable code module shifts to an earlier date inverse quantization/inverse transform block, intra-framed prediction module and inter prediction module one-level, effectively avoids the data of intermodule to wait for phenomenon, reduces time redundancy; Each module is more effective that flowing water gets up, and has greatly shortened decode time.According to experiment, shortened 27% to 33% the average time of separating a macro block.
Claims (10)
1. a high performance pipeline system that is used for the AVS Video Decoder comprises decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module, inter prediction module, reconstructed module, block-eliminating effect filtering module and control module, it is characterized in that:
Described decoding length changeable code module is used to resolve macro block header and decoding residual error coefficient, and output macro build information is to inverse quantization/inverse transform block, intra-framed prediction module, inter prediction module, block-eliminating effect filtering module; The output residual error coefficient is given inverse quantization/inverse transform block;
Described inverse quantization/inverse transform block is used for residual error coefficient is carried out inverse quantization and inverse transformation, and result exports reconstructed module to;
Described intra-framed prediction module is used to carry out intra-prediction process, and its input data are the reconstruction value of lastblock, and dateout is to reconstructed module;
Described inter prediction module is used to carry out inter prediction and handles, and its input data are the decoded picture behind block-eliminating effect filtering from former frame or two frames, and reconstructed module predicts the outcome between output frame;
Described reconstructed module is used for residual error coefficient after inverse quantization/inverse transformation and predicted value addition are obtained reconstruction value, and the output reconstruction value is given intra-framed prediction module and block-eliminating effect filtering module;
Described block-eliminating effect filtering module is used to carry out block-eliminating effect filtering, and the input reconstruction value outputs to the external decoder buffering area with the block-eliminating effect filtering result;
Described control module, be used to control the decoding length changeable code flow process and the streamline of macro-block level is coordinated, input is from the status signal of decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module and inter prediction module, and output enables and useful signal accordingly.
2. the high performance pipeline system that is used for the AVS Video Decoder as claimed in claim 1, it is characterized in that: there is the data buffer zone in each intermodule, in order to data cached, the data buffer zone comprises two kinds of data ping-pong ram and header storage FIFO, wherein, the data ping-pong ram is used to store data, guarantee that the pipeline system of data is handled, and header storage FIFO is used to store the macro block header.
3. the high performance pipeline system that is used for the AVS Video Decoder as claimed in claim 2 is characterized in that: existing with the piece between decoding length changeable code module and the inverse quantization/inverse transform block is the data ping-pong ram of unit; Existing with the piece between reconstructed module and the inverse quantization/inverse transform block is the unit data ping-pong ram; Existing with the macro block between reconstructed module and the inter prediction module is the unit data ping-pong ram; Existing with the macro block between reconstructed module and the block-eliminating effect filtering module is the data ping-pong ram of unit; There is header storage FIFO between decoding length changeable code module and the block-eliminating effect filtering module.
4. the high performance pipeline system that is used for the AVS Video Decoder as claimed in claim 1, it is characterized in that: described control module, according to macro block (mb) type with from the status signal of decoding length changeable code module, inverse quantization/inverse transform block, intra-framed prediction module and inter prediction module, through judging that output enables and useful signal accordingly, controls macro-block level flowing water;
For the infra-frame prediction type of mb, after the decoding length changeable code module has been separated the macro block header, control module is drawn high header useful signal and infra-frame prediction enable signal, feed back header respectively until inverse quantization/inverse transform block and intra-framed prediction module and read signal, control module just drags down above-mentioned two signals, simultaneously the decoding length changeable code enable signal is drawn high;
For the inter prediction type of mb, after the decoding length changeable code module has been separated the macro block header, control module is drawn high header useful signal and inter prediction enable signal, feed back header respectively until inverse quantization/inverse transform block and inter prediction module and read signal, control module just drags down above-mentioned two signals, simultaneously the decoding length changeable code enable signal is drawn high.
5. the high performance pipeline system that is used for the AVS Video Decoder as claimed in claim 1 is characterized in that: described decoding length changeable code module, before the new macro block that begins to decode, the enable signal that the inquiry control module is sent is if effectively, then begin to resolve the macro block header, otherwise, continue inquiry; After having separated the macro block header, the sky of the data ping-pong ram between inquiry and inverse quantization/inverse transform block is full, if having a sky at least, then is unit decoded residual coefficient with the piece, otherwise continues inquiry.
6. the high performance pipeline system that is used for the AVS Video Decoder as claimed in claim 1, it is characterized in that: described inverse quantization/inverse transform block, before beginning to handle a new macro block, the header useful signal that the inquiry control module is sent, if effectively, read away header and feed back to header of control module simultaneously and read signal, otherwise, inquiry continued; After reading away header, inquiry and decoding length changeable code module and and reconstructed module between the sky of data ping-pong ram full, if the former has at least a full and latter to have a sky at least, then be that unit carries out inverse quantization/inverse transformation to residual error coefficient, otherwise continue to inquire about with the piece.
7. the high performance pipeline system that is used for the AVS Video Decoder as claimed in claim 1, it is characterized in that: described intra-framed prediction module, before beginning to handle a new macro block, header useful signal and infra-frame prediction enable signal that the inquiry control module is sent, if simultaneously effectively, read away header and feed back to header of control module simultaneously and read signal, otherwise, inquiry continued; Read away to begin behind the header to carry out the infra-frame prediction of each piece in the macro block.
8. the high performance pipeline system that is used for the AVS Video Decoder as claimed in claim 1, it is characterized in that: described inter prediction module, before beginning to handle a new macro block, header useful signal and inter prediction enable signal that the inquiry control module is sent, if simultaneously effectively, read away header and feed back to header of control module simultaneously and read signal, otherwise, inquiry continued; After reading away header, the sky of the data ping-pong ram between inquiry and reconstructed module is full, if having a sky at least, then begins calculating kinematical vector, gets reference value to the relevant position and carries out motion compensation; Otherwise continue inquiry.
9. the high performance pipeline system that is used for the AVS Video Decoder as claimed in claim 1 is characterized in that: described reconstructed module, and to the infra-frame prediction type of mb, the result of gating infra-frame prediction and the residual error data addition after inverse quantization/inverse transformation obtain reconstruction value; To the inter prediction type of mb, the result of gating inter prediction and the residual error data addition after inverse quantization/inverse transformation obtain reconstruction value.
10. the high performance pipeline system that is used for the AVS Video Decoder as claimed in claim 1, it is characterized in that: described block-eliminating effect filtering module, before beginning to handle a new macro block, the sky of the data ping-pong ram between inquiry and reconstructed module is full, if have at least one to expire, then read corresponding macro block header, begin the reconstruction value of this macro block is carried out block-eliminating effect filtering, otherwise continue inquiry from storing in the FIFO with the header of decoding length changeable code intermodule.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100493193C (en) * | 2006-12-08 | 2009-05-27 | 北京中星微电子有限公司 | A method and device for carrying out buffer control to real time digital video stream |
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| CN100584019C (en) * | 2007-06-27 | 2010-01-20 | 中国科学院微电子研究所 | Inverse transforming method and device for transform scanning table in video decoding |
| CN101778288A (en) * | 2010-03-02 | 2010-07-14 | 青岛海信信芯科技有限公司 | Method and device for decoding digital video |
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| KR100624426B1 (en) * | 2004-07-06 | 2006-09-19 | 삼성전자주식회사 | Pipeline decoding apparatus and method, and computer-readable recording media for storing computer program for controlling the apparatus |
| KR20060060919A (en) * | 2004-12-01 | 2006-06-07 | 삼성전자주식회사 | Deblocking filter and method of deblock-filtering for eliminating blocking effect in h.264/mpeg-4 |
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| CN100493193C (en) * | 2006-12-08 | 2009-05-27 | 北京中星微电子有限公司 | A method and device for carrying out buffer control to real time digital video stream |
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