CN1306822C - Vido decoder based on software and hardware cooperative control - Google Patents
Vido decoder based on software and hardware cooperative control Download PDFInfo
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Abstract
The present invention relates to a video decoder based on soft hardware cooperation, which comprises a video decoding controller, a lengthening decoder, a motion compensating processor, an inverse quantization processor, an inverse transformation processor, an intra predicting and compensating processor, and a filtering and frame storing manager, wherein the video decoding controller operates in an embedded type CPU. The analysis of a coding code current and the control of an integral production line are completed by the assistance of the lengthening decoder, and other processors are totally used as a single hardware accelerator for realizing a specific decoding function. The cooperating control of soft hardware of a video decoder is achieved by the video decoder based on soft hardware cooperation of the present invention, the complexity of hardware logic is reduced, and the expandability of a decoder is enhanced. The handling efficiency of hardware is greatly improved by adopting macroblock-level running water operation, and therefore, the decoding speed of the decoder is enhanced, that is to say, the proper performance requirement of the hardware is greatly reduced under the requirements of satisfying the same decoding speed, and the cost of the decoder is reduced.
Description
Technical field
The present invention relates to the digit image coding/decoding technology, specifically, relate to a kind of Video Decoder based on software-hardware synergism control.
Background technology
Existing video coding and decoding technology nearly all adopts hybrid coding/decoding process, for example MPEG-1, MPEG-2, MPEG-4, H.26x reach AVS standard that China releasing etc.Typical decode structures as shown in Figure 1, this decode structures has adopted motion compensation, inverse transformation, inverse quantization and the modules such as entropy decoding (variable length decoding), infra-frame prediction, block elimination effect filter in time and space.
The encoded video code streams by using hierarchical structure, the i.e. structure of one deck bag one deck from outside to inside, be respectively sequence layer, image sets layer, image layer, chunk layer, macroblock layer and piece layer, concrete inclusion relation is: a sequence comprises a plurality of image sets, each image sets comprises a plurality of images, each image comprises a plurality of macro blocks, and each macro block comprises a plurality of, and each piece comprises real coded image data; The chunk layer then is used for mistake and recovers.The beginning of each layer all identifies with a unique code word, it is the information coding that each layer is constant to other thereafter, code word and information coding are called as header, for example, each layer is the same to the figure image width height that comprises in the sequence head information for other, promptly can not become, and coded image pattern wherein all is different for each image, therefore need encodes in image layer for a sequence.Sequence layer is the level that must pass through when beginning to decode a sequence, and therefore the incision at random in television broadcasting or streaming media playing need be from sequence head; And the image sets layer stipulates that image in this image sets can not predict the image information of other group when encoding and decoding, be about to this image sets as one independently coding unit handle, can make things convenient for the random access of image like this; Image layer then comprises the coded message of a two field picture, has different coding modes.
In the prior art, adopt hardware accelerator to realize in chip to the decoding of above-mentioned information, this scheme not only makes the logic of entire chip become very complicated, and lacks flexibility.Because video technique is applied in the different application field, what change generally is the process of video coding, and the core algorithm of decoding can not change, therefore the present invention detaches out with the control of video decode separately, realize that by software other video decode is still realized by hardware accelerator.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of Video Decoder based on software-hardware synergism control, can realize that the real-time decoding of high definition encoded video code stream shows, has high performance-price ratio and easy autgmentability.
Video Decoder of the present invention comprises video decode controller, length variable decoder, motion compensation processor, inverse quantization processor, inverse transformation processor, infra-frame prediction compensation processor and filtering and frame storage manager;
Described video decode controller is used for the decoding control of video code flow to be decoded, and the order that will send to each processor sends to described length variable decoder;
Described length variable decoder be used for carrying out the entropy decoding under the control of described video decode controller, and the order that will receive is transmitted to corresponding processor;
Described motion compensation processor is used to obtain reference frame data and carries out motion compensation, and the view data after the compensation is sent to described infra-frame prediction compensation processor;
Described inverse quantization processor is used to carry out inverse quantization and handles, and outputs to described inverse transformation processor;
Described inverse transformation processor is used to carry out inverse transformation and handles, and the residual error data that obtains is sent to described infra-frame prediction compensation processor;
Described infra-frame prediction compensation processor is used to carry out intra-prediction process, and according to the data reconstruction decoded macroblock data of described motion compensation processor and described inverse transformation processor output, outputs to described filtering and frame storage manager;
Described filtering and frame storage manager are used to carry out block-eliminating effect filtering, and current decoded macroblock data are write decoding buffer zone.
Video Decoder of the present invention has been realized the software-hardware synergism control of video decode, both reduced the complexity of hardware logic, improved the autgmentability of decoder again, by adopting the macro-block level water operation, improve the treatment effeciency of hardware greatly, thereby improve the decoding speed of decoder, that is to say, under the requirement of satisfying identical decoding speed, greatly reduce performance requirement to hardware itself, reduced the cost of decoder.
Description of drawings
Fig. 1 is existing video decode structural representation;
Fig. 2 is the software and hardware distribution diagram of Video Decoder of the present invention;
Fig. 3 is the structural representation of Video Decoder of the present invention;
Fig. 4 is a pile line operation stage schematic diagram of the present invention;
Fig. 5 is that the present invention is applied to the workflow diagram in the AVS1.0 video standard.
Embodiment
Below in conjunction with drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 1 is the decode structures schematic diagram of prior art, describes in background technology, repeats no more herein.The present invention proposes a kind of Video Decoder based on software-hardware synergism control, decoding control section is wherein divided and can be realized by software, other decoded portion realizes by hardware accelerator that then as shown in Figure 2, the decoding control section branch places Video Decoder as embedded type CPU.
Fig. 3 has provided the structural representation of Video Decoder of the present invention, comprises video decode controller, length variable decoder, motion compensation processor, inverse quantization processor, inverse transformation processor, infra-frame prediction compensation processor and filtering and frame storage manager.The video decode controller operates in the embedded type CPU, finish the parsing of encoding code stream and the control of whole streamline by the assistance of length variable decoder, and other processor is all realized the decoding function that certain is specific as an independent hardware accelerator.
The video decode controller can adopt software to realize, the decoding control and the order that are used for video code flow send control, comprises that the above decoding control module of macroblock layer, macroblock layer and following decoding control module and order send control module.The above decoding control of macroblock layer comprises code stream analyzing control, error control, the control that resets, Synchronization Control, random access/incision control, buffering area control, the control of macro block availability etc.; Macroblock layer and following decoding control are meant the parsing control of being responsible for a macro block, and the parameter that obtains is sent to the relevant hardware processor in the mode of ordering.In order to reduce the interface between the software and hardware, the order that the video decode controller is issued each hardware processor sends to length variable decoder by the unification of order transmission control module, is transmitted by length variable decoder.
Length variable decoder is supported the parsing of all syntactic elements in the encoding code stream, finish the entropy decode procedure by the control of video decode controller, as an interface of software and hardware communication, be responsible for the order that the video decode controller sends is transmitted to relevant hardware processor simultaneously.In addition, for alleviating the pressure of video decode controller, length variable decoder also can be separated some piece data code and directly send to the relevant hardware processor.
The reference frame address that motion compensation processor receiver, video decode controller sends obtains reference frame data in decoding buffer zone, carry out motion compensation then, and the view data after the motion compensation is sent to the infra-frame prediction compensation processor carries out image reconstruction.
Inverse quantization processor and inverse transformation processor are mainly finished inverse quantization and inverse transformation and are handled, and the data after handling through inverse quantization directly output to the inverse transformation processor, and the inverse transformation processor does not need to receive any order from the video decode controller; Inverse transformation processor output residual error data is in the infra-frame prediction compensation processor.
The infra-frame prediction compensation processor except the function of finishing infra-frame prediction, also be responsible for will through the view data after the motion compensation with pass through inverse transformation after residual error data reconstruct decoded macroblock data in addition mutually.
Filtering and frame storage accelerator are used to finish the block-eliminating effect filtering function, and current decoded macroblock data are write in the decoding buffer zone with the memory address that command mode passes over according to the video decode controller.
Consider the complexity of motion compensation processor, with its be divided into motion vector prediction, reference frame obtains and three modules of pixel interpolation, the motion vector prediction module is finished the motion vector calculation of motion compensation and is selected compensation model, the motion vector that reference frame address that the reference frame acquisition module passes over according to the video decode controller and motion vector prediction module pass over reads reference data from decoding buffer zone, pass to the pixel interpolation module then and carry out passing to the infra-frame prediction compensation processor behind the pixel interpolation.
In order to guarantee the decoding speed of Video Decoder, decoder of the present invention adopts the macro-block level water operation, as shown in Figure 4.It is 5 grades of flowing water that decoder of the present invention is divided into, wherein length variable decoder is in the 1st grade of flowing water, inverse quantization processor and motion vector prediction module are in the 2nd grade, inverse transformation processor and reference frame acquisition module are in 3rd level, infra-frame prediction compensation processor and pixel interpolation module are in the 4th grade, and filtering and frame storage manager then are in the 5th grade.
For realizing normally carrying out of above-mentioned water operation, the buffering area formation (to call FIFO in the following text) of first in first out is all arranged between each hardware processor, be used for data cached, comprise two kinds of data FIFO and order FIFO, wherein data FIFO is mainly used in the storage data, and order FIFO then stores relevant control information.Specifically: have order FIFO and data FIFO between length variable decoder and the inverse quantization processor; There are order FIFO and data FIFO between length variable decoder and the motion compensation processor; There are order FIFO and data FIFO between length variable decoder and the infra-frame prediction compensation processor; There is data FIFO between inverse quantization processor and the inverse transformation processor; There is data FIFO between inverse transformation processor and the infra-frame prediction compensation processor; There is data FIFO between motion compensation processor and the infra-frame prediction compensation processor; There is data FIFO between infra-frame prediction compensation processor and filtering and the frame storage manager.Therefore, may there be a plurality of FIFO for some processor, for example the infra-frame prediction compensation processor has 2 data FIFO and 1 order FIFO, wherein 1 data FIFO is used to receive the predicted macroblock data from motion compensation processor, another data FIFO receives the residual error data from the inverse transformation processor, for the macro block of interframe encoding mode have only all have among 2 data FIFO among available data and the order FIFO enough information is arranged after, the infra-frame prediction compensation processor just begins to handle.Therefore have only and have data among the FIFO, the processor of back just can carry out the processing of data; Simultaneously each superior processor will check all before handling whether the FIFO of its subordinate processors has living space, if not then need wait for.
In the AVS1.0 video encoding and decoding standard, its video decode framework is similar to H.264 (JVT), promptly structure as shown in Figure 1 adopts maximum two forward reference frame, comprises intraframe coding (I frame), forward predictive coded (P frame) and three kinds of image encoding patterns of bi-directional predictive coding (B frame); Pixel interpolation adopts 1/4 pixel interpolation; The macroblock prediction pattern comprises infra-frame prediction and two kinds of patterns of inter prediction.
Video Decoder of the present invention comprises based on the idiographic flow of AVS1.0 as shown in Figure 5:
The video decode controller detects the video decode enable signal, if do not enable, then waits for; Otherwise initializes video decoder comprises: the video decode controller is carried out initialization; Enable length variable decoder and show the control accelerator.The video decode controller is to the order of length variable decoder transmission search head syntactic element, and length variable decoder returns head type to the video decode controller after resolving.Whether the video decode controller detects the syntactic element of resolving correct, if find to make mistakes, a position of then notifying length variable decoder to search for next I frame is continued then to resolve, and returned head type; If the syntactic element of resolving is correct, then the video decode controller is resolved header under the assistance of length variable decoder.Mutual each time between video decode controller and the length variable decoder all needs the correctness of syntactic element is detected.
When resolving header, if sequence head then obtains necessary control information, and send to the relevant hardware processor, specifically comprise: Format Series Lines is sent to motion compensation processor and shows the control accelerator by length variable decoder; Figure image width high pass is crossed length variable decoder to send to motion compensation processor, filtering and frame storage manager and shows the control accelerator; Frame per second is sent to demonstration control accelerator by length variable decoder.Return the decoding of carrying out next header then.
If image head, then obtain necessary control information, and send to relevant hardware processor, specifically comprise: image pitch, image encoding type, filtering sign and parameter, weight estimation parameter and coding format are sent to motion compensation processor by length variable decoder; To push up end field sequential and number of repetition and send to demonstration control accelerator by length variable decoder.Calculate the address of buffering area then by the video decode controller, comprise reference frame address, present frame memory address and display frame address; And the reference frame address sent to motion compensation processor.Whether the decoded frame of judging the memory address correspondence is shown, if be not shown, then continues to wait for; If show, then the storage frame address is sent to filtering and frame storage manager.Enter the process of macro block decoding then, the video decode controller is resolved the macro block header under the assistance of length variable decoder, judge by length variable decoder whether the order FIFO of all other processors is full again, if finding all order FIFO all is discontented with, then concentrate and the macro-block level order is sent to each processor, for example quantization parameter is sent to the inverse quantization processor, the current macro position sends to motion compensation processor, filtering and frame storage manager and infra-frame prediction compensation processor etc. by length variable decoder.
After the video decode controller sends to each processor with the macro-block level order, just carry out the parsing of next macro block head, this moment is as long as have data among the FIFO of each processor input, and the FIFO of output is discontented, then this processor just can operate as normal, and then realizes the water operation of macro-block level.After two field picture decoding finishes, the decoding that enters the next frame image.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (7)
1, a kind of Video Decoder based on software-hardware synergism control, comprise motion compensation processor, inverse quantization processor, inverse transformation processor, infra-frame prediction compensation processor and filtering and frame storage manager, wherein said motion compensation processor, be used to obtain reference frame data and carry out motion compensation, the view data after the compensation is sent to described infra-frame prediction compensation processor;
Described inverse quantization processor is used to carry out inverse quantization and handles, and outputs to described inverse transformation processor;
Described inverse transformation processor is used to carry out inverse transformation and handles, and the residual error data that obtains is sent to described infra-frame prediction compensation processor;
Described infra-frame prediction compensation processor is used to carry out intra-prediction process, and according to the data reconstruction decoded macroblock data of described motion compensation processor and described inverse transformation processor output, outputs to described filtering and frame storage manager;
Described filtering and frame storage manager are used to carry out block-eliminating effect filtering, and current decoded macroblock data are write decoding buffer zone;
It is characterized in that, also comprise: video decode controller and length variable decoder; Described video decode controller is used for the decoding control of video code flow to be decoded, and the order that will send to each processor sends to described length variable decoder; Described length variable decoder be used for carrying out the entropy decoding under the control of described video decode controller, and the order that will receive is transmitted to corresponding processor.
2, the Video Decoder based on software-hardware synergism control according to claim 1, it is characterized in that described video decode controller comprises that further the above decoding control module of macroblock layer, macroblock layer and following decoding control module and order send control module; The above decoding control of macroblock layer comprises code stream analyzing control, error control, the control that resets, Synchronization Control, random access/incision control, buffering area control, the control of macro block availability; Macroblock layer and following decoding control are meant the parsing control of being responsible for a macro block; The control information of decoding control sends to length variable decoder in the mode of order by the unification of order transmission control module, is transmitted to other processor by length variable decoder.
3, the Video Decoder based on software-hardware synergism control according to claim 2 is characterized in that, described video decode controller adopts software to realize, places Video Decoder in the mode of embedded type CPU; Other processor adopting hardware accelerator is realized.
4, the Video Decoder based on software-hardware synergism control according to claim 1 is characterized in that described motion compensation processor is divided into motion vector prediction, reference frame obtains and three modules of pixel interpolation; Described motion vector prediction module is finished the motion vector calculation of motion compensation and is selected compensation model; The motion vector that reference frame address that described reference frame acquisition module passes over according to described video decode controller and described motion vector prediction module pass over reads reference data from decoding buffer zone, pass to described pixel interpolation module then and carry out pixel interpolation.
5, the Video Decoder based on software-hardware synergism control according to claim 4, it is characterized in that, described Video Decoder adopts the macro-block level water operation, being divided into is 5 grades of flowing water, wherein length variable decoder is in the 1st grade of flowing water, and inverse quantization processor and motion vector prediction module are in the 2nd grade, and inverse transformation processor and reference frame acquisition module are in 3rd level, infra-frame prediction compensation processor and pixel interpolation module are in the 4th grade, and filtering and frame storage manager then are in the 5th grade.
6, according to the arbitrary described Video Decoder of claim 1 to 5, it is characterized in that FIFO buffer formation FIFO is all arranged between each hardware processor except that the video decode controller, be used for the buffer memory macro block data based on software-hardware synergism control; Specifically comprise two kinds of data FIFO and order FIFO, wherein data FIFO is mainly used in the storage data, and order FIFO then stores relevant control information.
7, the Video Decoder based on software-hardware synergism control according to claim 6 is characterized in that, has order FIFO and data FIFO between length variable decoder and the inverse quantization processor; There are order FIFO and data FIFO between length variable decoder and the motion compensation processor; There are order FIFO and data FIFO between length variable decoder and the infra-frame prediction compensation processor; There is data FIFO between inverse quantization processor and the inverse transformation processor; There is data FIFO between inverse transformation processor and the infra-frame prediction compensation processor; There is data FIFO between motion compensation processor and the infra-frame prediction compensation processor; There is data FIFO between infra-frame prediction compensation processor and filtering and the frame storage manager.
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| CN101076124B (en) * | 2006-05-18 | 2010-09-08 | 北京大学深圳研究生院 | Filter for eliminating block |
| CN100466742C (en) * | 2006-08-07 | 2009-03-04 | 清华大学 | Combined processing method for entropy decoding and converting flow line stage |
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| CN101175210B (en) * | 2006-10-30 | 2010-08-11 | 中国科学院计算技术研究所 | Entropy decoding method and device used for decoding video estimation residual error coefficient |
| CN101883276B (en) * | 2009-05-06 | 2012-11-21 | 中国科学院微电子研究所 | Multi-format high-definition video decoder structure for software and hardware combined decoding |
| CN101710994B (en) * | 2009-12-17 | 2012-12-26 | 无锡中星微电子有限公司 | Method and system for video decoding |
| CN102065288B (en) * | 2010-06-30 | 2013-07-24 | 美商威睿电通公司 | Video processing system and method realized by combining software with hardware and device thereof |
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| CN104469488B (en) * | 2014-12-29 | 2018-02-09 | 北京奇艺世纪科技有限公司 | Video encoding/decoding method and system |
| CN107277505B (en) * | 2017-05-19 | 2020-06-16 | 北京大学 | AVS-2 video decoder device based on software and hardware partition |
| CN110798684A (en) * | 2019-09-30 | 2020-02-14 | 武汉兴图新科电子股份有限公司 | Image segment peak-shifting coding transmission method |
| CN112422986B (en) * | 2020-10-26 | 2023-12-22 | 眸芯科技（上海）有限公司 | Hardware decoder pipeline optimization method and application |
| CN117560501B (en) * | 2024-01-11 | 2024-04-12 | 杭州国芯科技股份有限公司 | Multi-standard video decoder |
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Owner name: ZHANXUN COMMUNICATIONS (SHANGHAI) CO., LTD. Free format text: FORMER OWNER: UNITED XINYUAN DIGITAL AUDIO-VIDEO TECHNOLOGY (BEIJING) CO., LTD. Effective date: 20070608 |
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Effective date of registration: 20070608 Address after: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park Lane 2288 newshow Center Building No. 1 Patentee after: Spreadtrum Communications (Shanghai) Inc. Address before: 100080 North building, room 6, 140 South Road, Haidian District Academy of Sciences, Beijing Patentee before: UNITED XINYUAN DIGITAL AUDIO V |
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Effective date of registration: 20190314 Address after: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing Patentee after: Xin Xin finance leasing (Beijing) Co.,Ltd. Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park Lane 2288 newshow Center Building No. 1 Patentee before: Spreadtrum Communications (Shanghai) Inc. |
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Application publication date: 20050302 Assignee: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Assignor: Xin Xin finance leasing (Beijing) Co.,Ltd. Contract record no.: X2021110000008 Denomination of invention: A video decoder based on hardware and software co control Granted publication date: 20070321 License type: Exclusive License Record date: 20210317 |
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Effective date of registration: 20221018 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech park, Spreadtrum Center Building 1, Lane 2288 Patentee after: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Address before: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing Patentee before: Xin Xin finance leasing (Beijing) Co.,Ltd. |
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Granted publication date: 20070321 |