CN1222039A - Digital information source decoder decoded by video - Google Patents
Digital information source decoder decoded by video Download PDFInfo
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- CN1222039A CN1222039A CN 98126137 CN98126137A CN1222039A CN 1222039 A CN1222039 A CN 1222039A CN 98126137 CN98126137 CN 98126137 CN 98126137 A CN98126137 A CN 98126137A CN 1222039 A CN1222039 A CN 1222039A
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Abstract
A digital signal source decoder for video decode in SDTV or HDTV has a core decode unit which is composed of data buffer, length-variable decoder, range decoder, coefficient generator, macro block memory, moving vector generator, moving compensator, IDCT circuit, decode controller and reference frame memory.Its advantages include conforming with international standard MPEG-2, reasonable structure, and flexible control.
Description
The present invention relates to a kind of digital video decoder.Be particularly related to the digital information source decoding device of the video decode of a kind of SDTV of being used for (digital standard definition television) or HDTV (digital high-definition television).
Digital information source decoding device is the visual plant of using in the digital video field, and video decode is the core of digital information source decoding device, realizes that therefore video decode is one of focus of this field development.At present, the general international standard in digital video field is a Moving Picture Experts Group-2.By ISO/IEC IS 13818 file descriptions.In Moving Picture Experts Group-2, the syntactic structure of video decode is had only some functional summarized introduction, and whole specific algorithms and hardware device are not provided.For this reason, be necessary to determine algorithm and the digital information source decoding device that video decode is provided according to the every decoding function and the device condition of defined in the standard.
The purpose of this invention is to provide the digital information source decoding device of the video decode of a kind of SDTV of being used for or HDTV, and make it meet Moving Picture Experts Group-2 fully, be applicable to the various types (Profile) and the level (Level) of this prescribed by standard.
According to above-mentioned purpose, the digital information source decoding device of video decode of the present invention is made up of decoding multiplexing unit, system control unit, core codec unit, display buffer unit, post-processing unit etc., its core codec unit is as video decoding unit, it comprises: data buffer is used to adjust the video code flow of input; Length variable decoder, it adopts the parallel decoding structure, is used for the serial code stream of data buffer output is carried out variable length decoding; Runlength decoder is connected to the output of length variable decoder, is used to finish runs decoding; Coefficient producer is used for recovering DC coefficient and other coefficient in the frame, and carries out inverse quantization after decoding; The macro block memory is used for writing wherein according to DC coefficient and other coefficient in the frame of certain scanning sequency after inverse quantization; Idct circuit is used for the IDCT computing; The motion vector generator is used for calculating motion vector value according to the data behind the variable length decoding; Decode controller is used for producing the address of reading reference frame memory according to motion vector value, and the address obtains reference data thus, and it also is used to control the whole decoding process of core codec unit; Movement compensating circuit obtains real reference value through the half-pix processing earlier with the reference data of importing, and carries out motion compensation calculations with the IDCT dateout, finally obtains yuv data, delivers to the display buffer unit, for demonstration; Reference frame memory when core codec unit output video yuv data, if preceding frame is I frame and P frame, then is written into wherein, as subsequently the P frame or the predictive frame of B frame.
The present invention has following advantage:
1, the present invention divides the function that complex video decode procedure in the Moving Picture Experts Group-2 has carried out science, makes whole decoding process clear in structure, the exchanges data advantages of simple.
2, each construction unit built-in function of dividing through science is clear and definite, and implementation method meets the Moving Picture Experts Group-2 regulation fully.
3, the decode controller among the present invention is the key that whole system realizes, it carries out Synchronization Control by the clock signal and the control signal of the various strictnesses that self produces to whole decoding process; Simultaneously, the parser by the microcode in programmable logic device and the outer loading/memorizing unit is formed makes whole decoding process carry out according to the regulation of Moving Picture Experts Group-2 fully, and makes easier control of decoding process and modification.
4, interior DC coefficient generator of the frame among the present invention and motion vector generator have been realized the differential decoding of video decoding process, and two groups of fallout predictors are reasonable in design, are convenient to control and hardware and realize.
Above-mentioned purpose of the present invention and other characteristics will become more clear in reference to the detailed description of each the drawings and specific embodiments.Wherein:
Fig. 1 represents the block diagram of the digital information source decoding device of video decode;
Fig. 2 represents the block diagram of core codec of the present invention unit;
Fig. 3 represents the block diagram of the interior DC coefficient generator of frame of core codec of the present invention unit;
The block diagram of the motion vector generator of Fig. 4 core codec of the present invention unit;
Fig. 5 represents the block diagram of digital HDTV source decoder of the video decode of the first embodiment of the present invention;
Fig. 6 represents the block diagram of digital SDTV source decoder of the video decode of the second embodiment of the present invention.
See figures.1.and.2, the digital information source decoding device of video decode of the present invention is described.In Fig. 1, the digital information source decoding device of video decode of the present invention is made up of demultiplexing unit 1, system control unit 2, core codec unit 3, display buffer unit 4, post-processing unit 5 etc.Wherein core codec unit 3 is as video decoding unit.In Fig. 2, core codec of the present invention unit 3 comprises: data buffer 21, length variable decoder 22, runlength decoder 23, coefficient producer 24, macro block memory 25, idct circuit 26, motion vector generator 27, decode controller 28, movement compensating circuit 29, reference frame memory 30.
Divide according to said units, the video code flow of input is admitted to length variable decoder 22 and runlength decoder 23 earlier after data buffer 21 is adjusted.Their major function is that serial code stream is carried out variable length decoding and runs decoding, and decoded data are delivered to coefficient producer 24 and motion vector generator 27 respectively.Length variable decoder 22 adopts the parallel decoding structure, can solve a code word in the cycle at a work clock, and no matter how long this code word has.The length variable decoder 22 of parallel organization is made up of two input registers, a Barrel Shifter, a lookup table circuit and an accumulator that has code word size.Runlength decoder 23 is connected on the output of length variable decoder 22, finishes the function of runs decoding.Runlength decoder 23 is made up of a plurality of comparators, Port Multiplier and register, and coefficient producer 24 is delivered in its output.
Data behind variable length decoding and the runs decoding are admitted to coefficient producer 24, recover DC coefficient and other coefficient in the frame by coefficient producer 24.Coefficient producer 24 is made up of two parts: the one, and DC coefficient generator in the frame, the 2nd, other coefficient producer.
Fig. 3 represents the block diagram of the interior DC coefficient generator of frame of core codec of the present invention unit.In Fig. 3, the information that the DC coefficient generator solves according to length variable decoder 22 in the frame, (as dct-dc-size, dct-dc-differential) and some decoding parametrics (as intra-precision) recover the difference of DC coefficient in the frame, and then, finally obtain DC coefficient in the frame with the value addition in the direct current fallout predictor in difference and the corresponding frame.Other coefficient producer is those coefficients that are used for recovering except that DC coefficient in the frame, and it is mainly finished other coefficient that runlength decoder 23 is exported and carries out the inverse quantization computing.In the inverse quantization calculating process, (v) (u) obtained through tabling look-up by the pairing row and column of coefficient employed W (w); Quantiser-scan is then obtained through tabling look-up by the code word quantiser-scale-code that solves from code stream.
Write macro block memory 25 by DC coefficient and other coefficient in the frame of coefficient producer 24 outputs according to certain scanning sequency.The data that are admitted to IDCT output through macro block memory 25 adjusted data are more directly sent into movement compensating circuit 29.Two macro block memories are arranged in the core codec unit 3, and its read-write hocketed by the macro block decoding cycle.The effect of macro block memory 25 is to realize counter-scanning conversion and the adaptive IDCT computing in frame/field.
Meanwhile, motion vector generator 27 will go out motion vector value according to the data computation behind the variable length decoding.The calculating of motion vector value is divided into two steps: the one, and the difference delta of calculating kinematical vector, the 2nd, carry out differential decoding.Motion-code and motion-residual that motion vector generator 27 at first solves according to length variable decoder 22, and the value of decoding parametric f-code according to the method for defined in the Moving Picture Experts Group-2, calculate the difference delta of motion vector.And then delta value that calculates and corresponding motion vector predictor addition, thereby obtain real motion vector value, upgrade corresponding fallout predictor simultaneously.Subsequently, decode controller 28 produces the address of reading reference frame memory 30 according to the motion vector value that calculates, and the reference data that obtains of address is sent to movement compensating circuit 29 thus.The block diagram of motion vector generator as shown in Figure 4.
In movement compensating circuit 29, reference data is handled through half-pix earlier and is obtained real reference value, then as the case may be, carries out motion compensation calculations with the IDCT dateout, finally obtains YUV video data.The YUV video data of core codec unit 3 output is sent to display buffer unit 4 on the one hand, for demonstration: on the other hand, if present frame is I frame or P frame, also will be written into reference frame memory 30 simultaneously by their, as subsequently the P frame or the predictive frame of B frame.
In core codec unit 3, whole decoding process is all controlled by decode controller 28.Decode controller 28 comprises isochronous controller and parser two parts.Isochronous controller mainly is responsible for the Synchronization Control to each decoding circuit.It is that the basis produces a series of fixed time sequence (comprising Slice, macro block, piece, IDCT sequential and the sequential relevant with various header informations) with the decode clock, produce various synchronizing signals according to these fixed time sequences then, and deliver to corresponding decoding circuit, thereby realize Synchronization Control to each circuit of video decode.Parser is carried out syntactic analysis with length variable decoder 22 to bit stream data, and the decoding parametric that solves is offered each decoding circuit, also provides various decodings required control signal simultaneously.Parser in this programme adds memory cell by programmable logic device and some to be formed, whole instructions that it can finish in the Moving Picture Experts Group-2 to be comprised, as: test, redirect, branch, condition, assignment, wait, circulation etc.; And the time of carrying out all instructions all have only a decode clock cycle, it is easy to each decoding circuit synchronous like this.There is microcode outside in the loading/memorizing unit according to the design of MPEG-2 and hardware decode procedure, by revising the flow direction that these microcodes can change decoding program, thus the decoding process of control of video decoder 3.
Fig. 5 represents the block diagram of digital HDTV source decoder of the video decode of the first embodiment of the present invention.In Fig. 5, wherein core codec unit 3 is at first adjusted the input video code stream with data buffer 51, and carry out variable length decoding and runs decoding according to various decoding parametrics, carry out the calculating of IDCT coefficient and motion vector value then respectively according to decoded data.On the one hand, the data of coefficient producer 54 in the core codec unit 3 after according to variable length decoding and runs decoding, recover DC coefficient and other coefficient in the frame, and carry out inverse quantization, then the data behind the inverse quantization are write macro block memory 55 according to certain scanning sequency.Be admitted to idct circuit 56 again through macro block memory 55 adjusted data, last, the data of IDCT output enter movement compensating circuit 59.On the other hand, the motion vector generator 57 in the core codec unit 3 calculates the difference of motion vector according to the data behind the variable length decoding, and with the value addition of motion vector predictor, obtain real motion vector value.Subsequently, the decode controller 58 in the core codec unit 3 produces the address of reading reference frame memory 60 according to motion vector value, and the address obtains data and is sent to movement compensating circuit 59 thus.In movement compensating circuit 59, reference data is handled through half-pix earlier and is obtained real reference value, then as the case may be, carries out motion compensation calculations with the IDCT dateout, finally obtains YUV video data.The YUV video data of core codec unit 3 outputs is sent to display buffer unit 4, on the one hand for demonstration; On the other hand, if present frame is I frame or P frame, then their simultaneously also will be written into reference frame memory 70, as subsequently the P frame or the predictive frame of B frame.
Fig. 6 represents the block diagram of digital SDTV source decoder of the video decode of the second embodiment of the present invention, in Fig. 6, core codec unit 3 is at first adjusted the video codeword data stream buffer 61 of input, and carry out variable length decoding and runs decoding during according to various decoding parametric, carry out the calculating of IDCT coefficient and motion vector value then respectively according to decoded data.On the one hand, the data of coefficient producer 64 in the core codec unit 3 after according to variable length decoding and runs decoding, recover DC coefficient and other coefficient in the frame, and carry out inverse quantization, then the data behind the inverse quantization are write macro block memory 65 according to certain scanning sequency.Be admitted to idct circuit 66 again through macro block memory 65 adjusted data, last, the data of IDCT output enter movement compensating circuit 69.On the other hand, the motion vector generator 67 in the core codec unit 3 calculates the difference of motion vector according to the data behind the variable length decoding, and with the value addition of motion vector predictor, obtain real motion vector value.Subsequently, the decode controller 68 in the core codec unit 3 produces the address of reading reference frame memory 70 according to motion vector value, and the address obtains reference data and is sent to movement compensating circuit 69 thus.In movement compensating circuit 69, reference data is handled through half-pix earlier and is obtained real reference value, then as the case may be, carries out motion compensation calculations with the IDCT dateout, finally obtains YUV video data.The YUV video data of core codec unit 3 outputs is sent to display buffer unit 4, on the one hand for demonstration; On the other hand, if present frame is I frame or P frame, then their simultaneously also will be written into reference frame memory 70, as subsequently the P frame or the predictive frame of B frame.Because the input bit rate of SDTV is lower than EDTV, so the operating frequency of each functional unit of SDTV source decoder also all is lower than HDTV.
In a word, the digital information source decoding device of video decode of the present invention not only can be used for digital high-definition television (HDTV) but also can be used for digital standard definition television (SDTV).
Claims (6)
1, a kind of digital information source decoding device that is used for the video decode of SDTV or HDTV, this decoder is formed by separating again with unit, system control unit, core codec unit, display buffer unit, post-processing unit etc., it is characterized in that, its core codec unit is as video decoding unit, and this unit comprises:
Data buffer is used to adjust the video code flow of input;
Length variable decoder, it adopts the parallel decoding structure, is used for the serial code stream of data buffer output is carried out variable length decoding;
Runlength decoder is connected to the output of length variable decoder, is used to finish runs decoding;
Coefficient producer is used for recovering DC coefficient and other coefficient in the frame, and carries out inverse quantization after decoding;
The macro block memory is used for writing wherein according to DC coefficient and other coefficient in the frame of certain scanning sequency after inverse quantization;
Idct circuit is used to carry out the IDCT computing;
The motion vector generator is used for calculating motion vector value according to the data behind the variable length decoding;
Decode controller is used for producing the address of reading reference frame memory according to motion vector value, and the address obtains reference data thus, and it also is used to control the whole decoding process of core codec unit;
Movement compensating circuit obtains real reference value with the reference data process half-pix processing of importing earlier, carries out motion compensation calculations with the IDCT dateout, finally obtains yuv data, delivers to the display buffer unit, for demonstration;
Reference frame memory when core codec unit output video yuv data, if preceding frame is I frame and P frame, then is written into wherein as the predicted value of P frame and B frame subsequently.
2, according to the digital information source decoding device of the video decode of claim 1, it is characterized in that the length variable decoder of its core codec unit is made up of two input registers, a Barrel Shifter, a lookup table circuit and an accumulator.
3, according to the digital information source decoding device of the video decode of claim 1, it is characterized in that the runlength decoder of its core codec unit is made up of a plurality of comparators, Port Multiplier and register.
4, according to the digital information source decoding device of the video decode of claim 1, it is characterized in that the coefficient producer of its core codec unit comprises:
DC coefficient generator in the frame according to decoded data, obtains DC coefficient in the frame;
Other coefficient producer recovers to remove those coefficients of DC coefficient in the frame, and carries out the inverse quantization computing.
5, according to the digital information source decoding device of the video decode of claim 1, it is characterized in that macro block memory on two is arranged in the core codec unit, its read-write hocketed by the macro block decoding cycle.
6, according to the digital information source decoding device of the video decode of claim 1, it is characterized in that the decode controller of core codec unit comprises:
Isochronous controller is used for each decoding circuit is carried out Synchronization Control;
Parser is used for bit stream data is carried out syntactic analysis, and provides decoding parametric and various control signal to each decoding circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 98126137 CN1222039A (en) | 1998-12-25 | 1998-12-25 | Digital information source decoder decoded by video |
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| CN 98126137 CN1222039A (en) | 1998-12-25 | 1998-12-25 | Digital information source decoder decoded by video |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1306822C (en) * | 2004-07-30 | 2007-03-21 | 联合信源数字音视频技术（北京）有限公司 | Vido decoder based on software and hardware cooperative control |
| CN100442853C (en) * | 2006-06-01 | 2008-12-10 | 上海交通大学 | Runs decoding, anti-scanning, anti-quantization and anti-inverting method and apparatus |
| CN1751518B (en) * | 2003-02-18 | 2010-12-01 | 诺基亚有限公司 | Picture coding method |
| CN101383897B (en) * | 2007-09-05 | 2011-08-17 | 索尼株式会社 | Image processing device and method |
| CN101822052B (en) * | 2007-08-09 | 2012-05-23 | 国立大学法人大阪大学 | Video stream processing device, its control method |
| CN1922884B (en) * | 2004-02-20 | 2012-05-23 | 三叉微系统(远东)有限公司 | Method of video decoding |
-
1998
- 1998-12-25 CN CN 98126137 patent/CN1222039A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1751518B (en) * | 2003-02-18 | 2010-12-01 | 诺基亚有限公司 | Picture coding method |
| CN1922884B (en) * | 2004-02-20 | 2012-05-23 | 三叉微系统(远东)有限公司 | Method of video decoding |
| CN1306822C (en) * | 2004-07-30 | 2007-03-21 | 联合信源数字音视频技术（北京）有限公司 | Vido decoder based on software and hardware cooperative control |
| CN100442853C (en) * | 2006-06-01 | 2008-12-10 | 上海交通大学 | Runs decoding, anti-scanning, anti-quantization and anti-inverting method and apparatus |
| CN101822052B (en) * | 2007-08-09 | 2012-05-23 | 国立大学法人大阪大学 | Video stream processing device, its control method |
| CN101383897B (en) * | 2007-09-05 | 2011-08-17 | 索尼株式会社 | Image processing device and method |
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