CN101516030B - Data processing circuit and processing method with multi-format image coding and decoding functions - Google Patents
Data processing circuit and processing method with multi-format image coding and decoding functions Download PDFInfo
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Abstract
The invention provides a data processing circuit and a processing method with multi-format image coding and decoding functions, wherein the data processing circuit includes a reading unit for reading a plurality of operation instructions and a plurality of original data from a memory; a plurality of execution units, wherein each execution unit is used for executing a image format coding and decoding instruction to operate the plurality of original data into corresponding a plurality of result data; and a instruction decoding unit for analyzing the plurality of operation instructions, generating corresponding a plurality of image format coding and decoding instructions, and sending the image format coding and decoding instructions to the plurality of corresponding execution units according to performance of the plurality of execution units.
Description
Technical field
The invention relates to a kind of data processing circuit, and particularly relevant for a kind of data processing circuit with multi-format image codec functions, can support video standards also can process simultaneously coding and the decoding of the data of video standards.
Background technology
Because the progress of science and technology, video coding and decoding technology be in the information communication scientific and technological industry technology such as consumer electronics take multimedia as main shaft application, information, network communication, indispensable guardian technique.International standard from video coding and decoding technology, with international telecommunication union telecommunication standardization's door (ITU-T) Video coding standard for example H.261, H.262, H.263 and H.264, and the video encoding standard that adopts of International Standards Organization (ISO) and International Electrotechnical Commission (IEC) MPEG-1 for example, MPEG-2, MPEG-4 and MPEG-21 are main, and its applicable various application comprise video conference and picture telephone, video storage (VCD/DVD/HD-DVD), the individual plays with oneself (Portable Media Player), home audio-visual center (Home Media Center), broadcasting video (cable TV, terrestrial broadcasting, satellite television and DSL), video monitoring and video streaming etc.
And construction image codec has two kinds of methods: the one, adopt Application Specific Integrated Circuit (hereinafter referred ASIC), the 2nd, single-instruction multiple-data stream (SIMD) (the Single Instruction Multiple Data of employing programmable, hereinafter referred SIMD) processing unit, in the SIMD processing unit, control a plurality of processing units with a controller, namely simultaneously in one group of data each is carried out respectively identical operation and come concurrency on the implementation space, the for example MMX of Intel or SSE, and the 3D Now! of AMD Technology.
Adopt traditional ASIC construction image codec, this image codec is with the advantage of tool low power consumption, but it needs long hardware designs and developmental research, and each ASIC can only be used for a kind of image codec of form, and the Video Codec standard still has too many parameter at present, to such an extent as to the exploitation ASIC circuit of can not taking risks.On the other hand, as adopt SIMD processing unit construction image codec, this kind image codec can be realized various software definition application and customized function (utilization high-level language) easily, can also reuse for hardware platform in each of holding mutually, but this kind image codec itself has higher electric quantity consumption, and needs to drop into the Software for Design research and development of higher degree.
Therefore being necessary provides a kind of new data processing circuit with multi-format image codec functions, and it has advantages of changeability, high-performance, low complex degree and low power consumption simultaneously, to address the above problem.
Summary of the invention
In view of the demand, the object of the present invention is to provide a kind of data processing circuit with multi-format image codec functions, can support video standards also can process simultaneously coding and the decoding of the data of video standards, and have advantages of simultaneously changeability, high-performance, low complex degree and low power consumption, that is the advantage of double ASIC and SIMD processing unit construction image codec.
The present invention proposes a kind of data processing circuit with multi-format image codec functions, and it comprises: a reading unit, in order to read a plurality of operational orders and a plurality of initial data from an internal memory; A plurality of performance elements, each execution units are carried out a kind of image format coding and decoding instruction, respectively above-mentioned a plurality of initial data computings are become corresponding result data; An and instruction decode unit, in order to analyzing above-mentioned a plurality of operational order and to produce corresponding a plurality of image format coding and decoding instruction, and according to the performance of above-mentioned a plurality of performance elements above-mentioned image format coding and decoding instruction is sent in the performance element of above-mentioned a plurality of correspondences.
The present invention also proposes a kind of data processing method with multi-format image codec functions, and it comprises the following steps: to capture a plurality of operational orders and corresponding a plurality of initial data from an internal memory; Analyzing above-mentioned a plurality of operational order makes each operational order produce a corresponding image format coding and decoding instruction; And according to the performance of a plurality of performance elements, above-mentioned image format coding and decoding instruction is sent into respectively in corresponding a plurality of performance elements, will above-mentioned a plurality of initial data computings to become the result data of correspondences.
The present invention discloses a kind of data processing circuit with multi-format image codec functions, can support video standards also can process simultaneously coding and the decoding of the data of video standards, and it has following advantages:
1. data processing circuit of the present invention can be processed the signal of the image of tool different coding form simultaneously, namely process simultaneously the divided frame of at least two kinds of different image coding forms of tool, for example can process simultaneously at least MPEG2, MPEG4, H.264, two kinds divided frame wherein in VC-1, RM or the following image coding form, will significantly promote the treatment efficiency of image data;
2. when HardwareUpgring or expansion, the software of data processing circuit of the present invention and firmware will need not revised, and namely data processing circuit can determine best image data treatment efficiency according to the performance of hardware;
3. process a plurality of instructions because data processing circuit of the present invention can be parallel to the same time, so that data turnover internal memory number of times reduces, therefore, will reduce the time of signal of video signal processing and the power consumption of data processing circuit;
4. because data processing circuit of the present invention has expandability, when future, new coded format occurred, only need to compare for new and old two kinds of coded formats, feature for new coded format, revise corresponding unit in the data processing circuit of originally supporting old coded format, this will significantly reduce the complexity that new treatment circuit is developed, and significantly shortens the exploitation time-histories of new treatment circuit.
Description of drawings
In order to make the auditor can further understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing, yet accompanying drawing only provide with reference to and explanation, the present invention is limited, wherein:
Fig. 1 is the structural representation that has the data processing circuit of multi-format image codec functions in the first embodiment of the invention.
Fig. 2 A is an improvement structural representation of the data processing circuit with multi-format image codec functions of first embodiment of the invention.
Fig. 2 B is another structure-improved schematic diagram of the data processing circuit with multi-format image codec functions of first embodiment of the invention.
Fig. 2 C is another structure-improved schematic diagram of the data processing circuit with multi-format image codec functions of first embodiment of the invention.
Fig. 3 is the flow chart that has the data processing method of multi-format image codec functions in the first embodiment of the invention.
Embodiment
For making narration of the present invention more detailed and complete, please refer to following description and cooperate relevant drawings.
Fig. 1 is the structural representation that has the data processing circuit of multi-format image codec functions in the first embodiment of the invention, as shown in the figure, instruction cycle with data processing circuit 100 of multi-format image codec functions has 5 stages: the acquisition of instruction and execution (Instruction Fetch and Execute, hereinafter referred I/DF) stage 110, instruction decoding (Instruction Decode, hereinafter referred ID) stage 120, (Execution is carried out in instruction, hereinafter referred EX) stage 130, memory access (Memory access, hereinafter referred MEM) stage 140 and write-back (Write Back, the hereinafter referred WB) stage 150.
Comprise instruction reading unit 112 and data-reading unit 114 in the I/DF stage 110, it utilizes direct memory access (DMA) from internal memory (not shown) acquisition operational order and arithmetic element desired data.Include instruction decoding unit 122 in the ID stage 120 is in order to decode operational order and to send into performance element corresponding in the EX stage 130.The EX stage 130 comprises variable length code (Variable Length Coding) or context adaptive binary coding (Context Adaptive Binary Arithmetic Coding) (hereinafter referred VLCD/CABAC) performance element 131 that counts, direct current exchanges prediction (AC/DC prediction) or scanner uni counter-scanning (hereinafter referred ADCD/SIS) performance element 132, quantize and inverse quantization (Quantization and Inverse Quantization, hereinafter referred QIQ) performance element 133, one conversion and inverse transform (Transform and Inverse Transform, hereinafter referred TIT) performance element 134, remove block effect filtering (De-blocking Filter, hereinafter referred DIF) performance element 135 and interpolation/dynamically estimate and compensate (Intra/Motion estimation and compensation, hereinafter referred Com/Est) performance element 136.In the MEM stage 140, utilize buffer cell 142 to store the temporal data that above-mentioned arbitrary performance element 131-136 sends into, these temporal datas again loopback return above-mentioned arbitrary performance element 131-136.In the WB stage 150, utilize to write back unit 152, deposit the bit crossfire (bit-stream) behind decoded image data or the coding in internal memory.
When in the ID stage 120, utilizing instruction decode unit 122 after instruction decoding, data processing circuit of the present invention can according to the feature of this instruction and in the EX stage 130 the present performance of performance element decide the flow direction of image data, this is the most important feature of the present invention, also therefore the performance element 131-136 in the EX stage 130 can carry out simultaneously as H.264, coded command or the decoding instruction of the data of MPEG4, MPEG2, the video standards such as VC-1, RM.In addition, the performance element 131-136 in the EX stage 130 also can continue and side by side carry out, to finish the image coding of single form.
Hereinafter will want to carry out H.264 simultaneously with the raw video data of data-reading unit 114 input, the example that is encoded to of MPEG4 describes.When the raw video data are carried out the MPEG4 image compression first, understand and to pass through Com/Est performance element 136 from the image data that data-reading unit 114 obtains, do dynamic pre-estimating, obtain its motion-vector (Motion Vector) and absolute difference and (SAD), when absolute difference with when too large, original image data is sent into TIT performance element 134 do discrete cosine transform (Discrete Cosine Transform), otherwise, then the image data of present image data and last reduction is done the difference computing, difference is sent into TIT performance element 134 do discrete cosine transform.Then, the data of again discrete cosine transform being finished is made quantization operations in QIQ performance element 133, and the data after will quantizing is done direct current interchange prediction (AC/DC prediction) in ADCD/SIS performance element 132, import the complete data of direct current interchange prediction into VLCD/CABAC performance element 131 more afterwards and do variable length code (Variable Length Code), the mode that original image data is compressed into basic bit crossfire (Base Layer Bits Stream) reaches buffer cell 142, and via writing back unit 152, basic bit crossfire is deposited back internal memory.
In addition, quantize complete data and do the direct current interchange prediction except importing ADCD/SIS performance element 132 into, also do the counter-rotating quantification with importing simultaneously QIQ performance element 133 into, the data after quantizing of will reversing are again imported TIT performance element 134 into and are done discrete cosine transform, then at Com/Est performance element 136, according to before the result that calculates during dynamic pre-estimating do dynamic compensation (Motion Compensation), to reconstruct an image as the reference image of next image.
On the other hand, want to carry out H.264 image compression such as these raw video data, data processing circuit of the present invention can be first according to the present performance of each performance element in the EX stage 130 and MPEG4 image compression and H.264 the difference of image compression form decide the flow direction of initial data.The MPEG4 image compression and H.264 the difference that has of image compression itself comprise:
H.264 image compression has 7 predictive pictures block size (macro block) types, these types have 6 * 16,16 * 8,8 * 16,8 * 8,8 * 4,4 * 8,4 * 4, in addition, and the difference of setting according to compressed software, reference picture at most can be forward 31 and 31 backward, motion-vector can be as accurate as 1/4th pixels, can significantly promote thus the pre-measuring precision on the time shaft.Therefore, when changing, be namely to adopt integer as conversion coefficient with 4 * 4 matrixes as the conversion elementary cell when H.264 integer DCT processes, therefore when TIT performance element 134 carries out inverse transform, do not have the problem that to mate after adopting the fractional arithmetic mode to reduce.Aspect the conversion coefficient data that quantized, it is the coded system of utilizing CABAC, namely the coded system of CABAC can be added up the probability that particular code occurs according to the content of coding automatically in VLCD/CABAC performance element 131, and then produces the coding schedule that is best suited for present image.VLCD also can do CAVLC coding H.264 in addition.
In addition, H.264 in the difference for compress mode, also divide into different configuration (Profile) according to different content application, these configurations are respectively Baseline Profile, Main Profile, Extension Profile, also have corresponding film size and bit rate grade in each configuration, in definition, then be to be distinguished to Level 5.1 by Level 1, contain different resolution and the flow application scopes such as little picture and HD picture.
Data processing circuit of the present invention can be according to H.264 configuration and VLCD/CABAC performance element 131, ADCD/SIS performance element 132, QIQ performance element 133, TIT performance element 134, DIF performance element 135 and Com/Est performance element 136 in the EX stage 130, whether each performance element is idle at present, decides to begin to carry out image compression H.264 or carry out a certain compression process in the image compression H.264.
In addition, data processing circuit of the present invention has extendibility, increase image data coding or decoding speed such as wish, can increase any number of VLCD/CABAC performance element 131 in the EX stage 130, ADCD/SIS performance element 132, QIQ performance element 133, TIT performance element 134, DIF performance element 135 or Com/Est performance element 136, at HardwareUpgring or after expanding, the software of data processing circuit of the present invention and firmware will need not revised, be that data processing circuit can determine best image data treatment efficiency according to the performance of hardware, please referring to Fig. 2 A.
Fig. 2 A is an improvement structural representation that has the data processing circuit of multi-format image codec functions in the first embodiment of the invention, as shown in the figure, the EX stage 330 in the data processing circuit 300 comprises two DIF performance element 335a and 335b and two Com/ Est performance element 336a and 336b, will increase image data coding or decoding speed by this design.In addition, have the part of identical diagram numbering among Fig. 2 A with Fig. 1, have identical function and feature, the related description of please showing referring to Fig. 1.
In addition, when future, new coded format occurred, data processing circuit of the present invention only needed to compare for new and old two kinds of coded formats, for the feature of new coded format, revises corresponding unit in the data processing circuit of originally supporting old coded format.For instance, new coded format is the improvement version of old coded format, the function of the two is close, image data coding or decoding speed have only significantly been increased, then can directly improve by a small margin for original data processing circuit, will significantly reduce the complexity of new treatment circuit exploitation by design of the present invention, significantly shorten the exploitation time-histories of new treatment circuit, please referring to Fig. 2 B.
Fig. 2 B is another structure-improved schematic diagram of the data processing circuit with multi-format image codec functions of first embodiment of the invention.As shown in the figure, every kind of performance element has two in the EX stage 430, the EX stage 430 in the data processing circuit 400 comprises VLCD/ CABAC performance element 431a and 431b, ADCD/ SIS performance element 432a and 432b, QIQ performance element 433a and 433b, TIT performance element 434a and 434b, DIF performance element 435a and 435b and Com/ Est performance element 436a and 436b, will significantly increase image data coding or decoding speed by this design.In addition, have the part of identical diagram numbering among Fig. 2 B with Fig. 1, have identical function and feature, the related description of please showing referring to Fig. 1.
Fig. 2 C is another structure-improved schematic diagram that has the data processing circuit of multi-format image codec functions in the first embodiment of the invention, as shown in the figure, the EX stage 530 in the data processing circuit 500 comprises new TIT performance element 534, in the image coding form in future, change, when future new coded format when H.265 occurring, data processing circuit of the present invention only need be for feature H.265, revise original unit corresponding in the data processing circuit of old coded format such as the TIT performance element 134 among Fig. 1 supported, modification by the part, can increase image data coding or decoding speed, will significantly reduce the complexity of new treatment circuit exploitation by design of the present invention, significantly shorten the exploitation time-histories of new treatment circuit.In addition, have the part of identical diagram numbering among Fig. 2 C with Fig. 1, have identical function and feature, the related description of please showing referring to Fig. 1.
Fig. 3 is the flow chart that has the data processing method of multi-format image codec functions in the first embodiment of the invention, at first, capture a plurality of operational orders and corresponding a plurality of initial data (step S201) from internal memory, then, analyzing above-mentioned operational order makes each operational order produce corresponding image format coding and decoding instruction (step S203), and according to the performance of a plurality of kinds of performance elements, above-mentioned image format coding and decoding instruction is sent into respectively in the corresponding performance element, so that above-mentioned initial data computing is become corresponding result data (step S205), every kind of performance element comprises a VLCD/CABAC performance element at least, the ADCD/SIS performance element, the QIQ performance element, the TIT performance element, DIF performance element or Com/Est performance element are the variable-length coded command in order to carry out corresponding image format coding and decoding instruction, the coded command that counts of context adaptive binary, direct current exchanges predict command, the instruction of scanner uni counter-scanning, quantize and the inverse quantization instruction, conversion and inverse transform instruction, block effect filter command or interpolation/dynamically estimate and compensating instruction.At last, optionally this result data is deposited back internal memory (step S207).
In sum, data processing circuit with multi-format image codec functions of the present invention, can support video standards also can process simultaneously coding and the decoding of the data of video standards, really can have the advantage of changeability, high-performance, low complex degree and low power consumption to reach purpose of the present invention.
Although the present invention discloses as above with preferred embodiment; right its be not to limit the present invention, anyly have the knack of this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that claims define.
Claims (23)
1. data processing circuit with multi-format image codec functions comprises:
Reading unit is in order to read a plurality of operational orders and a plurality of initial data from internal memory;
Instruction decode unit is in order to analyze above-mentioned a plurality of operational order and to produce corresponding a plurality of image format coding and decoding instruction; And
A plurality of performance elements, each execution units are carried out the corresponding image format coding and decoding instruction after above-mentioned this instruction decode unit is analyzed, respectively above-mentioned a plurality of initial data computings are become corresponding a plurality of result datas;
Wherein, above-mentioned data processing circuit with multi-format image codec functions is sent into above-mentioned image format coding and decoding instruction respectively in corresponding above-mentioned a plurality of performance elements according to the feature of the performance of above-mentioned a plurality of performance elements and above-mentioned a plurality of operational orders and is determined the execution sequence of above-mentioned a plurality of performance elements.
2. the data processing circuit with multi-format image codec functions according to claim 1, wherein above-mentioned each performance element comprises arithmetic element at least, in order to carry out a kind of above-mentioned image format coding and decoding instruction.
3. the data processing circuit with multi-format image codec functions according to claim 2, wherein above-mentioned arithmetic element is that count coding performance element, direct current of variable length code performance element, context adaptive binary exchanges prediction execution unit, scanner uni counter-scanning performance element, quantification and inverse quantization performance element, conversion and inverse transform performance element, block effect filtering performance element, interpolation estimation and compensation performance element, dynamically estimates and compensate performance element and interpolation and dynamically estimate and to compensate performance element wherein a kind of.
4. the data processing circuit with multi-format image codec functions according to claim 1, wherein above-mentioned a plurality of initial data is a plurality of raw video data, and the above results data are the image coding data.
5. the data processing circuit with multi-format image codec functions according to claim 4, wherein above-mentioned image coding data are MPEG2 formatted data, MPEG4 formatted data, H.264 formatted data, VC-1 formatted data or RM formatted data.
6. the data processing circuit with multi-format image codec functions according to claim 1, wherein above-mentioned a plurality of initial data is a plurality of image coding data, and the above results data are the raw video data.
7. the data processing circuit with multi-format image codec functions according to claim 6, wherein above-mentioned image coding data are MPEG2 formatted data, MPEG4 formatted data, H.264 formatted data, VC-1 formatted data or RM formatted data.
8. the data processing circuit with multi-format image codec functions according to claim 1 wherein also comprises:
Storage element is in order to store the above results data and to deposit the above results data in above-mentioned internal memory.
9. the data processing circuit with multi-format image codec functions according to claim 8, wherein above-mentioned storage element utilizes direct memory access to deposit the above results data in above-mentioned internal memory.
10. the data processing circuit with multi-format image codec functions according to claim 1, wherein above-mentioned reading unit utilizes direct memory access to capture above-mentioned a plurality of operational order and above-mentioned a plurality of initial data from above-mentioned internal memory.
11. the data processing circuit with multi-format image codec functions according to claim 1, wherein above-mentioned image format coding and decoding instruction be variable length code instruction, context adaptive binary count coded command, direct current exchange predict command, the instruction of scanner uni counter-scanning, quantification and inverse quantization instruction, conversion and inverse transform instruction, block effect filter command, interpolation estimation and compensating instruction, dynamically estimation and compensating instruction and interpolation with dynamically estimate and compensating instruction one of them.
12. the data processing method with multi-format image codec functions, it comprises the following steps:
Read a plurality of operational orders and corresponding a plurality of initial data from internal memory;
Analyzing above-mentioned a plurality of operational order makes each operational order produce corresponding image format coding and decoding instruction; And
According to the performance of a plurality of performance elements and the feature of above-mentioned a plurality of operational orders, send into respectively above-mentioned image format coding and decoding instruction in corresponding a plurality of performance elements and determine the execution sequence of above-mentioned a plurality of performance elements, will above-mentioned a plurality of initial data computings to become the result data of correspondences.
13. the data processing method with multi-format image codec functions according to claim 12, wherein above-mentioned each performance element comprises arithmetic element at least, in order to carry out a kind of above-mentioned image format coding and decoding instruction.
14. the data processing method with multi-format image codec functions according to claim 13, wherein above-mentioned arithmetic element is that count coding performance element, direct current of variable length code performance element, context adaptive binary exchanges prediction execution unit, scanner uni counter-scanning performance element, quantification and inverse quantization performance element, conversion and inverse transform performance element, block effect filtering performance element, interpolation estimation and compensation performance element, dynamically estimates and compensate performance element and interpolation and dynamically estimate and to compensate performance element wherein a kind of.
15. the data processing method with multi-format image codec functions according to claim 12, wherein above-mentioned a plurality of initial data is a plurality of raw video data, and the above results data are the image coding data.
16. the data processing method with multi-format image codec functions according to claim 15, wherein above-mentioned image coding data are MPEG2 formatted data, MPEG4 formatted data, H.264 formatted data, VC-1 formatted data or RM formatted data.
17. the data processing method with multi-format image codec functions according to claim 12, wherein above-mentioned a plurality of initial data is a plurality of image coding data, and the above results data are the raw video data.
18. the data processing method with multi-format image codec functions according to claim 17, wherein above-mentioned image coding data are MPEG2 formatted data, MPEG4 formatted data, H.264 formatted data, VC-1 formatted data or RM formatted data.
19. the data processing method with multi-format image codec functions according to claim 12 comprises the following steps:
Utilize buffer cell temporarily to store the above results data.
20. the data processing method with multi-format image codec functions according to claim 12 also comprises the following steps:
Deposit the above results data in above-mentioned internal memory.
21. the data processing method with multi-format image codec functions according to claim 20 wherein utilizes direct memory access to deposit the above results data in above-mentioned internal memory.
22. the data processing method with multi-format image codec functions according to claim 12 wherein also comprises from the step that above-mentioned internal memory captures above-mentioned a plurality of operational order and corresponding a plurality of initial data:
Utilize direct memory access to capture above-mentioned a plurality of operational order and above-mentioned a plurality of initial data from above-mentioned internal memory.
23. the data processing method with multi-format image codec functions according to claim 12, wherein above-mentioned image format coding and decoding instruction can be variable length code instruction, context adaptive binary count coded command, direct current exchange predict command, and counter-scanning instruction, quantification and inverse quantization instruction, conversion and inverse transform instruction, block effect filter command, interpolation estimation and compensating instruction, dynamically estimation and compensating instruction and interpolation with dynamically estimate and compensating unit one of them.
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