CN101778288A - Method and device for decoding digital video - Google Patents
Method and device for decoding digital video Download PDFInfo
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- CN101778288A CN101778288A CN 201010117136 CN201010117136A CN101778288A CN 101778288 A CN101778288 A CN 101778288A CN 201010117136 CN201010117136 CN 201010117136 CN 201010117136 A CN201010117136 A CN 201010117136A CN 101778288 A CN101778288 A CN 101778288A
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Abstract
The invention provides a method and a device for decoding a digital video. The method for decoding the digital video comprises the following steps: dividing a macro-block decoding process of the video into N decoding stages, wherein N is a natural number which is more than 1; and performing the first to Nth decoding stages sequentially on the current macro-block, wherein when the current macro-block is subjected to the ith decoding stage, the next macro-block is subjected to the i-1th decoding stage in parallel, i is a natural number and is less than or equal to N and more than 1. In the method, the macro-block decoding process is divided into a plurality of decoding stages and the decoding operation of each decoding stage is performed according to the dependency relation and the implementation complexity of each decoding task in the macro-block decoding process of the video. Through the pipelining decoding process, the decoding efficiency can be greatly improved and the high-definition real-time decoding can be realized.
Description
Technical field
The present invention relates to a kind of digital video decoding method and device.
Background technology
Through developing 10 years, significant change has all taken place in audio/video coding technology itself and industry application background more.At present the source encoding standard that can select of audio frequency and video industry mainly contains three: MPEG-2, MPEG-4 AVC (be called for short AVC, also claim JVT, H.264), AVS.
MPEG-2 was formulated in 1994, was finished by MPEG expert group, belonged to first generation information source standard.Through ten years development, MPEG-2 has become the most current in the world at present audio and video standard.
H.264 standard is united formulation by ISO/IEC and ITU-T, indicates that the latest developments .H.264 video coding new standard of video compression technology adopts a series of up-to-date compress techniques, has improved compression ratio picture quality greatly.
AVS (Audio Video Coding Standard) standard is the abbreviation of " information technology advanced audio/video coding " series standard, be by autonomous first audio/video encoding standard that proposes of China, it is 2.4 times of MPEG2 on compression efficiency, with H.264 suitable.
MPEG-2 is at present ripe a kind of audio/video encoding standard, but owing to the technological obsolescence more high reason of need upgrading and charge, stepping down from the stage of history in future is trend of the times; H.264 absolute predominance on higher compression ratio and the picture quality makes has possessed powerful competitiveness in the current and following audio frequency and video field, makes us and can't accept but its new patent grant policy is considered to too harshness; And AVS be based on China's innovative technology and part public technology from primary standard, code efficiency is with H.264 suitable, and technical scheme is succinct, the chip implementation complexity is low; And AVS has solved H.264 patent grant problem fast knot by succinct one-stop permission policy, is country, the international standard of open formulation, is easy to promote.
Therefore, in one current or quite long from now on period, the audio frequency and video field will present MPEG-2, H.264, the AVS situation of standing like the legs of a tripod.Quite a few market share will be continued capturing as first generation information source standard MPEG-2, H.264 also will progressively promote with its absolute technical advantage and come, and Chinese AVS with complete independent intellectual property right also will occupy a tiny space in the market in future (particularly continental market) with the terseness of its realization with than advantages such as low patent fees.This form a connecting link, the design of three standards coexistence multi-format decoders in period just is pushed to the arena of history thereupon.
MPEG-2, H.264, the system layer that adopted of AVS three all mainstream decoder is as follows:
1.MPEG-2 what video adopted is the system layer of MPEG-2, i.e. the 13818-1 agreement.
Move over 2.AVS the part of the system layer in the standard (being AVS-P1) is being shone the MPEG-2 system layer, therefore support the 13818-1 agreement fully.
3.H.264 then outside VCL, finished support to multiple transport layer by NAL:
1) is the RTP/TP agreement of various wired and any wireless network services in real time
2) file format such as ISO MP4 storage format and MMS form
3) wired H32X agreement of serving with wireless session
4) system of the MPEG-2 of broadcast service
Therefore, MPEG-2, AVS and be applied to broadcast service H.264 all adopted the MPEG-2 system layer.At DTV field MPEG-2, H.264, system layer agreement that AVS adopted also is that three kinds of standards integrated brought certain facility.
Support AVS, H.264, MPEG-2 multi-format decoder SD and high definition DTV chip, the integrated decoder of above-mentioned three kinds of video standards possesses the program decoding capability of three kinds of standards.But, before starting decoder, must at first judge the coding standard of video frequency program fast and effectively by corresponding recognizer, could be correct assign decoding instruction to corresponding decoder.The identification error of pattern will directly cause CPU to send wrong decoding instruction, and the speed of pattern recognition will directly influence the time of changing before program searching or the program.If can not normally carry out the phenomenon that the identification of Video Encoding Mode or identification error all will directly cause entire chip work paralysis or sound no shadow occur, image will seriously lag behind in the program handoff procedure and the speed of pattern recognition will cause more slowly.Therefore, effective pattern recognition fast design is to the performance important influence of whole DTV chip.And also must effectively remove after the pattern recognition AVS, H.264, the initial code among the MPEG-2 and AVS, the pseudo-initial code decoder in H.264 just can carry out follow-up normal decoder.The form difference of AVS, the pseudo-initial code in H.264, but have certain similitude.Therefore, take a kind of rational hardware designs can effectively remove AVS, H.264, the multiplexing of initial code among the MPEG-2 and pseudo-initial code consideration hardware capability as much as possible also be one of the major issue that will consider of numerous chip producer.
AVS is the latest digital Audio Video coding Standard with Chinese independent intellectual property right, is applied to great audio frequency and video fields such as high definition digital television, high definition VCD player, Web TV, video communication.The code efficiency of AVS is higher two to three times than MPEG2, with H.264 suitable.In realization, the complexity of AVS encoder be H.264 70%, the complexity of decoder be H.264 30%.The AVS standard of wideling popularize Chinese independent intellectual property right can be the patent fee that country saves multi-million dollar every year, has good market prospects and researching value.
For the AVS digital video decoder, especially for the great high-definition real-time AVS decoding of operand, the decoding computing of macro block mainly concentrates on obtain (the counter-scanning inverse quantization inverse transformation) of residual error data, the inter prediction data are obtained (comprise intra-prediction process, motion vector are obtained, picture element interpolation calculates, weight estimation handle) in the frame, data are rebuild, on these several big links of loop filtering.Simultaneously, data also are the keys that decoding realizes moving back and forth of interior external memory.
Present digital video decoding method generally is all links that order is carried out above-mentioned macro block decoding, like this, real-time decoding request operand for single-processor is too huge, needs processor to possess very strong calculation process ability, realizes that for hardware and software platform cost is very high.
Summary of the invention
The present invention aims to provide a kind of digital video decoding method and device, can solve the long problem of time of AVS decoding digital video process cost in the correlation technique.
According to an aspect of the present invention, provide a kind of digital video decoding method, it comprises: the macro-block decoding process of video is divided into N decode phase, and wherein, N is the natural number greater than 1; Current macro is carried out the 1st to N decode phase successively, wherein, when current macro is carried out i decode phase, concurrently next macro block is carried out i-1 decode phase, i is a natural number, and 1＜i≤N.
According to another aspect of the present invention, provide a kind of decoding digital video device, it comprises: N decoding unit, wherein, N is the quantity of the decode phase that is divided into of the macro-block decoding process of video, and j decoding unit carried out j decode phase, 1≤j≤N; Control unit is connected to N decoding unit, is used for controlling i-1 decoding unit and concurrently next macro block being carried out i-1 decode phase when i decoding unit carried out i decode phase to current macro, and wherein i is a natural number, and 1＜i≤N.
The present invention has realized following technique effect:
According to the dependence and the implementation complexity of each decoding task in the macro-block decoding process of video, the macro-block decoding process of video is divided into a plurality of decode phases, and the decode operation of parallel each decode phase of execution.By decode procedure like this streamline, can improve the decoding efficiency (especially for the AVS video) of various video greatly, realize high-definition real-time decoding.
Description of drawings
Fig. 1 is the schematic diagram according to dependence between the macroblock decode module of the AVS video of the embodiment of the invention;
Fig. 2 is the flow chart according to the digital video decoding method of the embodiment of the invention;
Fig. 3 is the schematic diagram according to the macro-block decoding process of the AVS video that is divided into 2 decode phases of the embodiment of the invention 1;
Fig. 4 is the schematic diagram according to each decode phase parallel processing of the embodiment of the invention 1;
Fig. 5 is the schematic diagram according to the macro-block decoding process of the AVS video that is divided into 4 decode phases of the embodiment of the invention 2;
Fig. 6 is the schematic diagram according to each decode phase parallel processing of the embodiment of the invention 2;
Fig. 7 is the decoding digital video schematic representation of apparatus according to the embodiment of the invention.
Embodiment
Below be example with the AVS video, describe digital video decoding method of the present invention in detail.But it will be appreciated by persons skilled in the art that digital video decoding method of the present invention can also be applied to the video of other kinds.
In AVS decoding realization flow, be that unit decodes with the macro block, the decoding of macro block is the core of whole AVS decoder.As shown in Figure 1, the decode procedure of each macro block is made up of following decoded portion:
1) the basic decoded information of macro block and residual error data decode phase, the macro block decoded portion that it mainly comprises has: macro block header information decoder (vld_header), residual error coefficient decoding (vld_luma and vld_chroma), motion vectors are calculated (get_pmv), predictive frame internal schema calculating (get_mode), are obtained the calculating of circle filtering intensity (get_bs), the inverse scan process (zigzag) on inter prediction reference block locations (get_ref_pos), each border of current macro;
2) inverse quantization of macro block and inverse transformation stage, the macro block decoded portion that it mainly comprises has: inverse quantization and inverse transformation process (dq_idct), read the reference block (dma_load) of each height piece of current macro by DMA;
3) forecasting process of macro block and data phase of regeneration, the macro block decoded portion that it mainly comprises has: and motion compensation (MotionCompensation, MC), in the frame or inter-frame block prediction (interpolation and intra_prediction) (so that obtaining predicting blocks of data), reconstructed blocks data (recon) (prediction data+residual error data);
4) loop filtering of macro block the processing stage, the macro block decoded portion that it mainly comprises has: loop filtering handles (deblocking), handle the back data stores (dma_save) on the chip external memory into by DMA.
Can analyze as shown in Figure 1 decoding dependence from the part of above-mentioned macro-block decoding process.
Digital video decoding method of the present invention is divided into a plurality of decode phases with above-mentioned macro-block decoding process, the above-mentioned decode phase of executed in parallel then, thus reduce decode time greatly, realize high-definition real-time AVS decoding.
As shown in Figure 2, the digital video decoding method according to the embodiment of the invention mainly comprises the steps:
S21 is divided into N decode phase with the macro-block decoding process of AVS video, and wherein, N is the natural number greater than 1;
S22 carries out the 1st to N decode phase successively to current macro, wherein, when described current macro is carried out i decode phase, concurrently next macro block is carried out i-1 decode phase, and wherein i is a natural number, and 1＜i≤N.
After described current macro is carried out i decode phase, be used for the entity that described current macro is carried out described i decode phase is read described next macro block, and described next macro block is carried out described i decode phase.
To describe digital video decoding method in detail by specific embodiment below.
Embodiment 1
In the present embodiment, N=2 promptly, is divided into first decode phase and second decode phase with above-mentioned macro-block decoding process.As shown in Figure 3, first decode phase mainly comprises: the inverse quantization of the basic decoded information of macro block and residual error data decode phase, macro block and inverse transformation stage, for example, the obtaining of the obtaining of the basic decoded information of macro block, residual error data, the inverse quantization of macro block and the inverse transformation of macro block; Second decode phase mainly comprises: the processing stage of the loop filtering of the forecasting process of macro block and data phase of regeneration, macro block, for example, the obtaining of the prediction data of macro block, the reconstruct of blocks of data and the loop filtering of macro block are handled.
Set forth the detailed process that the decode procedure of macro block is divided into first decode phase and second decode phase below.
1) as can be seen from Figure 1, the decoding of macro block header and residual error coefficient is the most basic part of whole system, the data that the decoding computing of other all modules all needs this part to provide.In addition, the variable that some important subsequent decodings use can directly calculate by the decoding of header, wherein, the variable of above-mentioned subsequent decoding use calculates and comprises: motion vectors is calculated, the predictive frame internal schema is calculated, obtain the inter prediction reference block locations.
In addition, as the two big branches that form of AVS decoding, obtaining of prediction data and residual error data is two paths of data, has independence completely.But before considering that carrying out prediction data calculates, be directed to inter prediction especially, need outside sheet, read in the sheet so that carry out interpolation calculation by DMA will locate reference block locations from reference frame data, this part data prepares to want equally spended time, therefore in the present embodiment, the inverse quantization of piece and the inverse transformation data-moving with DMA is got up synchronously.In fact, the inverse quantization in this stage and inverse transformation are handled and the data-moving of DMA walks abreast, and data operation quantity is also little, and the decode time of cost can be fewer.
Thereby, in the present embodiment, with the decode procedure (that is, the inverse quantization of the essential information of macro block and residual error data decode phase, macro block and inverse transformation stage) of above-mentioned macro block as first decode phase.
2) further, the type of macro block only is divided in the frame and interframe two big classes essentially, so the reconstruction of inter prediction processing and macro block in the frame is divided in the same decode phase.This wherein comprises the bigger pixel interpolation of operand and handles, but because its preparation (motion vector (motion vector, obtaining and the obtaining of reference data mv)) be assigned to first decode phase and finished, so the decode time of this a part of actual consumption is suitable with first decoded portion.
In addition, system is incorporated into macro-block level with loop filtering and realizes, rather than in the whole frame macro block uniform filtering when finishing of all decoding, and such benefit is the loop filtering intensity that can directly utilize first decode phase to calculate, and needn't go storage, expend memory source and process of reading once more.
In the present embodiment, with the decode procedure of above-mentioned macro block (that is, the loop filtering of the forecasting process of macro block and data phase of regeneration, macro block processing stage) as second decode phase.
Fig. 4 is the schematic diagram according to each decode phase parallel processing of the embodiment of the invention 1.As shown in Figure 4, after first macro block is executed first decode phase, first macro block is carried out second decode phase, and simultaneously second macro block carried out first decode phase.Equally, after second macro block executed first decode phase, second macro block carried out second decode phase, and simultaneously the 3rd macro block carried out first decode phase.
As seen, carry out first and second decode phases concurrently, thereby reduce decode time widely, improve decoding efficiency, realize high-definition real-time AVS decoding by above-mentioned.
Further, in the present embodiment, the operand of the operand of second decode phase and first decode phase is suitable, and just, the difference between the operand of first decode phase and second decode phase is less than threshold value.Be divided into two suitable decode phases of operand by decode procedure, win decode phase and second decode phase can be finished basically simultaneously, thereby further shortened decode time macro block.
Embodiment 2
In the present embodiment, N=4 promptly, is divided into above-mentioned macro-block decoding process: first decode phase, second decode phase, the 3rd decode phase and the 4th decode phase.As shown in Figure 5, first decode phase mainly comprises: the essential information of macro block and residual error data decode phase, for example, the obtaining of the obtaining of the essential information of macro block, residual error data; Second decode phase mainly comprises: the inverse quantization of macro block and inverse transformation stage, for example, the inverse quantization of macro block and the inverse transformation of macro block; The 3rd decode phase mainly comprises: the forecasting process of macro block and data phase of regeneration, for example, the reconstruct of the obtaining of the prediction data of macro block, blocks of data; The 4th decode phase mainly comprises: the processing stage of the loop filtering of macro block, for example, the loop filtering of macro block is handled.
Set forth the detailed process that the decode procedure of macro block is divided into first decode phase to the, four decode phases below.
1) as can be seen from Figure 1, the decoding of macro block header and residual error coefficient is the most basic part of whole system, the data that the decoding computing of other all modules all needs this part to provide.In addition, the variable that some important subsequent decodings use can directly calculate by the decoding of header (wherein, the variable that subsequent decoding uses calculates and comprises: motion vectors is calculated, the predictive frame internal schema is calculated, obtain the inter prediction reference block locations), therefore these partial fusion can be formed first decode phase together.The operand of this phase data is smaller, and major part is logic determines and jump instruction.
2) as the two big branches that form of AVS decoding, obtaining of prediction data and residual error data is two paths of data, has independence completely.But before considering that carrying out prediction data calculates, be directed to inter prediction especially, need outside sheet, read in the sheet so that carry out interpolation calculation by DMA will locate reference block locations from reference frame data, this part data prepares to want equally spended time, therefore the inverse quantization inverse transformation of the piece data-moving with DMA is got up synchronously, form second decode phase.In fact, the inverse quantization inverse transformation in this stage is handled and the data-moving of DMA walks abreast, and data operation quantity is also little, and the decode time of cost can be fewer, therefore also it can be included in first decode phase.
3) type of macro block only is divided in the frame and interframe two big classes essentially, so in the present embodiment the reconstruction of inter prediction processing and macro block in the frame is divided in the 3rd decode phase.This wherein comprises the bigger pixel interpolation of operand and handles, but because its preparation (motion vector (motion vector, obtaining and the obtaining of reference data mv)) be assigned to preceding two decode phases and finished, so the decode time of this a part of actual consumption is suitable with preceding two decode phases.
4) system is incorporated into the macro-block level realization with loop filtering, rather than in whole frame macro block uniform filtering when all decoding finishes, such benefit is the loop filtering intensity that can directly utilize first decode phase to calculate, and needn't go storage, expends memory source and process of reading once more.As the 4th decode phase, its operand and preceding three phases are also roughly suitable with the renewal of loop filtering and final deal with data.
Fig. 6 is the schematic diagram according to each decode phase parallel processing of the embodiment of the invention 2.As shown in Figure 4, after first macro block is executed first decode phase, first macro block is carried out second decode phase, and simultaneously second macro block carried out first decode phase.
Equally, after first macro block is executed second decode phase, first macro block is carried out the 3rd decode phase, and simultaneously second macro block carried out second decode phase and the 3rd macro block carried out first decode phase.
Equally, after first macro block is executed the 3rd decode phase, first macro block is carried out the 4th decode phase, and simultaneously second macro block carried out the 3rd decode phase, the 3rd macro block carried out second decode phase and the 4th macro block carried out first decode phase.
As seen, carry out four decode phases concurrently by above-mentioned, thereby reduce decode time widely, realize high-definition real-time AVS decoding.
Further, in the present embodiment, the operand of above-mentioned four decode phases is basic identical, and just, the difference of any two operand is less than threshold value in four decode phases.Be divided into four suitable decode phases of operand by decode procedure, make four decode phases can finish simultaneously basically, thereby further shortened decode time macro block.
In embodiment 1 and 2, for the division methods of the decode procedure of macro block, it realizes that substantially thought is that a decode phase is represented a thread, realizes the parallel processing of multithreading.Be example with embodiment 2 below, this realization thought is described further.
At first, for a macro block, when the each several part vld of macro block in first decode phase decoding is finished and obtained respective macroblock information, will start second decode phase.Then, after in second decode phase, finishing inverse quantization and inverse transformation and being ready to prediction data, can activate the processing of the 3rd decode phase predicted portions again.After finishing data reconstruction, the loop filtering in the 4th decode phase will enter decoding process.
Secondly, for macro block formation pending macro block formations such as (macro block will be one by one to be decoded) regarding as, after first decode phase of first macro block is finished, the kernel in this stage of being responsible for will enter the vld decode phase of second macro block at once, and be responsible for the processing that the kernel of first macro block second decode phase carries out inverse quantization and inverse transformation simultaneously and prepares prediction data this moment, realized good parallel mechanism between the two.In like manner, when the 3rd decode phase of first macro block enters processing, first decode phase of second decode phase of second macro block and the 3rd macro block also will enter processing simultaneously.By that analogy, finally will form the four thread parallel mechanism that the different decode phases of four macro blocks are performed simultaneously.
In four thread parallel treatment mechanisms, make four continuous macro blocks be in different decode phases simultaneously, except the communication interface (comprising the memory space that important transmission of separating data code and shared data are opened up) that each stage is set, four threads will be finished the sign of decode operation by being provided as of handshake, avoid the appearance of associated treatment confusion.System's outer data access operation of sheet of will decoding in the sheet of calculation process and bulk is all taken into account, form four suitable substantially threads of decoding operation time, in the parallel processing process, guarantee can not produce delay each other, the execution efficient of each thread of assurance of maximum possible, thus make whole system reach optimum.
In the foregoing description 1 and 2, the decode operation of each in N decode phase can be finished by a kernel of N core processor, and perhaps, the decode operation of each in N decode phase is finished by a processor.In addition, the present invention not only can be applied to the AVS Video Decoder based on the polycaryon processor realization, can also be applied to the AVS Video Decoder of realizing based on multi-stage pipeline ASIC.Go up the checking realization at present, by the test to AVS working group consistency code stream, stable performance at polycaryon processor (as PC and DSP) platform and FPGA.
In the present invention, to the digital video decoding method in AVS video employing the foregoing description 1 and 2, this is a kind of example, digital video decoding method of the present invention can also be applied to the video of other kinds, as long as the decode procedure of this kind video can be divided into a plurality of parts, for example, MPEC-2, H.264 wait.
Fig. 7 is the decoding digital video schematic representation of apparatus according to the embodiment of the invention.As shown in Figure 7, the decoding digital video device comprises: N decoding unit 71, wherein, N is the quantity of the decode phase that is divided into of the macro-block decoding process of video, j decoding unit carried out j decode phase, 1≤j≤N, in the present embodiment, above-mentioned video is the AVS video, promptly, N is the quantity of the decode phase that is divided into of the macro-block decoding process of AVS video, but those skilled in the art will also be appreciated that above-mentioned video and can also comprise the video of other kinds, as long as the decode procedure of this kind video can be divided into a plurality of parts, for example, MPEC-2, H.264 etc.; Control unit 72, be connected to a described N decoding unit, be used for when i decoding unit carried out i decode phase to current macro, controlling i-1 decoding unit and concurrently next macro block being carried out i-1 decode phase, wherein i is a natural number, and 1＜i≤N.
In the present embodiment, N can be 2, and is corresponding, and first decoding unit 71 is carried out first decode phase, and second decoding unit 71 carried out second decode phase.Above-mentioned 2 decoding units 71 can adopt processing method as shown in Figure 4 to carry out two decode phases concurrently, thereby by carrying out two decode phases concurrently, reduce decode time widely, realize high-definition real-time AVS decoding.Further, can make difference between the operand of first decode phase and second decode phase less than threshold value.Like this, be divided into two suitable decode phases of operand, win decode phase and second decode phase can be finished basically simultaneously, thereby further shortened decode time by decode procedure with macro block.
Perhaps, in the present embodiment, N can be 4, accordingly, first decoding unit 71 is carried out first decode phase, and second decoding unit 71 carried out second decode phase, the 3rd decoding unit 71 carried out the 3rd decode phase, and the 4th decoding unit 71 carried out the 4th decode phase.Above-mentioned 4 decoding units 71 can adopt processing method as shown in Figure 6 to carry out four decode phases concurrently, thereby by carrying out four decode phases concurrently, reduce decode time widely, realize high-definition real-time AVS decoding.Further, can make the difference of operand any two in four decode phases less than threshold value.Like this, be divided into four suitable decode phases of operand, make four decode phases can finish simultaneously basically, thereby further shortened decode time by decode procedure with macro block.
In embodiments of the present invention, utilize the parallel processing advantage of polycaryon processor to design the AVS Video Decoder, utilize mutual order, dependence and the implementation complexity of each module in the decoding process, whole decode procedure is divided into a plurality of decode phases, preferably, make the operand of each decode phase suitable substantially.Each nuclear in the polycaryon processor is born the decoding computing in one of them stage, thereby realizes the multi-threaded parallel treatment mechanism of whole AVS decoding.The multi-threaded parallel decoder is made the processing speed that doubly promotes the AVS decoder, is sound assurance for realizing that high-definition real-time AVS decodes.
In the present invention, adopt the decoding digital video device in the foregoing description that the AVS video is decoded, this is a kind of example, decoding digital video device of the present invention can also be applied to the video of other kinds, as long as the decode procedure of this kind video can be divided into a plurality of parts, for example, MPEC-2, H.264 wait.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a digital video decoding method is characterized in that, comprising:
The macro-block decoding process of video is divided into N decode phase, and wherein, N is the natural number greater than 1;
Current macro is carried out the 1st to N decode phase successively, wherein,
When described current macro is carried out i decode phase, concurrently next macro block is carried out i-1 decode phase, i is a natural number, and 1＜i≤N.
2. digital video decoding method according to claim 1 is characterized in that, described N=2, and when described current macro was carried out i decode phase, the process that next macro block is carried out i-1 decode phase comprised concurrently:
After first macro block is executed first decode phase, described first macro block is carried out second decode phase, and simultaneously second macro block carried out described first decode phase.
3. digital video decoding method according to claim 2 is characterized in that, the decode operation of described first decode phase comprises: the obtaining of the obtaining of the basic decoded information of macro block, residual error data, the inverse quantization of macro block and the inverse transformation of macro block; The decode operation of described second decode phase comprises: the reconstruct of the obtaining of the prediction data of macro block, blocks of data and the loop filtering of macro block are handled.
4. digital video decoding method according to claim 1 is characterized in that, described N=4, and when described current macro was carried out i decode phase, the process that next macro block is carried out i-1 decode phase may further comprise the steps concurrently:
After first macro block is executed first decode phase, described first macro block is carried out second decode phase, and simultaneously second macro block carried out described first decode phase;
After described first macro block is executed described second decode phase, described first macro block is carried out the 3rd decode phase, and simultaneously described second macro block carried out described second decode phase and the 3rd macro block carried out described first decode phase;
After described first macro block is executed described the 3rd decode phase, described first macro block is carried out the 4th decode phase, and simultaneously described second macro block carried out described the 3rd decode phase, described the 3rd macro block carried out described second decode phase and the 4th macro block carried out described first decode phase.
5. digital video decoding method according to claim 4 is characterized in that, the decode operation of described first decode phase comprises: the obtaining of the obtaining of the basic decoded information of macro block, residual error data; The decode operation of described second decode phase comprises: the inverse quantization of macro block and the inverse transformation of macro block; The decode operation of described the 3rd decode phase comprises: the reconstruct of the obtaining of the prediction data of macro block, blocks of data; The decode operation of described the 4th decode phase comprises: the loop filtering of macro block is handled.
6. according to each described digital video decoding method in the claim 1 to 5, it is characterized in that the decode operation of each in the described N decode phase is finished by a kernel of processor.
7. according to each described digital video decoding method in the claim 1 to 5, it is characterized in that the decode operation of each in the described N decode phase is finished by a processor.
8. according to each described digital video decoding method in the claim 1 to 5, it is characterized in that the difference of any two operand is less than threshold value in the described N decode phase.
9. a decoding digital video device is characterized in that, comprising:
N decoding unit, wherein, N is the quantity of the decode phase that is divided into of the macro-block decoding process of video, j decoding unit carried out j decode phase, 1≤j≤N;
Control unit, be connected to a described N decoding unit, be used for when i decoding unit carried out i decode phase to current macro, controlling i-1 decoding unit and concurrently next macro block being carried out i-1 decode phase, wherein i is a natural number, and 1＜i≤N.
10. decoding digital video device according to claim 9 is characterized in that, a described N decoding unit is integrated in the N core processor, and wherein, a kernel in the described N core processor is corresponding to a decoding unit; Perhaps
In the described N decoding unit each is integrated in the processor.
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| CN106658012A (en) * | 2017-01-06 | 2017-05-10 | 华南理工大学 | Parallel pipeline task division method for VP9 decoder |
| CN112839232A (en) * | 2019-11-22 | 2021-05-25 | 合肥杰发科技有限公司 | Data stream start code searching method and device and computer storage medium |
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| US20040008779A1 (en) * | 2002-06-18 | 2004-01-15 | Lai King Chung | Techniques for video encoding and decoding |
| CN1874512A (en) * | 2006-06-29 | 2006-12-06 | 上海交通大学 | High performance pipeline system in use for AVS video decoder |
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| US20040008779A1 (en) * | 2002-06-18 | 2004-01-15 | Lai King Chung | Techniques for video encoding and decoding |
| CN1874512A (en) * | 2006-06-29 | 2006-12-06 | 上海交通大学 | High performance pipeline system in use for AVS video decoder |
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| CN106658012A (en) * | 2017-01-06 | 2017-05-10 | 华南理工大学 | Parallel pipeline task division method for VP9 decoder |
| CN112839232A (en) * | 2019-11-22 | 2021-05-25 | 合肥杰发科技有限公司 | Data stream start code searching method and device and computer storage medium |
| CN112839232B (en) * | 2019-11-22 | 2023-01-17 | 合肥杰发科技有限公司 | Data stream start code searching method and device and computer storage medium |
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