CN1866479A - Power junction field effect transistor structure and making method thereof - Google Patents
Power junction field effect transistor structure and making method thereof Download PDFInfo
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- CN1866479A CN1866479A CN 200510072894 CN200510072894A CN1866479A CN 1866479 A CN1866479 A CN 1866479A CN 200510072894 CN200510072894 CN 200510072894 CN 200510072894 A CN200510072894 A CN 200510072894A CN 1866479 A CN1866479 A CN 1866479A
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Abstract
The invention discloses a power junction field effect transistor structure and making method, which comprises the following steps: (a) providing substrate with epitaxial layer; (b) forming oxide layer on the epitaxial layer; (c) proceeding the first photoetching to form grid bus and protective ring hole; (d) injecting the first doping material to form grid bus cavity area and protective ring area; (e) proceeding the second photoetching to form double-grid hole; (f) injecting the second doping material to form at least one double-grid and grid bus on the epitaxial layer; (g) forming dielectric layer on the oxide layer; (h) proceeding the third photoetching to form source electrode hole; (i) injecting the third doping material to form source electrode layer on the double-grid; (j) proceeding the fourth photoetching to form grid bus metal hole; (k) depositing metal layer to proceed the fifth photoetching to form grid bus metal layer and source electrode metal layer in connection with grid bus and source electrode layer.
Description
Technical field
The present invention relates to a kind of power field effect transistor structure and manufacture method thereof, refer to a kind of power junction field effect transistor structure and manufacture method thereof especially.
Background technology
In recent years, field-effect transistor (Field Effect Transistor, FET) device, mos field effect transistor (metal oxide semiconductor field effect transistor for example, MOSFET) or junction field effect transistor (Junction Field Effect Transistor, JFET) etc., on its operating characteristics and manufacturing process, all obtained very good progress.Electric field changed near field-effect transistor mainly caused carrier channels (channel) by control signal (voltage of grid), and channel characteristic is changed, and caused electric current (between source electrode and the drain electrode) to change.So field-effect transistor can be as voltage-controlled variable resistor or Voltage-controlled Current Source (VCCS) etc.
Wherein junction field effect transistor (JFET) operation principle mainly utilize grid and source electrode between drain electrode the width of depletion region between PN junction be the function of reverse bias, to change channel width by changing width of depletion region.Mos field effect transistor (MOSFET) then utilizes the semiconductor that is biased in mos field effect transistor (MOSFET) of grid and oxide layer to attract to conduct electricity charge carrier at the interface and forms raceway groove, and grid bias changes then that channel carrier changes.
Because the structure of mos field effect transistor (MOSFET) is particularly suitable for reducedization, and power demand is also little, therefore on same chip, makes up to ten million transistor switches and become feasible.Yet junction field effect transistor (JFET) is owing to structural difference, so slightly different with the occasion of mos field effect transistor (MOSFET) use.Junction field effect transistor (JFET) is many as analog switch and signal amplifiers, particularly low noise amplifier, but seldom be used in logical operation and power amplifier in the digital circuit.
In view of known junction field effect transistor (JFET) device, be subject to structure influence and cause it can't carry out Power Processing to use.Therefore, how to carry out device architecture and manufacture process change and adjustment, with improve known technology shortcoming and restriction, make its current vertical circulation, by the below drain electrode upward source electrode flow, and its magnitude of current also can by grid and source electrode pressure reduction do modulation, make this junction field effect transistor (JFET) device also can do a Power Processing application invention as mos field effect transistor (MOSFET).
Summary of the invention
Main purpose of the present invention is for providing a kind of junction field effect transistor (JFET) structure and method for making thereof.By modulation as mos field effect transistor (MOSFET) manufacture process, produce a junction field effect transistor (JFET) structure, make drain electrode upward the source electrode perpendicular flow of its electric current by the below, and its magnitude of current more can be done modulation by the pressure reduction of grid and source electrode, and then make this junction field effect transistor (JFET) device can handle big electric current and high voltage, carry out a Power Processing and use.
For reaching above-mentioned purpose, of the present invention one preferable enforcement sample attitude is for providing a kind of method of making junction field effect transistor structure, and its step comprises: substrate (a) is provided, has epitaxial loayer on it; (b) form oxide layer in the surface of this epitaxial loayer; (c) carry out photoetching first time etch process, partially-etched this oxide layer is to form grid bus opening and guard ring opening; (d) by this grid bus opening and this guard ring opening, inject first alloy, form grid bus well region and guard ring district to divide in this epitaxial loayer; (e) carry out photoetching second time etch process, partially-etched this oxide layer is to form the bigrid opening; (f) by this grid bus opening and this bigrid opening, inject second alloy, on this epitaxial loayer, to form a pair of grid and grid bus at least; (g) form dielectric substance layer on this oxide layer; (h) carry out photoetching etch process for the third time, partially-etched this dielectric substance layer and this oxide layer are to form the source layer opening; (i) by this source layer opening, inject the 3rd alloy, on this bigrid, to form source layer; (j) carry out the photoetching etch process the 4th time, partially-etched this dielectric substance layer and this oxide layer are to form grid bus metal knot opening; And (k) depositing metal layers, and carrying out the photoetching etch process the 5th time, partially-etched this metal level to form grid bus metal level and source metal, connects this grid bus and this source layer respectively.
According to conception of the present invention, wherein this substrate can be N+ type silicon substrate, and this epitaxial loayer can be N-type epitaxial loayer.
According to conception of the present invention, wherein this oxide layer can be field oxide.
According to conception of the present invention, wherein this first alloy can be P+ type alloy.
According to conception of the present invention, wherein this step (d) also comprises an annealing heat treatment process.
According to conception of the present invention, wherein this second alloy is a P+ type alloy.
According to conception of the present invention, wherein this step (f) also comprises an annealing heat treatment process.
According to conception of the present invention, wherein the 3rd alloy is a N+ type source dopant.
According to conception of the present invention, wherein this dielectric substance layer is a deposited oxide layer.
According to conception of the present invention, wherein this substrate and this epitaxial loayer of this bigrid below constitute a drain region.
According to conception of the present invention, wherein this method also comprises step: 1) deposit protective layer comprehensively; And m) carry out the photoetching etch process the 6th time, partially-etched this protective layer is to define the contact mat district of this grid bus metal level and this source metal.
According to conception of the present invention, wherein this protective layer is deposited oxide layer or deposited silicon nitride layer.
For reaching above-mentioned purpose, another preferable enforcement sample attitude of the present invention is for providing a kind of junction field effect transistor structure, and it comprises: substrate; Epitaxial loayer is formed on this substrate; Bigrid has two grid units that equate and be parallel to each other, and is formed in this epitaxial loayer of part; Grid bus is formed on this epitaxial loayer of part, and is connected to this bigrid; Source layer is formed at this epi-layer surface, and is covered on this bigrid; Oxide layer is formed on this epitaxial loayer, and has grid bus opening and source portion opening; With with grid bus metal level and source metal, be formed on this oxide layer, and by this grid bus opening and this source portion opening, be connected with this grid bus and this source layer respectively.
According to conception of the present invention, wherein this substrate is a N+ type silicon substrate, and this epitaxial loayer is a N-type epitaxial loayer.
According to conception of the present invention, wherein this oxide layer is constituted by field oxide and deposited oxide layer.
According to conception of the present invention, wherein this bigrid is made of P+ type grid implanted layer.
According to conception of the present invention, this structure also comprises P+ type grid bus well region, is formed on this grid bus.
According to conception of the present invention, wherein this source layer is constituted by N+ type source electrode implanted layer.
According to conception of the present invention, wherein this substrate of this bigrid below and this epitaxial loayer constitute the drain region.
According to conception of the present invention, this structure also comprises guard ring, is formed on this epitaxial loayer, and wherein this guard ring injects implanted layer for the P+ type.
According to conception of the present invention, this structure also comprises protective layer, be formed on this grid bus metal level and this source metal, and definition has contact mat district (pad areas) opening of this grid bus metal level and this source metal.
Power junction field effect transistor provided by the invention (JFET) device architecture and method for making, junction field effect transistor (JFET) structure by parallel grids such as tool biconjugates, make its electric current at parallel gate interpolars such as this biconjugates, drain region source electrode perpendicular flow upward by the below, its magnitude of current then can be done modulation by the pressure reduction of grid and source electrode, make this junction field effect transistor (JFET) device be handled big electric current and high voltage, carry out a Power Processing and use.
Description of drawings
Fig. 1 (a)-1 (h): it is the power junction field effect transistor structure flow process of a preferred embodiment of the present invention.
Wherein, description of reference numerals is as follows:
11: substrate 12: epitaxial loayer
13: oxide layer 131: the grid bus opening
132: guard ring opening 133: the bigrid opening
14: grid bus well region 15: the guard ring district
16: bigrid 17: grid bus
18: dielectric substance layer 181: the source layer opening
182: grid bus metal knot opening 19: source layer
201: grid bus metal level 202: source metal
21: protective layer 22: the contact mat district
161: grid unit 162: grid unit
Embodiment
Some exemplary embodiments that embody feature of the present invention and advantage will be described in detail in the explanation hereinafter.Be understood that the present invention can have various variations on different aspects, its neither departing from the scope of the present invention, and explanation wherein and the icon usefulness that ought explain in itself, but not in order to restriction the present invention.
See also Fig. 1 (a) to Fig. 1 (h), it shows the power junction field effect transistor structure flow chart of a preferred embodiment of the present invention.As shown in the figure, the method for making of junction field effect transistor of the present invention comprises the following step: at first, a substrate 11 is provided, and also has an epitaxial loayer 12 on this substrate 11.In the present embodiment, this substrate 11 can be N+ type silicon substrate, and this epitaxial loayer 12 then can be N-type epitaxial loayer.Then, utilize a thermal oxidation manufacture process, form an oxide layer 13 in the surface of this epitaxial loayer 12 comprehensively, wherein this oxide layer 13 is field oxide (Field Oxide), and the structure of gained is shown in Fig. 1 (a).Then; carry out an etch process of photoetching for the first time; partially-etched this oxide layer 13; to form a grid bus (gate runner) opening 131 and a guard ring (guard ring) opening 132; form grid bus and guard ring for subsequent manufacturing processes, and the structure of gained is shown in Fig. 1 (b).Afterwards,, carry out first cloth and plant manufacture process, inject first alloy, to form grid bus well region 14 and guard ring district 15 in this epitaxial loayer 12 by aforesaid grid bus opening 131 and guard ring opening 132.In certain embodiments, this first alloy can be P+ type alloy, so formed P+ type grid bus well region 14 and P+ type guard ring district 15 are shown in Fig. 1 (c).Certainly, after aforesaid injection technology, also can comprise an annealing heat treatment process (annealing), insert (drive-in) technology so that this P+ type grid bus well region 14 and P+ type guard ring district 15 finish.
After aforesaid step, carry out photoetching second time etch process, partially-etched this oxide layer 13 is to form another bigrid opening 133.Afterwards,, carry out second cloth and plant manufacture process, injecting second alloy, and on this epitaxial loayer 12, form bigrid 16 and grid bus 17 by this grid bus opening 131 and this bigrid opening 133.Wherein, this second alloy is a P+ type alloy, so P+ type bigrid 16 that forms and P+ type grid bus 17 are shown in Fig. 1 (d).Similarly, after aforesaid second cloth is planted manufacture process, also can comprise annealing heat treatment process (annealing), insert (drive-in) technology so that P+ type bigrid 16 and P+ type grid bus 17 are finished.Then, deposition forms a dielectric substance layer 18 comprehensively, and shown in Fig. 1 (e), wherein this dielectric substance layer 18 is a deposited oxide layer.Subsequently, carry out photoetching etch process for the third time, partially-etched this dielectric substance layer 18 and this oxide layer 13 and form one source pole layer opening 181.Then,, carry out the 3rd cloth again and plant manufacture process, inject the 3rd alloy, on this bigrid 16, to form one source pole layer 19 by this source layer opening 181.Wherein, the 3rd alloy can be N+ type alloy, so this source layer 19 is a N+ type source layer.And after aforesaid the 3rd cloth is planted manufacture process, also can comprise annealing heat treatment process (annealing), so that N+ type source layer 19 finishes and insert (drive-in) technology, and the structure of gained is shown in Fig. 1 (f).
Subsequently, carry out the photoetching etch process the 4th time, partially-etched this dielectric substance layer 18 and this oxide layer 13 and form grid bus metal knot opening 182 and one source pole layer opening 181.Then, deposit a metal level and carry out the photoetching etch process the 5th time, partially-etched this metal level, and form a grid bus metal level 201 and one source pole metal level 202, connect this grid bus 17 and this source layer 19 respectively, resulting structures is shown in Fig. 1 (g).Afterwards, deposit a protective layer 21 comprehensively and carry out the photoetching etch process the 6th time, partially-etched this protective layer 21 is so as to defining a contact mat district (pad areas) 22 of this grid bus metal level 201 and this source metal 202.Can obtain this power junction field effect transistor device architecture at last, shown in Fig. 1 (h).
Conception of the present invention can be applied to a power junction field effect transistor, and (Junction Field EffectTransistor is in structure JFET).According to preceding method, the present invention discloses a power junction field effect transistor structure simultaneously, sees also Fig. 1 (h), and its structure comprises: a substrate 11; One epitaxial loayer 12 is formed on this substrate 11; Bigrid 16 has two grid units 161 and 162 that equate and be parallel to each other, and is formed in this epitaxial loayer 12 of part; One grid bus (gate runner) 17 is formed on this epitaxial loayer 12 of part, and is electrically connected to this bigrid 16; One source pole layer 19 is formed at this epitaxial loayer 12 surfaces, and is covered in simultaneously on this bigrid 16; One oxide layer (in response to aforementioned manufacturing process, this oxide layer is constituted by a field oxide 13 (Field Oxide) and a deposited oxide layer 18) is arranged on this epitaxial loayer 12, and has a grid bus opening and one source pole portion opening; And a grid bus metal level 201 and an one source pole metal level 202, be formed on this oxide layer, and, be connected with this grid bus 17 and this source layer 19 respectively by this grid bus opening and this source portion opening.
When practical application, this substrate 11 can be N+ type silicon substrate, and this epitaxial loayer 12 can be N-type epitaxial loayer.Again, this bigrid 16 is made of P+ type grid implanted layer, and this grid bus 17 is made of P+ type grid implanted layer, and its periphery also comprises a P+ type grid bus well region 14.Constituted by N+ type source electrode implanted layer as for 19 of this source layers.
In the present embodiment structure, this substrate 11 of these bigrid 16 belows constitutes a drain region with this epitaxial loayer 12.In the pressure reduction that uses 19 of this bigrid 16 of time modulation and source layers, then just there is electric current to pass from the drain region of below (this substrate 11 of these bigrid 16 belows constitutes with this epitaxial loayer 12) that two of this bigrid 16 equates and the grid unit 161 that is parallel to each other and 162 and upward source layer 19 flows, and the magnitude of current is wherein just done modulation by this bigrid 16 and the pressure reduction of this source layer 19, makes this junction field effect transistor (JFET) device also can do a Power Processing as mos field effect transistor (MOSFET) and uses.
On the other hand, when practical application, this junction field effect transistor structure device also can comprise a guard ring district (guard ring) 15 certainly, is formed on this epitaxial loayer 12, and wherein this guard ring district 15 is a P+ type implanted layer in the present embodiment.In addition; this junction field effect transistor structure device the top also comprises a protective layer 21; form on this grid bus metal level 201 and this source metal 202; and definition has a contact mat district (pad areas) opening 22 of this grid bus metal level and this source metal; for follow-up usefulness of carrying out the metal wire binding, wherein this protective layer 21 can be made of a deposited oxide layer or a deposited silicon nitride layer.
Certainly, for those of ordinary skill in the art, can obviously understand, can have a plurality of power junction field effect transistor structures shown in above-mentioned embodiment,, be beneficial to the processing of big electric current each other to be connected in parallel at the semiconductor chip.
In sum, the invention provides a kind of power junction field effect transistor (JFET) device architecture and method for making, junction field effect transistor (JFET) structure by parallel grids such as tool biconjugates, make its electric current at parallel gate interpolars such as this biconjugates, drain region source electrode perpendicular flow upward by the below, its magnitude of current then can be done modulation by the pressure reduction of grid and source electrode, makes this junction field effect transistor (JFET) device be handled big electric current and high voltage, carries out a Power Processing and uses.
The present invention has been described in detail by the foregoing description and can have been undertaken modifying as all by those of ordinary skill in the art, but the scope of neither disengaging claims institute desire protection.
Claims (13)
1. method of making junction field effect transistor structure, its step comprises:
(a) provide a substrate, have an epitaxial loayer on it;
(b) form an oxide layer in the surface of this epitaxial loayer;
(c) carry out an etch process of photoetching for the first time, partially-etched this oxide layer is to form a grid bus opening and a guard ring opening;
(d) by this grid bus opening and this guard ring opening, inject one first alloy, to form a grid bus well region and a guard ring district respectively in this epitaxial loayer;
(e) carry out an etch process of photoetching for the second time, partially-etched this oxide layer is to form a pair of gate openings;
(f) by this grid bus opening and this bigrid opening, inject one second alloy, on this epitaxial loayer, to form an a pair of grid and a grid bus at least;
(g) form a dielectric substance layer on this oxide layer;
(h) carry out a photoetching etch process for the third time, partially-etched this dielectric substance layer and this oxide layer are to form one source pole layer opening;
(i) by this source layer opening, inject one the 3rd alloy, on this bigrid, to form the one source pole layer;
(j) carry out the photoetching etch process one the 4th time, partially-etched this dielectric substance layer and this oxide layer are to form grid bus metal knot opening; And
(k) deposition one metal level, and carry out the photoetching etch process one the 5th time, partially-etched this metal level to form a grid bus metal level and one source pole metal level, connects this grid bus and this source layer respectively.
2. the method for manufacturing junction field effect transistor structure as claimed in claim 1 it is characterized in that this substrate is a N+ type silicon substrate, and this epitaxial loayer is a N-type epitaxial loayer, and wherein this oxide layer is a field oxide, and this dielectric substance layer is a deposited oxide layer.
3. the method for manufacturing junction field effect transistor structure as claimed in claim 1 is characterized in that this first alloy is a P+ type alloy, and this second alloy is a P+ type alloy, and the 3rd alloy is a N+ type source dopant.
4. the method for manufacturing junction field effect transistor structure as claimed in claim 1, it is characterized in that this step (d) with and/or this step (f) also comprise an annealing heat treatment process.
5. the method for manufacturing junction field effect transistor structure as claimed in claim 1 is characterized in that this substrate and this epitaxial loayer of this bigrid below constitutes a drain region.
6. the method for manufacturing junction field effect transistor structure as claimed in claim 1 is characterized in that also comprising step:
L) deposit a protective layer comprehensively; And
M) carry out the photoetching etch process one the 6th time, partially-etched this protective layer is to define a contact mat district of this grid bus metal level and this source metal.
7. the method for manufacturing junction field effect transistor structure as claimed in claim 6 is characterized in that this protective layer is a deposited oxide layer or a deposited silicon nitride layer.
8. junction field effect transistor structure, it comprises:
One substrate;
One epitaxial loayer is formed on this substrate;
Bigrid has two grid units that equate and be parallel to each other, and is formed in this epitaxial loayer of part;
One grid bus is formed on this epitaxial loayer of part, and is connected to this bigrid;
The one source pole layer is formed at this epi-layer surface, and is covered on this bigrid;
One oxide layer is formed on this epitaxial loayer, and has a grid bus opening and one source pole portion opening; And
One grid bus metal level and one source pole metal level are formed on this oxide layer, and by this grid bus opening and this source portion opening, are connected with this grid bus and this source layer respectively.
9. junction field effect transistor structure as claimed in claim 8 is characterized in that this substrate is a N+ type silicon substrate, and this epitaxial loayer is a N-type epitaxial loayer, and wherein this oxide layer is constituted by a field oxide and a deposited oxide layer.
10. junction field effect transistor structure as claimed in claim 8, it is characterized in that this bigrid is made of P+ type grid implanted layer, and this substrate and this epitaxial loayer of this bigrid below constitute a drain region, and this source layer is then constituted by N+ type source electrode implanted layer.
11. junction field effect transistor structure as claimed in claim 8; it is characterized in that also comprising a P+ type grid bus well region, be formed on this grid bus, with and/or also comprise a guard ring; be formed on this epitaxial loayer, wherein this guard ring is a P+ type implanted layer.
12. junction field effect transistor structure as claimed in claim 8; it is characterized in that also comprising a protective layer; be formed on this grid bus metal level and this source metal, and definition has a contact mat district opening of this grid bus metal level and this source metal.
13. junction field effect transistor structure as claimed in claim 12 is characterized in that this protective layer is a deposited oxide layer or a deposited silicon nitride layer.
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| CN 200510072894 CN1866479A (en) | 2005-05-17 | 2005-05-17 | Power junction field effect transistor structure and making method thereof |
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| CN 200510072894 CN1866479A (en) | 2005-05-17 | 2005-05-17 | Power junction field effect transistor structure and making method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101320753B (en) * | 2007-05-29 | 2010-12-15 | 万国半导体股份有限公司 | Double gate manufactured with locos techniques |
| CN102881593A (en) * | 2011-03-25 | 2013-01-16 | 成都芯源系统有限公司 | Method for manufacturing junction field effect transistor |
-
2005
- 2005-05-17 CN CN 200510072894 patent/CN1866479A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101320753B (en) * | 2007-05-29 | 2010-12-15 | 万国半导体股份有限公司 | Double gate manufactured with locos techniques |
| CN102881593A (en) * | 2011-03-25 | 2013-01-16 | 成都芯源系统有限公司 | Method for manufacturing junction field effect transistor |
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