CN1862971A - High-speed coding method of low density check code - Google Patents
High-speed coding method of low density check code Download PDFInfo
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Abstract
The invention discloses the low dense checkout code high speed coding method, by the partition of the date source matrix and the building matrix, the multiplication operation between the date source matrix A and the building matrix B can be transformed into the multiplication operation between the n son matrix with the (m*a) dimensions of the matrix A and the nxc son matrix with the (axb) dimensions of the matrix B. The invention relates to the LDPC coding method, the LDPC coding setting can be realized cooperated with the FPGA by using the memorizer saving data source matrix and the building matrix such as the SDRAM. The realized LDPC coding setting has many merits such as the high operating speed, the low spending of the system and the good ability. Compared with the conventional LDPC coding method, the invention has the better project realizing ability and the quicker coding speed. The invention can avoids the speed bottleneck problem of the storage to improve the realizing ability of the LDPC coding setting when the large matrix multiplying.
Description
Technical field:
The invention belongs to the communications field, it is particularly related to channel LDPC encoder design and Project Realization technology in the communication.
Background technology:
Loe-density parity-check code (is called for short: LDPC) be a kind of error correction coding mode that is subjected to extensive concern in the communication.1962, Gallager proposed the linear code based on sparse check matrix, and promptly (Low-Density Parity-CheckCode LDPC), has proved that LDPC is a kind of good sign indicating number to loe-density parity-check code.Although but it has good performance, before Turbo code occurred, the LDPC sign indicating number did not cause enough attention.Up to date, owing to the performance that has near shannon limit, the LDPC sign indicating number just is applied in AWGN and the rayleigh fading channel.Verified, when the code length of LDPC sign indicating number was very big, the LDPC sign indicating number was well beyond the performance of convolutional encoding.But along with the increase of code length, the complexity of LDPC encoder also can significantly improve, and expense significantly increases, and is difficult to Project Realization, has greatly limited the application of LDPC sign indicating number.
Summary of the invention:
The implementation method that the purpose of this invention is to provide a kind of high-speed LDPC coding, the LDPC encoder that can realize adopting coding method that data source matrix and generator matrix multiply each other to encode according to the inventive method, make it have fast operation, overhead is low, characteristics such as function admirable.
The method that the coding method that adapts to any LDPC sign indicating number can adopt data source matrix and generator matrix to multiply each other realizes.
With matrix A representative data source matrix, B represents generator matrix.Deposit data to be encoded in the matrix A, deposit generator matrix in the matrix B.The coding method that then adapts to any LDPC sign indicating number can be expressed as matrix of consequence C=A * B.
Be without loss of generality, implementation method with matrix multiplication among Matrix C=A * B explanation the present invention, wherein the dimension of matrix A is m * (n * a) (wherein, m is the line number of matrix A, (n * a) is the columns of matrix A, if the columns of matrix A is not the product of n and a, can be 0 row polishing so with element entirely, make that the columns of matrix A is the product of n and a); The dimension of matrix B is that (n * a) * ((wherein, (n * a) is the line number of matrix B, and (c * b) is the columns of matrix B for c * b).If the line number of matrix B is not the product of n and a, can be 0 capable polishing so with element entirely, make that the line number of matrix B is the product of n and a; If the columns of matrix B is not the product of c and b, be 0 row polishing equally entirely with element, make that the columns of matrix B is the product of c and b).(annotate: m, n, a, b, c are the positive integer greater than zero)
Fig. 1 and Fig. 2 have described the dimension of matrix A and matrix B respectively.Along with the increase of matrix dimension, the increase that the data operation quantity of matrix multiplication also can be at double.
The invention provides a kind of implementation method of high-speed LDPC coding, it is characterized in that adopting following step that data source matrix and generator matrix are divided.
Below in conjunction with the concrete partiting step of setting forth of accompanying drawing to data source matrix and generator matrix:
Step 1: to the division of data source matrix A:
Fig. 3 is described the division methods of data source matrix A.Concrete steps are: matrix A is divided into n submatrix (if the columns of matrix A is not the integral multiple of n by row, can be 0 row polishing with element entirely, make that the columns of matrix A is the integral multiple of n, the matrix A that to mend then after 0 is divided into n submatrix by row), the columns of each submatrix is a, line number still is m, like this matrix A submatrix that just to be divided into n dimension be m * a.
Step 2: divide the first time to generator matrix B:
Fig. 4 is described the division methods first time of generator matrix B.Concrete steps are: matrix B is divided into c submatrix (if the columns of matrix B is not the integral multiple of c by row, can be 0 row polishing with element entirely, make that the columns of matrix B is the integral multiple of c, the matrix B that to mend then after 0 is divided into c submatrix by row), each submatrix columns is b, line number still is that (n * a), matrix B just is divided into c dimension and is (the submatrix of n * a) * b like this.
After the division of finishing the matrix B first time, continue each submatrix B1 to matrix B, B2......Br ... Bc further divides.
Step 3: divide the second time to any one submatrix Br of generator matrix B:
Fig. 5 is described the further division of some submatrix Br of matrix B.Concrete steps are: keep the row of matrix B r constant, matrix B r is divided into n submatrix (if the line number of matrix B r is not the integral multiple of n by row, can be 0 capable polishing with element entirely, make that the line number of matrix B r is the integral multiple of n, the matrix B r that will mend then after 0 is divided into n submatrix by row), the line number of each submatrix is a, and columns still is b, and matrix B r just is divided into n dimension and is (the submatrix of a * b) like this.In like manner, just can finish all submatrix B1 to matrix B, B2......Br ... the division of Bc.Through above-mentioned twice division to matrix B, it is (the submatrix of a * b) that matrix B just is divided into n * c dimension.
Through behind the above-mentioned partiting step to data source matrix A and generator matrix B, the LDPC coding method of adopting data source matrix and generator matrix to multiply each other, promptly the multiplication of data source matrix A and generator matrix B n dimension just being converted to matrix A is for (m * submatrix a) and the n * c of matrix B dimension are the (multiplication of the submatrix of a * b).
Like this, based on above-mentioned partiting step to data source matrix A and generator matrix B, the multiplying of data source matrix A and generator matrix B can be adopted following step:
Step 4: based on dividing the result first time of step 2 couple generator matrix B, the computing of A * B is decomposed into each submatrix B1, B2 of A and B, the multiplying that B3...Br...Bc multiplies each other respectively.
A * B=[A * B1, A * B2, A * B3, ..., A * Br ..., A * Bc] ... 1. step 5: based on dividing the result second time of the division result of step 1 pair data source matrix A and step 3 couple generator matrix B, with each submatrix B1, B2 of A and B, the multiplying of B3...Br...Bc, promptly (1≤r≤computing c) is decomposed into each submatrix Br of each submatrix A1, A2, A3...An and the Br of A to A * Br
1, Br
2, Br
3... Br
nThe computing that correspondence multiplies each other and adds up.
Fig. 6 is described the calculation procedure of A * Br.Concrete steps are:
First submatrix A with generator matrix A
1With first submatrix Br among the matrix B r
1Correspondence multiplies each other, and keeps the result after calculating is finished; Continue second sub-matrix A with matrix A
2With second sub-matrix B r in the Br matrix
2Correspondence multiplies each other, and keeps the result after calculating is finished; Then according to preceding method, with the 3rd, the 4th of matrix A ... i ... n submatrix respectively with the 3rd, the 4th of Br matrix ... i is individual ... n submatrix correspondence multiplies each other, and keep the result respectively, each time results added is promptly obtained the multiplied result of matrix A * Br.
Said process, as follows:
Step 6: according to the computational methods of step 5, (substitution as a result of 1≤r≤c) is the formula right-hand member 1., can obtain matrix A * B result, just the code word of LDPC with A * Br of obtaining.
Through above step, just can realize the LDPC coding.
Essence of the present invention is: for the LDPC coding method of adopting data source matrix and generator matrix to multiply each other, through behind the partiting step to data source matrix A and generator matrix B, promptly the multiplication of data source matrix A and generator matrix B n dimension just being converted to matrix A is for (m * submatrix a) and the n * c of matrix B dimension are the (multiplication of the submatrix of a * b).
Innovation part of the present invention is:
The present invention is by the division to data source matrix and generator matrix, and n the dimension that the multiplying of data source matrix A and generator matrix B is converted to matrix A is for (m * submatrix a) is (multiplying of the submatrix of a * b) with the n * c of matrix B dimension.By this scheme big data quantity is assigned in each submatrix, the LDPC encoder of Shi Xianing has fast operation thus, and overhead is low, characteristics such as function admirable.It has better engineering realizability than traditional LDPC coding method, and coding rate is faster.
Advantage of the present invention:
The present invention proposes a kind of coding method that adapts to any LDPC sign indicating number, the coding method that it is compared to previously presented LDPC sign indicating number has following advantage:
1). this scheme has solved the difficult problem of storage and data throughout effectively, makes that the LDPC encoder is easy to realize on engineering, has improved the LDPC sign indicating number in actual application in engineering;
2). the division owing to crossing to data source matrix and generator matrix, reasonably big data quantity is assigned in each submatrix, calculate when having avoided big data quantity, reduced overhead effectively, improve the realizability of LDPC sign indicating number coding;
3). owing to adopt parallel coded system, the present invention has effectively promoted the LDPC speed of coding.
The present invention calculates when having avoided big data quantity by two matrixes are divided, reasonably big data quantity is assigned in each submatrix, has improved LDPC and has been coded in the realizability of engineering in using.
Description of drawings:
Fig. 1: the structural representation of matrix A
The line number of m representing matrix A wherein, (columns of representing matrix A of n * a) is not (if the columns of matrix A is the integral multiple of a, can be 0 row polishing so with element entirely, make that the columns of matrix A is the integral multiple of a), the m * (dimension of expression data source matrix A of n * a).
Fig. 2: the structural representation of matrix B
Wherein (line number of representing matrix B of n * a), (c * b) columns of representing matrix B (if the line number of matrix B is not the integral multiple of a, can be 0 capable polishing so with element entirely, make that the line number of matrix B is the integral multiple of a; If the columns of matrix B is not the integral multiple of b, be 0 row polishing equally entirely with element, make that the columns of matrix B is the integral multiple of b), (n * a) * (dimension of expression generator matrix B of c * b).
Fig. 3: the division result schematic diagram of matrix A
Wherein A1, A2......A (n-1), An distinguish n the submatrix of representing matrix A, the line number of m representing matrix A and its n submatrix, the n of a representing matrix A sub-matrix column number, (the columns of representing matrix A of n * a), (n sub-matrix A 1 of the expression of m * a) data source matrix A, the dimension of A2......A (n-1), An, the m * (dimension of expression data source matrix A of n * a).
Fig. 4: the primary division result schematic diagram of matrix B
Wherein, c submatrix after B1, B2, B3...Br...Bc representing matrix B divide for the first time; (the line number of representing matrix B of n * a) and c submatrix thereof, the columns of each submatrix of b representing matrix B, (columns of representing matrix B of c * b), (n * a) * b represents c the sub-matrix B 1 of generator matrix B, the dimension of B2, B3...Bc, the (n * a) * (dimension of expression generator matrix B of c * b).
Fig. 5: divide result schematic diagram the second time of the submatrix Br of matrix B
Wherein, Br
1, Br
2... Br
nN the sub-matrix B r of Br represented in n the submatrix of difference representing matrix Br, a
1, Br
2... Br
nLine number, b represents n the sub-matrix B r of Br
1, Br
2... Br
nColumns, (line number of representing matrix Br of n * a), (dimension of n * a) * b representing matrix Br, (n the sub-matrix B r of representing matrix Br of a * b)
1, Br
2... Br
nDimension.
The computational methods schematic diagram of Fig. 6: A * Br
Fig. 7: FB(flow block) of the present invention
Embodiment:
Digital baseband in the design of B3G TDD mode down link sends the coding method that the LDPC encoder that partly uses can adopt LDPC among the present invention.In the design, adopt SDRAM storage data source matrix A (dimension is 64 * (32 * 76)) and generator matrix B (dimension is (32 * 76) * (8 * 483)), the Vertex II Pro chip Xc2vp70 of cooperation Xilinx company realizes the LDPC encoder among the present invention.Through checking, when system clock was operated in 80MHZ, this LDPC encoder can be finished the coding (length of each code block is 2404) to 1664 code blocks in the time of a TTI=40ms, and system data throughput has reached 100Mbps.
Therefore, the coding method of LDPC of the present invention can cooperate FPGA to realize the LDPC encoder by memory stores data source matrix and generator matrixes such as use SDRAM.This LDPC encoder has fast operation, and overhead is low, characteristics such as function admirable.When the present invention avoids large matrix to multiply each other, the speed bottle-neck problem of memory, thereby the realizability of raising LDPC encoder.
Claims (1)
1, a kind of implementation method of high-speed LDPC coding is characterized in that adopting following step:
Step 1: to the division of data source matrix A
Matrix A is divided into n submatrix by row:
If the columns of matrix A is the integral multiple of n, then the columns of each submatrix is a, and line number still is m, like this matrix A submatrix that just to be divided into n dimension be m * a;
If the columns of matrix A is not the integral multiple of n, can be 0 row polishing with element entirely, make that the columns of matrix A is the integral multiple of n, the matrix A that to mend then after 0 is divided into n submatrix by row, then the columns of each submatrix is a, line number still is m, like this matrix A submatrix that just to be divided into n dimension be m * a;
Step 2: divide the first time to generator matrix B:
Matrix B is divided into c submatrix by row:
If the columns of matrix B is the integral multiple of c, then each submatrix columns is b, line number still be (n * a), just to be divided into c dimension be the (submatrix of n * a) * b to matrix B like this;
If the columns of matrix B is not the integral multiple of c, can be 0 row polishing with element entirely, make that the columns of matrix B is the integral multiple of c, the matrix B that to mend then after 0 is divided into c submatrix by row, then each submatrix columns is b, line number still be (n * a), matrix B just is divided into c dimension and is (the submatrix of n * a) * b like this;
After the division of finishing the matrix B first time, continue each submatrix B1, B2 to matrix B ... Br ... Bc further divides;
Step 3: divide the second time to any one submatrix Br of generator matrix B:
Keep the row of matrix B r constant, matrix B r is divided into n submatrix by row
If the line number of matrix B r is the integral multiple of n, then the line number of each submatrix is a, and columns still be b, and just to be divided into n dimension be the (submatrix of a * b) to matrix B r like this;
If the line number of matrix B r is not the integral multiple of n, can be 0 capable polishing with element entirely, make that the line number of matrix B r is the integral multiple of n, the matrix B r that will mend then after 0 is divided into n submatrix by row, then the line number of each submatrix is a, columns still is b, and matrix B r just is divided into n dimension and is (the submatrix of a * b) like this;
M, n, a, b, c are the positive integer greater than zero;
In like manner, just can finish all submatrix B1, B2 to matrix B ... Br ... the division of Bc; Through above-mentioned twice division to matrix B, it is (the submatrix of a * b) that matrix B just is divided into n * c dimension;
Step 4: utilize divide the result first time of step 2 couple generator matrix B, the computing of data source matrix A * generator matrix B is decomposed into each submatrix B1, B2, the B3 of data source matrix A and generator matrix B ... Br ... the multiplying that Bc multiplies each other respectively;
A×B＝[A×B1，A×B2，A×B3，…，A×Br，…，A×Bc] …①
Step 5: based on dividing the result second time of the division result of step 1 pair data source matrix A and step 3 couple generator matrix B, each submatrix B1, B2, B3 with data source matrix A and generator matrix B ... Br ... the multiplying of Bc, promptly (1≤r≤computing c) is decomposed into each submatrix A1, A2, the A3 of A to A * Br ... each submatrix Br of An and Br
1, Br
2, Br
3... Br
nThe computing that correspondence multiplies each other and adds up;
First submatrix A with generator matrix A
1With first submatrix Br among the matrix B r
1Correspondence multiplies each other, and keeps the result after calculating is finished; Continue second sub-matrix A with matrix A
2With second sub-matrix B r in the Br matrix
2Correspondence multiplies each other, and keeps the result after calculating is finished; Then according to preceding method, with the 3rd, the 4th of matrix A ... i ... n submatrix respectively with the 3rd, the 4th of Br matrix ... i ... n submatrix correspondence multiplies each other, and keep the result respectively, each time results added is promptly obtained the multiplied result of matrix A * Br;
Said process, as follows:
Step 6: according to the computational methods of step 5, (substitution as a result of 1≤r≤c) is the formula right-hand member 1., can obtain the result of matrix A * B, i.e. the code word of LDPC with A * Br of obtaining;
Through above step, just can realize the LDPC coding.
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| FR2799592B1 (en) * | 1999-10-12 | 2003-09-26 | Thomson Csf | SIMPLE AND SYSTEMATIC CONSTRUCTION AND CODING METHOD OF LDPC CODES |
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| CN1252935C (en) * | 2002-12-13 | 2006-04-19 | 清华大学 | Information source-channel united coding method based on low-density odd-even check coding |
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