CN101834613A - Encoding method of LDPC (Low Density Parity Check) code and encoder - Google Patents

Abstract

The invention provides an encoding method of an LDPC (Low Density Parity Check) code. The encoding method comprises the following steps of: adjusting elements of a modular matrix Hbm by using an expanding factor zf to generate an adjusted modular matrix Hbmf; expanding by using the modular matrix Hbmf to generate a check matrix H, wherein the expanding mode is as follows: sub-matrixes Pi and j in the check matrix H expand according to the value of the modular matrix Hbmf, and each of the sub-matrixes Pi and j is a full zero matrix, a unit matrix or a unit matrix for left and right cyclic shifting according to a line direction; and encoding input information U by using the check matrix H and outputting encoding information V. The invention also provides an encoder of the LDPC code. According to the technical scheme proposed by the invention, through increasing the quantity of zero elements of the modular matrix Hbm, the processing complexity and the implementation complexity of the encoding and the decoding of the LDPC code can be reduced, and the processing speed of the encoding and the coding can be improved.

Description

Encoding method of LDPC code and encoder

Technical Field

The present invention relates to the field of digital communication, and in particular, to an encoding method and an encoder for an LDPC code.

Background

An LDPC (Low Density Parity Check) code is a block error correction code with a sparse Check matrix proposed by Gallager in 1962. In 1996, Mackay et al re-studied LDPC codes and found that LDPC codes have very good performance: approaching to the Shannon limit, simple coding, simple decoding and parallel computation.

In 2005, the IEEE std802.16e standard provided a structured LDPC code (structured LDPC). The coding structure of the LDPC code is based on a mode matrix H_bmAnd the cyclic shift identity matrix and the all-zero matrix are used as sub-matrixes for expansion, and a check matrix H required by coding is generated. The check matrix structure corresponding to the LDPC code is shown as formula (1-1).

$H=\left[\begin{array}{c}\begin{array}{ccccc}{P}_{\mathrm{1,1}}& P_{\mathrm{1,2}}& ......& P_{1,n_b-1}& P_{1,n_b}\\ P_{\mathrm{2,1}}& P_{\mathrm{2,2}}& ......& P_{2,n_b-1}& P_{2,n_b}\end{array}\\ \begin{array}{cccc}......& ......& ......& ......\end{array}\\ \begin{array}{ccccc}{P}_{m_b-\mathrm{1,1}}& P_{m_b-\mathrm{1,2}}& ......& P_{m_b-1,n_b-1}& P_{m_b-1,n_b}\\ P_{m_b,1}& P_{m_b,2}& ......& P_{m_b-1,n_b-1}& P_{m_b,n_b}\end{array}\end{array}\right]---(1-1)$

In the formula (1-1), the submatrix P in the check matrix H_i，jIs generated by expanding the unit matrix and the all-zero matrix of the cyclic shift as sub-matrixes, the sizes of the corresponding unit matrix and the all-zero matrix, z_fLine, z_fColumn, possibly with spreading factor z_fFlexibly changing the mode matrix H corresponding to the check matrix H_bmIs a natural number or is-1. Wherein, the natural number comprises 0 and positive integer, is cyclic shift value of the unit matrix, and represents the number of the unit matrix circularly shifted to the right according to the column, and the unit matrix circularly shifted to the right according to the column is used as the sub-matrix P in the corresponding check matrix H_i，j. Wherein-1 represents the corresponding check matrixSubmatrix P in H_i，jAnd the matrix is obtained by expanding the all-zero matrix. Mode matrix H_bmThe number of rows and columns is m_bAnd n_bAs shown in the formula (1-2),

$H_{\mathrm{bm}}=\left[\begin{array}{ccc}{h}_{\mathrm{1,1}}& ...& h_{1,n_b}\\ .& & .\\ .& & .\\ .& & .\\ h_{m_b,1}& ...& h_{m_b,n_b}\end{array}\right]---(1-2)$

wherein each element h_i，j(i＝1，…，m_b；j＝1，…，n_b) The value is a natural number or-1. Here, an element taking a positive integer is referred to as a positive integer element, an element taking a 0 is referred to as a zero element, and an element taking a-1 is referred to as an "-1" element.

The formula (1-2) can also be expressed as n_bA number of column vectors, each of which is,

$H_{\mathrm{bm}}=[h_1,...,h_{n_b}],---(1-3)$

wherein each column vector h_i(i＝1，…，n_b) Comprising m_bAnd (4) each element.

$h_i=\left[\begin{array}{c}{h}_{1,i}\\ .\\ .\\ .\\ h_{m_b,i}\end{array}\right]={[h_{1,i},...,h_{m_b,i}]}^T---(1-4)$

Wherein x is^TIndicating that the vector x is transposed.

The above-mentioned mode matrix H_bmIt can also be divided into 2 parts, as shown in FIG. 1, where the mode matrix H_bmExpressed as in equations (1-5):

$H_{\mathrm{bm}}=\left[\begin{array}{cc}{H}_{\mathrm{bm}}^S& H_{\mathrm{bm}}^P\end{array}\right]---(1-5)$

wherein,

a systematic bit portion corresponding to the check matrix H, which includes the matrix H_bmM on the left side of_bLine, k_bElements of the column, corresponding to H_bmLeft side k of_bA column vector h_i(i＝1，…，k_b) As shown in the formulas (1-6),

$H_{\mathrm{bm}}^S=[h_1,...,h_{k_b}]---(1-6)$

wherein,

a check bit portion corresponding to a check matrix H, which includes the matrix H_bmM on the right side of_bLine, m_bElements of the column, corresponding to H_bmRight side m of_bA column vector h_i(i＝k_b+1，…，n_b) As shown in the formulas (1-7),

$H_{\mathrm{bm}}^P=[h_{k_b+1},...,h_{n_b}]---(1-7)$

wherein k is_b+m_b＝n_b。

The matrix mentioned above

Or divided into 2 parts, as shown in equations (1-8),

wherein,

is a mode matrix H_bmKth of (1)_b+1 column vectors.

Including a mode matrix H_bmM on the right side of_bLine, m_b1 column of elements, corresponding to H_bmRight side m of_b1 column vector h_i(i＝k_b+2，…，n_b) As shown in the formulas (1-9),

${\hat{H}}_{\mathrm{bm}}^P=[h_{k_b+2},...,h_{n_b}]---(1-9)$

generally, a matrix

Adopts a double diagonal structure, as shown in formulas (1-10),

wherein, when i is 1, …, m_bAnd i ═ j or i ═ j +1, h_i，jThe value is 0, and the others are-1. As shown in Table 1, a modulus matrix H of LDPC coding is given for the IEEE std802.16e standard_bmWherein k is_b＝12，m_b＝12，n_b＝24。

TABLE 1 Modular matrix for LDPC coding

In order to flexibly support other shorter code lengths, a smaller spreading factor z is required_fMeanwhile, the above-mentioned mode matrix H is required to be adjusted according to the following formula (1-11)_bmGenerating an adjusted mode matrix H by taking the value of the element(s)_bmfIs composed of

Wherein p (i, j) represents the above-mentioned mode matrix H_bmThe value of the element or cyclic shift value of the ith row and the jth column of (b), p (f, i, j) is the value corresponding to the above-mentioned spreading factor z_fAdjusted mode matrix H of_bmfRow i, column j, or a cyclic shift value. z is a radical of₀Is the largest spreading factor. Z provided by the IEEE std802.16e standard₀＝96。

However, the LDPC code described above has a problem when the mode matrix H is_bmP (i, j) > 0 elements are relatively large, which means more complicated mathematical expressions in the formulas (1-11)

The calculation process of (a) also increases accordingly. In order to further reduce the processing complexity and implementation complexity of encoding and decoding of the LDPC code and increase the processing speed of encoding and decoding, it is necessary to match the mode matrix H_bmFurther improvement is made, so that the operation amount of the formulas (1-11) is further reduced, and the encoding and decoding speed of the LDPC code is improved. In addition, the above-mentioned mode matrix H_bmCan only take values of-1, 0 and positive integers, wherein the positive integers represent values of cyclic shift of the identity matrix to the right by columns, and all elements of the modulus matrix can not be negative integers. Therefore, it is necessary to provide a mode matrix H capable of bidirectional cyclic shift_bmThe flexibility of the encoding process is increased.

Disclosure of Invention

The present invention is directed to solving at least one of the above technical drawbacks, and in particular to solving the problems of reducing the processing complexity and implementation complexity of encoding and decoding of an LDPC code, increasing the processing speed of encoding and decoding, and increasing the flexibility of the encoding process.

In order to achieve the above object, an aspect of the present invention provides a method for encoding an LDPC code, including: using a spreading factor z_fAdjusting the mode matrix H_bmTo generate an adjusted mode matrix H_bmfThe matrix H_bmIs m_bLine n_bA matrix of columns, said matrix H_bmThe value of the element p (i, j) in (b) is-1, 0 or an integer n, and the matrix H_bmThe number of zero elements of (2) is not less than m_b+n_b-1, said matrix H_bmfElement (1) of

Wherein

Presentation pair

Rounding to zero, m_b、n_b、j、i、z_f、z₀Are all positive integers, and i is more than or equal to 1 and less than or equal to m_b，1≤j≤n_b，z_f≤z₀(ii) a Using said matrix H_bmfExpanding to generate a check matrix H, wherein the expansion mode is a sub-matrix P in the check matrix H_i，jExpanding according to the value of P (f, i, j), each sub-matrix P_i，jHas a size of z_f×z_fAnd P (f, i, j) is-1, and the corresponding sub-matrix P_i，jIs an all-zero matrix, and the corresponding sub-matrix P is when the value of P (f, i, j) is 0_i，jIs an identity matrix, and the value of p (f, i, j) is a positive integer

Time, corresponding sub-matrix P_i，jCyclic shift column by column for identity matrix

p (f, i, j) is a negative integer

Time, corresponding sub-matrix P_i,jCyclically shifting the identity matrix column by column to the left

And encoding the input information U by using the check matrix H, and outputting encoded information V.

According to an embodiment of the invention, the matrix H_bmIncluding n_bA column vector

Wherein each column vector h_i(i＝1，…，n_b) Comprising m_bEach element, each column vector h_i(i＝1，…，n_b) The number of the contained zero elements is not smallAt 1.

According to an embodiment of the invention, the matrix H_bmComprising a matrix

Sum matrix

Wherein

The systematic bit portion corresponding to the check matrix H, including the matrix H_bmM on the left side of_bLine, k_bThe elements of the column are,

a check bit portion corresponding to a check matrix H, including the matrix H_bmM on the right side of_bLine, m_bElements of a column, the matrix H_bmThe number of the zero elements of (2) is not less than_b+k_b-1 or 2n_b-k_b-1。

According to an embodiment of the present invention, the column vector h_i(i＝1，…，k_b+1) number of zero elements not less than 1, column vector h_i(i＝k_b+2，…，n_b) The number of zero elements included is 2.

According to an embodiment of the present invention, encoding input information U using the check matrix H includes the steps of: the following operation is performed on the input information U,

wherein u (j) ═ j1，...，k_b) A jth group of bits representing encoder input information U, v (i) (1. -, m)_b) I groups of bits representing the coded information V output by the coder, each group having z bits_f，

Representing a sub-matrix

X is more than or equal to 1 and less than or equal to m_b。

According to an embodiment of the invention, the matrix is a matrix of a plurality of matrices

Column vector h of_i(i＝1，…，k_b) M located foremost_b-1 element

The number of zero elements contained is not less than 1.

According to an embodiment of the invention, the matrix is a matrix of a plurality of matricesIs located atLine 1 to m_bBetween-1 lines, including 1 st and m_b-1 line.

According to an embodiment of the invention, the matrix is a matrix of a plurality of matricesColumn vector h of_i(i＝1，…，k_b) M located at the last_b-1 element

The number of zero elements contained is not less than 1.

According to an embodiment of the invention, the matrix is a matrix of a plurality of matricesIs located at

Line 1 to m_bBetween-1 lines, including 2 nd and m th lines_bAnd (6) rows.

According to an embodiment of the invention, the matrix is a matrix of a plurality of matrices

Column vector h of_i(i＝1，…，k_b) M located in the middle_b2 elements

The number of zero elements contained is not less than 1.

According to an embodiment of the invention, the matrix is a matrix of a plurality of matrices

Is located at

Line 2 to m_bBetween-1 lines, including 2 nd and m th lines_b-1 line.

In another aspect, the present invention provides an LDPC code encoder, which includes a matrix adjustment module, a matrix change module, a matrix storage module, and an encoding module: the matrix adjusting module is used for adjusting the matrix according to the expansion factor z_fAdjusting the mode matrix H_bmTo generate an adjusted mode matrix H_bmfThe matrix H_bmIs m_bLine n_bA matrix of columns, said matrix H_bmElement p (b) of (1)i, j) takes the value of-1, 0 or an integer n, and the matrix H_bmThe number of zero elements of (2) is not less than m_b+n_b-1, said matrix H_bmfElement (1) of

Wherein

Presentation pair

Rounding to zero, m_b、n_b、j、i、z_f、z₀Are all positive integers, and i is more than or equal to 1 and less than or equal to m_b，1≤j≤n_b，z_f≤z₀(ii) a The matrix transformation module is used for transforming the matrix H according to the matrix_bmfGenerating a check matrix H in an expansion mode in which a sub-matrix P in the check matrix H is stored in the matrix storage module_i，jExpanding according to the value of P (f, i, j), each sub-matrix P_i，jHas a size of z_f×z_fAnd P (f, i, j) is-1, and the corresponding sub-matrix P_i，jIs an all-zero matrix, and the corresponding sub-matrix P is when the value of P (f, i, j) is 0_i，jIs an identity matrix, and the value of p (f, i, j) is a positive integerTime, corresponding sub-matrix P_i，jCyclic shift column by column for identity matrix

p (f, i, j) is a negative integerTime, corresponding sub-matrix P_i，jCyclically shifting the identity matrix column by column to the left

The encoding module is used for encoding the input information U according to the check matrix H and outputting encoded information V; the matrix storage module is used for storing a matrix H required by coding_bm、H_bmfAnd H.

According to an embodiment of the invention, the matrix H_bmIncluding n_bA column vector

Wherein each column vector h_i(i＝1，…，n_b) Comprising m_bEach element, each column vector h_i(i＝1，…，n_b) The number of zero elements contained is not less than 1.

According to an embodiment of the invention, the matrix H_bmComprising a matrix

Sum matrix

Wherein

The systematic bit portion corresponding to the check matrix H, including the matrix H_bmM on the left side of_bLine, k_bThe elements of the column are,

a check bit portion corresponding to a check matrix H, including the matrix H_bmM on the right side of_bLine, m_bElements of a column, the matrix H_bmThe number of the zero elements of (2) is not less than_b+k_b-1 or 2n_b-k_b-1。

According to the inventionEmbodiment, the column vector h_i(i＝1，…，k_b+1) number of zero elements not less than 1, column vector h_i(i＝k_b+2，…，n_b) The number of zero elements included is 2.

According to the technical scheme provided by the invention, by adding a mode matrix H_bmThe number of the zero elements can reduce the processing complexity and the realization complexity of the encoding and decoding of the LDPC code and improve the processing speed of the encoding and decoding. The invention provides a mode matrix H_bmThe element values of (1) can be-1, 0 and positive integer, and can also be negative and positive number less than-1, so that the unit matrix can also carry out bidirectional cyclic shift, and not only right cyclic shift but also left cyclic shift is supported, thereby increasing the flexibility of coding processing. In addition, the mode matrix H_bmCan also become smaller so that the modulus matrix H_bmThe quantization bit of the element parameter value can be reduced, thereby saving the storage cost and the hardware expense and reducing the implementation complexity.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a mold matrix H_bmSchematic structural diagram of (a);

FIG. 2 is a flow chart of LDPC code encoding;

FIG. 3 is a structural diagram of an LDPC code encoder.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.

The invention provides a coding method of an LDPC code, which comprises the following steps: using a spreading factor z_fAdjusting the mode matrix H_bmTo generate an adjusted mode matrix H_bmfThe matrix H_bmIs m_bLine n_bA matrix of columns, said matrix H_bmThe value of the element p (i, j) in (b) is-1, 0 or an integer n, and the matrix H_bmThe number of zero elements of (2) is not less than m_b+n_b-1, said matrix H_bmfElement (1) of

Wherein

Presentation pair

Rounding to zero, m_b、n_b、j、i、z_f、z₀Are all positive integers, and i is more than or equal to 1 and less than or equal to m_b，1≤j≤n_b，z_f≤z₀(ii) a Using said matrix H_bmfExpanding to generate a check matrix H, wherein the expansion mode is a sub-matrix P in the check matrix H_{i， j}Expanding according to the value of P (f, i, j), each sub-matrix P_i，jHas a size of z_f×z_fAnd P (f, i, j) is-1, and the corresponding sub-matrix P_i，jIs an all-zero matrix, and the corresponding sub-matrix P is when the value of P (f, i, j) is 0_i，jIs an identity matrix, and the value of p (f, i, j) is a positive integerTime, corresponding sub-matrix P_i，jCyclic shift column by column for identity matrix

p (f, i, j) is a negative integer

Time, corresponding sub-matrix P_i，jCyclically shifting the identity matrix column by column to the left

Coding input information U by using the check matrix H and outputting coded information V

As shown in fig. 2, a flow chart of LDPC code coding proposed by the present invention includes the following steps:

s101: using a spreading factor z_fAdjusting the mode matrix H_bmGenerating an adjusted mode matrix H_bmf。

According to the technical scheme provided by the invention, the mode matrix H_bmThe number of rows and columns is m_bAnd n_bMatrix H as shown in equation (1-2)_bmThe value of the element p (i, j) in (a) is-1, 0 or an integer n. In order to reduce the processing complexity and the realization complexity of the encoding and decoding of the LDPC code and improve the processing speed of the encoding and decoding, the invention provides the modular matrix H_bmThe number of zero elements of (2) is not less than m_b+n_b-1。

Existing mode matrix H_bmCan only take values of-1, 0 and positive integers, wherein the positive integers represent shift values of the unit matrix circularly shifted to the right according to columns, and all elements of the existing module matrix can not be negative integers. The invention provides a mode matrix H_bmThe value of the element can be-1, 0 and positive integer, and can also be negative and positive number less than-1, the unit matrix can be circularly shifted in two directions, namely, the unit matrix not only supports right circular shift, but also supports left circular shift, and the coding position is increasedAnd (4) physical flexibility. In addition, the mode matrix H_bmCan also become smaller so that the modulus matrix H_bmThe quantization bit of the element parameter value can be reduced, thereby saving the storage cost and the hardware expense and reducing the implementation complexity.

Under this condition, the spreading factor z is used_fAdjusting the mode matrix H_bmGenerating an adjusted mode matrix H_bmf. Matrix H_bmfThe elements in (A) are adjusted to be:

wherein

Presentation pair

Rounding to zero, m_b、n_b、j、i、z_f、z₀Are all positive integers, and i is more than or equal to 1 and less than or equal to m_b，1≤j≤n_b、z _f≤z₀。

As an embodiment of the invention, matrix H_bmIncluding n_bA column vectorWherein each column vector h_i(i＝1，…，n_b) Comprising m_bEach element, each column vector h_i(i＝1，…，n_b) The number of zero elements contained is not less than 1.

As an embodiment of the invention, the invention proposes a mode matrix H_bmOr divided into 2 sections, as shown in FIG. 1, where the mode matrix H_bmExpressed as in equations (1-5):

$H_{\mathrm{bm}}=\left[\begin{array}{cc}{H}_{\mathrm{bm}}^S& H_{\mathrm{bm}}^P\end{array}\right]---(1-5)$

wherein,a systematic bit portion corresponding to the check matrix H, which includes the matrix H_bmM on the left side of_bLine, k_bElements of the column, corresponding to H_bmLeft side k of_bA column vector h_i(i＝1，…，k_b) As shown in the formulas (1-6),

$H_{\mathrm{bm}}^S=[h_1,...,h_{k_b}]---(1-6)$

wherein,

a check bit portion corresponding to a check matrix H, which includes the matrix H_bmM on the right side of_bLine, m_bElements of the column, corresponding to H_bmRight side m of_bA column vector h_i(i＝k_b+1，…，n_b) As shown in the formulas (1-7),

$H_{\mathrm{bm}}^P=[h_{k_b+1},...,h_{n_b}]---(1-7)$

wherein k is_b+m_b＝n_b。

At this time, as an embodiment of the present invention, the matrix H_bmThe number of the zero elements of (2) is not less than_b+k_b-1 or 2n_b-k_b-1。

As an embodiment of the invention, the column vector h_i(i＝1，…，k_b+1) number of zero elements not less than 1, column vector h_i(i＝k_b+2，…，n_b) The number of zero elements included is 2.

The matrix H provided by the invention_bmThere may also be multiple forms that are subject to the following conditions, for example:

matrix array

Column vector h of_i(i＝1，…，k_b) M located foremost_b-1 element

The number of contained zero elements is not less than 1; further, it may be a matrix

Is located at

Line 1 to m_bBetween-1 lines, including 1 st and m_b-1 line.

More specifically, momentMatrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝12、m_b＝12、n_b＝24：

TABLE 2(a)

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝20、m_b＝4、n_b＝24：

TABLE 3(a)

Matrix array

Column vector h of_i(i＝1，…，k_b) M located at the last_b-1 element

The number of contained zero elements is not less than 1; further, it may be a matrix

Is located atLine 1 to m_bBetween-1 lines, including 2 nd and m th lines_bAnd (6) rows.

More specifically, the matrix H_bmN of (A) to (B)_bIn the direction of each columnTaking n of a matrix_bA column vector of k_b＝16、m_b＝8、n_b＝24：

TABLE 4(a)

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝16、m_b＝8、n_b＝24：

TABLE 5(a)

Matrix array

Column vector h of_i(i＝1，…，k_b) M located in the middle_b2 elements

The number of contained zero elements is not less than 1; further, the matrix

Is located at

Line 2 to m_bBetween-1 lines, including 2 nd and m th lines_b-1 line.

More specifically, the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vectorWherein k is_b＝16、m_b＝12、n_b＝32：

Watch 6(a)

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝16、m_b＝16、n_b＝32：

TABLE 7(a)

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝16、m_b＝16、n_b＝32：

Watch 8(a)

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝16、m_b＝8、n_b＝24：

Watch 9(a)

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝18、m_b＝6、n_b＝24：

Watch 10(a)

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝18、m_b＝6、n_b＝24：

Watch 11(a)

Obviously, there are various expressions for each of the above matrix tables 2(a) to 11(a), and a specific mode matrix H is a specific example of one matrix in the above matrix tables 2(a) to 11(a)_bmComprises the following steps:

watch 12(b)

Or the matrix H_bmComprises the following steps:

watch 13(b)

Or the matrix H_bmComprises the following steps:

watch 14(b)

Or the matrix H_bmComprises the following steps:

watch 15(b)

Or the matrix H_bmComprises the following steps:

watch 16(b)

Or the matrix H_bmComprises the following steps:

watch 17(b)

Or the matrix H_bmComprises the following steps:

watch 18(b)

Or the matrix H_bmComprises the following steps:

watch 19(b)

Or the matrix H_bmComprises the following steps:

watch 20(b)

Or the matrix H_bmComprises the following steps:

watch 21(b)

S102: using adjusted mode matrix H_bmfAnd expanding to generate a check matrix H.

Determining the modulus matrix H according to step S101_bmAnd then expanding to generate a check matrix H for the input information. The expansion mode is a sub-matrix P in the check matrix H_i，jExpanding according to the value of P (f, i, j), each sub-matrix P_i，jHas a size of z_f×z_fAnd P (f, i, j) is-1, and the corresponding sub-matrix P_i，jIs an all-zero matrix, and the corresponding sub-matrix P is when the value of P (f, i, j) is 0_i，jIs an identity matrix, and the value of p (f, i, j) is a positive integer

Time, corresponding sub-matrix P_i，jCyclic shift column by column for identity matrix

p (f, i, j) is a negative integerTime, corresponding sub-matrix P_i，jCyclically shifting the identity matrix column by column to the left

S103: the input information is encoded using a check matrix H.

And encoding the input information according to the check matrix H obtained in the step S102. The following operation is performed on the input information U,

wherein u (j) 1_b) A jth group of bits representing encoder input information U, v (i) (1. -, m)_b) I groups of bits representing the coded information V output by the coder, each group having z bits_f，

Representing a sub-matrixX is more than or equal to 1 and less than or equal to m_b。

The method provided by the invention adds the mode matrix H_bmThe number of the zero elements can reduce the processing complexity and the realization complexity of the encoding and decoding of the LDPC code and improve the processing speed of the encoding and decoding. For example, the mode matrix H is calculated using the coding matrices of tables 2(a) and 2(b) proposed in the present invention, as compared to the coding matrix of WiMAX of Table 1_bmfComplexity of complex function of formula of elementThe coding method is relatively reduced by 25%, and the whole coding computation complexity of the coding method provided by the invention can be relatively reduced by 9.6%. In addition, the invention correspondingly reduces the processing complexity of the decoder for expanding the modulus matrix and generating the check matrix, improves the decoding processing speed and further reduces the expenses of the memory and the hardware by 12.5 percent. .

As shown in fig. 3, the present invention further provides an LDPC code encoder 300, which includes a matrix adjusting module 310, a matrix changing module, a matrix storing module 330, and an encoding module 340.

Wherein the matrix adjustment module 310 is configured to adjust the spreading factor z_fAdjusting the mode matrix H_bmTo generate an adjusted mode matrix H_bmfAnd stored in a matrix storage block 330, matrix H_bmIs m_bLine n_bMatrix of columns, matrix H_bmThe value of the element p (i, j) in (A) is-1, 0 or an integer n, and the matrix H_bmThe number of zero elements of (2) is not less than m_b+n_b-1, matrix H_bmfElement (1) ofWhereinPresentation pair

Rounding to zero, m_b、n_b、j、i、z_f、z₀Are all positive integers, and i is more than or equal to 1 and less than or equal to m_b，1≤j≤n_b，z_f≤z₀(ii) a The matrix transformation module 320 is used for transforming the matrix according to the matrix H_bmfGenerating a check matrix H by expansion and storing the check matrix H in the matrix storage module 330, wherein the expansion mode is a sub-matrix P in the check matrix H_i，jExpanding according to the value of P (f, i, j), each sub-matrix P_i，jHas a size of z_f×z_fAnd P (f, i, j) is-1, and the corresponding sub-matrix P_i，jThe value of p (f, i, j) is an all-zero matrixSub-matrix P corresponding to 0_i，jIs an identity matrix, and the value of p (f, i, j) is a positive integer

Time, corresponding sub-matrix P_i，jCyclic shift column by column for identity matrix

p (f, i, j) is a negative integer

Time, corresponding sub-matrix P_i，jCyclically shifting the identity matrix column by column to the left

The encoding module 340 is configured to encode the input information U according to the check matrix H, and output encoded information V; the matrix storage module 330 is used for storing the matrix H required by the coding_bm、H_bmfAnd H.

Matrix H used by encoder 300 as an embodiment of the present invention_bmIncluding n_bA column vector

Wherein each column vector h_i(i＝1，…，n_b) Comprising m_bEach element, each column vector h_i(i＝1，…，n_b) The number of zero elements contained is not less than 1.

As an embodiment of the invention, matrix H_bmComprising a matrix

Sum matrix

Wherein

The systematic bit portion corresponding to the check matrix H, including the matrix H_bmM on the left side of_bLine, k_bThe elements of the column are,

a check bit portion corresponding to a check matrix H, including the matrix H_bmM on the right side of_bLine, m_bElements of a column, matrix H_bmThe number of the zero elements of (2) is not less than_b+k_b-1 or 2n_b-k_b-1。

Matrix H used by encoder 300 as an embodiment of the present invention_bmColumn vector h of_i(i＝1，…，k_b+1) number of zero elements not less than 1, column vector h_i(i＝k_b+2，…，n_b) The number of zero elements included is 2.

Matrix H used by encoder 300 as an embodiment of the present invention_bmAlso included are matrices H shown in tables 2(a) to 11(a), 12(b) to 21(b)_bmExamples of (1).

The device provided by the invention is characterized in that a mode matrix H is added_bmThe number of the zero elements can reduce the processing complexity and the realization complexity of the encoding and decoding of the LDPC code and improve the processing speed of the encoding and decoding. The invention provides a mode matrix H_bmThe element values of (1) can be-1, 0 and positive integer, and can also be negative and positive number less than-1, so that the unit matrix can also carry out bidirectional cyclic shift, and not only right cyclic shift but also left cyclic shift is supported, thereby increasing the flexibility of coding processing. In addition, the mode matrix H_bmCan also become smaller so that the modulus matrix H_bmThe quantization bits of the parameter values of the elements of (1) can be reduced, thereby saving memory cost and hardware overhead in the encoderAnd the pin reduces the implementation complexity.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (19)

1. An encoding method of an LDPC code, comprising the steps of:

using a spreading factor z_fAdjusting the mode matrix H_bmTo generate an adjusted mode matrix H_bmfThe matrix H_bmIs m_bLine n_bA matrix of columns, said matrix H_bmThe value of the element p (i, j) in (b) is-1, 0 or an integer n, and the matrix H_bmThe number of zero elements of (2) is not less than m_b+n_b-1, said matrix H_bmfElement (1) of

Wherein

Presentation pair

Rounding to zero, m_b、n_b、j、i、z_f、z₀Are all positive integers, and i is more than or equal to 1 and less than or equal to m_b，1≤j≤n_b,z_f≤z₀；

Using said matrix H_bmfExpanding to generate a check matrix H, wherein the expansion mode is a sub-matrix P in the check matrix H_i，jExpanding according to the value of P (f, i, j), each sub-matrix P_i，jHas a size of z_f×z_fAnd P (f, i, j) is-1, and the corresponding sub-matrix P_i，jIs an all-zero matrix, and the corresponding sub-matrix P is when the value of P (f, i, j) is 0_i，jIs an identity matrix, and the value of p (f, i, j) is a positive integer

Time, corresponding sub-matrix P_i，jCyclic shift column by column for identity matrix

p (f, i, j) is a negative integerTime, corresponding sub-matrix P_i，jCyclically shifting the identity matrix column by column to the left

And encoding the input information U by using the check matrix H, and outputting encoded information V.

2. The encoding method of LDPC code according to claim 1, wherein the matrix H is_bmIncluding n_bA column vector

Wherein each column vector h_i(i＝1，…，n_b) Comprising m_bEach element, each column vector h_i(i＝1，…，n_b) The number of zero elements contained is not less than 1.

3. The encoding method of LDPC code according to claim 2, wherein the matrix H is_bmComprising a matrix

Sum matrix

Wherein

The systematic bit portion corresponding to the check matrix H, including the matrix H_bmM on the left side of_bLine, k_bThe elements of the column are,a check bit portion corresponding to a check matrix H, including the matrix H_bmM on the right side of_bLine, m_bElements of a column, the matrix H_bmThe number of the zero elements of (2) is not less than_b+k_b-1 or 2n_b-k_b-1。

4. The encoding method of LDPC code according to claim 3, wherein the column vector h_i(i＝1，…，k_b+1)Number of zero elements contained is not less than 1, column vector h_i(i＝k_b+2，…，n_b) The number of zero elements included is 2.

5. The encoding method of the LDPC code according to one of claims 3 to 4, wherein the encoding of the input information U using the check matrix H comprises the steps of: the following operation is performed on the input information U,

wherein u (j) 1_b) A jth group of bits representing encoder input information U, v (i) (1. -, m)_b) I groups of bits representing the coded information V output by the coder, each group having z bits_f，Representing a sub-matrix

X is more than or equal to 1 and less than or equal to m_b。

6. The encoding method of LDPC code according to claim 5, wherein the matrix is formed of a plurality of matrices

Column vector h of_i(i＝1，…，k_b) M located foremost_b-1 element

The number of zero elements contained is not less than 1.

7. The encoding method of the LDPC code according to claim 6, wherein the matrix is formed of a plurality of matrices

Is located at

Line 1 to m_bBetween-1 lines, including 1 st and m_b-1 line.

8. The encoding method of LDPC code according to claim 7,

the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝12、m_b＝12、n_b＝24：

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝20、m_b＝4、n_b＝24：

9. The encoding method of LDPC code according to claim 5, wherein the matrix is formed of a plurality of matrices

Column vector h of_i(i＝1，…，k_b) M located at the last_b-1 element

The number of zero elements contained is not less than 1.

10. The encoding method of LDPC code according to claim 9, wherein the matrix is a matrix of a plurality of bit lines

Is located at

Line 1 to m_bBetween-1 lines, including 2 nd and m th lines_bAnd (6) rows.

11. The encoding method of LDPC code according to claim 10,

the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝16、m_b＝8、n_b＝24：

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝16、m_b＝8、n_b＝24：

12. The encoding method of LDPC code according to claim 5, wherein the matrix is formed of a plurality of matrices

Column vector h of_i(i＝1，…，k_b) M located in the middle_b2 elements

The number of zero elements contained is not less than 1.

13. The method of encoding an LDPC code as claimed in claim 12 wherein the moment barriersIs located at

Line 2 to m_bBetween-1 lines, including 2 nd and m th lines_b-1 line.

14. The encoding method of LDPC code according to claim 13,

the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝16、m_b＝16、n_b＝32：

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝16、m_b＝16、n_b＝32：

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝16、m_b＝16、n_b＝32：

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝16、m_b＝8、n_b＝24：

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝18、m_b＝6、n_b＝24：

Or the matrix H_bmN of (A) to (B)_bThe column vectors are taken from n of the matrix_bA column vector of k_b＝18、m_b＝6、n_b＝24：

15. The encoding method of LDPC code according to claim 5, wherein the matrix H_bmComprises the following steps:

or the matrix H_bmComprises the following steps:

or the matrix H_bmComprises the following steps:

or the matrix H_bmComprises the following steps:

or the matrix H_bmComprises the following steps:

or the matrix H_bmComprises the following steps:

or the matrix H_bmComprises the following steps:

or the matrix H_bmComprises the following steps:

or the matrix H_bmComprises the following steps:

orThe matrix H_bmComprises the following steps:

16. an LDPC code encoder, comprising a matrix adjustment module, a matrix change module, a matrix storage module and an encoding module:

the matrix adjusting module is used for adjusting the matrix according to the expansion factor z_fAdjusting the mode matrix H_bmTo generate an adjusted mode matrix H_bmfThe matrix H_bmIs m_bLine n_bA matrix of columns, said matrix H_bmThe value of the element p (i, j) in (b) is-1, 0 or an integer n, and the matrix H_bmThe number of zero elements of (2) is not less than m_b+n_b-1, said matrix H_bmfElement (1) of

WhereinPresentation pair

Rounding to zero, m_b、n_b、j、i、z_f、z₀Are all positive integers, and i is more than or equal to 1 and less than or equal to m_b，1≤j≤n_b，z_f≤z₀；

The matrix transformation module is used for transforming the matrix H according to the matrix_bmfGenerating a check matrix H in an expansion mode in which a sub-matrix P in the check matrix H is stored in the matrix storage module_i，jExpanding according to the value of P (f, i, j), each sub-matrix P_i，jHas a size of z_f×z_fAnd P (f, i, j) is-1, and the corresponding sub-matrix P_i，jIs an all-zero matrix, and the corresponding sub-matrix P is when the value of P (f, i, j) is 0_i，jIs an identity matrix, and the value of p (f, i, j) is a positive integer

Time, corresponding sub-matrix P_i，jCyclic shift column by column for identity matrix

p (f, i, j) is a negative integer

Time, corresponding sub-matrix P_i，jCyclically shifting the identity matrix column by column to the left

The encoding module is used for encoding the input information U according to the check matrix H and outputting encoded information V;

the matrix storage module is used for storing a matrix H required by coding_bm、H_bmfAnd H.

17. The LDPC code encoder of claim 16, wherein the matrix H_bmIncluding n_bA column vector

Wherein each column vector h_i(i＝1，…，n_b) Comprising m_bEach element, each column vector h_i(i＝1，…，n_b) The number of zero elements contained is not less than 1.

18. The LDPC code encoder of claim 17, wherein the matrix H_bmComprising a matrix

Sum matrix

Wherein

The systematic bit portion corresponding to the check matrix H, including the matrix H_bmM on the left side of_bLine, k_bThe elements of the column are,

a check bit portion corresponding to a check matrix H, including the matrix H_bmM on the right side of_bLine, m_bElements of a column, the matrix H_bmThe number of the zero elements of (2) is not less than_b+k_b-1 or 2n_b-k_b-1。

19. The LDPC code encoder of claim 18, wherein the column vector h_i(i＝1，…，k_b+1) number of zero elements not less than 1, column vector h_i(i＝k_b+2，…，n_b) The number of zero elements included is 2.

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