CN108712174B - The method, apparatus and communication equipment of information processing - Google Patents

Abstract

This application discloses coding method, device, communication equipment and communication systems.This method comprises: being encoded using low-density checksum LDPC matrix to input bit sequence；Wherein, the LDPC matrix is obtained based on spreading factor Z and basic matrix, the basic matrix includes the 0th to 4 row and the 0th to 26 column in one of matrix shown in Fig. 3 b-1 to Fig. 3 b-10, alternatively, the basic matrix includes the 0th to 4 row in one of matrix shown in Fig. 3 b-1 to Fig. 3 b-10 and the part column in the 0th to 26 column.Coding method, device, communication equipment and the communication system of the application, can satisfy channel coding demand.

Description

The method, apparatus and communication equipment of information processing

Technical field

The present embodiments relate to the communications field more particularly to the methods and communication device of information processing.

Background technique

Low-density checksum (low density parity check, LDPC) code is a kind of with sparse check matrix Linear block coding, have flexible structure, the low feature of decoding complexity.Since it is calculated using the iterative decoding of part parallel Method, to have higher throughput than traditional Turbo code.LDPC code can be used for the error correcting code of communication system, to improve The reliability and power utilization of transmission.LDPC code can also be widely used in space communication, fiber optic communication, personal communication System, ADSL and magnetic recording equipment etc..It has contemplated that at present using LDPC code in the 5th third-generation mobile communication as channel coding side One of formula.

It in actual use, can be using the LDPC matrix with special construction feature.This has special construction The LDPC matrix H of feature can be extended to obtain by the LDPC basic matrix of quasi- circulation (quasi cycle, QC) structure.QC-LDPC is suitable The high hardware of merging rows degree, the throughput provided are higher.It can be allowed to be applied to channel volume by being designed to LDPC matrix Code.

The hardware that QC-LDPC is suitble to degree of parallelism high, the throughput provided are higher.It can be by being designed to LDPC matrix It is allowed to be applied to channel coding.

Summary of the invention

The embodiment of the invention provides a kind of method of information processing, communication device and systems, can support different lengths Information bit sequence coding and decoding.

In a first aspect, providing a kind of coding method and encoder, the encoder uses low-density checksum LDPC Matrix encodes list entries.

Second aspect, provides a kind of interpretation method and decoder, and the decoder uses low-density checksum LDPC Matrix decodes list entries.

In the first implementation of above-mentioned first aspect or second aspect: the LDPC matrix is based on spreading factor What Z and basic matrix obtained.

Based on above-mentioned implementation, the basic matrix of base Figure 30 a may include matrix 30b-10,30b-11,30b-20,30b- 21, the 0th~4 row and the 0th in one of matrix shown in 30b-30,30b-40,30b-50,30b-60,30b-70 and 30b-80 To 26 column, alternatively, the basic matrix includes matrix 30b-10,30b-11,30b-20,30b-21,30b-30,30b-40,30b- 50, the 0th~4 row in one of matrix shown in 30b-60,30b-70 and 30b-80 and the part column in the 0th to 26 column, or, base Matrix can be the row/column transformation of the 0th~4 row and the 0th to 26 column in one of matrix shown in matrix 30b-10 to 30b-80 Matrix afterwards, or, basic matrix can be matrix 30b-10,30b-11,30b-20,30b-21,30b-30,30b-40,30b-50, The row/column of the part column in the 0th to 4 row and the 0th to 26 column in one of matrix shown in 30b-60,30b-70 and 30b-80 becomes Matrix after changing.

Further, the basic matrix of base Figure 30 a can also include matrix 30b-10,30b-11,30b-20,30b-21,30b- 30, the 0th row in one of matrix shown in 30b-40,30b-50,30b-60,30b-70 and 30b-80 is gone to (m-1), Yi Ji 0 column to (n-1) arrange, or, basic matrix can be matrix 30b-10,30b-11,30b-20,30b-21,30b-30,30b-40, The 0th row to (m-1) row and the 0th in one of matrix shown in 30b-50,30b-60,30b-70 and 30b-80 is arranged to (n- 1) the transformed matrix of row/column arranged.5≤m≤46,27≤n≤68

In order to support that different masses are long, LDPC code needs different spreading factor Z, be based on aforementioned implementation, one kind can In the implementation of energy, corresponding basic matrix is used based on different spreading factor Z.For example, Z=a × 2^j, 0≤j < 7, a∈{2,3,5,7,9,11,13,15}。

If a=2, basic matrix may include the 0th to 4 row in matrix 30b-10 or 30b-11 and the 0th to 26 column, or Person, the basic matrix include the part column in the 0th to 4 row and the 0th to 26 column in matrix 30b-10 or 30b-11.Into one Step ground, basic matrix further include that the 0th row of matrix 30b-10 or 30b-11 are arranged to (m-1) row and the 0th column to (n-1).

If a=3, basic matrix may include the 0th to 4 row in matrix 30b-20 or 30b-21 and the 0th to 26 column, or Person, the basic matrix include the part column in the 0th to 4 row and the 0th to 26 column in matrix 30b-20 or 30b-21.Into one Step ground, basic matrix further include that the 0th row of matrix 30b-20 or 30b-21 are arranged to (m-1) row and the 0th column to (n-1).

If a=5, basic matrix may include the 0th to 4 row and the 0th to 26 column in matrix 30b-30, alternatively, the base Matrix includes the part column in the 0th to 4 row and the 0th to 26 column in matrix 30b-30.Further, basic matrix further includes square The 0th row of battle array 30b-30 is arranged to (m-1) row and the 0th column to (n-1).

If a=7, basic matrix may include the 0th to 4 row and the 0th to 26 column in matrix 30b-40, alternatively, the base Matrix includes the part column in the 0th to 4 row and the 0th to 26 column in matrix 30b-40.Further, basic matrix further includes square The 0th row of battle array 30b-40 is arranged to (m-1) row and the 0th column to (n-1).

If a=9, basic matrix may include the 0th to 4 row and the 0th to 26 column in matrix 30b-50, alternatively, the base Matrix includes the part column in the 0th to 4 row and the 0th to 26 column in matrix 30b-50.Further, basic matrix further includes square The 0th row of battle array 30b-50 is arranged to (m-1) row and the 0th column to (n-1).

If a=11, basic matrix may include the 0th to 4 row and the 0th to 26 column in matrix 30b-60, alternatively, the base Matrix includes the part column in the 0th to 4 row and the 0th to 26 column in matrix 30b-60.Further, basic matrix further includes square The 0th row of battle array 30b-60 is arranged to (m-1) row and the 0th column to (n-1).

If a=13, basic matrix may include the 0th to 4 row and the 0th to 26 column in matrix 30b-70, alternatively, the base Matrix includes the part column in the 0th to 4 row and the 0th to 26 column in matrix 30b-70.Further, basic matrix further includes square The 0th row of battle array 30b-70 is arranged to (m-1) row and the 0th column to (n-1).

If a=15, basic matrix may include the 0th to 4 row and the 0th to 26 column in matrix 30b-80, alternatively, the base Matrix includes the part column in the 0th to 4 row and the 0th to 26 column in matrix 30b-80.Further, basic matrix further includes square The 0th row of battle array 30b-80 is arranged to (m-1) row and the 0th column to (n-1).

Basic matrix can be the transformed matrix of row/column of correspondingly matrix.

Further, optionally, it is based on above-mentioned implementation, LDPC matrix can be based on spreading factor Z and to aforementioned each Matrix H s after basic matrix compensates is obtained, or after compensating based on spreading factor Z and to aforementioned each basic matrix The transformed matrix of the row/column of matrix H s obtains.Aforementioned each basic matrix is compensated, can be and be greater than in wherein one or more columns per page Or the deviant equal to 0 increases or decreases offset.

The base figure and basic matrix of LDPC matrix in above-mentioned each implementation can satisfy the performance of a variety of pieces of long code blocks Demand.

Based on any possible implementation of above-mentioned various aspects or various aspects, in another possible implementation In, further includes: determine spreading factor Z.For example, determining the value of spreading factor Z according to the length K of list entries, can be In the spreading factor set of support, the smallest Z is found₀As the size of spreading factor Z, and meet KbZ₀≥K.One kind can In the design of energy, Kb can be the columns of information bit in the basic matrix of LDPC code.For example, for base Figure 30 a, Kb=22.Again In a kind of possible design, the value of Kb can also change according to the value of K, but be no more than information ratio in the basic matrix of LDPC code Special columns.For example, when K is greater than the first thresholding, Kb=22；When K is less than or equal to the first thresholding, Kb=21.Alternatively, K is greater than When the first thresholding, Kb=22；K be less than or equal to the first thresholding, and K be greater than the second thresholding when, Kb=21；K is less than or waits When the second thresholding, Kb=20.

Wherein, spreading factor Z can be determined by encoder or decoder according to the length K of list entries, be also possible to Encoder or decoder are supplied to as input parameter after being determined by other devices.

It is alternatively possible to obtain LDPC square according to the spreading factor Z got basic matrix corresponding with spreading factor Z Battle array.

In second of implementation of above-mentioned first aspect or second aspect: the LDPC matrix is based on spreading factor What the parameter of Z and LDPC matrix obtained.

The parameter of LDPC matrix may include: the column where line number, nonzero element, nonzero element deviant, as table 3-10, Table 3-11, table 3-20, table 3-21, table 3-30, table 3-40, table 3-50, table 3-60, table 3-70 and table 3-80 mode save. It can also include row weight.Wherein each deviant is an a pair in each position and nonzero element deviant in the column where nonzero element It answers.

To which encoder encodes list entries according to the parameter of spreading factor Z and LDPC matrix.Wherein according to table The parameter that 3-10 is saved is corresponding with matrix 30b-10, and the parameter saved according to table 3-11 is corresponding with matrix 30b-11, according to table 3- The parameter of 20 preservations is corresponding with matrix 30b-20, and the parameter saved according to table 3-21 is corresponding with matrix 30b-21, according to table 3-30 The parameter of preservation is corresponding with matrix 30b-30, and the parameter saved according to table 3-40 is corresponding with matrix 30b-40, is protected according to table 3-50 The parameter deposited is corresponding with matrix 30b-50, and the parameter saved according to table 3-60 is corresponding with matrix 30b-60, is saved according to table 3-70 Parameter it is corresponding with matrix 30b-70, according to table 3-80 save parameter it is corresponding with matrix 30b-80.

For the communication equipment of transmitting terminal, carrying out coding to the list entries using LDPC matrix may include:

The list entries is encoded using spreading factor Z corresponding LDPC matrix；Or spreading factor Z is corresponding LDPC matrix have passed through row/column transformation, and the matrix after being encoded using the transformed matrix of row/column to list entries is to described List entries is encoded.Row/column transformation refers to row transformation, rank transformation or row transformation and rank transformation in the application.

For the communication equipment of receiving end, carrying out decoding to list entries using LDPC matrix includes:

List entries is decoded using spreading factor Z corresponding LDPC matrix；Or the corresponding LDPC of spreading factor Z Matrix have passed through row/column transformation, and the matrix after being encoded using the transformed matrix of row/column to list entries is to the input Sequence is encoded.Row/column transformation refers to row transformation, rank transformation or row transformation and rank transformation in the application.

In one possible implementation, LDPC matrix can be saved, list entries is carried out using the LDPC matrix Coding, or the LDPC matrix that (row/column transformation) or extension acquisition can be used for encoding is converted based on the LDPC matrix.

In alternatively possible implementation, parameter can be saved, according to the parameter can obtain for encode or The LDPC matrix of person's decoding, so as to which list entries is encoded or decoded based on LDPC matrix.The parameter includes At least one of: base figure, basic matrix are based on Ji Tu or the transformed transformation matrix of basic matrix row/column, are based on Ji Tu or group moment The extended matrix of battle array, in basic matrix the deviant of nonzero element or with any parameter for obtaining LDPC matrix correlation.

In another possible implementation, the basic matrix of LDPC matrix can be saved in memory.

In another possible implementation, the base figure of LDPC matrix is saved in memory, the group moment of LDPC matrix The deviant of nonzero element can save in memory in battle array.

In another possible implementation, the parameter of LDPC matrix is protected according to mode shown in table 3-10 to table 3-80 It is stored in memory.

A kind of base based on above-mentioned each possible implementation, in possible design, for LDPC coding or decoding At least one in figure and basic matrix is that at least one in the base figure and basic matrix of above-mentioned LDPC matrix exchanges or arrange friendship through space It is obtained after changing or going exchange and column exchange.

The third aspect, providing a kind of communication device may include for executing corresponding module in above method design. The module can be software and/or be hardware.

In a possible design, the communication device that the third aspect provides, including processor and transmitting-receiving subassembly, the processing Device and transmitting-receiving subassembly can be used for realizing the function of each section in above-mentioned coding or interpretation method.In this design, if this is logical T unit is that terminal, base station or other network equipments, transmitting-receiving subassembly can be transceiver, if the communication device is base band Chip or base band veneer, transmitting-receiving subassembly can be the input/output circuitry of baseband chip or base band veneer, for realizing defeated Enter/reception/transmission of output signal.The communication device can also include optionally memory, for storing data and/or refer to It enables.

In one implementation, the processor may include the encoder as described in above-mentioned first aspect and determination Unit.The determination unit is for determining to spreading factor Z needed for list entries coding.The encoder is for described in use The corresponding LDPC matrix of spreading factor Z encodes the list entries.

In another implementation, the processor may include decoder as described in above-mentioned second aspect and obtain Take unit.The acquiring unit is used to obtain the soft value and spreading factor Z of LDPC code.The decoder is used to be based on spreading factor The corresponding basic matrix H of Z_BThe soft value of LDPC code is decoded to obtain information bit sequence.

Fourth aspect provides a kind of communication device, including one or more processors.

In a kind of possible design, one or more processors can realize the function of encoder described in first aspect Can, in alternatively possible design, encoder described in first aspect can be a part of the processor, processor in addition to The function of realizing encoder described in first aspect, can also realize other function.

In a kind of possible design, one or more processors can realize the function of decoder described in second aspect Can, in alternatively possible design, decoder described in second aspect can be a part of the processor.

Optionally, the communication device can also include transceiver and antenna.

Optionally, the communication device can also include for generating the device of transmission block CRC, for code block segmentation and The device of CRC check, the interleaver for intertexture or modulator for modulation treatment etc..

Optionally, the communication device can also include the demodulator for demodulation operation, the deinterleaving for deinterleaving Device or device etc. for solving rate-matched.The function of these devices can be realized by one or more processors.

In a kind of possible design, the function of these devices can be realized by one or more processors.

5th aspect, the embodiment of the invention provides a kind of communication system, which includes described in the above-mentioned third aspect Communication device.

6th aspect, the embodiment of the invention provides a kind of communication system, which includes one or more fourth aspects The communication device.

In another aspect, program is stored thereon with the embodiment of the invention provides a kind of computer storage medium, when its operation When, so that computer executes method described in above-mentioned aspect.

The another aspect of the application provides a kind of computer program product comprising instruction, when it runs on computers When, so that computer executes method described in above-mentioned various aspects.

Method, apparatus, communication equipment and the communication system of the information processing of the embodiment of the present invention, in coding efficiency and mistake It can adapt to the flexible and changeable code length code rate needs of system on leveling.

Detailed description of the invention

Fig. 1 is the schematic diagram of the base figure of a LDPC code, basic matrix and its cyclic permutation matrices；

Fig. 2 is the structural schematic diagram of the base figure of a LDPC code；

Fig. 3 a is the schematic diagram for the LDPC code base figure that one embodiment of the invention provides；

Fig. 3 b-1 is the schematic diagram of a basic matrix provided in an embodiment of the present invention；

Fig. 3 b-2 is the schematic diagram of another basic matrix provided in an embodiment of the present invention；

Fig. 3 b-3 is the schematic diagram of another basic matrix provided in an embodiment of the present invention；

Fig. 3 b-4 is the schematic diagram of another basic matrix provided in an embodiment of the present invention；

Fig. 3 b-5 is the schematic diagram of another basic matrix provided in an embodiment of the present invention；

Fig. 3 b-6 is the schematic diagram of another basic matrix provided in an embodiment of the present invention；

Fig. 3 b-7 is the schematic diagram of another basic matrix provided in an embodiment of the present invention；

Fig. 3 b-8 is the schematic diagram of another basic matrix provided in an embodiment of the present invention；

Fig. 3 b-9 is the schematic diagram of another basic matrix provided in an embodiment of the present invention；

Fig. 3 b-10 is the schematic diagram of another basic matrix provided in an embodiment of the present invention；

Fig. 4 is performance schematic diagram provided in an embodiment of the present invention；

Fig. 5 be another embodiment of the present invention provides information processing method flow chart；

Fig. 6 be another embodiment of the present invention provides information processing method flow chart；

Fig. 7 be another embodiment of the present invention provides information processing unit structural schematic diagram；

Fig. 8 be another embodiment of the present invention provides communication system schematic diagram；

Fig. 9 be another embodiment of the present invention provides basic matrix deviant schematic diagram.

Specific embodiment

A little explanations are done to some nouns being related in the application below for ease of understanding.

In the application, noun " network " and " system " are often used alternatingly, and " device " and " equipment " is also often used alternatingly, But it will be appreciated by those skilled in the art that its meaning." communication device " can be chip (such as baseband chip or data-signal Handle chip or general-purpose chip etc.), terminal, base station or other network equipments.Terminal is a kind of with communication function Equipment, may include the handheld device with wireless communication function, mobile unit, wearable device, calculate equipment or connection To other processing equipments etc. of radio modem.Terminal can be called different titles in different networks, such as: it uses Family equipment, mobile station, subscriber unit, platform, cellular phone, personal digital assistant, radio modem, wireless communication are set It is standby, handheld device, laptop computer, wireless phone, wireless local loop platform etc..For convenience of description, in the application referred to as eventually End.Base station (base station, BS), alternatively referred to as base station equipment are that one kind is deployed in wireless access network to provide wirelessly The equipment of communication function.The call of base station may be different in different wireless access systems, such as and general shifting Base station is known as node in dynamic communication system (Universal Mobile Telecommunications System, UMTS) network

B (NodeB), and base station in the lte networks be known as evolution node B (evolved NodeB, eNB or ENodeB), the base station in (new radio, NR) network of newly eating dishes without rice or wine is known as transmitting-receiving point (transmission reception Point, TRP) or next generation node B (generation nodeB, gNB) or other various evolvement networks in base station Other calls may also be used.The present invention is not limited thereto.

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention is described.

LDPC code can usually be indicated with parity check matrix H.The parity check matrix H of LDPC code can pass through base figure (base graph) and offset (shift) value obtain.Base figure usually may include m*n matrix element (entry), can use m The matrix form of row n column indicates that the value of matrix element is 0 or 1, the element that intermediate value is 0, sometimes also referred to as neutral element, It indicates that the element can be replaced by the full null matrix (zero matrix) of Z*Z, is worth the element for 1, sometimes also referred to as non-zero Element indicates that the element can be replaced by the cyclic permutation matrices (circulant permutation matrix) of Z*Z.Also It is to say, what each matrix element represented is a full null matrix or a cyclic permutation matrices.10a show one as shown in figure 1 A illustrative m=5, n=27 have each element in the base figure of the LDPC code of QC structure.It should be noted that, in this document, The line number and row number of base figure and matrix are numbered from 0, it is only for explanation, such as the 0th list is facilitated to be shown as base The first row of figure and matrix, the 1st list is shown as the secondary series of Ji Tu and matrix, the 0th row indicates the first row of base figure and matrix, the 1 row is expressed as the second row of Ji Tu and matrix, and so on.

It is understood that line number and row number can also be numbered from 1, then corresponding line number and row number are illustrated herein Line number and row number on the basis of plus 1, for example, if line number or row number are numbered from 1, the 1st Lie Biao Shi Ji Tu and matrix First row, the secondary series of the 2nd Lie Biao Shi Ji Tu and matrix, the 1st row indicate indicate base figure and matrix the first row, the 2nd row table Show the second row of Ji Tu and matrix, and so on.

The element value that the i-th row jth arranges in Ruo Jitu is 1, deviant P_i,j, P_i,jFor the integer more than or equal to 0, The element for then indicating that the value of the i-th row jth column is 1 can be by P_i,jThe cyclic permutation matrices of corresponding Z*Z are replaced, the cyclic permutation Matrix can be by carrying out P for the unit matrix of Z*Z_i,jSecondary cyclic shift to the right obtains.As it can be seen that the member for being 0 by value each in base figure Element is replaced with the full null matrix of Z*Z, and each value is carried out for 1 element using the cyclic permutation matrices of the corresponding Z*Z of its deviant It replaces, then the parity matrix of available LDPC code.Base figure may be used to indicate the position of deviant, the non-zero entry in base figure Element is corresponding with deviant.Z is positive integer, can also be referred to as extension (lifting) factor, can also be referred to as sometimes Lifting size or lifting factor etc., can be according to the size for the code block size and information data that system is supported Determining.It can be seen that the size of parity check matrix H is (m*Z) * (n*Z).For example, spreading factor Z=4, then each neutral element quilt The full 0 matrix 11a replacement of one 4*4 size, if P_2,3=2, then the non-zero element of the 2nd row the 3rd column is by the cyclic permutation matrices of 4*4 11d replacement, the matrix be by 4*4 unit matrix 11b by 2 times to the right cyclic shift obtain, if P_2,4=0, then the 2nd row The non-zero element of 4th column is replaced by unit matrix 11b.It should be noted that be only merely illustrative herein, not as Limitation.

Due to P_i,jIt can be and obtained based on spreading factor Z, the element for being 1 for same position upper value, using difference Spreading factor Z there may be different P_i,j.It is realized to simplify, usual system can also define the basic matrix of m row n column (base matrix), sometimes also referred to as PCM (parity check matrix).Each element and Ji Tu in basic matrix In the position of each element correspond, the position in basic matrix of the neutral element in base figure is constant, can use -1 or null value " null " is indicated, the nonzero element that the i-th row jth train value is 1 in base figure position in basic matrix is constant, is represented by P_i,j, P_i,j It can be the deviant defined relative to a predetermined or specific spreading factor Z.In the embodiment of the present application, also will sometimes Basic matrix is known as the excursion matrix of base figure matrix.

10b show the corresponding basic matrix of base Figure 10 a as shown in figure 1.

It can also include built-in punching (built-in puncture) ratio of p column in the base figure or basic matrix of usual LDPC code Spy's column, p can be 0~2 integer, these column participate in coding, but it encodes corresponding systematic bits and is not sent, then LDPC The code rate of code basic matrix meets R=(n-m)/(n-p).By taking base Figure 10 a as an example, built-in punching bit column are arranged if there is 2, then code rate For (27-5)/(27-2)=0.88, it is similar to 8/9.

The LDPC code used in wireless communication system for QC-LDPC code, verification bit position have double diagonal arrangements or Raptor-like structure can simplify coding, and incremental redundancy mixing is supported to retransmit.It is usually adopted in the decoder of QC-LDPC code With QC-LDPC shift network (QC-LDPC shift network, QSN), Banyan network or Benes network implementations information Cyclic shift.

QC-LDPC code with raptor-like structure, it may include 5 that the matrix size of base figure, which is m row n column, Submatrix A, B, C, D and E, wherein the weight of matrix is determined by the number of nonzero element, and capable weight (row weight) refers to one The number for the nonzero element for including in row, the weight (column weight) of column refer to the number for the nonzero element for including in a column.In Fig. 2 Shown in 200, in which:

Submatrix A is m_ARow n_AThe matrix of column, size can be m_A*n_A, wherein each column corresponds to Z system in LDPC code System bit, systematic bits are sometimes referred to as information bit.

Submatrix B is m_ARow m_AThe square matrix of column, size can be m_A*m_A, each column is corresponding to Z school in LDPC code Test bit.Submatrix B includes the rectangular array (referred to as 3 column are rearranged) that submatrix B ' the He Yilie weight of double diagonal arrangements is 3, The rectangular array that middle column weight is 3 can be located at before submatrix B ', as shown in 20a in Fig. 2；Submatrix B can also include one column or The rectangular array (referred to as single-row rearrangement) that multiple row column weight is 1, for example, a kind of possible implementation such as 20b or 20c institute in Fig. 2 Show.

The matrix for being typically based on submatrix A and B generation is properly termed as kernel matrix, can be used to support the volume of high code rate Code.

Submatrix C is full null matrix, size m_A×m_D。

Submatrix E is unit matrix, size m_D×m_D。

Submatrix D size is m_D×(n_A+m_A), it usually can be used to the check bit for generating low bit- rate.

It is understood that the above-mentioned angle from mathematical definition states base figure, since C is full null matrix, E is single Bit matrix, in one possible implementation, the matrix or submatrix A, B and D structure that can also be made of submatrix A and B At matrix come simplifiedly presentation code or decoding matrix base figure.

Since the structure of submatrix C and E determine that the two-part structure of submatrix A, B and D is the coding and decoding of LDPC code relatively One of influence factor of performance.

When being encoded using the LDPC matrix of raptor-like structure, a kind of possible implementation is, can be first right The matrix of submatrix A and part B, that is, kernel matrix are encoded, and obtain the corresponding check bit of submatrix B, then to whole A matrix is encoded, and the corresponding check bit in the part submatrix E is obtained.Since submatrix B may include double diagonal arrangements The single-row rearrangement of submatrix B ' and one can first obtain the corresponding check bit of double diagonal arrangements in coding, then obtain single-row heavy Arrange corresponding check bit.

A kind of way of example of coding is given below.Assuming that the kernel matrix part that submatrix A and B are constituted is H_core, H_core In remove last line and last column, that is, remove it is single-row rearrangement and the column nonzero element where row, obtained square Battle array part is H_core-dual, H_core-dualIn check bit be partially shown as H_e=[H_e1H_e2],H_e1It is rearranged for 3 column, H_e2It is double diagonal Structure.It is defined according to LDPC code matrix, H_core-dual·[S P_e]^T=0, wherein S is list entries, is made of information bit Vector expression, P_eFor the vector that check bit is constituted, [S P_e]^TIt indicates by list entries S and P_eThe matrix transposition of composition.Therefore It can be first according to list entries S and H_core-dualCalculate H_core-dualCorresponding check bit includes all letters in list entries S Cease bit；Further according to obtaining H_core-dualSingle-row rearrangement pair in submatrix B is calculated in corresponding check bit and list entries S The check bit answered, at this time corresponding all check bits of available submatrix B；Further according to list entries S and submatrix B Corresponding check bit obtains the corresponding check bit of submatrix E using submatrix D code segment, to obtain all information Bit and all check bits, these bits constitute the sequence after coding, that is, a LDPC code sequence.

Optionally, LDPC code coding may also contain truncation (shortening) and punching (puncturing) operation.Quilt Truncated bit and the bit being perforated are not sent.

Wherein, truncate be usually truncated forward since last position of information bit, can in different ways into Row truncates.For example, the bit number s being truncated₀, can be by s last in list entries S₀A bit be set as known bits obtain it is defeated Enter sequence S ', be such as set as 0 perhaps null or some other value, then list entries S ' is compiled by LDPC matrix Code, in another example, it can also can be by (s last in list entries S₀Mod Z) a bit is set as known bits and obtains input sequence S ' is arranged, 0 perhaps null or some other value is such as set as, it will be last in submatrix AColumn are deleted and obtain LDPC matrix H ', using LDPC matrix H ' to list entries S ' encode or submatrix A in it is lastColumn are not involved in list entries The coding of S '.After completing coding, the bit being truncated is not sent.

Wherein, punching, which can be, punches punching bit built-in in list entries or check bit.To verification ratio It is generally also to be punched from last of check bit when spy's punching, it is of course also possible to according to the punching of systemic presupposition Sequence is punched.A kind of possible implementation is first to encode to list entries, the ratio being then perforated as needed Special number p, last p bit or p bit of punching sequential selection according to systemic presupposition in selection check bit, this p is compared Spy does not send.In another possible implementation, the p column for the corresponding matrix of bit that can also determine to be perforated and these P row in column where nonzero element, these row, column are not involved in coding, also just do not generate corresponding check bit.

It should be noted that only illustrating to coding mode here, base figure is provided based on the application and/or basic matrix may be used also To use other coding modes known to those skilled in the art, the application is not limited.Decoding involved in the application, can be with It is to use a variety of decoded modes, such as can use, min-sum (MS) decoded mode can also use belief Propagation decoded mode.MS interpretation method is otherwise referred to as Flood MS interpretation method.For example, initial to list entries Change, and be iterated processing, hard decision detection is carried out after iteration, and verify to hard decision result, if decoding result Meet check equations, then it is successfully decoded, iteration is terminated, and export court verdict.If not meeting check equations, change in maximum Processing is iterated in generation number again, if reaching maximum number of iterations, still verifies failure, then decoding failure.It is understood that It is that, it will be appreciated by those skilled in the art that the principle of MS decoding, this will not be detailed here.

It should be noted that being merely illustrative for decoded mode, for providing base figure and/or group moment based on the application Battle array can also use other decoded modes known to those skilled in the art, and the application does not limit decoded mode.

Usually LDPC code can be obtained by the design to Ji Tu or basic matrix.For example, can be to Ji Tu or base Matrix can determine the UPS upper performance score of LDPC code using the method for Density evolution, and be determined according to the deviant in basic matrix The error floor of LDPC code out.Coding or decoding performance, and drop can be improved by the design to Ji Tu perhaps basic matrix Low error floor.Code length is flexible and changeable in wireless communication system, for example, it may be 2560 bits, 38400 are than top grade, Fig. 3 a Base Figure 30 a example of one LDPC code, Fig. 3 b-1 to Fig. 3 b-10 are each basic matrix examples of base Figure 30 a, can be met a variety of pieces long Performance requirement.For convenience of description and understand, 3a and 3b-1 shows respectively into 3b-10 in top side and the leftmost side in attached drawing Row number and line number are gone out.

Fig. 3 a show base Figure 30 a example an of LDPC code, wherein top line 0 to 67 (i.e. 0 to 67 column) in figure Indicate column number, most one column 0~45 (i.e. 0 to 45 row) of the left side indicate row number, that is, the matrix size of base Figure 30 a is 46 rows 68 column.

In one implementation, the part of submatrix A and submatrix B can regard the kernel matrix of the base figure of LDPC code as Part can be used for high code rate coding.The matrix of 5 rows 27 column is constituted, the matrix of the column of 5 rows 27 as shown in base Figure 10 a can Using the kernel matrix part as base figure.

In one implementation, it in submatrix A may include that punching bit built in one or more columns per page arranges, such as: it can be with Built-in punching bit column are arranged including 2, then after punching, the code rate that kernel matrix can be supported is 0.88.

It wherein, may include that 1 column 3 column are rearranged in submatrix B, i.e. the 0th column (the 22nd column of kernel matrix) column of submatrix B Weight is 3, and the 1st to 3 column (the 23rd to 25 column of kernel matrix) of submatrix B, the double diagonal arrangements of the 0th to 3 behavior, submatrix B is also Column (the 26th column of kernel matrix) including 1 list column weight.

In one implementation, submatrix A can be with correspondence system bit, otherwise referred to as information bit, size m_ARow 22 arranges, wherein m_A=5, it is made of in base Figure 30 a the element of the 0th row to the 4th row and the 0th column to the 21st column；

In one implementation, submatrix B can correspond to check bit, size m_ARow m_AColumn, in base Figure 30 a It is made of the element of the 0th row to the 4th row and the 22nd column to the 26th column.

In order to obtain flexible code rate, submatrix C, submatrix D and son of corresponding size can be added based on kernel matrix Matrix E, to obtain different code rates.Since submatrix C is full null matrix, submatrix is unit matrix, and size is mainly root It is determined according to code rate, structure is relatively fixed.Influence compiling code performance essentially consists in kernel matrix and the part submatrix D.? Ranks are added on the basis of kernel matrix, form the available different code rates in the corresponding part C, D and E.

The columns m of submatrix D_DFor the sum of the columns of submatrix A and B, line number is mainly related to code rate.With base Figure 30 a For, the columns of submatrix D is 27 column.If the code rate that LDPC code is supported is R_m, then the size of its base figure or basic matrix is m row N column, wherein n=n_A/R_m+ p, m=n-n_A=n_A/R_m+p-n_A.If lowest bit rate R_m=1/3, built-in punching columns p=2, with base For Figure 30 a, then n=68, the line number m of m=46, submatrix D_DMaximum can be m-m_A=46-5=41, thus 0≤m_D≤41。

By taking base Figure 30 a as an example, wherein submatrix D may include m of the 5th row into the 41st row in base Figure 30 a_DRow.

In this application, the same row of adjacent rows at most only has 1 nonzero element in Ruo Jitu, then this two row is being each other just It hands over.Adjacent rows are in other column other than part arranges in Ruo Jitu, and same row at most only has 1 nonzero element, then the phase Adjacent two rows are quasi-orthogonal.For example, other other than built-in punching bit column arrange only one non-zero for adjacent rows Element, it may be considered that the adjacent rows are quasi-orthogonal.

The 5th row to the 41st row may include the quasi- orthohormbic structure of multirow and at least two row orthohormbic structures in base Figure 30 a.For example, The 5th row to the 41st row includes at least the row that 15 rows meet quasi- orthohormbic structure in base Figure 30 a, removes in 2 row of arbitrary neighborhood in this 15 row In remaining column other than built-in punching bit column, only one most nonzero element in same row.The 5th row is extremely in base Figure 30 a 41st row can also include that 10 to 26 rows meet the row of orthohormbic structure, that is, in these rows, and same row is most in 2 row of arbitrary neighborhood Also most only one nonzero element in only one more nonzero element, that is, built-in punching bit column.

If m_D=15, LDPC code base figure neutron matrix D size is 15 rows 27 column, can be the 5th row by base Figure 30 a to the The matrix of 19 rows, the 0th column to the 26th column is constituted, and the code rate that corresponding LDPC code is supported is 22/40=0.55, that is, in the code rate Under, the base figure of LDPC code corresponds to the 0th row to the 19th row of base Figure 30 a, and the 0th column to the 41st arrange the matrix part constituted, wherein Submatrix E is the unit matrix of 15 rows 15 column, and submatrix C is the full 0 matrix of 5 rows 15 column；

If m_D=19, LDPC code base figure neutron matrix D size is 19 rows 27 column, can be the 5th row by base Figure 30 a to the The matrix of 23 rows, the 0th column to the 26th column is constituted, and the code rate that corresponding LDPC code is supported is 22/44=1/2, that is, in the code rate Under, the base figure of LDPC code corresponds to the 0th row to the 23rd row of base Figure 30 a, and the 0th column to the 45th arrange the matrix part constituted, wherein Submatrix E is the unit matrix of 19 rows 19 column, and submatrix C is the full 0 matrix of 5 rows 19 column.

And so on, it does not illustrate one by one.

In a kind of design, row/column exchange can be done to Ji Tu and/or basic matrix, that is to say, that capable exchange is carried out, or Person arranges exchange, or row exchange and column exchange.The row/column swap operation does not change row weight and column weight, of nonzero element Also no change has taken place for number.Therefore, the base figure after row/column exchange and/or basic matrix influence system performance limited.That is It is said from whole, the influence to system performance is acceptable, in tolerance, for example, it may be possible to certain scenes or in certain models In enclosing, performance declines within the allowable range, but in certain scenes or certain ranges, performance makes moderate progress, and sees on the whole Performance is influenced little.

For example, the 34th row of base Figure 30 a and the 36th row can be swapped, and the 44th column and the 45th column are handed over It changes.In another example submatrix D includes m in matrix F_DRow, this m_DRow can be exchanged without row, can also will wherein a line or multirow Between carry out capable exchange, submatrix E is still diagonal arrangement, row, column exchange is not done, for example, by the 27th row of matrix F and the 29th row Capable exchange is carried out, submatrix D includes m in matrix F_DRow, submatrix E is still diagonal arrangement.It is understood that Ruo Jitu or base Matrix includes submatrix D, then column are also required to swap in corresponding submatrix D when the column to kernel matrix swap.

The matrix 30b-10 to 30b-80 as shown in Fig. 3 b-1 to Fig. 3 b-10 is respectively setting for multiple basic matrixs of base Figure 30 a Meter.Wherein, position of the nonzero element that the i-th row jth arranges in base Figure 30 a in each matrix of matrix 30b-10 to 30b-80 is constant, Value is deviant V_i,j, neutral element indicates in excursion matrix with -1 or null.Wherein, submatrix D is corresponding in basic matrix Part may include m of the 5th row of any basic matrix into the 45th row_DRow, can be according to the different selection m of code rate_D's Value.It is understood that basic matrix is also phase if base figure is the matrix carried out after space/rank transformation relative to base Figure 30 a Any of ground matrix 30b-10 to 30b-80 is answered to pass through the transformed matrix of row/column.

In a kind of possible design, the basic matrix of LDPC code may include any square shown in Fig. 3 b-1 to Fig. 3 b-10 The 0th to 4 row of battle array 30b-10 to 30b-80 and the 0th to 26 column, at this point, the 0th to 4 of matrix shown in Fig. 3 b-1 to Fig. 3 b-10 the The matrix that row and the 0th to 26 column are constituted can be used as the core of basic matrix.In the design, for the group moment of LDPC code The other parts of battle array, such as Matrix C, the structure of D, the part E do not limit, such as can be using shown in Fig. 3 b-1 to Fig. 3 b-10 Any structure, can also be using other matrix designs.

In alternatively possible design, the basic matrix of LDPC code may include: any shown in Fig. 3 b-1 to Fig. 3 b-10 The matrix that 0th to (m-1) row and 0th of the matrix 30b-10 into 30b-80 are constituted to (n-1) column, wherein 5≤m≤46, m are Integer, 27≤n≤68, n are integer.

In the design, the structure of the other parts of the basic matrix of LDPC code is not limited, such as can be using figure Any structure shown in 3b-1 to Fig. 3 b-10, can also be using other matrix designs.

In another possible design, the basic matrix of LDPC code may include: any shown in Fig. 3 b-1 to Fig. 3 b-10 Part column in the 0th to 4 row of matrix 30b-10 to 30b-80 and the 0th to 26 column.For example, can be to Fig. 3 b-1 to Fig. 3 b- The core (the 0th to 4 row and the 0th to 26 column) of matrix shown in 10 truncates (shortening) and/or punches (puncturing).In one implementation, the basic matrix of LDPC code can not include the bit pair for being truncated and/or punching The column answered.

In the design, the other parts of the basic matrix of LDPC code are not limited, such as be referred to Fig. 3 b-1 extremely Structure shown in Fig. 3 b-10, can also be using other structures.

In another possible design, the basic matrix of LDPC code may include: any shown in Fig. 3 b-1 to Fig. 3 b-10 The matrix that 0th to (m-1) row and 0th part column into (n-1) column of the matrix 30b-10 into 30b-80 are constituted, wherein 5 ≤ m≤46, m are integer, and 27≤n≤68, n are integer.For example, can be to any matrix shown in Fig. 3 b-1 to Fig. 3 b-10 0th to (m-1) row and 0th of the 30b-10 into 30b-80 are arranged to (n-1) to be truncated (shortening) and/or punches (puncturing).In one implementation, the basic matrix of LDPC code can not include the bit pair for being truncated and/or punching The column answered.In the design, the other parts of the basic matrix of LDPC code are not limited, such as are referred to Fig. 3 b-1 to figure Structure shown in 3b-10, can also be using other structures.

In one implementation, the truncation operation, can be and truncate to information bit.For example, with Fig. 3 b-1 to figure For any matrix shown in 3b-10,1 in 0 to 21 column is arranged or multiple row truncates, then the basic matrix of LDPC code can not Including 1 column being truncated in matrix shown in Fig. 3 b-1 to Fig. 3 b-10 or multiple row.For example, if the 21st column are truncated, then LDPC The basic matrix of code may include: the 0th to 20 column and the 22nd to 26 column of any matrix of 30b-10 to 30b-80.For the 0th to 4 For row and the 0th to 20 column and the 22nd to 26 column, at this moment code rate is 7/8.

In another implementation, the punching, which can be, punches check bit.For example, with Fig. 3 b-1 to Fig. 3 b- For any matrix shown in 10,1 in the 22nd to the 26th column is arranged or multiple row is punched.So basic matrix of LDPC code can be with It does not include 1 column being perforated in matrix shown in Fig. 3 b-1 to Fig. 3 b-10 or multiple row.For example, if the 26th column are perforated, then The basic matrix of LDPC code may include: the 0th to 25 column of any matrix of 30b-10 to 30b-80.

Different spreading factor Z is devised, for LDPC code to support the information bit sequence of different length.One kind can In the design of energy, preferable performance can be obtained using different basic matrixs to different spreading factors.For example, spreading factor Z=a ×2^j, 0≤j < 7, a ∈ { 2,3,5,7,9,11,13,15 }.Table 1 be a kind of possible support spreading factor set 2,3,4,5, 6,7,8,9,10,11,12,13,14,15,16,18,20,22,24,26,28,30,32,36,40,44,48,52,56,60,64, 72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384 }, Wherein other than top line and the most left side one arrange, each lattice indicate the value of the correspondingly corresponding Z of value of a and j, example Such as, this column of a=2, and j=1 this line, Z=4, in another example, a=11 and j=3, Z=88.And so on, it repeats no more.

Table 1

Z	A=2	A=3	A=5	A=7	A=9	A=11	A=13	A=15
									J=0	2	3	5	7	9	11	13	15
J=1	4	6	10	14	18	22	26	30
									J=2	8	12	20	28	36	44	52	60
J=3	16	24	40	56	72	88	104	120
									J=4	32	48	80	112	144	176	208	240
J=5	64	96	160	224	288	352
									J=6	128	192	320
J=7	256	384

Since the spreading factor set that base figure is supported can be all spreading factors in table 1, it is also possible to a part of expansion The factor is opened up, for example, can be 24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104, 112,120,128,144,160,176,192,208,224,240,256,288,320,352,384 }, that is, Z be greater than or Equal to 24.In another example can for one in { 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22 } or It is multiple with 24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,1 12,120,128, 144,160,176,192,208,224,240,256,288,320,352,384 } union.It should be noted that being herein only to lift Example.The spreading factor set that base figure is supported can be divided into different subsets according to the value of a.For example, a=2, spreading factor The subset of Z may include one or more of { 2,4,8,16,32,64,128,256 }, in another example, a=3, spreading factor Z's Subset may include one or more of { 3,6,12,24,48,96,192,384 }, and so on.

The spreading factor set that base figure is supported can be divided according to the different values of a, so that it is determined that corresponding group moment out Battle array:

If a=2 or spreading factor Z value are one in { 2,4,8,16,32,64,128,256 }, basic matrix can To include the 0th to 4 row and the 0th to 26 column in matrix 30b-10 or 30b-11, alternatively, basic matrix includes matrix 30b-10 Or the 0th to (m-1) row and the 0th in 30b-11, to (n-1) column, wherein 5≤m≤46, m are integer, 27≤n≤68, n are Integer；Alternatively, basic matrix includes the 0th to (m-1) row and the 0th portion into (n-1) column of matrix 30b-10 or 30b-11 Divide column, wherein 5≤m≤46, m are integer, 27≤n≤68, n are integer.

If a=3 or spreading factor Z value are one in { 3,6,12,24,48,96,192,384 }, basic matrix It may include the 0th to 4 row and the 0th to 26 column in matrix 30b-20 or 30b-21, alternatively, basic matrix includes matrix 30b- The the 0th to (m-1) row and the 0th in 20 or 30b-21 are arranged to (n-1), wherein 5≤m≤46, m are integer, 27≤n≤68, n For integer；Alternatively, basic matrix includes the 0th to (m-1) row and the 0th of matrix 30b-20 or 30b-21 into (n-1) column Part arranges, wherein 5≤m≤46, m are integer, 27≤n≤68, n are integer.

If a=5 or spreading factor Z value are one in { 5,10,20,40,80,160,320 }, basic matrix can To include the 0th to 4 row in matrix 30b-30 and the 0th to 26 column, alternatively, basic matrix include in matrix 30b-30 the 0th to (m-1) row and the 0th is to (n-1) column, wherein 5≤m≤46, m are integer, 27≤n≤68, n are integer；Alternatively, basic matrix packet The the 0th to (m-1) row and the 0th part into (n-1) column for including matrix 30b-30 arrange, wherein 5≤m≤46, m are integer, 27 ≤ n≤68, n are integer.

If a=7 or spreading factor Z value are one in { 7,14,28,56,112,224 }, basic matrix be can wrap The 0th to 4 row and the 0th to 26 column in matrix 30b-40 are included, alternatively, basic matrix includes the 0 to (m-1) in matrix 30b-40 Row and the 0th is to (n-1) column, wherein 5≤m≤46, m are integer, 27≤n≤68, n are integer；Alternatively, basic matrix includes matrix The the 0th to (m-1) row of 30b-40 and the 0th part into (n-1) column arrange, wherein 5≤m≤46, m are integer, 27≤n≤ 68, n be integer.

If a=9 or spreading factor Z value are one in { 9,18,36,72,144,288 }, basic matrix be can wrap The 0th to 4 row and the 0th to 26 column in matrix 30b-50 are included, alternatively, basic matrix includes the 0 to (m-1) in matrix 30b-50 Row and the 0th is to (n-1) column, wherein 5≤m≤46, m are integer, 27≤n≤68, n are integer；Alternatively, basic matrix includes matrix The the 0th to (m-1) row of 30b-50 and the 0th part into (n-1) column arrange, wherein 5≤m≤46, m are integer, 27≤n≤ 68, n be integer.

If a=11 or spreading factor Z value are one in { 11,22,44,88,176,352 }, basic matrix can be with Including the 0th to 4 row and the 0th to 26 column in matrix 30b-60, alternatively, basic matrix includes the 0 to (m- in matrix 30b-60 1) row and the 0th is to (n-1) column, wherein 5≤m≤46, m are integer, 27≤n≤68, n are integer；Alternatively, basic matrix includes square The the 0th to (m-1) row of battle array 30b-60 and the 0th part into (n-1) column arrange, wherein 5≤m≤46, m are integer, 27≤n≤ 68, n be integer.

If a=13 or spreading factor Z value are one in { 13,26,52,104,208 }, basic matrix be can wrap The 0th to 4 row and the 0th to 26 column in matrix 30b-70 are included, alternatively, basic matrix includes the 0 to (m-1) in matrix 30b-70 Row and the 0th is to (n-1) column, wherein 5≤m≤46, m are integer, 27≤n≤68, n are integer；Alternatively, basic matrix includes matrix The the 0th to (m-1) row of 30b-70 and the 0th part into (n-1) column arrange, wherein 5≤m≤46, m are integer, 27≤n≤ 68, n be integer.

If a=15 or spreading factor Z value are one in { 15,30,60,120,240 }, basic matrix be can wrap The 0th to 4 row and the 0th to 26 column in matrix 30b-80 are included, alternatively, basic matrix includes the 0 to (m-1) in matrix 30b-80 Row and the 0th is to (n-1) column, wherein 5≤m≤46, m are integer, 27≤n≤68, n are integer；Alternatively, basic matrix includes matrix The the 0th to (m-1) row of 30b-80 and the 0th part into (n-1) column arrange, wherein 5≤m≤46, m are integer, 27≤n≤ 68, n be integer.

It optionally, can be to a column or multiple row non-zero entry in matrix for the basic matrix that a LDPC code gives The deviant of element increases or decreases offset Offset_s, and system performance is influenced little.The compensation of nonzero element in different lines Value can be the same or different, for example, the one or more columns per page to matrix compensates, the offset of different lines can be identical, It can also be different, the application does not limit.

Influence not referring to very much that the influence to system performance is acceptable to system performance, in tolerance.For example, it may be possible to right Certain scenes or in certain ranges, performance declines within the allowable range, but in certain scenes or certain ranges, property It can make moderate progress, see influences less performance on the whole.

Such as each deviant of the matrix 30b-10 into 30b-80 in any matrix in s column more than or equal to 0 is distinguished Increase or decrease offset Offset_sThe compensation matrix Hs of the available matrix, wherein Offset_sIt is whole more than or equal to 0 Number, 0≤s < 23.The offset Offsets of one or more columns per page may be the same or different.

In performance map shown in Fig. 4, for the performance curve of the LDPC code encoded based on matrix 30b-10 to 30b-80, horizontal seat Mark indicates that the length of information bit sequence, unit are bit, and ordinate is the symbol signal-to-noise ratio (Es/ for reaching corresponding BLER and needing N0), it is 0.01 and 0.0001 two kind of situation that each code rate two lines, which respectively correspond BLER,.Under same code rate, 0.01 is corresponding upper Curve, the 0.0001 corresponding curve under.Each curve smoothing illustrates that matrix all has preferably performance on different masses are long.

Attached drawing 1 to the structure of Fig. 3 a, Fig. 3 b-1 to Fig. 3 b-10 to base figure and basic matrix that LDPC code is related to is opened up Show.In order to absolutely prove the design in embodiment of the present invention for Ji Tu and/or basic matrix, the following table 2-10 to table can be passed through 2-11 is further illustrated.

In a kind of design, base figure described in the 10a in Fig. 1 be 5 rows 27 column and matrix, the parameter being related to can use table 2-10 is indicated.

Table 2-10

In a kind of design, the size of basic matrix shown in 10b is the matrix of 5 rows 27 column in Fig. 1, and the parameter being related to can be with It is indicated with table 2-11.

Table 2-11

In a kind of design, matrix 30b-10 in Fig. 3 b-1 can be indicated with table 3-10.

Table 3-10

In a kind of design, matrix 30b-11 in Fig. 3 b-2 can be indicated with table 3-11.

Table 3-11

In a kind of design, matrix 30b-20 in Fig. 3 b-3 can be indicated with table 3-20.

Table 3-20

In a kind of design, matrix 30b-21 in Fig. 3 b-4 can be indicated with table 3-21.

Table 3-21

In a kind of design, matrix 30b-30 in Fig. 3 b-5 can be indicated with table 3-30.

Table 3-30

In a kind of design, matrix 30b-40 in Fig. 3 b-6 can be indicated with table 3-40.

Table 3-40

In a kind of design, matrix 30b-50 in Fig. 3 b-7 can be indicated with table 3-50.

Table 3-50

In a kind of design, matrix 30b-60 in Fig. 3 b-8 can be indicated with table 3-60.

Table 3-60

In a kind of design, matrix 30b-70 in Fig. 3 b-9 can be indicated with table 3-70.

Table 3-70

In a kind of design, matrix 30b-80 in Fig. 3 b-10 can be indicated with table 3-80.

Table 3-80

It is appreciated that above-mentioned Fig. 1 to Fig. 3 a, Fig. 3 b-1 to Fig. 3 b-10 and table 2-10, table 2-11, table 3-10 to 3-80 It is to help the design understood for Ji Tu and matrix, the form of expression is not limited only to Fig. 1 to Fig. 3 a, Fig. 3 b-1 extremely Fig. 3 b-10 or above-mentioned table 2-10, table 2-11, the form of expression of table 3-10 to 3-80.It can also include other possible deformations.

In one implementation, above-mentioned table 2-10, table 2-11, " row weight " this parameter of table 3-10 into 3-80 can also To omit.How many nonzero element of this line can be known by the column where a line nonzero element, because this journey weight also just obtains Cicada.

In one implementation, for above-mentioned table 2-10, " the nonzero element place of table 2-11, table 3-10 into 3-80 Column " in parameter value, can not also be arranged according to ascending sequence, as long as where parameter value indexes nonzero element Column are just.In addition, for table 2-10, parameter value in " the nonzero element deviant " of table 2-11, table 3-10 to 3-80 is also different The fixed sequence according to column arranges, as long as the ginseng in the parameter value in " nonzero element deviant ", with " column where nonzero element " Numerical value corresponds.

In a kind of design, in order to save memory space, for the relatively-stationary part of structure in Ji Tu or basic matrix, The position of nonzero element can be calculated according to column locations, can not save the position of these nonzero elements.

For example, submatrix E is diagonal matrix, only there is nonzero element on the diagonal, nonzero element on these diagonal lines Deviant be 0, the position of the column where wherein nonzero element can be calculated according to line number, can also be according to row number meter It calculates and obtains the position of row where nonzero element, for the matrix 30b-50 shown in Fig. 3 b-7, for m_eRow, m_e>=4, it is non- The position of column where neutral element is m_e+K_bIt arranges, herein K_b=22, for example, being classified as the 29th where nonzero element in the 7th row Column, deviant 0.

In another example double diagonal arrangement B ' are located at the 0th to 3 row and the 23rd to 25 column in matrix 30b-50 in submatrix B, it can The position of the column where wherein nonzero element to be calculated according to line number, nonzero element institute can also be calculated according to row number Row position, for m_BRow, if 0 < m_B< 3, the position of nonzero element includes m in the row_B+K_bColumn and m_B+K_b+ 1 column, if m_B=0 or m_B=3, the position of nonzero element includes m in the row_B+K_bIt arranges, in submatrix B in double diagonal arrangements The deviant of nonzero element is also 0.It can of course see, in the 23rd to the 25th column, belong to the part of submatrix D, that is, The position of nonzero element and be not fixed in 5th to 47 row, deviant is also not 0, the position of the nonzero element of this part and There is still a need for save for deviant.

In another example in submatrix B in single-row rearrangement, that is, matrix 30b-50 the 26th column, if m_B=4, non-zero in the row The position of element includes m_B+K_bColumn, the deviant of nonzero element is also 0.

If table 3-90 show parameter involved in each row in matrix 30b-50, it is non-into the 25th column that the 0th column can be saved The position of column where neutral element, the position without saving column of the 26th column into the 68th column where nonzero element, that is, not Save the column in the single-row rearrangement of submatrix E and submatrix B where nonzero element:

Table 3-90

If table 3-91 show parameter involved in each row in matrix 3b-50, the 0th column non-zero into the 26th column can be saved The position of column where element without saving the position of column of the 27th column into the 68th column where nonzero element, that is, is not protected Deposit the column in submatrix E where nonzero element:

Table 3-91

In table 3-10 into 3-91, row is optionally that the column where line number and nonzero element indicate non-zero in every row again Position where element, that is, LDPC matrix base figure information.It, can be according to table 3-10 to 3-91's in a kind of design Mode saves the base figure and offset value information of LDPC matrix.

In another design, the base figure of LDPC matrix and the deviant of LDPC matrix can save respectively, LDPC matrix Offset value information can into 3-91, line number and nonzero element deviant be saved by table 3-10, the base figure of LDPC can be adopted It is saved with diversified forms, for example, the matrix form of base Figure 30 a or table the 3-10 line number and non-into table 3-91 as shown in Figure 3a Position where neutral element, alternatively, being considered as 2 system numbers according to 1 and the 0 of every a line or each column for base figure, using 10 systems Or 16 system number preservation can save memory space.By taking base Figure 30 a as an example, every row can save preceding 26 with 4 16 system numbers The position of column or preceding 27 column nonzero element, such as 26 be classified as 11,110,110 01,111,101 10,111,111 00 before the 0th row, then The position that the 0th row nonzero element can be denoted as is 0xF6,0x7D, 0xBF, 0x00, that is, every 8 column form 16 system numbers, For wherein last 2 column or 3 column, 8 can be reached by filling 0 and obtain corresponding 16 system number, other rows and so on, this Place repeats no more.

Optionally, in above-mentioned various designs, the deviant of LDPC can also be saved by other transformed forms, example Such as, in order to facilitate the processing of cyclic shift, difference of the deviant with respect to previous deviant in the column where the deviant can be saved Value.Fig. 9 show the 0th to 4 row in matrix 3b-50 and the deviant after the 0th to 26 rank transformation, exemplified by with the 0th row For initial row, the 0th row offset value is constant, and neutral element is constant in every row, and the deviant of nonzero element is matrix 30b- in every a line The difference of the deviant of same position and previous nonzero element in the deviant column in 50, if in the deviant column Without nonzero element before the row, then deviant is constant.Such as: the 0th column offset value of the 1st row is 179 in matrix 30b-50, and Fig. 9 In the 0th column offset value of the 1st row be the 179 and the 0th arrange in previous deviant 211 difference -32；Because the 0th row the 4th of Fig. 9 is classified as zero Element, the 4th column offset value of the 1st row are identical as the 4th column offset value of the 1st row in matrix 30b-50；The 2nd row the 3rd is classified as zero in Fig. 9 Element, the 1st row the 3rd is classified as nonzero element, therefore the deviant of the 3rd row the 3rd column is the offset of the 3rd row the 3rd of matrix 30b-50 column The difference of value 166 and the deviant 223 of the 1st row the 3rd column, -57, and so on.Limited as space is limited, matrix 30b-50 other Row is not shown in Figure 9, can and so on, it repeats no more.Here the difference of deviant is positive, and indicates to recycle unit matrix It moves to right, difference is negative expression to unit matrix ring shift left.It correspondingly, can be inclined in above-mentioned table 3-10 nonzero element into 3-91 Transformed deviant, that is, the difference of deviant are saved at shifting value.It above are only citing, be not limited thereto.

Fig. 5 gives the design of processing data procedures.The process for handling data can realize with communication device, the communication Device can be base station, terminal or other entities etc., such as communication chip, encoder/decoder etc..

501 parts obtain list entries.

In one implementation, the list entries of coding can be information bit sequence.Information bit sequence is sometimes Referred to as code block (code block), for example, it may be carrying out the output sequence after code block division to transmission block.Optionally, it inputs Following one kind: filling bit or cyclic redundancy check (CRC) bit can be included at least in sequence.In a kind of possible design In, information bit sequence can be filled to obtain list entries, so that the length K=K of list entries_bZ, Z=K/K_b。 The filling of information bit sequence can be realized in code block division, can also be realized after code block division.

In a kind of possible design, it can be used as and be filled out with the Null value that perhaps value is 0 or other systems are arranged The value of bit is filled, so that these filling bits, which can be identified, not to be sent after coding.The present invention is not limited thereto System.

In one implementation, the list entries of decoding can be the soft value sequence of LDPC code.

502 parts carry out coding/decoding to the list entries based on LDPC matrix；The basic matrix of the LDPC matrix can Think any basic matrix in aforementioned exemplary.

In one implementation, LDPC matrix H, which can be, is obtained based on spreading factor Z and basic matrix.

In one implementation, the relevant parameter of LDPC matrix H can be saved, these parameters include with next or more It is a:

A) it for obtaining the parameter in any basic matrix enumerated in above-mentioned each implementation, can obtain based on the parameter Obtain the basic matrix；For example, the parameter may include following one or more: line number, row weight, the position of nonzero element, base Deviant in matrix, nonzero element deviant and corresponding position, offset, spreading factor, base figure, code rate etc..

B) any basic matrix enumerated in above-mentioned each implementation；

C) any basic matrix enumerated in above-mentioned each implementation is by at least one compensated compensation matrix Hs of column；

D) based on the matrix after the basic matrix or its compensation matrix Hs extension；

E) transformed by row/column based on any basic matrix or compensation matrix Hs enumerated in above-mentioned each implementation Basic matrix.

F) based on the matrix after the transformed basic matrix of the row/column or compensation matrix Hs extension.

G) being truncated or being beaten based on any basic matrix or compensation matrix Hs enumerated in above-mentioned each implementation Matrix behind hole.

In one possible implementation, list entries encode based on low-density checksum LDPC matrix/ Decoding, can be during coding/decoding, one or more kinds of progress in the following way:

I. basic matrix, the basic matrix coding/decoding based on acquisition a) are obtained based on above-mentioned；Or the basic matrix based on acquisition Row/column exchange is carried out, the transformed basic matrix coding/decoding of row/column, or the compensation matrix of the basic matrix based on acquisition are based on Carry out coding/decoding, or the compensation matrix Hs of the basic matrix based on acquisition encode into the transformed matrix of property row/column/ Decoding.It here can also include optionally the extension based on basic matrix based on basic matrix or compensation matrix Hs coding/decoding Matrix perhaps the extended matrix coding/decoding of compensation matrix Hs or based on basic matrix or compensation matrix carry out truncate or Matrix coder/decoding after punching；

Ii. based on b), c) d) or e) save basic matrix (save basic matrix H or Hs or preservation based on group moment The battle array H perhaps transformed basic matrix of Hs row/column) coding/decoding or the basic matrix based on the preservation carry out row/column transformation, Based on the transformed basic matrix coding/decoding of row/column.Here, it is based on basic matrix or compensation matrix Hs coding/decoding, it is optional , it can also include the perhaps extended matrix coding/decoding of compensation matrix Hs or based on base of the extended matrix based on basic matrix Matrix or compensation matrix truncated or punched after matrix coder/decoding；

Iii. based on d), f) or g) carry out coding/decoding.

503 parts, the bit sequence after exports coding/decoding.

Fig. 6 gives a kind of design for obtaining processing data procedures, can be used for 502 parts in attached drawing 5.

601 parts obtain spreading factor Z.

In a kind of implementation, spreading factor Z can be determined according to the length K of list entries.For example, it may be supporting Spreading factor set in, find the smallest Z₀As the size of spreading factor Z, and meet KbZ₀≥K.One kind is possible to be set In meter, Kb can be the columns of information bit in the basic matrix of LDPC code.For base Figure 30 a, the wherein columns of information bit Kb_max=22, it is assumed that base Figure 30 a support spreading factor collection be combined into 24,26,28,30,32,36,40,44,48,52,56,60, 64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352, 384}。

If the length K=529 bit of list entries, Z 26, if the length K=5000 bit of list entries, Z are 240.It should be noted that be only for example herein, it is not limited thereto system.

In another example the value of Kb can also change according to the value of K, but it is no more than information bit in the basic matrix of LDPC code Columns.Such as, when K is greater than the first thresholding, Kb=22；When K is less than or equal to the first thresholding, Kb=21.Alternatively, K is greater than first When thresholding, Kb=22；K be less than or equal to the first thresholding, and K be greater than the second thresholding when, Kb=21；K is less than or equal to the When two thresholdings, Kb=20.It should be noted that herein by way of example only, being not limited thereto system.

In addition, based on the basis of any of the above-described implementation, can also to specific message length K, for example, for The rule that 104≤K≤512, Z can be defined according to system is chosen, and K is that other length are selected still according to any of the above-described implementation It takes, e.g., meets KbZ₀The smallest Z of >=K₀, wherein Kb value is 22 either determining according to threshold value.

In a kind of design, when 104≤K≤512, the selection of Z is as shown in table 4-1, other length are according to any of the above-described realization Mode is chosen:

Table 4-1

In another possible design, selection meets KbZ₀The smallest Z of >=K₀, wherein when 104≤K≤512, Kb's Value can also change according to the value of K, for example, as shown in table 4-2；When K is other length, according to any of the above-described implementation It chooses, is determined such as Kb=22 or according to threshold value:

Table 4-2

Wherein, spreading factor Z can be determined by communication device according to the length K of list entries, be also possible to by communicating Device is obtained from other entities (such as processor).

602 parts obtain LDPC matrix based on spreading factor and basic matrix.

Basic matrix is any basic matrix enumerated in aforementioned each embodiment, alternatively, relative to the aforementioned any base enumerated The compensation matrix that at least one column compensate in matrix, or relative to the aforementioned any basic matrix or compensation matrix enumerated And transformation occurs for words and deeds sequence or column sequence converts, or the basic matrix that row sequence and column sequence convert, Base figure includes at least submatrix A and submatrix B.It optionally can also include submatrix C, submatrix D and submatrix E, each section Can be with reference to the description in foregoing embodiments, details are not described herein again.

In one possible implementation, corresponding basic matrix is determined according to spreading factor Z, and according to spreading factor Z replaces the basic matrix to obtain LDPC matrix.

In one implementation, the corresponding relationship of spreading factor and basic matrix, the extension that 601 parts obtain be can store Factor Z determines corresponding basic matrix.

For example, Z is 26, a=13, basic matrix may include the 0th to~4 rows in matrix 30b-70 and the 0th to 26 column, Alternatively, basic matrix include in matrix 30b-70 the 0th~to 4 rows and the 0th to 26 column in part arrange,；Further, or Basic matrix further includes that matrix 0 to m row and the 0th to n arranges, wherein 5≤m≤46, m are integer, 27≤n≤68, n are integer, or Person, basic matrix includes the 0th of matrix 30b-70 arranging to m row and the 0th to n, wherein 5≤m≤46, m are integer, 27≤n≤68, N is row and 27th column column into 67th column of the 5th row of integer 30b-70 into the 45th row.According to spreading factor Z to this Basic matrix is replaced to obtain LDPC matrix.

It should be noted that being here only to be illustrated for matrix shown in a=13, Fig. 3 b-7 with Z=26.Herein only For citing, the invention is not limited thereto.It is appreciated that spreading factor is different, then basic matrix is also different.

In a kind of possible implementation, the corresponding relationship of spreading factor and basic matrix can be as shown in table 5, according to table 5 Determine the corresponding basic matrix index of spreading factor.A kind of possible design, PCM1 can be the matrix 30b- as shown in Fig. 3 b-1 10, or the matrix 30b-11 as shown in Fig. 3 b-2；PCM2 can be the matrix 30b-20 as shown in Fig. 3 b-3, or as schemed Matrix 30b-21 shown in 3b-4；PCM3 can be the matrix 30b-30 as shown in Fig. 3 b-5；PCM4 can be such as Fig. 3 b-6 institute The matrix 30b-40 shown；PCM5 can be the matrix 30b-50 as shown in Fig. 3 b-7；PCM6 can be the square as shown in Fig. 3 b-8 Battle array 30b-60；PCM7 can be the matrix 30b-70 as shown in Fig. 3 b-9；PCM8 can be the matrix 30b- as shown in Fig. 3 b-8 80.It is only for example herein, is not limited thereto system.

Table 5

In a kind of possible design, as shown in table 6, index of set is arranged in 8 spreading factor set in table 5:

Table 6

Each index of set is corresponding with a PCM, such as 1 corresponding PCM1, and 2 corresponding PCM2,3 corresponding PCM3 ..., 8 is corresponding PCM8, and so on.

Optionally, in a kind of possible design, for spreading factor Z, the i-th row jth column element P in basic matrix_i,jIt can To meet following relationships:

Wherein, V_i,jIt can be the deviant of the element of the i-th row jth column in the basic matrix gathered where spreading factor Z, or Person is the deviant of the nonzero element of the i-th row jth column of the basic matrix of the largest extension factor in set where spreading factor Z.

For example, by taking Z is 13 as an example, the element P of the i-th row jth column in basic matrix_i,jMeet

Wherein, V_i,jIt is PCM7, the deviant for the nonzero element that the i-th row jth arranges in matrix 30b-70.For Z=13 Speech, the deviant V for the nonzero element for needing to arrange the i-th row jth in matrix 30b-70_i,jTo Z=13 modulus.

It should be noted that be only for example herein, the invention is not limited thereto.

603 parts carry out coding/decoding to list entries based on LDPC matrix.

In one implementation, the list entries of coding can be information bit sequence.In another implementation, The list entries of decoding can be the soft value sequence of LDPC code, the associated description being referred in Fig. 5.

In one possible implementation, the list entries c={ c of coding₀,c₁,c₂,...,c_K-1, list entries c long Degree is K, the output sequence d={ d that list entries c is obtained after coding₀,d₁,d₂,...,d_N-1, K is the integer greater than 0, K It can be the integral multiple of spreading factor Z.

It wherein include the K in list entries c in output sequence d₀Check bit in a bit and verification sequence w, K₀For Greater than 0, and it is less than or equal to the integer of K, the length of verification sequence w is N-K₀,

Wherein, check bit sequence w and list entries c meets formula (1):

Wherein, c^T=[c₀,c₁,c₂,...,c_K-1]^T, it is the transposed vector of the vector of each bit composition in list entries,For bit each in verification sequence composition vector transposed vector, 0^TFor column vector, wherein institute The value for having element is 0.

Wherein H is the LDPC matrix obtained based on any base figure enumerated in foregoing embodiments or basic matrix, the base figure of H Size is m row n column, can be any base figure enumerated in previous embodiment, for example, base Figure 30 a.

It include the built-in punching column of p column in a kind of design, in the base figure of H, p is the integer more than or equal to 0, in p column It sets the corresponding information bit of punching column not exported, does not also include that the built-in punching of p column arranges corresponding information bit in output sequence, Then K₀=K-pZ, for example, p=2, then K₀The length of=K-2Z, verification sequence w are N+2Z-K.If the built-in punching column of p column Coding is participated in, then K₀The length of=K, verification sequence w are N-K.

Correspondingly, H can arrange for M row (N+pZ) column or M row N, base figure size m=M/Z,

The base figure of LDPC matrix H can be expressed as [H_BG H_BG,EXT], wherein Indicate m_c ×n_cThe full null matrix of size,Indicate n_c×n_cThe unit matrix of size.

In a kind of possible design,For foregoing embodiments base figure neutron Matrix C,For aforementioned each implementation Submatrix E in example, thenA, B and D are respectively foregoing embodiments base figure neutron matrix A, B and D, then m_c =5,0≤n_c≤ 41, H_BGLine number be less than or equal to 46, and be more than or equal to 5, H_BGColumns be equal to 27.

In another possible design, a single-row rearrangement is classified as due to the 26th, and wherein nonzero element is located at the 5th row, ThereforeIt also may include preceding 4 row of the 26th column and for foregoing embodiments neutron Matrix C in foregoing embodiments base figure In preceding 4 row,It also may include the 5th to the 46th row and son of the column of base figure submatrix E and the 26th in foregoing embodiments Last 1 row of Matrix C, then m_c=4,0≤n_c≤42；H_BGFor the part of foregoing embodiments base figure neutron matrix A, B and D composition Remove the matrix that last column is constituted, H_BGLine number be less than or equal to 46, and be more than or equal to 5, H_BGColumns be equal to 26.Optionally, code rate, H are further increased if necessary_BGLine number can be 4 rows, that is, the 0th to 3 row.

Correspondingly, LDPC matrix H can be expressed as H=[H₁H₂].Wherein,

H₁It can be H_BGIn each neutral element be substituted for the full null matrix of Z*Z size, each nonzero element is substituted for Z*Z The cyclic permutation matrices h of size_i,jIt obtains, wherein cyclic permutation matrices h_i,jIt is by the unit matrix ring shift right P of Z*Z size_i,j It obtains, also uses I (P sometimes_i,j) indicate.Wherein, i is line number, and j is row number, P in a kind of possible design_i,j=mod (V_i,j, Z), V_i,jIt is the corresponding spreading factor index of set i of Z_LSThe nonzero element that the i-th row jth arranges in corresponding basic matrix.

H₂It can be H_BG,EXTIn each neutral element be substituted for the full null matrix of Z*Z size, each nonzero element is substituted for The unit matrix of Z*Z size obtains.

Encoder can be encoded and be exported using various ways, below base Figure 30 a to enumerate in previous embodiment And be illustrated for basic matrix 30b-50, wherein Ji Tu and basic matrix line number are up to 46 rows, and columns is up to 68 column, packet Include the built-in punching column of 2 column, for the convenience of description, in the present invention sometimes by line number is maximum and columns also maximum base figure is referred to as complete Integral basis figure, line number is maximum and columns also maximum basic matrix is known as complete basic matrix.

Mode one:

It is encoded based on complete base figure or complete basic matrix, to get check bit as much as possible.At this point, m= 46, n=68, that is, the 0th to the 45th row and the 0th to the 67th column of above-mentioned base Figure 30 a, alternatively, the 0th in basic matrix 30b-50 The deviant arranged to the 45th row and the 0th to the 67th.

Accordingly for LDPC matrix H, M=46Z, if output sequence includes that built-in punching arranges corresponding information ratio Spy, then N=68Z, if output sequence does not include except the corresponding 2Z information bit of built-in punching column, N=66Z.

Can be determined from the output sequence that encoder generates in subsequent processing link need the information bit that sends and Check bit.

Mode two:

It is encoded based on the part row, column of complete base figure or complete basic matrix.It can according to need the code rate of transmission, or Person, information bit and check bit number etc. select row, column to encode from complete base figure or basic matrix.

For example, code rate be 8/9, m=5, n=27, that is, based on the 0th to 4 row in base Figure 30 a and the 0th to 26 arrange Code segment, or the deviant coding arranged based on the 0th to 4 row in basic matrix 30b-50 and the 0th to 26.

Accordingly for LDPC matrix H, M=5Z, if output sequence includes that built-in punching arranges corresponding information ratio Spy, then N=27Z, if output sequence does not include that built-in punching arranges corresponding information bit, N=25Z.

In another example code rate 1/3, m=46, n=68.

As it can be seen that the base figure or basic matrix size of H is 5≤m≤46,27≤n≤68 under this mode, correspondingly for LDPC matrix H, 5Z≤M≤46Z, 27Z≤N≤68Z.

It, can be to single-row heavy in kernel matrix since the 26th is classified as single-row rearrangement in base Figure 30 a in a kind of possible design Column are punched, so that kernel matrix accordingly reduces 1 row and 1 column, so that m is 4, n=26, that is, are based on above-mentioned base Figure 30 a Or the code segment of the 0th to 3 row and the 0th to 25 column in basic matrix 30b-50.This mode is available to arrive higher code Rate.To which Ji Tu or basic matrix size are 4≤m≤46,26≤n≤68, correspondingly for LDPC matrix H, 4Z≤M≤ 46Z, 26Z≤N≤68Z.

It is the inverse process encoded due to decoding, afore-mentioned code can be found in the description of LDPC matrix H and its base figure, basic matrix Method.Can also be decoded based on complete base figure or complete basic matrix when being decoded, alternatively, based on complete base figure or The part row, column of the complete basic matrix of person decodes.

When carrying out coding/decoding to list entries, the LDPC matrix H that basic matrix can be extended according to Z.It is right Each nonzero element P in basic matrix_i,j, determine the cyclic permutation matrices h of Z*Z size_i,j, wherein h_i,jPass through P for unit matrix_i,j The cyclic permutation matrices that secondary cyclic shift obtains, by h_i,jReplace nonzero element P_i,j, the full null matrix of Z*Z size is replaced into group moment Battle array H_BIn neutral element, to obtain parity check matrix H.

In one possible implementation, the basic matrix of LDPC code can be stored in memory, and communication device obtains The corresponding LDPC matrix of spreading factor Z is taken, to carry out coding/decoding to list entries.

In one possible implementation, due to the basic matrix of LDPC code have it is multiple, according to matrix structure preservation can account for With biggish memory space, the base figure of LDPC code can also be saved in memory, progressively or column by column saves each base respectively Then the deviant of nonzero element in matrix obtains LDPC square according to the deviant of Ji Tu and the corresponding basic matrix of spreading factor Z Battle array.

Base figure can indicate the position of each basic matrix nonzero element, according to Ji Tu and the corresponding basic matrix of spreading factor Z Deviant obtains LDPC matrix and is also possible to the position according to each nonzero element and the deviant of the corresponding basic matrix of spreading factor Z Obtain LDPC matrix.

In another possible implementation, saving base figure can be the position for saving wherein nonzero element.Non-zero entry The position of element can be indicated by the row and column where nonzero element, such as the position of the column in every a line where nonzero element, Alternatively, the position of the row in each column where nonzero element.In another possible implementation, saves base figure and be also possible to The position for saving wherein neutral element can also equally be indicated by the row and column where neutral element.Such as neutral element in every a line The position of row in the position of the column at place or every a line where neutral element, then the position of corresponding nonzero element can lead to The position crossed where excluding neutral element obtains.It should be noted that be only for example herein, the present invention is not limited thereto.

It in one possible implementation, can also be according to table 2-10,2-11,3-10 to 3-80 and 3-90 and 3-91 Mode save the deviant of nonzero element in each basic matrix, as the parameter of LDPC matrix, wherein table 2-10,2-11,3-10 Into 3-80 and 3-90 and 3-91, " row weight " column are optional, that is, " row weight " this column can be saved optionally or not protected It deposits.By the column where a line nonzero element, how many nonzero element of this line known, because this journey weight is also just known.? A kind of " non-zero entry in possible implementation, for above-mentioned table 2-10, in 2-11,3-10 to 3-80 and 3-90 and 3-91 Parameter value in column where plain ", can not also arrange according to ascending sequence, as long as parameter value indexes nonzero element The column at place are just." nonzero element offset in addition, for table 2-10, in 2-11,3-10 to 3-80 and 3-90 and 3-91 Parameter value in value " is also not necessarily arranged according to the sequence of column, as long as the parameter value in " nonzero element deviant ", with " non-zero Parameter value in column where element " corresponds, and communication device would know that nonzero element deviant is corresponding which column of which row Nonzero element with regard to property.Such as:

In one possible implementation, the associated description being referred in Fig. 5 protects the relevant parameter of LDPC matrix It deposits.

In one possible implementation, when saving the relevant parameter of LDPC matrix, Fig. 1 can not also be saved to figure All rows of matrix shown in 3a, 3b-1 to 3b-10 or table 2-10,2-11,3-10 to 3-80 and 3-90 and 3-91, can To save parameter indicated by row accordingly in table according to the row for including in basic matrix.For example, above-described embodiment can be saved Described in LDPC matrix basic matrix included by the square that is constituted of the matrix that is constituted of row and column or the row and column Relevant parameter involved in battle array.

For example, if basic matrix include the 0th to 4 row in 30b-10 to 30b-80 and 3-90 and any matrix of 3-91 with And the 0th to 26 column then can save the 0th to 4 row and the 0th to 26 the constituted matrix of column, and/or save the 0th to 4 The relevant parameter of row and the 0th to 26 the constituted matrix of column, is referred to institute in table 3-10 to 3-80 and 3-90 and 3-91 The parameter shown and the description of above-mentioned part.

If basic matrix include in 30b-10 to 30b-80 and 3-90 and any matrix of 3-91 the 0th to (m-1) row and 0th arranges to (n-1), wherein 5≤m≤46, m are integer, 27≤n≤68, n are integer, then, can save the described 0th to (m-1) Row and the 0th matrix constituted to (n-1) column, and/or preservation the described 0th to (m-1) row and the 0th arrange institute to (n-1) The relevant parameter of the matrix of composition is referred to parameter shown in table 3-10 to 3-80 and 3-90 and 3-91 and above-mentioned portion The description divided.

It in one possible implementation, can be in table 3-10 to 3-80 and 3-90 and 3-91 either table at least one Each deviant more than or equal to 0 that position s is indicated in a " column where nonzero element " increases or decreases offset Offset_s。

It in one possible implementation, can be to " non-zero in table 3-10 to 3-80 and 3-90 and 3-91 either table Element offset value " saves deviant after transformation as in the foregoing embodiment, deviant as shown in Figure 9.

In another design, the base figure of LDPC matrix and the deviant of LDPC matrix can save respectively, LDPC matrix Offset value information can into 3-91, line number and nonzero element deviant be saved by table 3-10, the base figure of LDPC can be adopted It is saved with diversified forms, for example, the matrix form of base Figure 30 a or table the 3-10 line number and non-into table 3-91 as shown in Figure 3a Position where neutral element, alternatively, being considered as 2 system numbers according to 1 and the 0 of every a line or each column for base figure, using 10 systems Or 16 system number preservation can save memory space.By taking base Figure 30 a as an example, every row can save preceding 26 with 4 16 system numbers The position of column or preceding 27 column nonzero element, such as 26 be classified as 11,110,110 01,111,101 10,111,111 00 before the 0th row, then The position that the 0th row nonzero element can be denoted as is 0xF6,0x7D, 0xBF, 0x00, that is, every 8 column form 16 system numbers, For wherein last 2 column or 3 column, 8 can be reached by filling 0 and obtain corresponding 16 system number, other rows and so on, this Place repeats no more.It should be noted that only illustrate herein, it is not limited thereto system.

By taking Fig. 1 as an example, basic matrix H is determined_BAfterwards, the 0th to 3 row and of list entries and basic matrix can be first passed through 0 to the 25th column, that is, H_core-dualPart obtains the corresponding check bit of the 22nd to 25 column；Further according to list entries and H_core-dualCorresponding check bit obtains the 26th column, that is, the corresponding check bit of single-row rearrangement；Then according to list entries And the 22nd to 26 the corresponding check bit of column and the corresponding code segment of submatrix D obtain the corresponding verification in the part submatrix E Bit, to complete to encode.The cataloged procedure of LDPC code can be described with reference to aforementioned implementation, and details are not described herein again.

In one possible implementation, LDPC matrix H can before encoding according to spreading factor Z to spreading factor into Row expansion, that is, corresponding cyclic permutation matrices are replaced according to deviant；

In another possible implementation, when being encoded according to the corresponding nonzero element of bit encoded Position obtains corresponding deviant, replaces corresponding cyclic permutation matrices to the nonzero element and handles；

In another possible implementation, LDPC matrix H is not unfolded directly in use, and according to deviant Connection relationship between calculating equivalent matrice ranks is treated the bit in list entries and is handled；

In another possible implementation method, it can be encoded using QSN method, to each nonzero element to be processed, According to the deviant of the nonzero element, corresponding bit section to be encoded is done into shifting function；Later, displacement was done to all Bit section after operation directly carries out encoding operation.

In another possible implementation, the generator matrix G of LDPC matrix H can also be saved, then list entries c and Output sequence d meets formula (2):

D=cG (2)

It is wherein unit matrix I on the right side of H ' if converting LDPC matrix H procession to obtain H ', left side matrix is P then H ' =[P I], then wherein generator matrix G meets following formula (3):

G=[I P^T] (3)

It should be noted that above-mentioned is citing, the present invention is not limited thereto.

Optionally, in a communications system, LDPC code is obtained after above method coding can be used.After obtaining LDPC code, communication Device can also carry out following one or more operations: carry out rate-matched to LDPC code；According to interleaving scheme to rate-matched LDPC code afterwards is interleaved；The LDPC code after intertexture is modulated according to modulation scheme to obtain bit sequence X；Send bit Sequence X.

Decoding is the inverse process of coding, and the basic matrix that decoding process uses has phase with the basic matrix that cataloged procedure uses Same feature.The cataloged procedure of LDPC code can be described with reference to aforementioned implementation, and details are not described herein again.In a kind of implementation In, before decoding, communication device can also carry out following one or more operations: receive the letter comprising encoding based on LDPC Number, signal is demodulated, deinterleaves and solves rate-matched and obtain the soft value sequence of LDPC code, to the soft value sequence of LDPC code It is decoded.

Preservation involved in the application, what can be referred to is stored in one or more memory.It is one or Multiple memories can be individual setting, be also possible to be integrated in encoder or decoder, processor, chip, communication dress It sets or terminal.One or more of memories are also possible to a part and are separately provided, a part be integrated in decoder, In processor, chip, communication device or terminal, the type of memory can be any form of storage medium, and the application is simultaneously Not to this restriction.

Corresponding to Fig. 5, the design for the data handling procedure of Fig. 6 provided, the embodiment of the invention also provides corresponding logical T unit, the communication device include the module for executing each partial response in Fig. 5 or Fig. 6.The module can be soft Part, is also possible to hardware or software and hardware combines.Such as module may include memory, electronic equipment, the ministry of electronics industry Part, logic circuit etc. or any of the above-described combination.Fig. 7 gives a kind of structural schematic diagram of communication device 700, and device 700 can be used In realizing method described in above method embodiment, the explanation in above method embodiment may refer to.The communication device 700 can be chip, base station, terminal or other network equipments.

The communication device 700 includes one or more processors 701.The processor 701 can be general processor Or application specific processor etc..Such as it can be baseband processor or central processing unit.Baseband processor can be used for communication protocols View and communication data handled, central processing unit can be used for communication device (e.g., base station, terminal or chip etc.) into Row control, executes software program, the data of processing software program.

It is a kind of it is possible be related to, as one or more module in 5, Fig. 6 may be by one or more processing Device is realized or one or more processor and memory are realized.

In a kind of possible design, the communication device 700 includes one or more processors 701, and described one A or multiple processors 701 can realize that the function of above-mentioned coding/decoding, such as communication device can be encoder or decoding Device.In alternatively possible design, processor 701 can also realize other function in addition to realizing coding/decoding function.

The communication device 700 is based on LDPC matrix and carries out coding/decoding to list entries；The basic matrix of the LDPC matrix Can for any basic matrix in aforementioned exemplary or relative to the aforementioned any basic matrix enumerated and words and deeds sequence occur transformation, Perhaps column sequence converts or row sequence is converted with column sequence basic matrix, or enumerated based on aforementioned Any basic matrix truncates or the basic matrix of punching, or enumerates the matrix after any basic matrix extends based on aforementioned.About The processing of coding or/decoding may refer to the description of Fig. 5 and Fig. 6 relevant portion, and details are not described herein.

Optionally, in a kind of design, processor 701 may include that instruction 703 (is referred to as code or journey sometimes Sequence), described instruction can be run on the processor, be described in above-described embodiment so that the communication device 700 executes Method.In another possible design, communication device 700 also may include circuit, and aforementioned reality may be implemented in the circuit Apply the coding/decoding function in example.

It optionally, may include one or more memories 702 in the communication device 700, thereon in a kind of design There is instruction 704, described instruction can be run on the processor, so that the communication device 700 executes above method reality Apply method described in example.

Optionally, data can also be stored in the memory.Also can store in optional processor instruction and/or Data.The processor and memory can be separately provided, and also can integrate together.

Optionally, " preservation " described in above-described embodiment, which can be, saves in memory 702, is also possible to be stored in it In the memory or storage equipment of his peripheral hardware.

For example, one or more storages 702 can store the parameter with the above-mentioned LDPC matrix correlation enumerated, for example, base The parameter of matrix correlation, such as deviant, base figure expand to matrix, each row in basic matrix, spreading factor, base based on base figure Matrix expands to matrix etc. based on basic matrix.It specifically may refer to the associated description of the above-mentioned part Fig. 5.

Optionally, the communication device 700 can also include transceiver 705 and antenna 706.The processor 701 can With referred to as processing unit, communication device (terminal or base station) is controlled.It is single that the transceiver 505 is properly termed as transmitting-receiving Member, transceiver, transmission circuit or transceiver etc., for realizing the transmission-receiving function of communication device by antenna 506

Optionally, the communication device 700 can also include for generating the device of transmission block CRC, for code block segmentation With the device of CRC check, the interleaver for intertexture, the device for rate-matched or for the modulator of modulation treatment Deng.The function of these devices can be realized by one or more processors 701.

Optionally, the communication device 700 can also include the demodulator for demodulation operation, the solution for deinterleaving Interleaver, the device for solving rate-matched or for code block cascade and device of CRC check etc..One can be passed through Or multiple processors 701 realize the function of these devices.

Fig. 8 gives a kind of schematic diagram of communication system 800, includes that communication equipment 80 and communication are set in communication system 800 Standby 81, wherein information data sends and receivees between communication equipment 80 and communication equipment 81.Communication equipment 80 and 81 can be The communication assembling device 700 or communication equipment respectively include communication device 700 for 80 and 81, receive to information data And/or it sends.In one example, communication equipment 80 can be terminal, and corresponding communication equipment 81 can be base station；Another In a example, communication equipment 80 is base station, and corresponding communication equipment 81 can be terminal.

Art technology is any it will also be appreciated that the various illustrative components, blocks that the embodiment of the present invention is listed (illustrative logical block) and step (step) can by electronic hardware, computer software, or both knot Conjunction is realized.Such function is that the design for depending on specific application and whole system is realized by hardware or software It is required that.Those skilled in the art can be used various methods and realize the function, but this for every kind of specific application Kind, which is realized, is understood not to the range beyond protection of the embodiment of the present invention.

Technology described herein can be realized by various modes.For example, these technologies can with hardware, software or The mode of person's combination of hardware is realized.For hardware realization, for communication device (for example, base station, terminal, network entity or Chip) at execute the processing units of these technologies, may be implemented in one or more general processors, digital signal processor (DSP), digital signal processing device (DSPD), specific integrated circuit (ASIC), programmable logic device (PLD), scene can compile Journey gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components or above-mentioned In what combination.General processor can be microprocessor, and optionally, which may be any traditional processing Device, controller, microcontroller or state machine.Processor can also be realized by the combination of computing device, such as digital signal Processor and microprocessor, multi-microprocessor, one or more microprocessors combine a digital signal processor core, or appoint What its similar configuration is realized.

The finger that the step of method described in the embodiment of the present invention or algorithm can be directly embedded into hardware, processor executes Order or the combination of the two.Memory can be RAM memory, flash memory, ROM memory, eprom memory, EEPROM and deposit Other any form of storaging mediums in reservoir, register, hard disk, moveable magnetic disc, CD-ROM or this field.For example, storage Device can be connect with processor, so that processor can read information from memory, and can be to memory stored and written information. Optionally, memory can also be integrated into the processor.Processor and memory can be set in ASIC, and ASIC can be set In UE.Optionally, processor and memory also can be set in the different components in UE.

Through the above description of the embodiments, it is apparent to those skilled in the art that the present invention can be with It is realized with hardware realization or firmware realization or their combination mode.When using software program realize when, can all or It partly realizes in the form of a computer program product, the computer program product includes one or more computer instructions. When loading on computers and executing the computer instruction, entirely or partly generate according to stream described in the embodiment of the present invention Journey or function.When being realized using software program, above-mentioned function can also be stored in computer-readable medium or as meter One or more instructions or code on calculation machine readable medium are transmitted.The computer can be general purpose computer, dedicated Computer, computer network or other programmable devices.The computer instruction can store in computer-readable storage medium In matter, or transmit from a computer readable storage medium to another computer readable storage medium.Computer-readable medium Including computer storage media and communication media, wherein communication media includes convenient for transmitting and counting from a place to another place Any medium of calculation machine program.Storage medium can be any usable medium that computer can access.As example but unlimited In: computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storages, magnetic disk storage medium or Other magnetic storage apparatus or can be used in carry or store have instruction or data structure form desired program code simultaneously It can be by any other medium of computer access.Furthermore.Any connection appropriate can become computer-readable medium.Example Such as, if software is using coaxial cable, optical fiber cable, twisted pair, Digital Subscriber Line (DSL) or such as infrared ray, wirelessly What the wireless technology of electricity and microwave etc was transmitted from website, server or other remote sources, then coaxial cable, optical fiber light The wireless technology of cable, twisted pair, DSL or such as infrared ray, wireless and microwave etc includes in the definition of affiliated medium.Such as Used in the present invention, disk (Disk) and dish (disc) include compression optical disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and Blu-ray Disc, the usually magnetic replicate data of which disk, and dish is then with laser come optical replicate data.On The combination in face should also be as including within the protection scope of computer-readable medium.

It should be noted that "/" in the application indicate and/or, such as " coding/decoding (coding and/or decoding) is The coding of finger or decoding or coding and decoding.

In short, being not intended to limit of the invention the foregoing is merely the preferred embodiment of technical solution of the present invention Protection scope.All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should be included in Within protection scope of the present invention.

Claims (34)

1. a kind of coding method characterized by comprising

Sequence after being encoded based on basic matrix and spreading factor Z to list entries, wherein the basic matrix includes more A nonzero element (i, j), wherein i is line number, and j is row number, and the nonzero element (i, j) corresponds to the cyclic permutation of Z*Z size Matrix I (P_i,j), the cyclic permutation matrices I (P_i,j) correspond to the unit matrix P to the right of Z*Z size_i,jAfter secondary cyclic shift Matrix, P_i,j=mod (V_i,j, Z), the nonzero element (i, j) and its corresponding value V_i,jIt is as follows:

I=0, j=0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23, V_i,jRespectively 211, 198,188,186,219,4,29,144,116,216,115,233,144,95,216,73,261,1,0；

I=1, j=0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24, V_i,jRespectively 179, 162,223,256,160,76,202,117,109,15,72,152,158,147,156,119,0,0；

I=2, j=0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25, V_i,jRespectively 258,167, 220,133,243,202,218,63,0,3,74,229,0,216,269,200,234,0,0；

I=3, j=0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25, V_i,jRespectively 187, 145,166,108,82,132,197,41,162,57,36,115,242,165,0,113,108,1,0；

I=4, j=0,1,26, V_i,jRespectively 246,235,0.

2. wherein m and n is whole the method according to claim 1, wherein the basic matrix includes m row n column Number, 5≤m≤46,27≤n≤68.

3. according to the method described in claim 2, it is characterized in that, the basic matrix further include following nonzero element (i, j) and Its corresponding value V_i,j:

I=5, j=0,1,3,12,16,21,22,27, V_i,jRespectively 261,181,72,283,254,79,144,0；

I=6, j=0,6,10,11,13,17,18,20,28, V_i,jRespectively 80,144,169,90,59,177,151,108,0；

I=7, j=0,1,4,7,8,14,29, V_i,jRespectively 169,189,154,184,104,164,0；

I=8, j=0,1,3,12,16,19,21,22,24,30, V_i,jRespectively 54,0,252,41,98,46,15,230,54, 0；

I=9, j=0,1,10,11,13,17,18,20,31, V_i,jRespectively 162,159,93,134,45,132,76,209,0；

I=10, j=1,2,4,7,8,14,32, V_i,jRespectively 178,1,28,267,234,201,0；

I=11, j=0,1,12,16,21,22,23,33, V_i,jRespectively 55,23,274,181,273,39,26,0；

I=12, j=0,1,10,11,13,18,34, V_i,jRespectively 225,162,244,151,238,243,0；

I=13, j=0,3,7,20,23,35, V_i,jRespectively 231,0,216,47,36,0；

I=14, j=0,12,15,16,17,21,36, V_i,jRespectively 0,186,253,16,0,79,0；

I=15, j=0,1,10,13,18,25,37, V_i,jRespectively 170,0,183,108,68,64,0；

I=16, j=1,3,11,20,22,38, V_i,jRespectively 270,13,99,54,0,0；

I=17, j=0,14,16,17,21,39, V_i,jRespectively 153,137,0,0,162,0；

I=18, j=1,12,13,18,19,40, V_i,jRespectively 161,151,0,241,144,0；

I=19, j=0,1,7,8,10,41, V_i,jRespectively 0,0,118,144,0,0；

I=20, j=0,3,9,11,22,42, V_i,jRespectively 265,81,90,144,228,0；

I=21, j=1,5,16,20,21,43, V_i,jRespectively 64,46,266,9,18,0；

I=22, j=0,12,13,17,44, V_i,jRespectively 72,189,72,257,0；

I=23, j=1,2,10,18,45, V_i,jRespectively 180,0,0,165,0；

I=24, j=0,3,4,11,22,46, V_i,jRespectively 236,199,0,266,0,0；

I=25, j=1,6,7,14,47, V_i,jRespectively 205,0,0,183,0；

I=26, j=0,2,4,15,48, V_i,jRespectively 0,0,0,277,0；

I=27, j=1,6,8,49, V_i,jRespectively 45,36,72,0；

I=28, j=0,4,19,21,50, V_i,jRespectively 275,0,155,62,0；

I=29, j=1,14,18,25,51, V_i,jRespectively 0,180,0,42,0；

I=30, j=0,10,13,24,52, V_i,jRespectively 0,90,252,173,0；

I=31, j=1,7,22,25,53, V_i,jRespectively 144,144,166,19,0；

I=32, j=0,12,14,24,54, V_i,jRespectively 0,211,36,162,0；

I=33, j=1,2,11,21,55, V_i,jRespectively 0,0,76,18,0；

I=34, j=0,7,15,17,56, V_i,jRespectively 197,0,108,0,0；

I=35, j=1,6,12,22,57, V_i,jRespectively 199,278,0,205,0；

I=36, j=0,14,15,18,58, V_i,jRespectively 216,16,0,0,0；

I=37, j=1,13,23,59, V_i,jRespectively 72,144,0,0；

I=38, j=0,9,10,12,60, V_i,jRespectively 190,0,0,0,0；

I=39, j=1,3,7,19,61, V_i,jRespectively 153,0,165,117,0；

I=40, j=0,8,17,62, V_i,jRespectively 216,144,2,0；

I=41, j=1,3,9,18,63, V_i,jRespectively 0,0,0,183,0；

I=42, j=0,4,24,64, V_i,jRespectively 27,0,35,0；

I=43, j=1,16,18,25,65, V_i,jRespectively 52,243,0,270,0；

I=44, j=0,7,9,22,66, V_i,jRespectively 18,0,0,57,0；

I=45, j=1,6,10,67, V_i,jRespectively 168,0,144,0.

4. method according to any one of claims 1 to 3, which is characterized in that further include multiple null elements in the basic matrix Element, each neutral element correspond to the null matrix of Z*Z size.

5. method according to any one of claims 1 to 3, which is characterized in that the Z is in 9,18,36,72,144,288 One of.

6. according to the method described in claim 5, it is characterized in that, the basic matrix and spreading factor Z of being based on is to list entries Sequence after being encoded, comprising:

LDPC matrix H is obtained based on the spreading factor Z and the basic matrix；

Sequence after being encoded according to the LDPC matrix H to the list entries.

7. according to the method described in claim 6, the list entries is expressed as c={ c₀,c₁,c₂,...,c_K-1, the coding Sequence afterwards is expressed as d={ d₀,d₁,d₂,...,d_N-1, wherein K and N is positive integer；

The sequence d includes the check bit in the list entries c in K-2Z bit and verification sequence w, the verification Sequence is expressed as w={ w₀,w₁,w₂,...,w_N+2Z-K-1, wherein K is the integral multiple of Z.

8. according to the method described in claim 7, K=22Z, N=66Z.

9. according to the method described in claim 8, the verification sequence w and list entries c meets

Wherein, c^T=[c₀,c₁,c₂,...,c_K-1]^T, w^T=[w₀,w₁,w₂,...,w_N+2·Z-K-1]^T, 0^TFor column vector, all members The value of element is 0.

10. according to the method described in claim 5, described encode list entries based on basic matrix and spreading factor Z Code after sequence include:

Transformation matrix based on the spreading factor Z and the basic matrix obtains LDPC matrix H,

Sequence after being encoded according to the LDPC matrix H to the list entries, wherein the basic matrix Transformation matrix corresponds to matrix of the basic matrix after space exchanges or arranges exchange or row exchange and column exchange.

11. method according to any one of claims 1 to 3, the list entries is expressed as c={ c₀,c₁,c₂,..., c_K-1, the sequence after the coding is expressed as d={ d₀,d₁,d₂,...,d_N-1, wherein K and N is positive integer；

The sequence d includes the check bit in the list entries c in K-2Z bit and verification sequence w, the verification Sequence is expressed as w={ w₀,w₁,w₂,...,w_N+2Z-K-1, wherein K is the integral multiple of Z.

12. according to the method for claim 11, K=22Z, N=66Z.

13. according to the method for claim 11, the verification sequence w and list entries c meets

Wherein, c^T=[c₀,c₁,c₂,...,c_K-1]^T, w^T=[w₀,w₁,w₂,...,w_N+2·Z-K-1]^T, 0^TFor column vector, all members The value of element is 0.

14. a kind of encoder, for executing such as the described in any item methods of claim 1 to 13.

15. a kind of communication device, which is characterized in that the communication device includes one or more processors, one or more A processor is used for

Sequence after being encoded based on basic matrix and spreading factor Z to list entries, wherein the basic matrix includes more A nonzero element (i, j), wherein i is line number, and j is row number, and the nonzero element (i, j) corresponds to the cyclic permutation of Z*Z size Matrix I (P_i,j), the cyclic permutation matrices I (P_i,j) correspond to the unit matrix P to the right of Z*Z size_i,jAfter secondary cyclic shift Matrix, P_i,j=mod (V_i,j, Z), the nonzero element (i, j) and its corresponding value V_i,jIt is as follows:

I=0, j=0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23, V_i,jRespectively 211, 198,188,186,219,4,29,144,116,216,115,233,144,95,216,73,261,1,0；

I=1, j=0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24, V_i,jRespectively 179, 162,223,256,160,76,202,117,109,15,72,152,158,147,156,119,0,0；

I=2, j=0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25, V_i,jRespectively 258,167, 220,133,243,202,218,63,0,3,74,229,0,216,269,200,234,0,0；

I=3, j=0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25, V_i,jRespectively 187, 145,166,108,82,132,197,41,162,57,36,115,242,165,0,113,108,1,0；

I=4, j=0,1,26, V_i,jRespectively 246,235,0.

16. communication device according to claim 15, the basic matrix includes m row n column, and wherein m and n is integer, 5≤ M≤46,27≤n≤68.

17. communication device according to claim 16, which is characterized in that the basic matrix further includes following nonzero element (i, j) and its corresponding value V_i,j:

I=5, j=0,1,3,12,16,21,22,27, V_i,jRespectively 261,181,72,283,254,79,144,0；

I=6, j=0,6,10,11,13,17,18,20,28, V_i,jRespectively 80,144,169,90,59,177,151,108,0；

I=7, j=0,1,4,7,8,14,29, V_i,jRespectively 169,189,154,184,104,164,0；

I=8, j=0,1,3,12,16,19,21,22,24,30, V_i,jRespectively 54,0,252,41,98,46,15,230,54, 0；

I=9, j=0,1,10,11,13,17,18,20,31, V_i,jRespectively 162,159,93,134,45,132,76,209,0；

I=10, j=1,2,4,7,8,14,32, V_i,jRespectively 178,1,28,267,234,201,0；

I=11, j=0,1,12,16,21,22,23,33, V_i,jRespectively 55,23,274,181,273,39,26,0；

I=12, j=0,1,10,11,13,18,34, V_i,jRespectively 225,162,244,151,238,243,0；

I=13, j=0,3,7,20,23,35, V_i,jRespectively 231,0,216,47,36,0；

I=14, j=0,12,15,16,17,21,36, V_i,jRespectively 0,186,253,16,0,79,0；

I=15, j=0,1,10,13,18,25,37, V_i,jRespectively 170,0,183,108,68,64,0；

I=16, j=1,3,11,20,22,38, V_i,jRespectively 270,13,99,54,0,0；

I=17, j=0,14,16,17,21,39, V_i,jRespectively 153,137,0,0,162,0；

I=18, j=1,12,13,18,19,40, V_i,jRespectively 161,151,0,241,144,0；

I=19, j=0,1,7,8,10,41, V_i,jRespectively 0,0,118,144,0,0；

I=20, j=0,3,9,11,22,42, V_i,jRespectively 265,81,90,144,228,0；

I=21, j=1,5,16,20,21,43, V_i,jRespectively 64,46,266,9,18,0；

I=22, j=0,12,13,17,44, V_i,jRespectively 72,189,72,257,0；

I=23, j=1,2,10,18,45, V_i,jRespectively 180,0,0,165,0；

I=24, j=0,3,4,11,22,46, V_i,jRespectively 236,199,0,266,0,0；

I=25, j=1,6,7,14,47, V_i,jRespectively 205,0,0,183,0；

I=26, j=0,2,4,15,48, V_i,jRespectively 0,0,0,277,0；

I=27, j=1,6,8,49, V_i,jRespectively 45,36,72,0；

I=28, j=0,4,19,21,50, V_i,jRespectively 275,0,155,62,0；

I=29, j=1,14,18,25,51, V_i,jRespectively 0,180,0,42,0；

I=30, j=0,10,13,24,52, V_i,jRespectively 0,90,252,173,0；

I=31, j=1,7,22,25,53, V_i,jRespectively 144,144,166,19,0；

I=32, j=0,12,14,24,54, V_i,jRespectively 0,211,36,162,0；

I=33, j=1,2,11,21,55, V_i,jRespectively 0,0,76,18,0；

I=34, j=0,7,15,17,56, V_i,jRespectively 197,0,108,0,0；

I=35, j=1,6,12,22,57, V_i,jRespectively 199,278,0,205,0；

I=36, j=0,14,15,18,58, V_i,jRespectively 216,16,0,0,0；

I=37, j=1,13,23,59, V_i,jRespectively 72,144,0,0；

I=38, j=0,9,10,12,60, V_i,jRespectively 190,0,0,0,0；

I=39, j=1,3,7,19,61, V_i,jRespectively 153,0,165,117,0；

I=40, j=0,8,17,62, V_i,jRespectively 216,144,2,0；

I=41, j=1,3,9,18,63, V_i,jRespectively 0,0,0,183,0；

I=42, j=0,4,24,64, V_i,jRespectively 27,0,35,0；

I=43, j=1,16,18,25,65, V_i,jRespectively 52,243,0,270,0；

I=44, j=0,7,9,22,66, V_i,jRespectively 18,0,0,57,0；

I=45, j=1,6,10,67, V_i,jRespectively 168,0,144,0.

It further include multiple neutral elements in the basic matrix, often 18. 5 to 17 described in any item communication devices according to claim 1 One neutral element corresponds to the null matrix of Z*Z size.

19. 5 to 17 described in any item communication devices according to claim 1, the Z is it in 9,18,36,72,144,288 One.

20. communication device according to claim 19, which is characterized in that one or more of processors are specifically used for:

LDPC matrix H is obtained based on the spreading factor Z and the basic matrix；

Sequence after being encoded according to the LDPC matrix H to the list entries.

21. communication device according to claim 20, the list entries is expressed as c={ c₀,c₁,c₂,...,c_K-1, institute Sequence after stating coding is expressed as d={ d₀,d₁,d₂,...,d_N-1, wherein K and N is positive integer；

The sequence d includes the check bit in the list entries c in K-2Z bit and verification sequence w, the verification Sequence is expressed as w={ w₀,w₁,w₂,...,w_N+2Z-K-1, wherein K is the integral multiple of Z.

22. communication device according to claim 21, K=22Z, N=66Z.

23. communication device according to claim 22, the verification sequence w and the list entries c meet formula

Wherein, c^T=[c₀,c₁,c₂,...,c_K-1]^T, w^T=[w₀,w₁,w₂,...,w_N+2·Z-K-1]^T, 0^TFor column vector, all members The value of element is 0.

24. communication device according to claim 23 further includes memory, following one or more for storing: group moment Battle array, parameter related with basic matrix, base figure, the deviant of the related parameter of base figure or nonzero element.

25. communication device according to claim 24 further includes transceiver, the transceiver includes the volume for sending The signal of sequence after code.

26. further including following one or more according to the described in any item communication devices of claim 25:

For generating the device of transmission block CRC, used for the device of code block segmentation and CRC check for the device of rate-matched Interleaver in intertexture and the modulator for modulation treatment.

27. communication device according to claim 19, one or more of processors are specifically used for:

Transformation matrix based on the spreading factor Z and the basic matrix obtains LDPC matrix H,

According to the LDPC matrix H to the sequence after being encoded to the list entries, wherein the basic matrix Transformation matrix correspond to the basic matrix through space exchange or arrange exchange or row exchange and column exchange after matrix.

28. 5 to 17 described in any item communication devices according to claim 1, the list entries is expressed as c={ c₀,c₁, c₂,...,c_K-1, the sequence after the coding is expressed as d={ d₀,d₁,d₂,...,d_N-1, wherein K and N is positive integer；

The sequence d includes the check bit in the list entries c in K-2Z bit and verification sequence w, the verification Sequence is expressed as w={ w₀,w₁,w₂,...,w_N+2Z-K-1, wherein K is the integral multiple of Z.

29. communication device according to claim 28, K=22Z, N=66Z.

30. communication device according to claim 28, the verification sequence w and the list entries c meet formula

Wherein, c^T=[c₀,c₁,c₂,...,c_K-1]^T, w^T=[w₀,w₁,w₂,...,w_N+2·Z-K-1]^T, 0^TFor column vector, all members The value of element is 0.

31. 5 to 17 described in any item communication devices according to claim 1 further include memory, for storing with the next item down or It is multinomial: basic matrix, parameter related with basic matrix, base figure, the deviant of the related parameter of base figure or nonzero element.

32. communication device according to claim 31 further includes transceiver, the transceiver includes the volume for sending The signal of sequence after code.

33. communication device according to claim 32 further includes following one or more:

For generating the device of transmission block CRC, used for the device of code block segmentation and CRC check for the device of rate-matched Interleaver in intertexture and the modulator for modulation treatment.

34. a kind of computer readable storage medium, including instruction, when run on a computer, so that computer executes such as The described in any item methods of claim 1 to 13.