CN103391104A - Method and device for processing LDPC encoding - Google Patents
Method and device for processing LDPC encoding Download PDFInfo
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- CN103391104A CN103391104A CN2012101454816A CN201210145481A CN103391104A CN 103391104 A CN103391104 A CN 103391104A CN 2012101454816 A CN2012101454816 A CN 2012101454816A CN 201210145481 A CN201210145481 A CN 201210145481A CN 103391104 A CN103391104 A CN 103391104A
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Abstract
The invention provides a method and device for processing LDPC encoding. The method comprises the steps of determining the number of RAMs according to the number of lines of a mother matrix of LDPC, sequentially writing information bits input every time and data bits read from RAM units of the RAMs corresponding to each line of the mother matrix every time into the RAM units of the RAMs corresponding to each line into the RAM units of the RAMs corresponding to each line in an iteration mode according to the value of information bits in each line of the mother matrix, and the step of outputting the data bits stored in the RAM units of the RAMs corresponding to each line until the last information bit of each line. By means of the method and device for processing the LDPC encoding, the problems that LDPC encoding in the prior art is low in encoding efficiency and narrow in applicable occasions, a corresponding encoder structure is complex and resources are wasted are solved, and the purposes that delay is small, the structure is simple, the handling capacity is large, and the generality is good are achieved.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of low density parity check code LDPC code processing method and device.
Background technology
Microwave communication is called as three large Main Means of modern communications transmission together with optical fiber communication, satellite communication.The point-to-point transmission means of the general employing of microwave communication, be mainly used in the bearer network that 2G/3G moves at present, and the transmission of voice-and-data business is provided for mobile operator, have transmission capacity large, long-distance transmission quality is stable, small investment, the characteristics such as the construction period is short, and is easy to maintenance.Encoding scheme in microwave communication adopts low density parity check code (Low Density Parity Check Code, referred to as LDPC) coding to realize.
Initial LDPC code encryption algorithm is the same with common block code, first by Gaussian reduction, the verification matrix conversion is become generator matrix, then with information sequence and generator matrix, multiplies each other to obtain code word.But traditional encryption algorithm of gaussian elimination needs a large amount of memory spaces, and implementation complexity is higher, therefore, is difficult for realizing when middle long code is long.
In order to reduce the encoder complexity of LDPC code, can adopt half random LDPC code, its coder structure is simple, and parameter is selected also very flexible simultaneously.Produced thus the linear Effective Encoding Algorithm for Low Density of a kind of encoder complexity and code length, it becomes the letter of verification matrixing by preliminary treatment the form of lower triangle or near lower triangular, then directly utilize check matrix to realize the approximately linear coding, but the required memory cell of this algorithm has too much limited its application.
Another kind utilizes the QC-LDPC encryption algorithm of shift register, and its check matrix has circulation or quasi-cyclic, decrease the needed memory cell of encoder, can realize linear complexity coding with shift register.But this algorithm need to use a large amount of shift registers, thereby has increased the area of this encoder and power consumption etc., has greatly limited its scope of application.
Therefore, LDPC coding of the prior art exists code efficiency low, and applicable situation is narrow, and corresponding coder structure is complicated, the problem of waste resource.
Summary of the invention
The invention provides a kind of low density parity check code LDPC code processing method and device, to solve at least prior art LDPC coding, exist code efficiency low, applicable situation is narrow, and corresponding coder structure is complicated, the problem of waste resource.
According to an aspect of the present invention, provide a kind of low density parity check code LDPC code processing method, having comprised: the number of determining random access memory ram according to the line number of female code matrix of described LDPC; According to the information bit of each input and the data bit that reads from the ram cell of the corresponding RAM of described female code every row of matrix at every turn, for the value of every row information bit in described female code matrix, iteration writes in the ram cell of the corresponding RAM of every row successively; Until last information bit in every row is exported the data bit of storing in the ram cell of the corresponding RAM of described every row.
Preferably, according to the information bit of each input and the data bit that reads from the ram cell of the corresponding RAM of described female code every row of matrix at every turn, for the value of every row information bit in described female code matrix, the ram cell that iteration writes the corresponding RAM of every row comprises successively: the initial address that obtains RAM corresponding to every row according to first value of the every row information bit in described female code matrix; From the initial address of RAM corresponding to every row, the operation result that the data bit that reads the information bit of input and ram cell from RAM corresponding to every row is carried out obtaining after computing writes in the ram cell of RAM corresponding to described every row; According to the next one value in every row, repeat the obtaining step of initial address, and the information bit that will next time input and the operation result iteration that obtains after the data bit that writes according to a upper value carries out computing write the step in the ram cell of RAM corresponding to described every row, until last information bit in every row.
Preferably, also comprise: read according to last information bit in every row and write data bit in the ram cell of RAM corresponding to described every row; The summed result that data bit in the ram cell of the RAM that described every row is corresponding carries out after summation operation writes in the 2nd RAM; Data bit in the RAM corresponding according to every row and/or the ram cell of described the 2nd RAM obtains the check digit of described female code matrix.
Preferably, the check digit of obtaining described female code matrix of the data bit in the ram cell of the RAM corresponding according to every row and/or described the 2nd RAM comprises: the one or more described RAM that determines to carry out the check digit computing; Start to read successively data bit the ram cell of definite one or more described RAM from address location 0; The described data bit that will read in the corresponding ram cell of one or more described RAM carries out XOR and obtains the check digit of described female code matrix.
Preferably, code check according to described female code matrix is controlled the number of the information bit of iterative operation in described female code matrix, wherein, the code check of described female code matrix is the ratio of the number of check digit in number and the described female yard matrix of information bit in described female code matrix.
According to a further aspect in the invention, provide a kind of low density parity check code LDPC code processing apparatus, having comprised: the first determination module is used for determining according to the line number of female code matrix of described LDPC the number of random access memory ram; Writing module, be used for information bit and each data bit that reads from the ram cell of the corresponding RAM of described female code every row of matrix according to each input, for the value of every row information bit in described female code matrix, iteration writes in the ram cell of the corresponding RAM of every row successively; Output module, be used for until last information bit of every row is exported the data bit of storing in the ram cell of the corresponding RAM of described every row.
Preferably, the said write module comprises: the first acquisition module is used for obtaining according to first value of every row information bit of described female code matrix the initial address of RAM corresponding to every row; The first writing module, be used for from the initial address of RAM corresponding to every row, the operation result that the data bit that reads the information bit of input and ram cell from RAM corresponding to every row is carried out obtaining after computing writes in the ram cell of RAM corresponding to described every row; The iteration writing module, be used for the next one value according to every row, repeat the obtaining step of initial address, and the information bit that will next time input and the operation result iteration that obtains after the data bit that writes according to a upper value carries out computing write the step in the ram cell of RAM corresponding to described every row, until last information bit in every row.
Preferably, also comprise: the first read module is used for reading according to last information bit of every row and writes data bit in the ram cell of RAM corresponding to described every row; The second writing module, the data bit that is used for the ram cell of the RAM that described every row is corresponding carries out summation operation summed result afterwards and writes in the 2nd RAM; The second acquisition module, the data bit that is used for the ram cell of the RAM corresponding according to every row and/or described the 2nd RAM obtains the check digit of described female code matrix.
Preferably, described the second acquisition module comprises: the first determination module is used for the one or more described RAM that determines to carry out the check digit computing; The second read module, for read successively the data bit of the ram cell of definite one or more described RAM from address location 0 beginning; The 3rd acquisition module, be used for carrying out XOR at the described data bit that the corresponding ram cell of one or more described RAM reads and obtain the check digit of described female code matrix.
Preferably, control module, be used for according to the code check of described female code matrix, the number of the information bit of described female code matrix iterative operation being controlled, wherein, the code check of described female code matrix is the ratio of the number of check digit in number and the described female yard matrix of information bit in described female code matrix.
By the present invention, the number of random access memory ram is determined in employing according to the line number of female code matrix of described LDPC; According to the information bit of each input and the data bit that reads from the ram cell of the corresponding RAM of described female code every row of matrix at every turn, for the value of every row information bit in described female code matrix, iteration writes in the ram cell of the corresponding RAM of every row successively; Until last information bit in every row, export the data bit of storing in the ram cell of the corresponding RAM of described every row, having solved LDPC coding of the prior art exists code efficiency low, applicable situation is narrow, and corresponding coder structure is complicated, the problem of waste resource, so reached postpone little, simple in structure, throughput large and versatility effect preferably.
Description of drawings
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, and illustrative examples of the present invention and explanation thereof are used for explaining the present invention, do not form improper restriction of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart according to the low density parity check code LDPC code processing method of the embodiment of the present invention;
Fig. 2 is the structured flowchart according to the low density parity check code LDPC code processing apparatus of the embodiment of the present invention;
Fig. 3 is the structured flowchart according to writing module 24 in the low density parity check code LDPC code processing apparatus of the embodiment of the present invention;
Fig. 4 is the structured flowchart of low density parity check code LDPC code processing apparatus according to the preferred embodiment of the invention;
Fig. 5 is the structured flowchart according to the second acquisition module 46 in the low density parity check code LDPC code processing apparatus of the embodiment of the present invention;
Fig. 6 is the structured flowchart of low density parity check code LDPC code processing apparatus according to the preferred embodiment of the invention;
Fig. 7 is the schematic diagram according to the whole LDPC coding implementation structure of the embodiment of the present invention;
Fig. 8 is the schematic diagram according to the single RAM operation of LDPC coding access of the embodiment of the present invention;
Fig. 9 is the flow chart according to the verification computational process of the embodiment of the present invention;
Figure 10 is the flow chart according to the check digit output of the embodiment of the present invention.
Embodiment
Hereinafter with reference to accompanying drawing, also describe in conjunction with the embodiments the present invention in detail.Need to prove, in the situation that do not conflict, embodiment and the feature in embodiment in the application can make up mutually.
A kind of low density parity check code LDPC code processing method is provided in the present embodiment, and Fig. 1 is that as shown in Figure 1, this flow process comprises the steps: according to the flow chart of the low density parity check code LDPC code processing method of the embodiment of the present invention
Step S102, determine the number of random access memory ram according to the line number of female code matrix of low density parity check code;
Step S104, according to the information bit of each input and the data bit that reads from the ram cell of the corresponding RAM of above-mentioned female code every row of matrix at every turn, for the value of every row information bit in above-mentioned female code matrix, iteration writes in the ram cell of the corresponding RAM of every row successively;
Step S106, until last information bit in every row is exported the data bit of storing in the ram cell of the corresponding RAM of every row.
pass through above-mentioned steps, the mode that adopts iteration to use RAM to write and read, information bit need not be stored, can directly export, saved the time that information interweaves, reduced greatly the delay of encoder information position, in addition, only adopt the ram cell of several sizes, area and the resource of encoder have been reduced, and said method goes for the calculating of the extended code of polytype female code matrix, LDPC coding of the prior art exists code efficiency low, applicable situation is narrow, and corresponding coder structure is complicated, the problem of waste resource, and then it is little to have reached delay, simple in structure, large and the versatility of throughput is effect preferably.
Preferably, when the corresponding RAM of every row carries out iteration in female code matrix, according to the information bit of each input and the data bit that reads from the ram cell of the corresponding RAM of female code every row of matrix at every turn, successively for the value of every row information bit in above-mentioned female code matrix, iteration writes in the ram cell of the corresponding RAM of every row, can adopt following processing mode: the initial address that obtains RAM corresponding to every row according to first value of the every row information bit in female code matrix; From the initial address of RAM corresponding to every row, the operation result that the data bit that reads the information bit of input and ram cell from RAM corresponding to every row is carried out obtaining after computing writes in the ram cell of RAM corresponding to every row; According to the next one value in every row, repeat the obtaining step of initial address, and the information bit that will next time input and the operation result iteration that obtains after the data bit that writes according to a upper value carries out computing write the step in the ram cell of RAM corresponding to every row, until last information bit in every row.
In last information bit in every row, after exporting the data bit of storing in the ram cell of the corresponding RAM of every row, in order to obtain encoding efficiency more accurately, the data bit of storing in can the ram cell according to the corresponding RAM of every row that obtains obtains corresponding check digit, for example, can adopt following processing mode to obtain corresponding check digit: to read according to last information bit in every row and write data bit in the ram cell of RAM corresponding to every row; The summed result that data bit in the ram cell of the RAM that every row is corresponding carries out after summation operation writes in the 2nd RAM; Data bit in the RAM corresponding according to every row and/or the ram cell of the 2nd RAM obtains the check digit of female code matrix, wherein, the 2nd RAM herein for above-mentioned female code matrix in the corresponding RAM of every row distinguish, therefore, while according to the line number in female code matrix, determining the RAM number, the number of RAM should be more than the line number in female code matrix, and the 2nd RAM is used for the data of temporary computational process.
Data bit in the RAM corresponding according to every row and/or the ram cell of the 2nd RAM obtains the mode of the check digit of female code matrix also can be a variety of, wherein, that the data of storing in above-mentioned RAM are carried out computing comparatively easily, namely, the data of storing in corresponding unit in RAM are carried out computing, for example, can adopt the compute mode of simple xor operation, namely determine to carry out one or more RAM of check digit computing, namely, select to remove the RAM of computing from above-mentioned all kinds of RAM, this RAM can select according to concrete coding rule; Start to read successively data bit the ram cell of definite one or more RAM from address location 0; The data bit that will read in the corresponding ram cell of one or more RAM carries out XOR and obtains the check digit of female code matrix, and will carry out the result that XOR obtains and write in corresponding RAM, and with its output, then carry out the calculating output of next check digit, this time, need to prove, can adopt the mode of streamline above-mentioned a plurality of RAM to be selected to operate the check digit of obtaining correspondence.
Adopt the mode of above-mentioned coding can support multiple different code check, also can support the coding of multiple different code length, namely can control the number of the information bit of iterative operation in female code matrix according to the code check of female code matrix, wherein, the code check of female code matrix be the ratio of the number of check digit in number and the female yard matrix of information bit in female code matrix.For example, if code check, lower than 28/32, can reduce the data amount check that reads in female code matrix by control and realize, and if code check higher than 28/32, only need to carry out that data bit corresponding in each RAM is carried out asking respectively of corresponding positions and get final product.
A kind of low density parity check code LDPC code processing apparatus also is provided in the present embodiment, and this device is used for realizing above-described embodiment and preferred implementation, had carried out repeating no more of explanation.As used below, the combination of software and/or the hardware of predetermined function can be realized in term " module ".Although the described device of following examples is preferably realized with software, hardware, perhaps the realization of the combination of software and hardware also may and be conceived.
Fig. 2 is the structured flowchart according to the low density parity check code LDPC code processing apparatus of the embodiment of the present invention, and as shown in Figure 2, this device comprises the first determination module 22, writing module 24 and output module 26.Below this device is described.
The first determination module 22, be used for determining according to the line number of female code matrix of LDPC the number of random access memory ram; Writing module 24, be connected to above-mentioned the first determination module 22, be used for information bit and each data bit that reads from the ram cell of the corresponding RAM of female code every row of matrix according to each input, for the value of every row information bit in female code matrix, iteration writes in the ram cell of the corresponding RAM of every row successively; Output module 26, be connected to above-mentioned writing module 24, is used for until last information bit of every row is exported the data bit of storing in the ram cell of the corresponding RAM of every row.
Fig. 3 is the structured flowchart according to writing module 24 in the low density parity check code LDPC code processing apparatus of the embodiment of the present invention, as shown in Figure 3, this is incorporated into module 24 and comprises the first acquisition module 242, the first writing module 244 and iteration writing module 246, below this device is described.
The first acquisition module 242, be used for obtaining according to first value of every row information bit of female code matrix the initial address of RAM corresponding to every row; The first writing module 244, be connected to above-mentioned the first acquisition module 242, be used for from the initial address of RAM corresponding to every row, the operation result that the data bit that reads the information bit of input and ram cell from RAM corresponding to every row is carried out obtaining after computing writes in the ram cell of RAM corresponding to every row; Iteration writing module 246, be connected to above-mentioned the first writing module 244, be used for the next one value according to every row, repeat the obtaining step of initial address, and the information bit that will next time input and the operation result iteration that obtains after the data bit that writes according to a upper value carries out computing write the step in the ram cell of RAM corresponding to every row, until last information bit in every row.
Fig. 4 is the structured flowchart of low density parity check code LDPC code processing apparatus according to the preferred embodiment of the invention, as shown in Figure 4, this device is except comprising all modules shown in Figure 2, also comprise the first read module 42, the second writing module 44 and the second acquisition module 46, below this preferred embodiment is described.
The first read module 42, be connected to above-mentioned output module 26, is used for reading according to last information bit of every row writing data bit in the ram cell of RAM corresponding to every row; The second writing module 44, be connected to above-mentioned the first read module 42, and the data bit that is used for the ram cell of the RAM that every row is corresponding carries out summation operation summed result afterwards and writes in the 2nd RAM; The second acquisition module 46, be connected to above-mentioned the second writing module 44, and the data bit that is used for the ram cell of the RAM corresponding according to every row and/or the 2nd RAM obtains the check digit of female code matrix.
Fig. 5 is the structured flowchart according to the second acquisition module 46 in the low density parity check code LDPC code processing apparatus of the embodiment of the present invention, as shown in Figure 5, this second acquisition module 46 comprises the first determination module 462, the second read module 464 and the 3rd acquisition module 466, below this module is described.
The first determination module 462, be used for the one or more RAM that determine to carry out the check digit computing; The second read module 464, be connected to above-mentioned the first determination module 462, is used for reading successively from address location 0 beginning the data bit of the ram cell of definite one or more RAM; The 3rd acquisition module 466, be connected to above-mentioned the second read module 464, is used for carrying out XOR at the data bit that the corresponding ram cell of one or more RAM reads and obtains the check digit of female code matrix.
Fig. 6 is the structured flowchart of low density parity check code LDPC code processing apparatus according to the preferred embodiment of the invention, as shown in Figure 6, this device is except comprising all modules shown in Figure 2, also comprise control module 62, this control module 62, be connected to above-mentioned the first determination module 22 and writing module 24, be used for according to the code check of female code matrix, the number of the information bit of female code matrix iterative operation being controlled, wherein, the code check of female code matrix be the ratio of the number of check digit in number and the female yard matrix of information bit in female code matrix.
Complicated for various LDPC coding structures in correlation technique, consumption of natural resource is larger, can not support the characteristics of the use of multiple occasion, for area and the resource that reduces encoder, the mode that a kind of RAM of recycling that the above embodiment of the present invention and preferred implementation propose writes and reads, realized little delay, resource-saving, is a kind of hardware implementations of supporting the LDPC coding of many code lengths multi code Rate of Chinese character, that is, corresponding microwave modulation /demodulation LDPC coding implementation method and LDPC code device.
The iteration reference to storage that passes through that above-described embodiment and preferred implementation provide is realized the mode of the calculating of LDPC coding checkout position, possesses following characteristics: (1) postpones little.Information bit does not need to store on the one hand, can directly export, and has saved the time that information interweaves, and has reduced greatly the delay of encoder information position.The data of input are directly used in the calculating of check digit on the other hand, guarantee the timely output of check digit.(2) simple in structure, take resource little.Only need several undersized random asccess memory (random access memory, referred to as RAM) unit, some registers and selector, adopt the method for iteration reference to storage to realize the LDPC coding, and write again the operation of RAM after not needing shift register to be shifted.(3) throughput is large.Because the time that does not have data interlacing to calculate, so the needed time interval while having omitted data interlacing.The data of a code block length can be inputted continuously, and do not need to wait for, and can export in real time, have greatly improved throughput of system.Can meet the demand of high-throughput and the demand of high speed data transfer; (4) versatility is relatively good, can support the calculating of extended code of female code matrix of different ranks types, and can support the LDPC coding of various code rate, and does not need to increase in addition control circuit., if the line number of female code matrix increases, only need to increase corresponding RAM number and get final product; If the line number order does not change, just increase column number, corresponding code check and the code length of input message position also will change, and the circuit result can realize corresponding operation without any need for changing.
Below in conjunction with accompanying drawing, embodiments of the invention and preferred implementation are described.
Chnnel coding in microwave modulation /demodulation project adopts the LDPC code of quasi-cyclic, the verification battle array of the LDPC code of quasi-cyclic can obtain by female code matrix H b expansion, this mother's code matrix H b is the capable c row of r, wherein the information bit part is shown in front s list, last b(b=c-s) the corresponding check digit part of row, spreading factor corresponding to each value in female code matrix is z., for computational process is described, introduce as an example of female code matrix of 4 row 32 row example here.The information bit part is shown in front 28 lists in this matrix, and the check digit part is shown in last 4 lists.So female code code check is 28/32, spreading factor is 512., according to simplification of a formula, can adopt the method for iteration reference to storage to realize.
The core of LDPC coding is exactly the access control to RAM.We suppose that input message is each clock cycle 1bit, and information bit is just encoded in input process, and input information bits is not stored.Value in female code matrix is definite value, only has 4x28 the data (maximum data is `d512) that 10bit is wide,, so it can be stored in a ROM, also it can be stored in a register file.
Fig. 7 is the schematic diagram according to the whole LDPC coding implementation structure of the embodiment of the present invention, and as shown in Figure 7, wherein line number and the spreading factor of the information bit in the degree of depth of RAM and bit wide and female yard matrix are relevant.Female code matrix herein has 4 row, so need 5 RAM, last RAM is used for the data of temporary computational process; The RAM bit wide determines by spreading factor, and spreading factor herein is 512, so the RAM bit wide is 1bit.In Fig. 7, signal bit wide p representative has relation with the RAM degree of depth, because the RAM degree of depth is 512, so this value is 9.Detailed computational process is as follows:
S1, at the information bit input phase, need to carry out two operations: the bit that 1) will input is deposited rear direct output; Signal bit in corresponding diagram 1; 2) read first value of every row in female code matrix, and according to this value, calculate the initial address that needs four RAM of access.The initial address of the corresponding RAM1 of data of the first row in female code matrix; The initial address of the corresponding RAM2 of data of the second row in female code matrix; The initial address of the corresponding RAM3 of data of the third line in female code matrix; The initial address of the corresponding RAM4 of data of fourth line in female code matrix.Concrete account form is carried out complementary operation with this value exactly.And five RAM are carried out initialization write 0 operation.Completing of this step is that first module information position input phase control signal in Fig. 1 produces in circuit and completes.
S2, visit corresponding ram cell according to the initial address of the RAM that calculates in previous step, and information bit input phase control signal produces circuit module and produces the corresponding enable signal of reading simultaneously.At first read data (data of reading this moment be 0) from the address location of correspondence, carry out XOR with the bit that arrives, and operation result is write in same address location.Fig. 8 is that as shown in Figure 8, the address of RAM adds 1 simultaneously, waits for the arrival of next bit according to the schematic diagram of the single RAM operation of LDPC coding access of the embodiment of the present invention.When arriving, carries out next bit same operation: sense data from unit corresponding to the address of RAM, and carry out XOR with the bit that arrives, and operation result is write in same address location.And the address signal of RAM adds 1.Be that address is while being 511 address location until have access to last address of RAM, address signal carries out zero clearing, the 0th address location of access RAM, until complete the calculating of 512 bit informations, the address of this moment should be that the initial address of RAM subtracts the address location after.This process is the parallel work-flow of four RAM.
S3, read the next data of every row in female code matrix, and according to these data, use the mode same with step S1 to calculate the initial address of RAM, and use and the same mode of step S2 are calculated.Different is a bit: read this moment from RAM data are the data that write RAM in step 2, but not full 0.
S4, circulation execution step S3, until in female code matrix, the information bit part all reads complete.
S5, the information bit part that this moment, LDPC encoded has been inputted complete, starts to carry out calculating and the output of check digit.The data that 0 address from RAM1 ~ RAM4 of Fig. 7 starts to read successively in all address locations are carried out summation operation, and result is write in the memory cell that the intermediate address (namely 256) of RAM5 starts.The data that namely read respectively in 0 address location of RAM1 ~ RAM4 are carried out summation operation, and the address that writes RAM5 is in 256 memory cell, and the address that writes simultaneously RAM4 is in 0 memory cell; Data in reading address unit 1 are carried out summation operation again, and are in 257 memory cell with writing address as a result, and the address that writes simultaneously RAM4 is in 1 memory cell; The like, until the data in the address location 511 of four RAM are read and carry out summation operation, the address that result writes RAM5 is in 255 address location, the address that writes simultaneously RAM4 is in 511 memory cell.As shown in Figure 9, Fig. 9 is the flow chart according to the verification computational process of the embodiment of the present invention.
S6, the output stage of check digit.Data in step S5 after XOR write in RAM4 and RAM5 on the one hand, can directly export on the other hand, because this value is the data of first group of check digit P (0).After P (0) output is complete, after address location 0 starts to read successively the data RAM5 and RAM1 and carry out XOR, write in RAM1, and this value is exported,, until in two RAM, the data in all memory cell all read completely, and calculate and complete.At this moment, completed the calculating of check digit P (1).During calculation check position P (2), can be undertaken writing RAM2 after XOR by the data that read in RAM1 and RAM2, and output.During calculation check position P (3), the data that read in RAM2, RAM3 and RAM4 carry out directly exporting after XOR.This process can adopt the method for streamline to calculate and export.Completed the output of all information bits and calculating and the output procedure of check digit this moment, and as shown in figure 10, Figure 10 is the flow chart according to the check digit output of the embodiment of the present invention.
S7, if need to support the coding of different code check different code lengths, if code check, lower than 28/32, can reduce the data amount check that reads in female code matrix by control and realize.For example,, if code check is 1/2, only need to reads last four column datas of information bit part in female code matrix and can realize.If code check, higher than 28/32, is 28/29 as code check, just can not need the computational process of step 6 to complete.Because only need this moment one group of check digit P of output (0) can complete calculating.
In sum, this LDPC coding structure has the following advantages: 1, delay is little, and the information bit of input does not need storage, can directly export; And after the information bit input and output are complete, but every group of check digit of continuous wave output, and centre does not almost postpone; 2, the RAM degree of depth in the circuit implementation structure is relevant with spreading factor z, and general spreading factor is 512,, if data bit width is 8bit, can be 64 with the degree of depth so, and bit wide is that the RAM of 8bit realizes, circuit structure is simple, and resource overhead is smaller; 3, can support the LDPC coding of various code rate, and not need to increase in addition control circuit.If during the ranks number of variations of 4 female code matrixes, many if line number becomes, only need to increase corresponding RAM number and get final product; If the line number order does not change, just increase column number, corresponding code check and the code length of input message position also will change, and the circuit result does not need to change the operation that can realize correspondence.
obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with general calculation element, they can concentrate on single calculation element, perhaps be distributed on the network that a plurality of calculation elements form, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in storage device and be carried out by calculation element, and in some cases, can carry out step shown or that describe with the order that is different from herein, perhaps they are made into respectively each integrated circuit modules, perhaps a plurality of modules in them or step being made into the single integrated circuit module realizes.Like this, the present invention is not restricted to any specific hardware and software combination.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a low density parity check code LDPC code processing method, is characterized in that, comprising:
Determine the number of random access memory ram according to the line number of female code matrix of described LDPC;
According to the information bit of each input and the data bit that reads from the ram cell of the corresponding RAM of described female code every row of matrix at every turn, for the value of every row information bit in described female code matrix, iteration writes in the ram cell of the corresponding RAM of every row successively;
Until last information bit in every row is exported the data bit of storing in the ram cell of the corresponding RAM of described every row.
2. method according to claim 1, it is characterized in that, according to the information bit of each input and the data bit that reads from the ram cell of the corresponding RAM of described female code every row of matrix at every turn, for the value of every row information bit in described female code matrix, the ram cell that iteration writes the corresponding RAM of every row comprises successively:
Obtain the initial address of RAM corresponding to every row according to first value of the every row information bit in described female code matrix;
From the initial address of RAM corresponding to every row, the operation result that the data bit that reads the information bit of input and ram cell from RAM corresponding to every row is carried out obtaining after computing writes in the ram cell of RAM corresponding to described every row;
According to the next one value in every row, repeat the obtaining step of initial address, and the information bit that will next time input and the operation result iteration that obtains after the data bit that writes according to a upper value carries out computing write the step in the ram cell of RAM corresponding to described every row, until last information bit in every row.
3. method according to claim 1 and 2, is characterized in that, also comprises:
Read according to last information bit in every row and write data bit in the ram cell of RAM corresponding to described every row;
The summed result that data bit in the ram cell of the RAM that described every row is corresponding carries out after summation operation writes in the 2nd RAM;
Data bit in the RAM corresponding according to every row and/or the ram cell of described the 2nd RAM obtains the check digit of described female code matrix.
4. method according to claim 3, is characterized in that, the check digit that the data bit in the RAM corresponding according to every row and/or the ram cell of described the 2nd RAM obtains described female code matrix comprises:
Determine to carry out the one or more described RAM of check digit computing;
Start to read successively data bit the ram cell of definite one or more described RAM from address location 0;
The described data bit that will read in the corresponding ram cell of one or more described RAM carries out XOR and obtains the check digit of described female code matrix.
5. method according to claim 3, it is characterized in that, also comprise, code check according to described female code matrix is controlled the number of the information bit of iterative operation in described female code matrix, wherein, the code check of described female code matrix is the ratio of the number of check digit in number and the described female yard matrix of information bit in described female code matrix.
6. a low density parity check code LDPC code processing apparatus, is characterized in that, comprising:
The first determination module, be used for determining according to the line number of female code matrix of described LDPC the number of random access memory ram;
Writing module, be used for information bit and each data bit that reads from the ram cell of the corresponding RAM of described female code every row of matrix according to each input, for the value of every row information bit in described female code matrix, iteration writes in the ram cell of the corresponding RAM of every row successively;
Output module, be used for until last information bit of every row is exported the data bit of storing in the ram cell of the corresponding RAM of described every row.
7. device according to claim 6, is characterized in that, the said write module comprises:
The first acquisition module, be used for obtaining according to first value of every row information bit of described female code matrix the initial address of RAM corresponding to every row;
The first writing module, be used for from the initial address of RAM corresponding to every row, the operation result that the data bit that reads the information bit of input and ram cell from RAM corresponding to every row is carried out obtaining after computing writes in the ram cell of RAM corresponding to described every row;
The iteration writing module, be used for the next one value according to every row, repeat the obtaining step of initial address, and the information bit that will next time input and the operation result iteration that obtains after the data bit that writes according to a upper value carries out computing write the step in the ram cell of RAM corresponding to described every row, until last information bit in every row.
8. according to claim 6 or 7 described devices, is characterized in that, also comprises:
The first read module, be used for reading according to last information bit of every row and write data bit in the ram cell of RAM corresponding to described every row;
The second writing module, the data bit that is used for the ram cell of the RAM that described every row is corresponding carries out summation operation summed result afterwards and writes in the 2nd RAM;
The second acquisition module, the data bit that is used for the ram cell of the RAM corresponding according to every row and/or described the 2nd RAM obtains the check digit of described female code matrix.
9. device according to claim 8, is characterized in that, described the second acquisition module comprises:
The first determination module, be used for the one or more described RAM that determines to carry out the check digit computing;
The second read module, for read successively the data bit of the ram cell of definite one or more described RAM from address location 0 beginning;
The 3rd acquisition module, be used for carrying out XOR at the described data bit that the corresponding ram cell of one or more described RAM reads and obtain the check digit of described female code matrix.
10. device according to claim 8, it is characterized in that, also comprise, control module, be used for according to the code check of described female code matrix, the number of the information bit of described female code matrix iterative operation being controlled, wherein, the code check of described female code matrix is the ratio of the number of check digit in number and the described female yard matrix of information bit in described female code matrix.
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