CN1862452A - System command transmission method for computer system - Google Patents
System command transmission method for computer system Download PDFInfo
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- CN1862452A CN1862452A CN 200510071437 CN200510071437A CN1862452A CN 1862452 A CN1862452 A CN 1862452A CN 200510071437 CN200510071437 CN 200510071437 CN 200510071437 A CN200510071437 A CN 200510071437A CN 1862452 A CN1862452 A CN 1862452A
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 27
- 230000002093 peripheral effect Effects 0.000 claims abstract description 66
- 230000008054 signal transmission Effects 0.000 claims description 9
- 230000004044 response Effects 0.000 claims description 7
- 238000007726 management method Methods 0.000 description 15
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000002618 waking effect Effects 0.000 description 1
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Abstract
The present invention relates to a transmission method of system instruction in computer system. Said method includes the following steps: implementing power supply management instruction initialization between CPU and second system chip; second system chip executes said power supply management instruction; transferring said power-supply management instruction to first system chip by second system chip; second system chip executes said power supply management instruction; peripheral equipment responds second system chip and implementing said power supply management instruction; notifying it to second system chip; driving peripheral equipment coupled with second system chip and making it implement said power supply management instruction.
Description
Technical field
The present invention relates to the transmission method of system directive in a kind of computer system, particularly transmit the instruction that enters battery saving mode, make the peripheral unit of coupling system chip can enter battery saving mode smoothly by original instruction host-host protocol between System on Chip/SoC.
Background technology
Each assembly in the computer system, periphery need operate by the transmission of information, wherein use the bus (bus) of transmitting digital data stream, as peripheral component connecting interface (Peripheral ComponentInterconnect, PCI), AGP (Accelerated Graphics Port, AGP), also borrow bus to be connected between central processing unit (CPU) and north and south bridge chip or Installed System Memory, a plurality of peripheries or each assembly are coupled to this bus with transmission information or data.
As shown in Figure 1, commonly use and in computer system, use peripheral component connecting interface (PCI) bus 16 to couple a plurality of peripheral unit a, b, c, under the System Operation of supporting battery saving mode (low power mode), behind CPU (central processing unit) 10 reception power-saving instructions wherein, can carry out a PCI recursion instruction (PCI cycle), promptly by north and south bridge chip (North, South Bridge) 11,12 controls are passed on instruction by pci bus 16, and, make peripheral unit a, b by ROM-BIOS (BIOS), c enters battery saving mode, even the bus of battery saving mode information by separately is passed to Installed System Memory 13 or display chip 14 enters power down mode.
United States Patent (USP) the 6th, 357, also disclose a kind of computer system for No. 013 and transmit the instruction of multiple battery saving mode by pci bus, yet, it seems compared with present PCI framework, pci interface and all peripheral data transmission, can only come the bandwidth of shared in common 133MB/s to transfer data to South Bridge chip by a main trunk road, and data transmission is arranged fully sequentially, if run into bigger data, be easy to allow computer system speed slack-off, similarly be the device of transmission at a high speed such as sequential ATA (SerialATA) device of new development or Gigabit hierarchical network, if operate under the PCI framework, usefulness can reduce because of the phenomenon of bandwidth deficiency.
Be different from and pass (Multi-Drop) parallel bus technology under the existing pci bus multiple spot, PCIExpress introduces switch type (Switch) point-to-point sequence transmission technology (Point-to-Point), PCIExpress then forms transmitting terminal and receiving end by one group of simplex channel (Lane) at the physical layer of data transmission, every group of PCI Express independently uses channel and the South Bridge chip transmission of oneself, it no longer is the framework of shared bus, not only remove the problem that data transmission interferes with each other from, and each data all has the privilege of first priority processing, therefore single with regard to the framework of PCI Express transmission, compare existing pci bus, will become the main selection of computer system bus.
Under PCI Express framework, L2 and L3 electric source modes have been defined to peripheral device provisioning power supply, be primary power (Main Power) and all be removed under the situation that only keeps accessory power supply (Auxiliary Power) as the L2 electric source modes with reference to clock pulse (Reference Clock), make device be in the state of minimum power consumption, still have fast the function of waking (Wake-up) system up.The L3 electric source modes then for the primary power of device with all remove with reference to clock pulse and system does not provide the state of accessory power supply, if need rebooting device, then need be by the process of start again.
In the prior art, after the information transmission, finish the initialization of battery saving mode when CPU (central processing unit) and South Bridge chip, promptly define L2 or L3 electric source modes, the direct power management of operating system (OS DirectPower Management, OSPM) preparation of its power saving conversion of the first initialization of module meeting, advance rank power management assembly (Advanced Configuration and PowerInterface because of of the prior art one this moment, ACPI) be to be arranged in the South Bridge chip, allow the PCI Express peripheral unit that couples South Bridge chip learn the preparation that enters power down mode.But,, then do not provide the mechanism of notifying its electric source modes in the prior art as drafting card, express network card etc. if the periphery that is coupled to north bridge chips by PCI Express bus is arranged yet.So the invention provides the instruction that a kind of agreement of utilizing information transmission between System on Chip/SoC transmits the particular power source state, solve the method that the peripheral unit that adopts PCI Express bus enters this power supply status.
Summary of the invention
The transmission method of system directive in a kind of computer system, it is the battery saving mode signal transmission that is applied between several peripheries that a computer system and its adopt PCI Express bus interface, the instruction that transmits the particular power source state by agreement as signal transmission between System on Chip/SoCs such as north and south bridge, make the peripheral unit of coupling system chip can enter the particular power source pattern smoothly, solving may be because the problem that System on Chip/SoC does not dispose Power Management Unit to be caused under this framework.
Wherein, the method of information transmission comprises finishes the initial step of transmitting a system directive earlier, and carry out this system directive by second System on Chip/SoC, make the peripheral unit that couples this second System on Chip/SoC begin to enter an electric source modes, the transfer system instruction is to first System on Chip/SoC again, and carry out this system directive, make the peripheral unit that couples this first System on Chip/SoC enter the particular power source pattern.Then, notify second System on Chip/SoC, the peripheral unit that expression couples this first System on Chip/SoC has been finished this system directive, and drives the peripheral unit that couples this second System on Chip/SoC and enter this electric source modes.
The transmission method of system directive is the battery saving mode signal transmission that is applied between a plurality of peripheries that a computer system and its adopt PCI Express bus interface in the computer system, the step of its preferred embodiment comprises and judges whether to enter battery saving mode earlier, and transmit preparation by CPU (central processing unit) and enter power-saving mode instruction to the second System on Chip/SoC, respond this CPU (central processing unit) again, then, CPU (central processing unit) transmits one again and enters power-saving mode instruction to the second System on Chip/SoC.Afterwards, the peripheral unit that driving couples second System on Chip/SoC enters battery saving mode, and transmit and to enter power-saving mode instruction to the first System on Chip/SoC, drive the peripheral unit that couples this first System on Chip/SoC and enter battery saving mode, respond first System on Chip/SoC again and finished power-saving mode instruction.And, notify second System on Chip/SoC by signal transfer protocol therebetween, expression couples the peripheral unit of first System on Chip/SoC and finished power-saving mode instruction, and is last, drives the peripheral unit that couples second System on Chip/SoC and finishes this power-saving mode instruction.
Description of drawings
Fig. 1 is a prior art computer system architecture synoptic diagram;
Fig. 2 is cpu instruction transmission synoptic diagram of the present invention;
Fig. 3 is computer system of the present invention and peripheral device transport stream signal journey;
Fig. 4 is the embodiment process flow diagram of computer system of the present invention and the transmission of peripheral device signal.
Description of reference numerals:
10 CPU (central processing unit)
11 north bridge chips
12 South Bridge chips
13 internal memories
14 display chips
15 ROM-BIOS
16 pci buss
A, b, c peripheral unit
20 CPU (central processing unit)
21 first System on Chip/SoCs
22 second System on Chip/SoCs
221 Power Management Unit
23 drawing chips
24 network chips
25,26 other peripheries
27 crosspoints
271,272 peripheral units
201 first signals
202 secondary signals
203 the 3rd signals
204 the 4th signals
205 the 5th signals
206 the 6th signals
207 the 7th signals
Embodiment
Do not need to respond the framework that the CPU (central processing unit) power management message promptly enters the particular power source pattern of this bus with respect to the existing peripheral device of pci bus that uses, as battery saving mode, use the peripheral device of PCIExpress bus then to need to respond this power managing signal; And under this framework, only the standard PCI Express that couples South Bridge chip (South Bridge) is with the mechanism of this response signal outward, but there is no the periphery that standard is coupled to north bridge chips (North Bridge) and how to respond this signal, so the present invention is promptly after the peripheral unit that is coupled to South Bridge chip enters the particular power source pattern, promptly by the signal transfer protocol between original and north bridge chips (as PCI, point-to-point interconnection technique between integrated circuit such as Hypertransport) transmits this power managing signal in, can obtain this power managing signal so that be coupled to the peripheral unit of north bridge chips, make and enter identical electric source modes synchronously.
See also signal shown in Figure 2 and transmit synoptic diagram, first System on Chip/SoC 21 that wherein couples CPU (central processing unit) 20 is one of system chipset (chipset), can be north bridge chips, and also couple this first System on Chip/SoC 21 for second System on Chip/SoC 22 of one of system chipset, and each System on Chip/SoC all couples separately peripheral unit with PCI Express bus, at least couple a drawing chip 23 as first System on Chip/SoC 21, one network chip 24 and other periphery 25, second System on Chip/SoC 22 also is coupled with a plurality of peripheral units 271 through the crosspoint (Switch) 27 of a PCI Express bus, 272, and with graphic in other periphery 26 of coupling.
Generally speaking, north bridge chips mainly is responsible for data, the signal transmission between CPU (central processing unit) (CPU), primary memory and display interface (Graphic Interface) bus, and be connected with South Bridge chip by specific host-host protocol, South Bridge chip then is responsible for the reception and the transmission of every peripheral device output input signal on the motherboard, and with interrupt request that these peripheral devices sent, be passed to CPU (central processing unit) by north bridge chips, allow the CPU (central processing unit) program that shares out the work, and carry out desired action.
Dotted line in graphic is represented the signal transmission, when computer system is required to enter an electric source modes, CPU (central processing unit) 20 is promptly assigned the power management instruction to its System on Chip/SoC, when CPU (central processing unit) 20 and second System on Chip/SoC 22 reach finish because of the characteristic that adopts PCI Express bus instruction transmit with response after, promptly transmit first signal, 201 to second System on Chip/SoCs 22, preferred embodiment is in the present invention instructed as entering power managements such as battery saving mode, by a Power Management Unit (the Power Management Unit that is provided with in second System on Chip/SoC 22, PMU) 221 receive, the rank power management assemblies (ACPI) that advance in second System on Chip/SoC 22 use the peripheral unit of PCI Express bus to carry out power supply control to it.
When second System on Chip/SoC 22 receives this first signal 201, and the peripheral unit that couples with secondary signal 202 notices enters the particular power source pattern, again with and the signal transfer protocol of 21 of first System on Chip/SoCs transmit the 3rd signal 203 to first System on Chip/SoCs 21, then, first System on Chip/SoC 21 makes the peripheral unit that is coupled to first System on Chip/SoC 21 also enter this particular power source pattern by the 4th signal 204.
After the peripheral unit that is coupled to first System on Chip/SoC 21 enters the particular power source pattern, promptly respond the 5th signal 205 to first System on Chip/SoCs 21, at this moment, first System on Chip/SoC 21 promptly notifies second System on Chip/SoC, 22 these peripheral units to finish the particular power source pattern that enters with the 6th signal 206, then be coupled to second System on Chip/SoC 22 and notify its peripheral unit, rank power management assembly (ACPI) of advancing by wherein make its peripheral unit enter the particular power source pattern, as close the PORT COM etc. of its peripheral unit, at last again with the 7th signal 207 responses second System on Chip/SoC 22.
See also the transport stream signal journey figure of system directive in the computer system of the embodiment of the invention shown in Figure 3.
Be coupled to before the System on Chip/SoC peripheral unit enters the particular power source pattern, the CPU and second System on Chip/SoC are reached the initial step of transmission system instruction (as the power management instruction), as program (step S301) such as (handshake) is held in the friendship of finishing dealing;
Afterwards, second System on Chip/SoC receives the system directive that is transmitted by CPU, promptly carries out this system directive, makes the peripheral unit that couples begin to enter specific electric source modes (step S303);
Utilize the signal transfer protocol between System on Chip/SoC again, second System on Chip/SoC transmits this system directive to the first System on Chip/SoC (step S305), and carry out this system directive by first System on Chip/SoC, make the particular power source pattern (step S307) in the peripheral unit entry instruction that couples;
After peripheral unit enters this electric source modes, promptly finish this system directive (step S309) with a signal response first System on Chip/SoC, and then notify second System on Chip/SoC, represent that its peripheral unit that couples first System on Chip/SoC has entered particular power source pattern (step S311), then, promptly drive the peripheral unit that couples second System on Chip/SoC and finish this system directive, need respond second System on Chip/SoC at last and finish instruction (step S313).
Step as described in Figure 3 is that the peripheral unit that couples first System on Chip/SoC earlier enters this particular power source pattern, makes the peripheral unit that couples second System on Chip/SoC enter the particular power source pattern in proper order again.If system architecture corresponding shown in Figure 2, its system directive can be a power management instruction that enters battery saving mode, and the signal transmission of 22 of first System on Chip/SoC 21 and second System on Chip/SoCs is by original transfer bus therebetween, after second System on Chip/SoC 22 receives instruction by CPU (central processing unit) 20, can be so as to notifying first System on Chip/SoC 21, and after finishing instruction, reinform second System on Chip/SoC 22, finish the instruction that CPU (central processing unit) 20 is paid.
Shown in Figure 4 then is preferred embodiment flow process of the present invention:
During beginning, judge whether to enter battery saving mode (step S401) by CPU, can also can judge that system's user mode, electricity usage state etc. determine whether entering battery saving mode by the program of operating system by the instruction that the user sent, battery saving mode also can be divided into various modes according to different conditions;
CPU transmits preparation and enters power-saving mode instruction to the second System on Chip/SoC (step S403), then, second System on Chip/SoC response CPU (step S405) again by CPU move instruction to the second System on Chip/SoC, makes its peripheral unit begin to enter battery saving mode (step S407);
After receiving this instruction, the peripheral unit that driving couples second System on Chip/SoC enters battery saving mode (step S409), and, second System on Chip/SoC transmits this with its signal specific host-host protocol and enters power-saving mode instruction to the first System on Chip/SoC (step S411), then drive the peripheral unit that couples first System on Chip/SoC and enter battery saving mode (step S413), when its peripheral unit finish enter battery saving mode after, this peripheral unit responds first System on Chip/SoC and has finished power-saving mode instruction (step S415).
After first System on Chip/SoC is finished instruction, promptly notify second System on Chip/SoC (step S417) with the signal transfer protocol between System on Chip/SoC, the peripheral unit that makes its driving couple second System on Chip/SoC is finished power-saving mode instruction, and after finishing instruction, responds this second System on Chip/SoC (step S419).
By above-mentioned flow process, can make each periphery of coupling system chip under PCI Express bus architecture enter battery saving mode smoothly, solving may be because System on Chip/SoC dispose Power Management Unit and causes the problem that can not enter battery saving mode simultaneously under this framework.
In sum, the present invention is the transmission method of system directive in the computer system, by the signal transmission between System on Chip/SoC, making the peripheral unit of coupling system chip can enter battery saving mode smoothly, is rare invention article in fact, and practicality, novelty and progressive on the tool industry, meet the application for a patent for invention condition fully, therefore file an application in accordance with the law, would like to ask detailed survey and grant this case patent, to ensure inventor's rights and interests.
But the above only is a preferable possible embodiments of the present invention, is not so limits claim of the present invention, and therefore the equivalent structure done of every utilization instructions of the present invention and accompanying drawing content changes, and all is equal to be contained in the claim scope of the present invention.
Claims (10)
1. the transmission method of system directive in the computer system, this method step includes:
Finish the initial step of transmitting a system directive, finish the initialize signal transmission between a CPU (central processing unit) and one second System on Chip/SoC;
Carry out this system directive, make the peripheral unit that couples this second System on Chip/SoC begin to enter an electric source modes;
Transmit this system directive to one first System on Chip/SoC;
Carry out this system directive, make the peripheral unit that couples this first System on Chip/SoC enter this electric source modes;
Notify this second System on Chip/SoC, expression couples the peripheral unit of this first System on Chip/SoC and has finished this system directive; And
The peripheral unit that driving couples this second System on Chip/SoC enters this electric source modes.
2. the transmission method of system directive is characterized in that in the computer system as claimed in claim 1, and described first System on Chip/SoC is a north bridge chips.
3. the transmission method of system directive is characterized in that in the computer system as claimed in claim 1, and described second System on Chip/SoC is a South Bridge chip.
4. the transmission method of system directive is characterized in that in the computer system as claimed in claim 1, and described system directive is power management instruction.
5. the transmission method of system directive is characterized in that in the computer system as claimed in claim 1, after the peripheral unit that couples this second System on Chip/SoC enters this electric source modes, promptly with this second System on Chip/SoC of signal response.
6. the transmission method of system directive in the computer system is the battery saving mode signal transmission that is applied between a plurality of peripheries that a computer system and its adopt PCI Express bus interface, and this method step includes:
Judge whether to enter battery saving mode;
Transmit a preparation and enter power-saving mode instruction to one second System on Chip/SoC, transmit by a CPU (central processing unit);
Respond this CPU (central processing unit);
Transmit one and enter power-saving mode instruction, transmit by a CPU (central processing unit) to this second System on Chip/SoC;
The peripheral unit that driving couples this second System on Chip/SoC enters battery saving mode;
Transmit this and enter power-saving mode instruction to one first System on Chip/SoC;
The peripheral unit that driving couples this first System on Chip/SoC enters battery saving mode;
Respond this first System on Chip/SoC and finished this power-saving mode instruction;
Notify this second System on Chip/SoC, expression couples the peripheral unit of this first System on Chip/SoC and has finished this power-saving mode instruction; And
Driving couples the peripheral unit of this second System on Chip/SoC and finishes this power-saving mode instruction.
7. the transmission method of system directive is characterized in that in the computer system as claimed in claim 6, and described first System on Chip/SoC is a north bridge chips.
8. the transmission method of system directive is characterized in that in the computer system as claimed in claim 6, and described second System on Chip/SoC is a South Bridge chip.
9. the transmission method of system directive is characterized in that in the computer system as claimed in claim 6, and described power-saving mode instruction is to be received by the Power Management Unit in this second System on Chip/SoC.
10. the transmission method of system directive is characterized in that in the computer system as claimed in claim 6, after the peripheral unit that couples this second System on Chip/SoC enters this electric source modes, promptly with this second System on Chip/SoC of signal response.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100714375A CN100397300C (en) | 2005-05-12 | 2005-05-12 | System command transmission method for computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100714375A CN100397300C (en) | 2005-05-12 | 2005-05-12 | System command transmission method for computer system |
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| Publication Number | Publication Date |
|---|---|
| CN1862452A true CN1862452A (en) | 2006-11-15 |
| CN100397300C CN100397300C (en) | 2008-06-25 |
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| CNB2005100714375A Expired - Fee Related CN100397300C (en) | 2005-05-12 | 2005-05-12 | System command transmission method for computer system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101159649B (en) * | 2007-09-21 | 2010-04-14 | 杭州华三通信技术有限公司 | PCI high-speed bus system and energy management method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7185212B2 (en) * | 2003-07-21 | 2007-02-27 | Silicon Integrated Systems Corp. | Method for PCI express power management using a PCI PM mechanism in a computer system |
| US7185213B2 (en) * | 2003-07-21 | 2007-02-27 | Silicon Integrated Systems Corp. | Method for PCI Express power management using a PCI PM mechanism in a computer system |
| TWI221214B (en) * | 2003-10-15 | 2004-09-21 | Via Tech Inc | Interrupt signal control system and control method |
| CN1278204C (en) * | 2004-09-06 | 2006-10-04 | 威盛电子股份有限公司 | Power source management state control method |
| CN1609817A (en) * | 2004-10-13 | 2005-04-27 | 李�诚 | Method for monitoring PCI Express plate card and apparatus thereof |
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2005
- 2005-05-12 CN CNB2005100714375A patent/CN100397300C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101159649B (en) * | 2007-09-21 | 2010-04-14 | 杭州华三通信技术有限公司 | PCI high-speed bus system and energy management method thereof |
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