CN100403228C - Power supply management for central processing unit with a plurality of main bridges - Google Patents
Power supply management for central processing unit with a plurality of main bridges Download PDFInfo
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- CN100403228C CN100403228C CNB2005100829025A CN200510082902A CN100403228C CN 100403228 C CN100403228 C CN 100403228C CN B2005100829025 A CNB2005100829025 A CN B2005100829025A CN 200510082902 A CN200510082902 A CN 200510082902A CN 100403228 C CN100403228 C CN 100403228C
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Abstract
The present invention relates to a power supply management method for a CPU connected with a plurality of main bridges, which is used for a computer system of which the CPU is connected with a first main bridge and a second main bridge. The method comprises the steps of firstly recording whether the two main bridges receive a bus master signal; sending a command to drive the two main bridges to receive the bus master signal and not sending to the CPU when detecting that the record shows the two main bridges either do not receive the bus master signal but drives the CPU to enter a C3 state of an interface of a stepping configuration power supply; after the CPU enters the C3 state, driving the CPU to leave the C3 state and driving the two main bridges to transfer the signal to the CPU after detecting the record that one of the two main bridges receive the bus master signal. The present invention can achieve the goal of electricity saving.
Description
Technical field
The present invention relates to a kind of method for managing power supply of CPU (central processing unit), particularly relate to a kind of method for managing power supply that connects the CPU (central processing unit) of plural main bridge, to allow CPU (central processing unit) can enter into rank configuration power supply interface (Advanced Configuration and Power Interface, ACPI) C3 power management states reaches more purpose of power saving.
Background technology
Computer system, be the indispensable basic life instrument of modern, nearly so far 70 years of computer system development, especially the quickest with development in nearly ten years, computer system is because of powerful now, cause power consumption also with raising, therefore, the power management of computer system is the important indicator of computer system development, in order to improve the power supply service efficiency of computer system, company of Microsoft (Microsoft) once developed and into rank power management (Advanced Power Management, APM) to improve the power supply effective utilization, but advance the rank power management is not to carry out the power management action according to user's user mode, therefore can't reach the purpose of effective use power supply, in view of this, Intel (Intel), configuration power supply interface, rank (advanced configurationand power interface windows is advanced in Microsoft and Toshiba (Toshiba) the common formulation of three big computer system taps, ACPI) as the power management standard, entering configuration power supply interface, rank is the operating system of utilizing computer system, carries out the computer power management.
Because the user passes through operating system, so that computer system is carried out control action, therefore operating system can be according to user's user mode, carry out more efficient power management, and the user also can utilize operating system, directly adjust configuration power supply interface, rank, to reach the convenience of use, the functional status that enters configuration power supply interface, rank is divided into system state (Global again, G), unit state (Device, D), dormant state (Sleeping, S) and the CPU (central processing unit) state (CPU C) waits four kinds.
Because, the common people now are for the increase that becomes of healing of the demand of the function of computer system, cause CPU (central processing unit) only to use the conventional arrangement of single main bridge (Host Bridge), can't effectively promote the function of computer system, so developing direction of present most of computer systems, all use plural main bridge development towards CPU (central processing unit), but, CPU (central processing unit) with plural main bridge can't enter the into C3 state of the CPU (central processing unit) state at rank configuration power supply interface, before desiring to make CPU (central processing unit) enter the C3 state, must order about main bridge when receiving bus master controller (Bus Master) signal, stop transfer bus primary controller signal to CPU (central processing unit), yet computer system is because of only sending an order to a main bridge, and all the other main bridges and can't receive this order, so will cause CPU (central processing unit) to enter the C3 state after, all the other main bridges are when receiving the bus master controller signal, still transfer to CPU (central processing unit), so will have problems.
So, the neither support CPU (central processing unit) of computer system that has the CPU (central processing unit) of plural main bridge now enters the C3 state, make CPU (central processing unit) can't have perfect power management, because of the C3 state is the CPU (central processing unit) state of power saving the most, so even if CPU (central processing unit) is under the standby situation and still can't enters the most effective dormant state, so will expend power supply, this problem is particularly important for portable computer, because this situation will consumes battery electric weight, so reduce the effective utilization of portable computer.
The present invention is promptly proposing a kind of method for managing power supply that connects the CPU (central processing unit) of plural main bridge at the problems referred to above, not only can improve CPU (central processing unit) and can't enter the C3 state, and electrical source consumption shortcoming fast, further can reduce the battery charge frequency of portable computer, use the increase battery life.
This shows, the computer system of above-mentioned existing CPU (central processing unit) with plural main bridge structure with use, obviously still have inconvenience and defective, and demand urgently further being improved.The problem that exists for the computer system that solves CPU (central processing unit) with plural main bridge, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of method for managing power supply of CPU (central processing unit) of the main bridge of connection plural number of new structure, just become the current industry utmost point to need improved target.
Because the defective that above-mentioned existing computer system with CPU (central processing unit) of plural main bridge exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, method for managing power supply in the hope of the CPU (central processing unit) of the main bridge of connection plural number of founding a kind of new structure, can improve general existing computer system, make it have more practicality with CPU (central processing unit) of plural main bridge.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to, overcome the defective that existing computer system with CPU (central processing unit) of plural main bridge exists, and a kind of method for managing power supply of CPU (central processing unit) of the main bridge of connection plural number of new structure is provided, technical matters to be solved is to make it that a kind of method for managing power supply that connects the CPU (central processing unit) of plural main bridge is provided, by a main bridge in receiving one when stopping the transfer bus primary controller to the order of CPU (central processing unit), also order about another main bridge and stop the transfer bus primary controller to CPU (central processing unit), prevent that the bus master controller signal from transferring to CPU (central processing unit), so that CPU (central processing unit) can enter the into C3 state at rank configuration power supply interface, reach purpose of power saving.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of method for managing power supply that connects the CPU (central processing unit) of plural main bridge according to the present invention's proposition, be applied to connect a computer system of a CPU (central processing unit) of one first main bridge and one second main bridge, this method includes the following step: whether record two these main bridges receive a bus master controller signal; Operating system is detected this record and is continued for some time, and when this is recorded as two these main bridges and does not all have when receiving this bus master controller signal in this time, sends an order to this first main bridge; Order about this first main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal, and send one and control signal to this second main bridge to this CPU (central processing unit); Order about this second main bridge when receiving this bus master controller signal according to this control signal, do not transmit this bus master controller signal to this CPU (central processing unit); And order about this CPU (central processing unit) and enter a C3 state that enters configuration power supply interface, rank; Wherein, after this CPU (central processing unit) enters this C3 state, when detecting this and being recorded as this first main bridge or this second main bridge this bus master controller signal of reception is arranged, order about this CPU (central processing unit) and leave this C3 state, and order about two these main bridges and transmit this bus master controller signal to this CPU (central processing unit).
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection, wherein said CPU (central processing unit) has plural independent bus line, and this first main bridge and this second main bridge are connected to this independent bus line.
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection, wherein said CPU (central processing unit) have one and share bus, and this first main bridge and this second main bridge are connected in this shared bus.
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection, wherein write down the step whether two these main bridges receive a bus master controller signal, this first main bridge or this second main bridge are when receiving this bus master controller signal, send a tracer signal, this bus master controller signal of reception is arranged for this main bridge of a recorder trace.
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection, wherein ordering about this first main bridge when receiving this bus master controller signal, do not transmit the step of this bus master controller signal to this CPU (central processing unit), order about this first main bridge, close a moderator of being located at this first main bridge, with in this first main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal to this CPU (central processing unit).
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection, wherein ordering about this second main bridge when receiving this bus master controller signal, do not transmit the step of this bus master controller signal to this CPU (central processing unit), order about this second main bridge and close a set moderator, with in this second main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal to this CPU (central processing unit).
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection wherein orders about this CPU (central processing unit) and enters a step of advancing a C3 state at configuration power supply interface, rank, more includes the following step:
Utilize an operating system to send one and enter the South Bridge chip of C3 order to this computer system;
Order about this South Bridge chip and transmit a clock pulse stop signal to this CPU (central processing unit); And
Order about this CPU (central processing unit) and transmit an agreement stop signal to this South Bridge chip, this CPU (central processing unit) enters this C3 state.
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection, when wherein detecting this and being recorded as this first main bridge or this second main bridge this bus master controller signal of reception is arranged, order about this CPU (central processing unit) and leave the step of this C3 state, utilize a South Bridge chip of this computer system to detect this record, and transmit a termination clock pulse stop signal to this CPU (central processing unit), order about this CPU (central processing unit) and leave this C3 state, and send an open command to this first main bridge by an operating system, order about this first main bridge and can transmit this bus master controller signal to this CPU (central processing unit), this first main bridge also sends a control signal to this second main bridge, orders about this second main bridge and can transmit this bus master controller signal to this CPU (central processing unit).
The object of the invention to solve the technical problems also adopts following technical scheme to realize.A kind of method for managing power supply that connects the CPU (central processing unit) of plural main bridge according to the present invention's proposition, be applied to have a computer system of sharing a CPU (central processing unit) of bus, this shared bus connects one first main bridge and one second main bridge, it is characterized in that this method includes: whether record two these main bridges receive a bus master controller signal; Operating system is detected this record and is continued for some time, and when this is recorded as two these main bridges and does not all have when receiving this bus master controller signal in this time, sends an order to this first main bridge; Order about this first main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal to this CPU (central processing unit); Order about this second main bridge and detect this order by this shared bus, this second main bridge is ordered according to this, when receiving this bus master controller signal, does not transmit this bus master controller signal to this CPU (central processing unit); And order about this CPU (central processing unit) and enter a C3 state that enters configuration power supply interface, rank; Wherein, after this CPU (central processing unit) enters this C3 state, when detecting this and being recorded as this first main bridge or this second main bridge this bus master controller signal of reception is arranged, order about this CPU (central processing unit) and leave this C3 state, and order about two these main bridges and transmit this bus master controller signal to this CPU (central processing unit).
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection, wherein write down the step whether two these main bridges receive a bus master controller signal, this first main bridge or this second main bridge are when receiving this bus master controller signal, send a tracer signal, this bus master controller signal of reception is arranged for this main bridge of a recorder trace.
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection, wherein ordering about this first main bridge when receiving this bus master controller signal, do not transmit the step of this bus master controller signal to this CPU (central processing unit), order about this first main bridge, close a moderator of being located at this first main bridge, with in this first main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal to this CPU (central processing unit).
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection, wherein order about this second main bridge and detect the step of this order by this shared bus, be to close the set moderator of this second main bridge according to this order, with in this second main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal to this CPU (central processing unit).
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection wherein orders about this CPU (central processing unit) and enters a step of advancing a C3 state at configuration power supply interface, rank, more includes the following step:
Utilize an operating system to send one and enter the South Bridge chip of C3 order to this computer system;
Order about this South Bridge chip and transmit a clock pulse stop signal to this CPU (central processing unit); And
Order about this CPU (central processing unit) and transmit an agreement stop signal to this South Bridge chip, this CPU (central processing unit) enters this C3 state.
The method for managing power supply of the CPU (central processing unit) of the plural main bridge of aforesaid connection, when wherein detecting this and being recorded as this first main bridge or this second main bridge this bus master controller signal of reception is arranged, order about this CPU (central processing unit) and leave the step of this C3 state, be to utilize a South Bridge chip of this computer system to detect this record, and transmit a termination clock pulse stop signal to this CPU (central processing unit), order about this CPU (central processing unit) and leave this C3 state, and send an open command to this first main bridge by an operating system, order about this first main bridge and can transmit this bus master controller signal to this CPU (central processing unit), this second main bridge is detected this open command, according to this detecting order, transmit this bus master controller signal to this CPU (central processing unit).
By technique scheme, the method for managing power supply that the present invention connects the CPU (central processing unit) of plural main bridge has following advantage at least:
The present invention by a main bridge in receiving one when stopping the transfer bus primary controller to the order of CPU (central processing unit), also order about another main bridge and stop the transfer bus primary controller to CPU (central processing unit), prevent that the bus master controller signal from transferring to CPU (central processing unit), so that CPU (central processing unit) can enter the into C3 state at rank configuration power supply interface, thereby reach purpose of power saving.
In sum, the method for managing power supply of the CPU (central processing unit) of the main bridge of connection plural number of special construction of the present invention, it has above-mentioned many advantages and practical value, and in like product, do not see have similar structural design to publish or use and really genus innovation, no matter it all has bigger improvement on product structure or function, have large improvement technically, and produced handy and practical effect, and more existing computer system with CPU (central processing unit) of plural main bridge has the multinomial effect of enhancement, thereby be suitable for practicality more, and have the extensive value of industry, really be a novelty, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the calcspar of a preferred embodiment of the present invention.
Fig. 2 is the process flow diagram of a preferred embodiment of the present invention.
Fig. 3 is the calcspar of another preferred embodiment of the present invention.
Fig. 4 is the process flow diagram of another preferred embodiment of the present invention.
10 CPU (central processing unit)
20 first main bridges
25 first moderators
30 second main bridges
35 second moderators
40 first peripheral devices
50 second peripheral devices
60 South Bridge chips
65 registers
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, its embodiment of method for managing power supply, structure, feature and the effect thereof of the CPU (central processing unit) of the main bridge of connection plural number that foundation the present invention is proposed, describe in detail as after.
See also Fig. 1, the present invention is applied to connect the computer system of the CPU (central processing unit) of plural main bridge, as shown in the figure, one CPU (central processing unit) 10 has two independent bus lines, and be connected with one first main bridge 20 and one second main bridge 30 respectively, the first main bridge 20 is connected with plural first peripheral device 40, and be provided with one first moderator (Arbitor) 25, the second main bridge 30 then is connected with plural second peripheral device 50, and be provided with one second moderator 35, first moderator 25 and second moderator 35, respectively in order to arbitrate the bus master controller signal that first peripheral device 40 and second peripheral device 50 are sent, bus master controller signal with peripheral device, transfer to CPU (central processing unit) 10, handle, after promptly the bus master controller signal of first peripheral device 40 must be arbitrated through first moderator 25 of the first main bridge 20, just can transfer to CPU (central processing unit) 10, and the bus master controller signal of second peripheral device 50 equally must second moderator 35 arbitration through the second main bridge 30 after, just can transfer to CPU (central processing unit) 10.
The present invention is by at a South Bridge chip 60 register 65 being set, write down the bus master controller the signal whether first main bridge 20 and the second main bridge 30 have reception first peripheral device 40 and second peripheral device 50 to be sent, register 65 can be a working storage, recording mode is for when the first main bridge 20 or the second main bridge 30 during in reception bus master controller signal, will send a tracer signal to South Bridge chip 60, for register 65 records two main bridges 20, one of 30 persons have the bus master controller of reception signal, register 65 also can be located at the other system chip, the present invention can be by the operating system detecting register 65 of computer system, to learn whether the first main bridge 20 and the second main bridge 30 have the bus master controller of reception signal, whether enter the C3 state with decision, if operating system detecting register 65 continues for some time, all not writing down the first main bridge 20 and the second main bridge 30 has when receiving the bus master controller signal, and operating system promptly can determine to allow CPU (central processing unit) 10 enter the C3 state.
Seeing also Fig. 2, is the process flow diagram of a preferred embodiment of the present invention; As shown in the figure, method for managing power supply of the present invention at first shown in step S1, writes down the bus master controller the signal whether first main bridge 20 and the second main bridge 30 have reception first peripheral device 40 and second peripheral device 50 to be sent; Afterwards, shown in step S2, when detecting register 65 by operating system, learn that register 65 continues record a period of time, when the first main bridge 20 and the second main bridge 30 all do not receive the bus master controller signal, promptly determine CPU (central processing unit) 10 can enter the C3 state, promptly send an order to the first main bridge 20 by operating system, then, shown in step S3, promptly order about the first main bridge 20 when receiving the bus master controller signal that first peripheral device 40 sent, transmission bus primary controller signal is not to CPU (central processing unit) 10, that is order about the first main bridge 20 and close first moderator 25, and the first main bridge 20 also sends one and controls signal to the second main bridge 30, carries out step S4.
Continue, shown in step S4, order about the second main bridge 30 when receiving the bus master controller signal that second peripheral device 50 sent, transfer bus primary controller signal is not to CPU (central processing unit) 10, promptly allow the second main bridge 30 close second moderator 35, above-mentioned steps S3 and step S4 are after being used to prevent that the bus master controller signal is through first moderator 25 and 35 arbitrations of second moderator, and transfer to CPU (central processing unit) 10; Afterwards, get final product execution in step S5, order about CPU (central processing unit) 10 and enter the into C3 state at rank configuration power supply interface, it is to enter C3 by operating system transmission one to order to South Bridge chip 60, South Bridge chip 60 in receive enter C3 order after, to transmit a clock pulse stop signal (STPCLK) to CPU (central processing unit) 10, enter the into C3 state at rank configuration power supply interface to order about CPU (central processing unit) 10, CPU (central processing unit) 10 is after receiving the clock pulse stop signal, when affirmation can enter the C3 state, to transmit one and agree stop signal (STPGNT) to South Bridge chip 60, CPU (central processing unit) 10 will enter the C3 state, to reduce electrical source consumption.
When CPU (central processing unit) 10 is in the C3 state, when the first main bridge 20 or the second main bridge 30 receive the bus master controller signal, because this moment, first moderator 25 and second moderator 35 were all closed, therefore the bus master controller signal can't transfer to CPU (central processing unit) 10, so can't handle, but the first main bridge 20 and the second main bridge 30 still can the transmission log signals, for register 65 records, the present invention detects register 65 by South Bridge chip 60 after CPU (central processing unit) 10 enters the C3 state, to learn that the first main bridge 20 or the second main bridge 30 have the bus master controller of reception signal, and necessary execution in step S6, order about CPU (central processing unit) 10 and leave the C3 state, but to order about the first main bridge 20 and the second main bridge 30 transfer bus primary controller signals to CPU (central processing unit), handle, promptly open first moderator 25 and second moderator 35.
The present invention carries out step S6, be to send one by South Bridge chip 60 to stop the clock pulse stop signal to CPU (central processing unit) 10, use and wake the CPU (central processing unit) 10 that is in the C3 state up, leave the C3 state, after CPU (central processing unit) 10 is left the C3 state, can send the main bridge 20 of an open command to the first by operating system, order about the first main bridge 20 transfer bus primary controller signals to CPU (central processing unit) 10 but use, and send a control signal to the second main bridge 30, but with order about second moderator 30 also transfer bus primary controller signal to CPU (central processing unit) 10, for CPU (central processing unit) 10, handle, promptly open first moderator 25 and second moderator 35.
See also Fig. 3 and Fig. 4, as shown in Figure 3, the embodiment difference of this embodiment and Fig. 1 is, the CPU (central processing unit) 10 of this embodiment has one and shares bus, so the first main bridge 20 and the second main bridge 30, be connected in CPU (central processing unit) 10 by shared bus, all the other all are same as the embodiment of Fig. 1, the present invention is directed to this kind framework another kind of method for managing power supply is provided, the method as shown in Figure 4, at first shown in step S11 and step S12, write down the first main bridge 20 and whether the second main bridge 30 receives the bus master controller signal, when detecting is recorded as the first main bridge 20 and the second main bridge 30 and does not have the bus master controller of reception signals, send a command to the first main bridge 20, to carry out step S13, order about the first main bridge 20 when receiving the bus master controller signal, be not sent to CPU (central processing unit) 10, the step S3 that this step is different from an embodiment is that the first main bridge 20 does not send a control signal to the second main bridge 30.
Because, the framework of this embodiment is that the first main bridge 20 and the second main bridge 30 are connected in shared bus, so can be shown in step S14, order about the second main bridge 30 by shared bus detecting order, the like this second main bridge 30 can be learnt this order, so can with when receiving the bus master controller signal, not be sent to CPU (central processing unit) 10 according to order; Afterwards, get final product execution in step S15, order about CPU (central processing unit) 10 and enter the into C3 state at rank configuration power supply interface, after CPU (central processing unit) 10 enters the C3 state, when learning that by the detecting record the first main bridge 20 or the second main bridge 30 receive the bus master controller signal, with execution in step S16, order about CPU (central processing unit) 10 and leave the C3 state; Afterwards, send the main bridge 20 of open command to the first by operating system, to open first moderator 25, and the second main bridge 30 can detect open command by shared bus, and open second moderator 35 according to open command, so get final product transfer bus primary controller signal to CPU (central processing unit) 10, handle for CPU (central processing unit) 10.
In addition, the framework of Fig. 3, also can use the method for Fig. 2, promptly send a control signal to the second main bridge 30 by the first main bridge 20, order about the second main bridge 30 when receiving the bus master controller signal, stop to transfer to CPU (central processing unit) 10 and maybe can transfer to CPU (central processing unit) 10, make CPU (central processing unit) 10 can enter or break away from the C3 state.
In sum, the present invention connects the method for managing power supply of the CPU (central processing unit) of plural main bridge, be applied to the situation that CPU (central processing unit) is connected with plural main bridge, because operating system is before ordering about the C3 state that CPU (central processing unit) enters rank configuration power supply interface into, only send a command to the first main bridge, therefore be connected to the situation of CPU (central processing unit) in the main bridge of plural number, the first main bridge must transmit control signal relatively to control the running of all the other main bridges, and the main bridge that is connected in shared bus can utilize shared bus, the detecting operating system is sent to the order of the first main bridge, and connect according to this order and move, so, can make the computer system of the CPU (central processing unit) that is connected with plural main bridge can support CPU (central processing unit) and enter the into C3 state at rank configuration power supply interface, to reach the purpose of more improving power management.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (14)
1. method for managing power supply that connects the CPU (central processing unit) of plural main bridge is applied to connect a computer system of a CPU (central processing unit) of one first main bridge and one second main bridge, it is characterized in that this method includes the following step:
Whether record two these main bridges receive a bus master controller signal;
Operating system is detected this record and is continued for some time, and when this is recorded as two these main bridges and does not all have when receiving this bus master controller signal in this time, sends an order to this first main bridge;
Order about this first main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal, and send one and control signal to this second main bridge to this CPU (central processing unit);
Order about this second main bridge when receiving this bus master controller signal according to this control signal, do not transmit this bus master controller signal to this CPU (central processing unit); And
Order about this CPU (central processing unit) and enter a C3 state that enters configuration power supply interface, rank;
Wherein, after this CPU (central processing unit) enters this C3 state, when detecting this and being recorded as this first main bridge or this second main bridge this bus master controller signal of reception is arranged, order about this CPU (central processing unit) and leave this C3 state, and order about two these main bridges and transmit this bus master controller signal to this CPU (central processing unit).
2. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 1, it is characterized in that wherein said CPU (central processing unit) has plural independent bus line, this first main bridge and this second main bridge are connected to this independent bus line.
3. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 1, it is characterized in that wherein said CPU (central processing unit) has one and shares bus, this first main bridge and this second main bridge are connected in this shared bus.
4. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 1, it is characterized in that writing down the step whether two these main bridges receive a bus master controller signal, this first main bridge or this second main bridge are when receiving this bus master controller signal, send a tracer signal, this bus master controller signal of reception is arranged for this main bridge of a recorder trace.
5. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 1, it is characterized in that wherein ordering about this first main bridge when receiving this bus master controller signal, do not transmit the step of this bus master controller signal to this CPU (central processing unit), order about this first main bridge, close a moderator of being located at this first main bridge, with in this first main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal to this CPU (central processing unit).
6. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 1, it is characterized in that wherein ordering about this second main bridge when receiving this bus master controller signal, do not transmit the step of this bus master controller signal to this CPU (central processing unit), order about this second main bridge and close a set moderator, with in this second main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal to this CPU (central processing unit).
7. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 1 is characterized in that wherein ordering about this CPU (central processing unit) and enters a step of advancing a C3 state at configuration power supply interface, rank, more includes the following step:
Utilize an operating system to send one and enter the South Bridge chip of C3 order to this computer system;
Order about this South Bridge chip and transmit a clock pulse stop signal to this CPU (central processing unit); And
Order about this CPU (central processing unit) and transmit an agreement stop signal to this South Bridge chip, this CPU (central processing unit) enters this C3 state.
8. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 1, when it is characterized in that wherein detecting this and being recorded as this first main bridge or this second main bridge this bus master controller signal of reception is arranged, order about this CPU (central processing unit) and leave the step of this C3 state, utilize a South Bridge chip of this computer system to detect this record, and transmit a termination clock pulse stop signal to this CPU (central processing unit), order about this CPU (central processing unit) and leave this C3 state, and send an open command to this first main bridge by an operating system, order about this first main bridge and can transmit this bus master controller signal to this CPU (central processing unit), this first main bridge also sends a control signal to this second main bridge, orders about this second main bridge and can transmit this bus master controller signal to this CPU (central processing unit).
9. method for managing power supply that connects the CPU (central processing unit) of plural main bridge, be applied to have a computer system of sharing a CPU (central processing unit) of bus, this shared bus connects one first main bridge and one second main bridge, it is characterized in that this method includes:
Whether record two these main bridges receive a bus master controller signal;
Operating system is detected this record and is continued for some time, and when this is recorded as two these main bridges and does not all have when receiving this bus master controller signal in this time, sends an order to this first main bridge;
Order about this first main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal to this CPU (central processing unit);
Order about this second main bridge and detect this order by this shared bus, this second main bridge is ordered according to this, when receiving this bus master controller signal, does not transmit this bus master controller signal to this CPU (central processing unit); And
Order about this CPU (central processing unit) and enter a C3 state that enters configuration power supply interface, rank;
Wherein, after this CPU (central processing unit) enters this C3 state, when detecting this and being recorded as this first main bridge or this second main bridge this bus master controller signal of reception is arranged, order about this CPU (central processing unit) and leave this C3 state, and order about two these main bridges and transmit this bus master controller signal to this CPU (central processing unit).
10. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 9, it is characterized in that wherein writing down the step whether two these main bridges receive a bus master controller signal, this first main bridge or this second main bridge are when receiving this bus master controller signal, send a tracer signal, this bus master controller signal of reception is arranged for this main bridge of a recorder trace.
11. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 9, it is characterized in that wherein ordering about this first main bridge when receiving this bus master controller signal, do not transmit the step of this bus master controller signal to this CPU (central processing unit), order about this first main bridge, close a moderator of being located at this first main bridge, with in this first main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal to this CPU (central processing unit).
12. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 9, it is characterized in that wherein ordering about this second main bridge is detected this order by this shared bus step, be to close the set moderator of this second main bridge according to this order, with in this second main bridge when receiving this bus master controller signal, do not transmit this bus master controller signal to this CPU (central processing unit).
13. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 9 is characterized in that wherein ordering about this CPU (central processing unit) and enters a step of advancing a C3 state at configuration power supply interface, rank, more includes the following step:
Utilize an operating system to send one and enter the South Bridge chip of C3 order to this computer system;
Order about this South Bridge chip and transmit a clock pulse stop signal to this CPU (central processing unit); And
Order about this CPU (central processing unit) and transmit an agreement stop signal to this South Bridge chip, this CPU (central processing unit) enters this C3 state.
14. the method for managing power supply of the CPU (central processing unit) of the plural main bridge of connection according to claim 9, when it is characterized in that wherein detecting this and being recorded as this first main bridge or this second main bridge this bus master controller signal of reception is arranged, order about this CPU (central processing unit) and leave the step of this C3 state, be to utilize a South Bridge chip of this computer system to detect this record, and transmit a termination clock pulse stop signal to this CPU (central processing unit), order about this CPU (central processing unit) and leave this C3 state, and send an open command to this first main bridge by an operating system, order about this first main bridge and can transmit this bus master controller signal to this CPU (central processing unit), this second main bridge is detected this open command, according to this detecting order, transmit this bus master controller signal to this CPU (central processing unit).
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| CNB2005100829025A CN100403228C (en) | 2005-07-05 | 2005-07-05 | Power supply management for central processing unit with a plurality of main bridges |
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| CNB2005100829025A CN100403228C (en) | 2005-07-05 | 2005-07-05 | Power supply management for central processing unit with a plurality of main bridges |
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| CN100403228C true CN100403228C (en) | 2008-07-16 |
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| CN100397301C (en) * | 2006-01-09 | 2008-06-25 | 威盛电子股份有限公司 | Power-saving method of central processor |
| CN100397302C (en) * | 2006-01-17 | 2008-06-25 | 威盛电子股份有限公司 | Power saving method and system for CPU |
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| US6357013B1 (en) * | 1995-12-20 | 2002-03-12 | Compaq Computer Corporation | Circuit for setting computer system bus signals to predetermined states in low power mode |
| US6799278B2 (en) * | 2000-12-21 | 2004-09-28 | Dell Products, L.P. | System and method for processing power management signals in a peer bus architecture |
| CN1598799A (en) * | 2003-09-15 | 2005-03-23 | 联发科技股份有限公司 | Methode for controlling bridge and relative bridge |
| CN1619467A (en) * | 2004-12-09 | 2005-05-25 | 威盛电子股份有限公司 | Computer system and power source management state |
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| US6357013B1 (en) * | 1995-12-20 | 2002-03-12 | Compaq Computer Corporation | Circuit for setting computer system bus signals to predetermined states in low power mode |
| US6799278B2 (en) * | 2000-12-21 | 2004-09-28 | Dell Products, L.P. | System and method for processing power management signals in a peer bus architecture |
| CN1598799A (en) * | 2003-09-15 | 2005-03-23 | 联发科技股份有限公司 | Methode for controlling bridge and relative bridge |
| CN1619467A (en) * | 2004-12-09 | 2005-05-25 | 威盛电子股份有限公司 | Computer system and power source management state |
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