CN1858723A - JIAG linkage method and device for using said method - Google Patents
JIAG linkage method and device for using said method Download PDFInfo
- Publication number
- CN1858723A CN1858723A CN 200610033387 CN200610033387A CN1858723A CN 1858723 A CN1858723 A CN 1858723A CN 200610033387 CN200610033387 CN 200610033387 CN 200610033387 A CN200610033387 A CN 200610033387A CN 1858723 A CN1858723 A CN 1858723A
- Authority
- CN
- China
- Prior art keywords
- jtag
- interface
- chain
- expansion
- mouth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
This invention discloses a chaining method for JTAG and a device, in which, said method includes: a, carrying out I/O interface expansion to general CPU, b, utilizing said expanded I/O interface and a selected device to form two JTAG chains, when said selector is connected to one of the input interfaces and a JTAG load head, it sets up a JTAG chain used in debug phase with them, when the selector is connected with the other interface and said expanded I/O interface, it sets up another on-line upgrade JTAG chain with them, which increases the minimum logic device to expand the programmable I/O interface of the CPU and increases bus selectors or similar devices to finish the load selection of JTAG chains.
Description
Technical field
The present invention relates to chip input and output technology, specifically, the JTAG chaining that relates to veneer loads and the online upgrading technology.
Background technology
A plurality of devices that require software loading such as BIOS (Basic Input or Output System (BIOS)), FLASH, PLD (steering logic device) etc. have generally been designed on the existing veneer.JTAG (Joint Test Action Group joint test group) is a kind of international standard test protocol, be mainly used in the chip internal test, ultimate principle is to carry out test to internal node at the jtag test instrument of a TAP of device inside definition (Test Access Port test access mouth) by special use, and JTAG allows a plurality of devices to be cascaded by jtag interface and forms a JTAG chain.Just because of this, carry out online programming by jtag interface usually now, just so-called J TAG chaining loads.
In order to accelerate the speed of production of veneer, adopt the JTAG chaining to load a kind of more and more general mode that becomes, but the mode that the JTAG chaining loads also has its deficiency, because the complicacy of veneer and business processing, sometimes may need change owing to former code has problem, or because the variation of demand need be changed code, usually requirement can be carried out online upgrading to the code in these devices, to strengthen scalable maintainable ability, reduce maintenance cost.But chaining loads and these two contradiction often of online upgrading because with the CPU chaining after device, if CPU is in the JTAG chain, in case the JTAG chain is started working, then CPU has also just entered the JTAG scanning mode, can't operate as normal, also just can't finish the on-line loaded of CPU control.The scheme that prior art addresses this problem employing is to realize simultaneously that by the CPU such as the communication processor that have general purpose I/O interface the JTAG chaining in online upgrading and the production loads, but also there is tangible deficiency in this scheme, does not have the CPU of general purpose I/O interface such as some universal cpus then can't accomplish this point.In addition, also have in the prior art and adopt logical device that universal cpu is carried out the I/O mouth to expand, to solve that universal cpu does not have the I/O interface and the problem that can't realize online upgrading.But this scheme have a following deficiency: 1, the logic of this expansion has also been finished other a lot of functions usually, in case demand changes, then this logic is not scalable; 2, in the process of producing, to finish respectively BIOS by different loading heads, FLASH, the loading of each logical device, production efficiency is lower, is unfavorable for large-scale production.
Summary of the invention
The object of the present invention is to provide a kind of JTAG chaining method to utilize the device of this method, solve the problem that in the prior art logical device chaining in the chip is loaded the back online upgrading.
For achieving the above object, the present invention adopts following technical scheme: a kind of JTAG chaining method, and described method may further comprise the steps:
A, universal cpu is carried out input and output I/O mouth expansion;
B, utilize described expansion I/O mouth and selector to make up two JTAG chains, when described selector is communicated with one of them input interface and JTAG loading head, make up a JTAG chain that is used to produce the debug phase, when described selector is communicated with another input interface and described expansion I/O mouth, make up the JTAG chain that another is used for online upgrading.
The wherein said JTAG chain that is used to produce the debug phase is that the jtag interface on the logical device that is loaded by input interface of the jtag interface on JTAG loading head, described CPU and the expansion I/O mouth thereof, described selector and output interface and needs is cascaded and constitutes.
The wherein said JTAG chain that is used for online upgrading is by another input interface and the output interface of described CPU and expansion I/O mouth thereof, described selector and needs the jtag interface of the logical device of online upgrading to be cascaded to constitute.
Wherein said selecting arrangement selects the SEL signal " to put height " sheet or " putting low " controlled to the selection of input interface is logical.
The wherein said JTAG chain that is used to produce the debug phase adopts model selection/clock control signal of JTAG that the device on the chain is controlled when loading.
The wherein said JTAG chain that is used for online upgrading provides control signal by described CPU through expansion I/O interface the device on the chain is controlled when upgrading.
The invention also discloses the device of a kind of JTAG of utilization chain to the CPU online upgrading, comprise I/O mouth extended device, JTAG loading head and, it is characterized in that, described device also comprises the selector that is used for making up two JTAG chains, described selector is communicated with one of them input interface and the JTAG loading head makes up a JTAG chain that is used to produce the debug phase, and described selector is communicated with another input interface and described expansion I/O mouth makes up the JTAG chain that another is used for online upgrading.
Jtag interface on the logical device that the wherein said JTAG chain that is used to produce the debug phase is loaded by input interface of the jtag interface on JTAG loading head, described CPU and the expansion I/O mouth thereof, described selector and output interface and needs is cascaded and constitutes.
The wherein said JTAG chain that is used for online upgrading is by another input interface and the output interface of described CPU and expansion I/O mouth thereof, described selector and need the jtag interface of the logical device of online upgrading to be cascaded to constitute.
Description of drawings
Fig. 1 is the schematic diagram of the embodiment of the invention.
Embodiment
Be described in detail inventing described technical scheme below in conjunction with the drawings and specific embodiments.
Programmable I/O interface that the embodiment of the invention is come extension CPU by increasing minimum logical device, finish the loading of JTAG chain and select by increasing bus selector or similar device, finally reach and not only can realize that the JTAG chaining loads but also can realize the purpose to the online upgrading of logical device.
The schematic diagram of the embodiment of the invention as shown in Figure 1, wherein A represents the JTAG loading head; B is not for the CPU of general purpose I/O interface; C be one small, logical device with low cost (as the CPLD of 32 or 64 macroelements); D, E are respectively alternative devices, can adopt bus selector or similar device; F and G are the steering logic device of relative complex, and logical device F and logical device G belong to the logical device that needs online upgrading in the present embodiment; H is BIOS or FLASH device.
C can be regarded as the I/O expansion of CPU B in the present embodiment, is a functional module from function B and C promptly, and the I/O mouth of C can be regarded as the universaling I/O port of CPU B.Simultaneously C also finishes the required minimum logic function of single board starting, because content is few, so the simple stability of code is also high, can think that the code of logic C is that do not need also cannot online upgrading.
As shown in Figure 1, the height of SEL signal level will cause two kinds of different connected modes, wherein every kind of mode corresponding separately a JTAG Line (JTAG chain):
Article one, be JTAG Line L, the SEL of this moment should be initial state fixed level (selecting high level this moment), alternative device D is communicated with interface 2 and interface 3 shown in attached 1 figure, alternative device E is communicated with as shown in Figure 1 interface 4 and interface 6 simultaneously, wherein interface 2 connects JTAG TDO (data output) interface of logical device C, interface 3 connects JTAG TDI (data input) interface of logical device F, interface 4 connects TMS/TCK (model selection/clock) signal of JTAG loading head A, interface 6 connects the TMS/TCK interface of logic control device F and G, in this JTAG Line L, by the JTAG loading head, jtag interface on CPU and the expansion I/O mouth thereof, logical device F that the input interface 2 of alternative device D and output interface 3 and needing loads and the jtag interface on the logical device G are cascaded and constitute a complete JTAG chain, control signal TMS/TCK (model selection/clock) is simultaneously to the JTAG loading head, CPU and expansion I/O mouth logical device F thereof and logical device G control, data are sent to CPU B after the TDI interface output of JTAG loading head, be sent to logical device C from CPU B then, TDO interface by logical device C reaches alternative device D, arrive logical device F and logical device G then, be connected to the TDO interface of JTAG loading head at last.Transfer the initial stage of surveying in process of production or at veneer, because logic C does not have loading content, peripheral interface is a high resistant, by pull-up resistor R signal end SEL is changed to high level.At this moment, above-mentioned JTAG Line L connects, JTAG loading head A, universal cpu B and expansion I/O mouth C, logical device F and logical device G are on the JTAG Line L, can finish loading by jtag interface A in process of production or at the initial stage that veneer transfer to be surveyed, finish that also BIOS or FLASH device H are loaded above-mentioned all devices on the JTAG chain Line L.
Another is as accompanying drawing 1 described JTAG Line K, the signal level of the SEL of this moment should be opposite with above-mentioned initial state fixed level (selecting low level at this moment), when the SEL signal level when low, alternative device D is communicated with its interface 1 and interface 3, alternative device E will be communicated with as its interface 5 and interface 6 simultaneously, wherein interface 1 and interface 5 are the programmable interface of logical device C (the expansion I/O mouth of CPU), can carry out online upgrading to logical device by these programmable interfaces.In JTAG Line K, by another input interface 1 and the output interface 3 of CPU and expansion I/O mouth thereof, alternative device D and need the logical device F of online upgrading and the jtag interface of logical device G is cascaded and constitutes a complete JTAG chain, simultaneously logical device F and logical device G are connected in separately independently on the JTAGLine K, and being subjected to the control of expansion I/O mouth logical device C, logical device C can be controlled by programming by CPU B.Under logical device C control, data reach logical device D from the I/O interface of logical device C, reach the TDI interface of logical device F then by the interface 3 of logical device D, the TDO interface from logical device F reaches logical device G then, is communicated with another I/O interface of logical device C at last.If in transferring the survey process, need the code in the veneer changed or veneer needs veneer is upgraded after dispatching from the factory, then can issue orders the SEL signal wire on the C logical device put and low finish change, reach the purpose of online upgrading the code among logical device F and the logical device G etc. by steering logic C by CPU B.
Claims (9)
1, a kind of JTAG chaining method is characterized in that described method may further comprise the steps:
A, universal cpu is carried out input and output I/O mouth expansion;
B, utilize described expansion I/O mouth and selector to make up two JTAG chains, when described selector is communicated with one of them input interface and JTAG loading head, make up a JTAG chain that is used to produce the debug phase, when described selector is communicated with another input interface and described expansion I/O mouth, make up the JTAG chain that another is used for online upgrading.
2, method according to claim 1, it is characterized in that the described JTAG chain that is used to produce the debug phase is that the jtag interface on the logical device that is loaded by input interface of the jtag interface on JTAG loading head, described CPU and the expansion I/O mouth thereof, described selector and output interface and needs is cascaded and constitutes.
3, method according to claim 1, it is characterized in that the described JTAG chain that is used for online upgrading is by another input interface and the output interface of described CPU and expansion I/O mouth thereof, described selector and needs the jtag interface of the logical device of online upgrading to be cascaded to constitute.
According to claim 2 or 3 described methods, it is characterized in that 4, described selecting arrangement selects the SEL signal " to put height " sheet or " putting low " controlled to the selection of input interface is logical.
According to claim 1 or 2 described methods, it is characterized in that 5, the described JTAG chain that is used to produce the debug phase adopts model selection/clock control signal of JTAG that the device on the chain is controlled when loading.
According to claim 1 or 3 described methods, it is characterized in that 6, the described JTAG chain that is used for online upgrading provides control signal by described CPU through expansion I/O interface the device on the chain is controlled when upgrading.
7, a kind of device that utilizes the JTAG chain to the CPU online upgrading, comprise I/O mouth extended device, JTAG loading head and, it is characterized in that, described device also comprises the selector that is used for making up two JTAG chains, described selector is communicated with one of them input interface and the JTAG loading head makes up a JTAG chain that is used to produce the debug phase, and described selector is communicated with another input interface and described expansion I/O mouth makes up the JTAG chain that another is used for online upgrading.
8, method according to claim 7, it is characterized in that the jtag interface on the logical device that the described JTAG chain that is used to produce the debug phase is loaded by input interface of the jtag interface on JTAG loading head, described CPU and the expansion I/O mouth thereof, described selector and output interface and needs is cascaded and constitutes.
9, method according to claim 7, it is characterized in that the described JTAG chain that is used for online upgrading is by another input interface and the output interface of described CPU and expansion I/O mouth thereof, described selector and need the jtag interface of the logical device of online upgrading to be cascaded to constitute.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100333876A CN100373359C (en) | 2006-01-24 | 2006-01-24 | JIAG linkage method and device for using said method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100333876A CN100373359C (en) | 2006-01-24 | 2006-01-24 | JIAG linkage method and device for using said method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1858723A true CN1858723A (en) | 2006-11-08 |
| CN100373359C CN100373359C (en) | 2008-03-05 |
Family
ID=37297632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100333876A Expired - Fee Related CN100373359C (en) | 2006-01-24 | 2006-01-24 | JIAG linkage method and device for using said method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100373359C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461105C (en) * | 2007-02-01 | 2009-02-11 | 中兴通讯股份有限公司 | Update and repair method of intellectualized equipment and system thereof |
| CN101645055A (en) * | 2009-09-10 | 2010-02-10 | 成都市华为赛门铁克科技有限公司 | Logic device on-line loaded method, system and processor |
| CN104156288A (en) * | 2014-06-26 | 2014-11-19 | 西安空间无线电技术研究所 | Fault locating and software upgrading circuit based on JTAG link and implementation method thereof |
| CN104901830A (en) * | 2015-05-12 | 2015-09-09 | 武汉烽火网络有限责任公司 | FPGA online upgrade method in exchanger device, device thereof and system thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0826974B1 (en) * | 1996-08-30 | 2005-10-19 | Texas Instruments Incorporated | Device for testing integrated circuits |
| CN1163083C (en) * | 2001-02-28 | 2004-08-18 | 上海贝尔有限公司 | Digital signal and instruction treatment device for program controlled switchboard |
-
2006
- 2006-01-24 CN CNB2006100333876A patent/CN100373359C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461105C (en) * | 2007-02-01 | 2009-02-11 | 中兴通讯股份有限公司 | Update and repair method of intellectualized equipment and system thereof |
| CN101645055A (en) * | 2009-09-10 | 2010-02-10 | 成都市华为赛门铁克科技有限公司 | Logic device on-line loaded method, system and processor |
| WO2011029385A1 (en) * | 2009-09-10 | 2011-03-17 | 成都市华为赛门铁克科技有限公司 | Method, system and processor for loading logic devices online |
| CN104156288A (en) * | 2014-06-26 | 2014-11-19 | 西安空间无线电技术研究所 | Fault locating and software upgrading circuit based on JTAG link and implementation method thereof |
| CN104156288B (en) * | 2014-06-26 | 2018-01-05 | 西安空间无线电技术研究所 | A kind of fault location and software upgrading circuit and its implementation based on JTAG chains |
| CN104901830A (en) * | 2015-05-12 | 2015-09-09 | 武汉烽火网络有限责任公司 | FPGA online upgrade method in exchanger device, device thereof and system thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100373359C (en) | 2008-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100383737C (en) | SCM online loading and updating method and system | |
| US20100153684A1 (en) | Modular Avionics System of an Aircraft | |
| CN100440805C (en) | Method and system for remote-maintaining JTAG device in ATCA | |
| CN101645055B (en) | Logic device on-line loaded method, system and processor | |
| CN100498708C (en) | Firmware download method and device using personal computer | |
| CN102541942B (en) | Data bulk transfer system and method thereof | |
| CN1858723A (en) | JIAG linkage method and device for using said method | |
| EP2469407A1 (en) | Method of bypassing an AUTOSAR software component of an AUTOSAR software system | |
| CN101630182A (en) | Computer system capable of configuring SIO | |
| CN101872308A (en) | Memory bar control system and control method thereof | |
| US7716458B2 (en) | Reconfigurable integrated circuit, system development method and data processing method | |
| CN101582688A (en) | Dynamic configuration circuit with FPGA loading mode | |
| CN111190855A (en) | FPGA multiple remote configuration system and method | |
| CN101313290B (en) | Performing an N-bit write access to an MxN-bit-only peripheral | |
| CN104866460A (en) | Fault-tolerant self-adaptive reconfigurable system and method based on SoC | |
| CN201400787Y (en) | Computer control system of embroidery machine | |
| CN109491959A (en) | A kind of programmable logic device configurator | |
| CN100495954C (en) | Method and system for loading or updating logic device | |
| CN101140315A (en) | FPGA logical code downloading method under JTAG downloading mode and downloading system thereof | |
| CN104239084A (en) | Implementing method for automatically loading DSP (digital signal processor) procedures | |
| CN201378317Y (en) | Codes download system adopting JTAG mode | |
| CN104021103A (en) | Serial port expansion device for embedded microprocessor | |
| CN100442254C (en) | Method and device for proceeding on line load against multiple proprammable logic devices | |
| CN104007739A (en) | Charge-discharge middle position computer, numerical control system and working method thereof | |
| CN100395729C (en) | Method for using exterior program storage unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170914 Address after: 065000 Langfang City, Hebei province Guangyang District Golden Triangle District Jin Yu Li 4 Building 6 unit 202 room Patentee after: Dong Chunliang Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: Huawei Technologies Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080305 Termination date: 20180124 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |