CN1848681B - A fast code disturbance generator and realizing method thereof - Google Patents

Abstract

A quick generator of scramble code consists of counter for generating low order counting value, counter for generating high order counting value and at least two sets of displacement registers for quickly converting code number of scramble code to be initial phase of scramble code and for quickly converting initial phase of scramble code to be code word of scramble code at any phase. The method of generating scramble code by utilizing said generator is also disclosed.

Description

A kind of fast code disturbance generator and its implementation

Technical field

The invention belongs to the scrambling generator technical field, specifically a kind of fast code disturbance generator and its implementation.

Technical background

In the WCDMA mobile communication, scrambling generator is one of the most basic theoretical foundation, in the up-downgoing generation and reception of WCDMA, all can use scrambling generator.So-called scrambling generator in fact is exactly the pseudo-random sequence generator of realizing with shift register, and this pseudo random sequence has series of algorithms computings such as good autocorrelation and cross correlation.

In the prior art, the production method of descending scrambler during 3G TS 25.213V3.4.0 distribution has proposed with modulation (Spreading andmodulation) technology, existing descending scrambler production method is as follows:

Descending scrambler has 2 ¹⁸-1=262,143 scramblers, label are 0～262,142.Scrambler is divided into 512 scrambler collection, and each scrambler collection has 16 scramblers, and wherein 1 is main scrambler (primary scrambling code), and other 15 is from scrambler (secondary scrambling code).Main scrambler comprises scrambler n=16 * i (i=0～511), i the collection comprise scrambler 16 * i+k (k=1～15) from scrambler.Main scrambler and be unique correspondence from scrambler.Therefore, scrambler k=0～8191 obtain utilizing.

512 main scramblers further are divided into 64 scrambler groups again, and each scrambler group comprises 8 scramblers.16×8×j+16×k(j＝0～63，k＝0～7)。Main scrambler of each cell allocation.

Descending scrambler sequence is to be merged into complex sequences by two real sequences, and each real sequence is added 38400 segments (scrambler length is 38400) of the sequence of generation by two m sequence moulds 2.The generator polynomial exponent number of each m sequence is 18, is 1+x to x ⁷+ x ¹⁸, y is 1+y ⁵+ y ⁷+ y ¹⁰+ y ¹⁸Therefore, scrambler is 38400 segments of Gold sequence.

Above-mentioned explanation be scrambler in the agreement.The concrete generation method of scrambler sees also scrambling generator scrambler generation figure in Fig. 1 prior art.The concrete generation method of scrambler be with scrambler number for the scrambler of n generates with sequence zn, i symbol of zn (i) expression n scrambler.

Initial condition:

x(0)＝1，x(1)＝x(2)＝...＝x(16)＝x(17)＝0

y(0)＝y(1)＝...＝y(16)＝y(17)＝1

Recurrence formula:

x(i+18)＝x(i+7)+x(i)mod2，i＝0，...，2 ¹⁸-20

y(i+18)＝y(i+10)+y(i+7)+y(i+5)+y(i)mod2，i＝0，...，2 ¹⁸-20

Therefore, Gold sequence zn is

z _n(i)＝x((i+n)mod(2 ¹⁸-1))+y(i)mod2，i＝0，...，2 ¹⁸-2.

Then scrambler number for the scrambler of n is:

S _dl，n(i)＝z _n(i)+jz _n(i+M)，i＝0，...，N-1.

Wherein j represents imaginary number, and M=131072, N are chip period, promptly 38400.

When the sign indicating number of configuration number is n, need be to the displacement of the x sequence among Fig. 1 n time, the required scrambler that just can come out then produces the n scrambler if desired M the code word that phase place is later, then needs to continue to be shifted the x sequence being carried out on n basis after the displacement that x sequence and y sequence are carried out M time simultaneously again.

Though prior art provides a kind of concrete generation method of scrambler; but in implementation procedure; run into any yard number the code word that need in very short time, produce needs in arbitrary phase through regular meeting; producing the time that scrambler will postpone n+M at least in this way could produce required code word, does not so just satisfy the requirement of real-time in the implementation procedure probably.Simultaneously, if produce scrambler in real time, the time that can shift to an earlier date n+M produces scrambler, this has no doubt satisfied the requirement of real-time, but in the time of this n+M, this scrambling generator will be monopolized, and can not be used as its way, may need some cover scrambling generators to satisfy search or the demodulation function that realizes different multipaths or channel.The 3rd, the method that produces scrambler has in advance increased the power consumption of device, produces the complexity that scrambler has also increased control in advance.Owing to these 3 reasons, all there is bigger waste in traditional scrambler method for generation on control complexity, power consumption and resource.

Summary of the invention

For overcoming the deficiencies in the prior art, the object of the present invention is to provide a kind of fast code disturbance generator and its implementation, can in the WCDMA system, produce the scrambler of sign indicating number arbitrary phase arbitrarily.

Another object of the present invention is to provide a kind of fast code disturbance generator and its implementation, improves the real-time of scrambler.

A further object of the present invention is to provide a kind of fast code disturbance generator and its implementation, reduces resource occupation, improves multiplexing level, realizes scrambler generation function with less scrambling generator.

For finishing the foregoing invention purpose, the overall technical architecture that the present invention adopts is: a kind of fast code disturbance generator comprises:

One produces the counter of low level count value, and its input receives the scrambler enable signal, and output connects the counter of the high-order count value of a generation, is used to produce the low level count value of the every coefficient of multinomial that resolves into corresponding to scrambler translation sequence number;

One produces the counter of high-order count value, and its input connects the counter of described generation low level count value, is used to produce the high-order count value of two-wheeled;

At least two shift register group, it links to each other with the counter that produces high-order count value with the counter that produces the low level count value, be used for the scrambler sign indicating number number being changed into fast during high-order count value the scrambler first phase producing the first round, producing second scrambling code that the scrambler first phase is transformed into fast when taking turns high-order count value arbitrary phase.

The counter of described generation low level count value is mould 19 counters, and its output connects the input of the counter that produces high-order count value through an OR circuit.

The counter of the high-order count value of described generation is mould 18 counters.

First shift register group of described two shift register group is made up of at least 18 d type flip flops, the x sequence of input scrambler first phase, second shift register group is made up of at least 18 d type flip flops, complete 1 value is inserted the y sequence, is used for that the scrambler sign indicating number number changed into the scrambler first phase fast and the scrambler first phase is transformed into fast the scrambling code of arbitrary phase.

A kind of implementation method of fast code disturbance generator, scrambling generator comprise the counter that produces the low level count value, counter and at least two shift register group that produce high-order count value, and this method may further comprise the steps at least:

The counter of step 1, generation low level count value receives the scrambler enable signal, produces the low level count value and the output of the every coefficient of multinomial that resolves into corresponding to scrambler translation sequence number;

Step 2, the counter that produces high-order count value produce high-order count value of the first round, and two shift register group number change into the scrambler first phase with the scrambler sign indicating number;

The counter of step 3, the high-order count value of generation produces second and takes turns high-order count value, and two shift register group transform into the scrambler first phase scrambling code of arbitrary phase.

Also comprise first shift register group of the scrambler first phase of sub-district to be measured being inserted corresponding x sequence before the described step 1, complete 1 value is inserted the step corresponding to second shift register group of y sequence.

Scrambler enable signal in the described step 1 is effective at high level state.

Multinomial in the described step 1 is meant the x of scrambler translation, the multinomial that the y sequence becomes with Using Convolution.

Described polynomial exponent number is 18.

The every coefficient value of multinomial in the described step 1 is 1 of 1 expression shift register translation, is 0 to represent not translation.

Described step 1 further comprises the steps:

The counter of step 11, generation low level count value receives the scrambler enable signal;

The counter of step 12, generation low level count value produces the low level count value of the every coefficient of multinomial that resolves into corresponding to scrambler translation sequence number;

Step 13, the low level count value that produces is outputed in the counter that produces high-order count value.

Two shift register group number change into the scrambler first phase with the scrambler sign indicating number in the described step 2, and the corresponding register by described two shift register group carries out XOR to be realized.

Step 2 further comprises the steps:

The counter of step 21, the high-order count value of generation produces high-order count value of the first round;

The corresponding register of step 22, two shift register group carries out XOR, and the XOR result is write first shift register group;

Step 23, judge that the low level count value is whether full, discontented then repeating step 22, full then the value of first shift register group is inserted in the corresponding register of second shift register group and first shift register group of zero clearing, the scrambler sign indicating number number is changed into the scrambler first phase fast.

Low level count value in the described step 23 is full of and refers to that the low level count value reaches 18.

Described step 3 further comprises the steps:

The counter of step 31, the high-order count value of generation produces second and takes turns high-order count value;

The corresponding register of step 32, two shift register group is inserted the value of first shift register group in the corresponding register of second shift register group, the scrambler first phase is transformed into fast the scrambling code of arbitrary phase.

The present invention has significant advantage and good effect.Adopt the method for convolution to generate multinomial, the x sequence is carried out rapid traverse produce scrambler number conversion to the scrambler first phase, x sequence and y sequence are carried out the conversion of rapid traverse generation scrambler first phase to any scrambling code phase, can in the WCDMA system, produce the scrambler of sign indicating number arbitrary phase arbitrarily.And improved the real-time that scrambler produces, reduced resource occupation, improved multiplexing level, realized scrambler generation function with less scrambling generator.

Description of drawings

Fig. 1 is that the scrambling generator scrambler produces figure in the prior art;

Fig. 2 is a scrambler generation module sequential chart of the present invention;

Fig. 3 is a formation picture of device of the present invention;

Fig. 4 is mould 18 counter signals processing procedure schematic diagrames of the present invention;

Fig. 5 is two shift register signal processing procedures of the present invention schematic diagram;

Fig. 6 calculates sequential chart for fast code disturbance first phase of the present invention;

Fig. 7 is a main flow chart of the present invention.

Embodiment

Below in conjunction with Figure of description the specific embodiment of the present invention is described.

The computational methods of sign indicating number arbitrary phase scrambler can adopt the method that descending scrambler produces fast arbitrarily.Descending scrambler is gold (Gold) sign indicating number, and according to the periodicity of m, M the m sequence mutually that move to right can realize by original series is done convolution.Scrambler sign indicating number number to the conversion of scrambler first phase and scrambler just in opposite directions the conversion of the scrambling code of arbitrary phase ask exactly the x sequence of descending scrambler or the such problem of initial value behind x sequence and the y sequence translation a from all being the same in essence.

See also Fig. 2 scrambler generation module of the present invention sequential chart, c is a scrambler corresponding phase value on absolute time mark just; I is that the scrambler sign indicating number number changes into the scrambler first phase and begins to calculate constantly, and e is that the scrambler sign indicating number number changes into scrambler first phase finish time, s be scrambler just in opposite directions the arbitrary phase scrambling code transform the finish time.

Like this, only need 18 * 19 * 2 the interior scrambler that just can produce any scrambler sign indicating number arbitrary phase of time.Why identifying this moment of c among the figure, is because scrambler is the m sequence of blocking, so in the scrambler production process, constantly the scrambler first phase must be inserted at c.Can guarantee the continuity of scrambler generator in whole correlated process like this.

For x sequence translation n, the present invention is with a convolution polynomial repressentation that affacts on the shift register, and promptly translation n can resolve into the translation sum that maximum k high repses are not more than k.

So m=0 is at first stored in concrete being calculated as, 1 ..., the convolution multinomial of 17 correspondences

a _m0+a _m1X+...+a _m17X ¹⁷，m＝0，...，17，a _mi＝0，1，i＝0，...，17.

Polynomial coefficient a _Mi=0,1, i=0 ..., 17, m=0 ..., 17., totally 18 groups, polynomial coefficient is 1 to be illustrated in this round translation 1 time, is 0 to represent not translation.

Just the conversion of the scrambling code of arbitrary phase is from all being the same in essence in opposite directions because scrambler sign indicating number number is to the conversion of scrambler first phase and scrambler, and only the former is shifted to the x sequence, and the latter is shifted to x sequence and y sequence.

So-called fast code disturbance generator in fact is made up of two parts function: first is exactly the function that the scrambler sign indicating number number is changed into fast the scrambler first phase; Second portion is exactly the function that the scrambler first phase is transformed into fast the scrambling code of arbitrary phase.What this two parts function was used is with a kind of scrambler generation way.

Be exactly that the scrambler sign indicating number number is changed into the scrambler first phase in the time of among Fig. 2 preceding 18 * 19, the time of back 18 * 19 is exactly the scrambling code that the scrambler first phase is transformed into fast arbitrary phase, and it produces principle is the same.

Produce algorithm according to fast code disturbance, for moving to right of scrambler, need translation x sequence and y sequence, and requirement is from e move to right the possible phase place after n time of scrambler sequence that begins constantly to be shifted, therefore translation n can be resolved into the translation sum that maximum k high repses are not more than k, here k=18.So as shown in Figure 2: when initial value calculated startup e arrival, with the shift register that the scrambler first phase of sub-district to be measured is inserted corresponding x sequence, complete 1 value was inserted the shift register for the y sequence, begins to calculate initial value simultaneously.

For scrambler translation n, the following polynomial repressentation of n:

n＝n ₀+n ₁*2+n ₂*2 ²+n ₃*2 ³+...n ₁₇*2 ¹⁷，n _i＝0，1

18 coefficient n in the formula _iThe counting of corresponding 18 rounds, in following formula, n _iBeing 1, representing that this round translation is effective, is 0 this not translation of round of expression.As can be known, finish altogether here and be not more than 18 translations.

As the counting of shift count in then corresponding every wheel of two groups of polynomial coefficients of table 1 and table 2, if this coefficient is 1, the coefficient of respective items is 1 of 1 expression shift register translation, is 0 to represent not translation. every shift count of taking turns is not more than 18 times.

For the translation of x sequence, the translation of corresponding each round is by following 18 polynomial coefficients (ai, 17ai, 16ai, 15.....ai, 1 ai, 0) decision, for the translation of y sequence, the translation of corresponding each round is by following 18 polynomial coefficients (bi, 17bi, 16bi, 15.....bi, 1 bi, 0) and decision.

Table 1X sequence fast code disturbance generates coefficient table

X sequence round	The x sequence multinomial	X sequence displacement coefficient (ai, 17ai, 16ai, 15.....ai, 1ai, 0)
			u[0]	x	18’b00_0000_0000_0000_0010
u[1]	x2	18’b00_0000_0000_0000_0100
			u[2]	x4	18’b00_0000_0000_0001_0000
u[3]	x8	18’b00_0000_0001_0000_0000
			u[4]	x16	18’b01_0000_0000_0000_0000
u[5]	x3+x10+x14	18’b00_0100_0100_0000_1000
			u[6]	x2+x6+x9+x10+x17	18’b10_0000_0110_0100_0100
u[7]	1+x2+x4+x5+x7+x9+x16	18’b01_0100_0010_1011_0101
			u[8]	x3+x4+x7+x8	18’b00_0000_0001_1001_1000
u[9]	x6+x8+x14+x16	18’b01_0100_0001_0100_0000
			u[10]	x3+x12+x14+x16+x17	18’b11_0101_0000_0000_1000
u[11]	x3+x5+x12+x13+x14+x16+x17	18’b11_0111_0000_0010_1000

X sequence round	The x sequence multinomial	X sequence displacement coefficient (ai, 17ai, 16ai, 15.....ai, 1ai, 0)
			u[12]	x3+x5+x8+x10+x12+x13+x14+x15+x1 6+x17	18’b11_1111_0101_0010_1000
u[13]	x+x2+x3+x5+x9+x10+x13+x14+x15+x 17	18’b10_1110_0110_0010_1110
			u[14]	1+x+x4+x5+x6+x7+x9+x15+x16+x17	18’b11_1000_0010_1111_0011
u[15]	x+x2+x3+x5+x7+x12+x16	18’b01_0001_0000_1010_1101
			u[16]	x2+x3+x4+x13	18’b00_0000_0010_0001_1100
u[17]	x4+x6+x15	18’b00_1000_0000_0101_0000

Table 2Y sequence fast code disturbance generates coefficient table

Y sequence round	The y sequence multinomial	Y sequence displacement coefficient (bi, 17bi, 16bi, 15.....bi, 1bi, 0)
			v[0]	18′h2	18’b00_0000_0000_0000_0010
v[1]	18′h4	18’b00_0000_0000_0000_0100
			v[2]	18′h10	18’b00_0000_0000_0001_0000
v[3]	18′h100	18’b00_0000_0001_0000_0000
			v[4]	18′h10000	18’b01_0000_0000_0000_0000
v[5]	18′h1440a	18’b01_0100_0100_0000_1010
			v[6]	18′h3c04e	18’b11_1100_0000_0100_1110
v[7]	18′h08501	18’b00_1000_0101_0000_0001
			v[8]	18′h341d7	18’b11_0100_0001_1101_0111
v[9]	18′h39712	18’b11_1001_0111_0001_0010
			v[10]	18′h23cb0	18’b10_0011_1100_1011_0000
v[11]	18′h084fc	18’b00_1000_0100_1111_1100
			v[12]	18′h21486	18’b10_0001_0100_1000_0110

Y sequence round	The y sequence multinomial	Y sequence displacement coefficient (bi, 17bi, 16bi, 15.....bi, 1bi, 0)
			v[13]	18′h06e59	18’b00_0110_1110_0101_1001
v[14]	18′h27e51	18’b10_0111_1110_0101_0001
			v[15]	18′h242d8	18’b01_0100_0010_1101_1000
v[16]	18′h3d7ec	18’b11_1101_0100_1110_1100
			v[17]	18′hff60	18’b00_1111_1111_0110_0000

See also Fig. 3 formation picture of device of the present invention.Fast code disturbance generator of the present invention comprises following component part:

One produces counter mould 19 counters 1 (fsr_low_cnt) of low level count value, its input is accepted the scrambler enable signal, output connects the input of counter mould 18 counters 2 of the high-order count value of a generation through OR circuit, the counter that produces the low level count value is used to produce the low level count value, the every coefficient of multinomial that its corresponding scrambler translation sequence number resolves into;

One produces counter mould 18 counters 2 (fsr_high_cnt) of high-order count value, and its input connects the output of described mould 19 counters 1 through OR circuit, can produce the high-order count value of two-wheeled;

Two shift register group 3,4, first shift register group 3 is made up of 18 d type flip flops, the x sequence of input scrambler first phase, second shift register group 4 is shift registers that 18 d type flip flops are formed, complete 1 value is inserted the y sequence, during displacement, two registers group 3,4 corresponding register carries out XOR and the XOR result is write first shift register group 3, when the low level count value is full, the value of first shift register group 3 is inserted in the corresponding register of second shift register group 4, be used in the first round scrambler sign indicating number number being changed into the scrambler first phase fast, second takes turns the scrambling code that the scrambler first phase is transformed into fast arbitrary phase.

See also signal processing schematic diagram of the present invention shown in Figure 4 and Fig. 6 fast code disturbance first phase and calculate sequential chart, generation low level technical value gets counter mould 19 counters a scrambler enable signal (fsr_cal_start) input, and enable signal is effective when high level; Also have a scrambler useful signal (fsr_cal_valid) input, useful signal is effective when high level.After scrambler enable signal (fsr_cal_start) triggers, begin to calculate fast code disturbance, be that scrambler useful signal (fsr_cal_valid) is the state of high level among Fig. 4 the computing time of fast code disturbance, mould 19 counters 1 output signal is 18 a low level count value, the every coefficient of multinomial that the corresponding scrambler translation sequence of low level count value number resolves into, mould 19 counters are connected with mould 18 counters 2 by an OR circuit, mould 18 counters 2 also have enable signal (fsr_cal_start) input, enable signal also is effective when high level, the high-order count value of mould 18 counters, 2 output two-wheeleds.

The signal processing schematic diagram and Fig. 6 fast code disturbance first phase that see also Fig. 5 two registers group of the present invention are calculated sequential chart, fast code disturbance generator realizes in the circuit two shift register group being arranged, first shift register group 3 is made up of 18 d type flip flops, second shift register that shift register group 4 is made up of 18 d type flip flops worked as n _iJust be shifted in=1 o'clock, direction of displacement is among the figure shown in the arrow.

When realizing the fast code disturbance method for generation, at first translation n resolves into:

n＝n ₀+n ₁*2+n ₂*2 ²+n ₃*2 ³+...n ₁₇*2 ¹⁷，n _i＝0，1

n _iIn the count value i of corresponding mould 18 counters of i, i.e. the corresponding mould 18 rolling counters forwards value 0 of n0, n ₁Corresponding mould 18 rolling counters forwards value 1 ..., n ₁₇Corresponding mould 18 rolling counters forwards value 17.

a _IjIn i and n _iI corresponding, a _IjIn the count value j of corresponding mould 19 counters of j, i.e. a _I0Corresponding mould 19 rolling counters forwards value 0, a _I1Corresponding mould 19 rolling counters forwards value 1 ..., a _I17Corresponding mould 19 rolling counters forwards value 17.

Work as a _Ij=1 o'clock, the corresponding register of registers group 3 and registers group 4 carried out XOR, i.e. the D of registers group 3 ₁₇D with registers group 4 ₁₇XOR ..., the D of registers group 3 ₀D with registers group 4 ₀XOR writes registers group 3 with the XOR result then.

Whenever mould 19 rolling counters forwards by 18 o'clock, the value of registers group 3 is inserted in the corresponding register of registers group 4, i.e. the D of registers group 3 ₁₇D with registers group 4 ₁₇Correspondence ..., the D of registers group 3 ₀D with registers group 4 ₀Correspondence is simultaneously with registers group 3 zero clearings.

See also Fig. 7 main flow chart of the present invention, at first, the scrambler first phase of sub-district to be measured is inserted first shift register group 3 of corresponding x sequence, complete 1 value is inserted second shift register 4 for y, begins to calculate initial value simultaneously.

Then, mould 19 counters 1 are accepted the scrambler enable signal at high level state, the low level count value of the every coefficient of multinomial that generation is resolved into corresponding to scrambler translation sequence number, the every coefficient of multinomial that the corresponding scrambler translation sequence of low level count value number resolves into, and output to the OR circuit of a connection mode 18 counters 2.

Mould 18 counters 2 are also effective at high level state, it produces the high-order count value of two-wheeled according to the low level count value of mould 19 counters 1 output, mould 18 counters 2 are from 0～17 counting two-wheeled, in the first round scrambler sign indicating number number is changed into the scrambler first phase fast, take turns the scrambling code that the scrambler first phase is transformed into fast arbitrary phase second. in output first round during high-order count value, the corresponding register of two shift register group carries out computing and operation result is write first shift register group 3, the scrambler sign indicating number number is changed into the scrambler first phase fast. detailed process is: mould 18 counters 2 produce high-order count value of the first round, two shift register group 3,4 corresponding register carries out XOR and the XOR result is write first shift register group 3, when aij=1, the corresponding register of registers group 3 and registers group 4 carries out XOR, be the D17 of registers group 3 and the D17 XOR of registers group 4, ..., the D0 XOR of the D0 of registers group 3 and registers group 4 writes registers group 3. with the XOR result then

Whenever mould 19 counters 1 count down at 18 o'clock, the value of first shift register group 3 is inserted in the corresponding register of second shift register group 4, the D17 that is registers group 3 is corresponding with the D17 of registers group 4, ..., the D0 of registers group 3 is corresponding with the D0 of registers group 4, simultaneously with registers group 3 zero clearings.

Judging that the low level count value is whether full, promptly whether reach 18, is then the value of first shift register group 3 to be inserted in the corresponding register of second shift register group 4, and the scrambler sign indicating number number is changed into the scrambler first phase fast;

Afterwards, mould 18 counters 2 produce second and take turns high-order count value, the corresponding register of two shift register group is inserted the value of first shift register group in the corresponding register of second shift register group, the scrambler first phase is transformed into fast the scrambling code of arbitrary phase.When high-order count value is taken turns in 2 generations second of mould 18 counters, the correspondence of two shift register group 3,4 is deposited the value of first shift register group 3 is inserted in the corresponding register of second shift register group 4, the scrambler first phase is transformed into fast the scrambling code of arbitrary phase.

During as above pseudo-code was described, if calculate the scrambler sign indicating number number conversion to the scrambler first phase, then the n in the formula was scrambler sign indicating number number; If the first arbitrary phase in opposite directions of generation scrambler is as postponing the scrambling code of m code word, then the n in the formula is scrambler m.

The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within the claim scope of the present invention.

Claims (15)

1. fast code disturbance generator is characterized in that it comprises:

One produces the counter of low level count value, and its input receives the scrambler enable signal, and output connects the counter of the high-order count value of a generation, is used to produce the low level count value of the every coefficient of multinomial that resolves into corresponding to scrambler translation sequence number;

One produces the counter of high-order count value, and its input connects the counter of described generation low level count value, is used to produce the high-order count value of two-wheeled;

At least two shift register group, it links to each other with the counter that produces high-order count value with the counter that produces the low level count value, be used for the scrambler sign indicating number number being changed into fast during high-order count value the scrambler first phase producing the first round, producing second scrambling code that the scrambler first phase is transformed into fast when taking turns high-order count value arbitrary phase.

2. fast code disturbance generator according to claim 1 is characterized in that, the counter of described generation low level count value is mould 19 counters, and its output connects the input of the counter that produces high-order count value through an OR circuit.

3. fast code disturbance generator according to claim 1 is characterized in that, the counter of the high-order count value of described generation is mould 18 counters.

4. fast code disturbance generator according to claim 1, it is characterized in that, first shift register group of described two shift register group is made up of at least 18 d type flip flops, the x sequence of input scrambler first phase, second shift register group is made up of at least 18 d type flip flops, complete 1 value is inserted the y sequence, is used for that the scrambler sign indicating number number changed into the scrambler first phase fast and the scrambler first phase is transformed into fast the scrambling code of arbitrary phase.

5. the implementation method of a fast code disturbance generator, scrambling generator comprise the counter that produces the low level count value, counter and at least two shift register group that produce high-order count value, it is characterized in that this method may further comprise the steps at least:

The counter of step 1, generation low level count value receives the scrambler enable signal, produces the low level count value and the output of the every coefficient of multinomial that resolves into corresponding to scrambler translation sequence number;

Step 2, the counter that produces high-order count value produce high-order count value of the first round, and two shift register group number change into the scrambler first phase with the scrambler sign indicating number;

The counter of step 3, the high-order count value of generation produces second and takes turns high-order count value, and two shift register group transform into the scrambler first phase scrambling code of arbitrary phase.

6. the implementation method of fast code disturbance generator according to claim 5, it is characterized in that, also comprise first shift register group of the scrambler first phase of sub-district to be measured being inserted corresponding x sequence before the described step 1, complete 1 value is inserted the step corresponding to second shift register group of y sequence.

7. the implementation method of fast code disturbance generator according to claim 5 is characterized in that, the scrambler enable signal in the described step 1 is effective at high level state.

8. the implementation method of fast code disturbance generator according to claim 5 is characterized in that, the multinomial in the described step 1 is meant the x of scrambler translation, the multinomial that the y sequence becomes with Using Convolution.

9. the implementation method of fast code disturbance generator according to claim 8 is characterized in that, described polynomial exponent number is 18.

10. the implementation method of fast code disturbance generator according to claim 8 is characterized in that, the every coefficient value of the multinomial in the described step 1 is 1 of 1 expression shift register translation, is 0 to represent not translation.

11. the implementation method of fast code disturbance generator according to claim 5 is characterized in that, described step 1 further comprises the steps:

The counter of step 11, generation low level count value receives the scrambler enable signal;

The counter of step 12, generation low level count value produces the low level count value of the every coefficient of multinomial that resolves into corresponding to scrambler translation sequence number;

Step 13, the low level count value that produces is outputed in the counter that produces high-order count value.

12. the implementation method of fast code disturbance generator according to claim 5, it is characterized in that, two shift register group number change into the scrambler first phase with the scrambler sign indicating number in the described step 2, and the corresponding register by described two shift register group carries out XOR to be realized.

13. the implementation method of fast code disturbance generator according to claim 5 is characterized in that step 2 further comprises the steps:

The counter of step 21, the high-order count value of generation produces high-order count value of the first round;

The corresponding register of step 22, two shift register group carries out XOR, and the XOR result is write first shift register group;

Step 23, judge that the low level count value is whether full, discontented then repeating step 22, full then the value of first shift register group is inserted in the corresponding register of second shift register group and first shift register group of zero clearing, the scrambler sign indicating number number is changed into the scrambler first phase fast.

14. the implementation method of fast code disturbance generator according to claim 13 is characterized in that, the low level count value in the described step 23 is full of and refers to that the low level count value reaches 18.

15. the implementation method of fast code disturbance generator according to claim 5 is characterized in that, described step 3 further comprises the steps:

The counter of step 31, the high-order count value of generation produces second and takes turns high-order count value;

The corresponding register of step 32, two shift register group is inserted the value of first shift register group in the corresponding register of second shift register group, the scrambler first phase is transformed into fast the scrambling code of arbitrary phase.

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