CN101222318A - Chaotic sequence generation method and sequence generator of high speed high-precision chaotic function - Google Patents

Abstract

The invention discloses a chaotic sequence generation method and a sequence generator for high-speed high-accuracy chaotic functions. An initial key circuit stores the initial value of a chaotic latch unit, a u value key circuit stores a sequence ui value; each cp chaotic function finishes one-time interactive operation: a bitwise conversion circuit outputs a bitwise XOR to the chaotic latch unit, the bitwise XOR is used to realize a subtraction operation N minus one and minus the absolute value of xi and so on; a shift data selector takes the ui as an address code of the data selector, the data is shifted with a plurality of bits toward right, then the subtraction is used to realize a multiplication that the ui is multiplied by the data; the subtraction result is stored into the chaotic latch unit at the rising edge of the cp, each cp generates a 160-bit chaotic output; the randomness is good due to the existence of an initial key and a u value key; the precision is far greater than that of the double type, the cycle of the cp can reach 90ns, the encryption of a 128-bit plaintext needs 1.7us; the invention can be realized by using FPGAs, GPLDs and ASICs and so on, and is used in the network security technical field, particularly in the wireless networks and the wireless sensor networks.

Description

The chaos sequence generation method of high speed high-precision chaotic function and sequencer

(1) technical field

The invention belongs to the network security technology field, specifically a kind of chaos sequence generation method of high speed high-precision chaotic function and sequencer.

(2) technical background

Encryption is the important means of guaranteeing data security property now.The rise of Internet, wireless network and wireless sensor network at present makes encryption technology become and becomes more and more important.Traditional cryptographic means such as DES though present all use very extensive such as RSA also shows very strong fail safe, finish under the sufficient prerequisite based on resource, are not suitable for the wireless network and the wireless sensor network of resource wretched insufficiency.For example DES decodes now, slow 100 times of RSA speed than DES, and the computing cost is very high, and ellipse garden curve is encrypted and is expended great amount of hardware resources, and quantum cryptography is the encryption technology that is perfectly safe in theory, but is in the exploratory development stage.Occurred a kind of chaos encrypting method at present, it utilizes in the chaos system the initial value sensitivity, and is unpredictable, and characteristics such as topology dependence produce secret key, and then encrypt, and show than conventional cryptography more performance.But because of speed slower, the floating-point operation difficulty, finite precision effect, problems such as short period response make it not be used widely.

Chaos system be because to the sensitiveness of initial value, very little initial value error just can be amplified by system, so the chronicity of system is uncertain, so it can produce random number series, is well suited for the sequential encryption technology.See in theory and utilize chaos principle that data are encrypted, can take precautions against attack methods such as frequency analysis attack, exhaustive attack, make that password is difficult to analyze, decode.

The problem that existing chaos encrypting method exists:

1. finite precision effect

Most of chaotic functions all are to be based upon earlier on the strict Fundamentals of Mathematics, study with mathematical method, utilize chaotic function strict on this mathematics to realize chaos sequence generator then, reality always realizes under limited precision, the result is incomplete same with its mathematical theory, makes manyly can't realize based on mathematical chaos system.The scholar is arranged even thinks that finite precision effect is a great problem that occurs during present chaology is moved towards to use:

1. the generation of a lot of chaos sequences realizes with computer or programming device, for example uses computer C language and C ⁺⁺Programming, the highest with the precision of double, the double data are expressed as d * 10 ^J, wherein d is a mantissa, and J is an index, and double 64 bits commonly used are represented d and J, and precision depends on the figure place of d, the number of bits of d≤56, higher accuracy computation machine is difficult for realizing.As realizing that with programming device for example Nios CPU only can be configured to 16 * 16 → 32 hardware multipliers; And the C54x CPU of dsp chip only is 17 * 17 hardware multipliers, and adder only is 40.This shows that the precision such as the Lorenz chaos system that realizes with FPGA and dsp chip hardware multiplier and adder must be lower than the double type.

2. also the generation of a lot of chaos sequences is to adopt modulus integrating circuit and analog to digital conversion circuit ADC, and for example the Lorenz chaos system also often adopts the integrating circuit that operational amplifier is formed.Integrating circuit is an analog circuit, and analog circuit is influenced seriously by zero drift and thermal noise, and precision is far below digital circuit; ADC cost height, ADC precision only are tens, and figure place is difficult to improve again, does not see 50 ADC as yet, and obviously the ADC precision is far below computer double type.

Realize that the chaos system that number of bits=160,256 etc. are higher than double type precision has not yet to see report.

2. the difficulty of in wireless network and wireless sensor network, using.

Wireless network and wireless sensor network are current important development directions, but the wireless sensor network node volume is little, and computing capability is low, memory space is few, the resource wretched insufficiency; Because of using powered battery, also has the requirement of low energy consumption and real-time again.At present the chaotic maps encryption system is based on that the sufficient legacy network of resource finishes, and to the wireless network and the wireless sensor network of resource wretched insufficiency, can not copy the information security method and the thinking of legacy network fully.The little node of a volume of wireless sensor network also will be finished Routing Protocol except chaos encryption, functions such as and multiple sensor data acquisition and wireless receipts/send out are finished encryption under resource is serious restricted, and this is the difficult problem of another kind of type.For example, be about at the program capacity and finish these tasks in the 4K byte, be exactly a very difficult thing.

Because of figure place is high more, multiplication speed is slow more, and the hardware device amount is big more, for improving data precision, avoids multiplying as far as possible, each iterative process, and the multiply-add operation number of times is few more good more, does not preferably have multiplying, and reduces operation times as far as possible.Because of node powered battery, particularly wireless sensor network node militarily are to arrive the enemy with the aircraft throwing, battery is changed in inconvenience, requires energy consumption extremely low again, operand and receipts/send out time minimizing as far as possible, and require high-speed cruising.Chaotic maps is used for wireless network and wireless sensor network is brand-new problem,

3. short period response

The research of existing chaos sequence is to be based upon in the statistical analysis for the estimation of the periodicity pseudo-randomness of institute's formation sequence, complexity, cross correlation etc., be difficult to guarantee its each realize sequence cycle (t → ∞) enough greatly, complexity is enough high, reduced the confidentiality of chaos encryption system to a certain extent, thereby can not make the people adopt it to encrypt relievedly.Under the situation that the short period response exists, the security performance that improves the chaos encryption system is the problem of a very worth research.

Some researchs at present adopt fully long running time T to carry out computer simulation for meeting the condition of t → ∞ on the mathematics, and during as T=24 or the more time, the randomness of the chaos sequence that thus chaos system is described and is generated is good, meets the mathematics requirement.Yet from practical aspect, the network node powered battery is especially for (node is hidden the enemy) in the military affairs, battery is changed in inconvenience, requires energy consumption extremely low, and it is fast that speed is wanted, operating time will lack, and can not work in continuous 24 hours, and the short period Computer simulation results is all the better near actual.

(3) summary of the invention

The present invention seeks to disclose a kind of precision height, speed height, circuit is simple, is adapted at using in wireless network and the wireless sensor network chaos sequence generation method of the high speed high-precision chaotic function that Information Security is good.

The chaos sequence generation method of high speed high-precision chaotic function of the present invention is achieved in that this high speed high-precision chaotic function is a kind of chaotic function f (x that meets the computer hardware characteristics _i), be expressed as

N=2 ^K, K=positive integer, formula one

| x _i| ∈ [0,2N-1], | μ _i| ∈ [0,2], formula two

According to described chaotic function f (x _i) the chaos sequence generation method finished is as follows:

Chaos value x _iExist in the chaos latch, the chaos latch is by K+1 D-latch Q _KQ _K-1Q _K-2～Q ₀Form, wherein Q _KDeposit x _iSymbol, Q _K-1Q _K-2～Q ₀Deposit x _iAbsolute value | x _i|; Initial value key circuit is deposited chaos latch initial value, and μ value key circuit is deposited sequence μ _iValue; The lead code decision circuit judges whether come, signal is not come, and opens trigger Q if sending signal _S=0, chaos latch initial value is inserted Q _KQ _K-1Q _K-2～Q ₀Signal is come, and puts Q immediately _S=1, start chaos sequence generator, each clock cp chaos sequence generator is carried out a chaotic function interative computation, generates a K position chaos output Y _K-1～Y ₀The concrete method that generates 1 chaos output is: 1. the step-by-step translation circuit is with Q _K-1And Q _K-2～Q ₀Make the step-by-step XOR, carry out the subtraction N-1-|x of formula one thus _i| or | x _i|-N, output d _K-2～d ₀2. the shifted data selector is with μ _iAs the address code of data selector, with data d _K-2～d ₀H μ moves to right _i+ c position carries out 2 thus ^{-(h μ i+c)}* data d _K-2～d ₀, output g _K-2-c～g ₀3. subtraction circuit carries out d earlier _K-2～d ₀Subtract g _K-2-c～g ₀=S _K-2～S ₀, the then S as a result of subtraction _K-2～S ₀With line to moving to left 1, extreme lower position 1, i.e. the input D of D-latch _K-1Meet S _K-2, D _K-2Meet S _K-3... D ₁Meet S ₀, D ₀Connect 1; Realize the multiplication μ of formula two thus with subtraction circuit _i* data ± 1=2 (1-2 ^{-(h μ i+c))}* data and ± 1, subtraction circuit output D _K-1D _K-2～D ₀4. at the cp rising edge subtraction circuit is exported D _K-1D _K-2～D ₀Deposit chaos latch Q in _K-1Q _K-2～Q ₀, and with μ _iValue sign bit and Q _K-1XNOR is deposited Q _K5. chaos output circuit Q _KAnd Q _K-1～Q ₀Step-by-step XOR and Q _KNegate is with positive negative binary number Q _KQ _K-1～Q ₀Be converted into positive binary number chaos output Y _K-1～Y ₀After this each cp is repeated above-mentioned steps 1.～5. carry out, constantly produce chaos output Y _K-1～Y ₀, generate chaos sequence output.

The chaos sequence generation method of chaotic function of the present invention also has some technical characterictics like this:

1, gets K=160, N=2 ¹⁶⁰, μ j 〉=0, c=10, h=4, chaos value x _iExist in the chaos latch, the chaos latch is by 161 D-latch Q ₁₆₀Q ₁₅₉Q ₁₅₈～Q ₀Form, wherein Q ₁₆₀Deposit x _iSymbol, Q ₁₅₉Q ₁₅₈～Q ₀Deposit x _iAbsolute value | x _i|; Initial value key circuit is deposited chaos latch initial value, and μ value key circuit is deposited sequence μ _iValue; The lead code decision circuit is judging whether come, signal is not come, and opens trigger Q if sending signal _S=0, chaos latch initial value is inserted Q ₁₅₉Q ₁₅₈～Q ₀Signal is come, and puts Q immediately _S=1, chaos sequence generator is started working, and each clock cp chaos sequence generator is finished the chaotic function interative computation one time, generates a K position chaos output Y ₁₅₉～Y ₀A concrete chaos output intent that generates is that 1. the step-by-step translation circuit is with Q ₁₅₉And Q ₁₅₈～Q ₀Make the step-by-step XOR, carry out the subtraction N-1-|x of formula one thus _i| or | x _i|-N, output d ₁₅₈～d ₀2. the shifted data selector is with μ _iAs the address code of data selector, with data d ₁₅₈～d ₀4 μ move to right _i+ 10, carry out 2 thus ^{-(4 μ i+10)}* data d ₁₅₈～d ₀, output g ₁₄₈～g ₀3. subtraction circuit carries out d earlier ₁₅₈～d ₀Subtract g ₁₄₈～g ₀=S ₁₅₈～S ₀, follow S as a result with subtraction ₁₅₈～S ₀With line to moving to left 1, extreme lower position 1, i.e. D ₁₅₉Meet S ₁₅₈, D ₁₅₈Meet S ₁₅₇... D ₁Meet S ₀, D ₀Connect 1, realize the multiplication μ of formula two thus with subtraction circuit _i* data ± 1=2 (1-2 ^{-(4 μ i+10)}) * data and ± 1, subtraction circuit output D ₁₅₉D ₁₅₈～D ₀4. at the cp rising edge subtraction circuit is exported D ₁₅₉D ₁₅₈～D ₀Deposit chaos latch Q in ₁₅₉Q ₁₅₈～Q ₀, and with Q ₁₅₉Deposit Q ₁₆₀5. chaos output circuit Q _KAnd Q _K-1～Q ₁Step-by-step XOR and Q _KNegate is with positive negative binary number Q ₁₆₀Q ₁₅₉～Q ₀Be converted into positive binary number chaos output Y ₁₅₉～Y ₀After this each cp is repeated above-mentioned steps 1.～5. carry out, constantly produce chaos sequence output Y ₁₅₉～Y ₀

Another purpose of the present invention is the chaos sequence generator that discloses a kind of high speed high-precision chaotic function, and this chaos sequence generator core comprises chaos latch, step-by-step translation circuit, shifted data selector, subtraction circuit and chaos output circuit: 1. the chaos latch is by K+1 position D-latch Q _KQ _K-1Q _K-2～Q ₀Form highest order Q _KThe is-symbol position, other K position Q _K-1Q _K-2～Q ₀Be the chaos data bit, Q _K-1Q _K-2～Q ₀Output connect step-by-step translation circuit input; 2. the step-by-step translation circuit is made up of K-1 XOR gate, and each XOR gate has an input to meet Q _K-1, another input meets Q successively _K-2～Q ₀, step-by-step translation circuit output d _K-2～d ₀Both connect the input of shifted data selector data, connect the subtraction circuit input again; 3. the shifted data selector is made up of K-2-c data selector, and its address code input connects the output of μ value key circuit, and its data input connects the output of step-by-step translation circuit, and its output connects the subtraction circuit input, output g _K-2-c～g ₀4. subtraction circuit is made up of K-1 position binary adder and inverter; The adder input meets d _K-2～d ₀With inverter output, the inverter input meets g _K-2-c～g ₀, subtraction circuit output D _K-1D _K-2～D ₀Meet chaos latch Q _K-1Q _K-2～Q ₀D input, Q _K-1And μ _iSign bit is different non-or meet Q _KD input; 5. chaos output circuit Q _KAnd Q _K-1～Q ₁Step-by-step XOR and Q _KWith μ _iThe sign bit XOR is with positive negative binary number Q _KQ _K-1～Q ₀Be converted into positive binary number chaos output Y _K-1～Y ₀K position chaotic signal of each clock cp output; In addition, also have initial value key circuit, μ value key circuit, lead code decision circuit and open trigger, initial value key circuit is put the number input with the initial value key for presetting several chaos latch initial values that connect, and μ value key circuit connects the input of shifted data selector address with sequence μ value; The lead code decision circuit receives and judges whether wireless receipts/signalling comes, and opens flip-flop toggle and stops foregoing circuit.

The chaos sequence generator of chaotic function of the present invention also comprises some technical characterictics like this:

1, gets K=160, N=2 ¹⁶⁰, μ _i〉=0, c=10, h=4, the chaos sequence generator core of high speed high-precision chaotic function comprises chaos latch, step-by-step translation circuit, shifted data selector, subtraction circuit and chaos output circuit: 1. the chaos latch is by 161 D-latch Q ₁₆₀Q ₁₅₉Q ₁₅₈～Q ₀Form highest order Q ₁₆₀The is-symbol position, other 160 Q ₁₅₉Q ₁₅₈～Q ₀Be the chaos data bit, Q ₁₅₉Q ₁₅₈～Q ₀Output connect step-by-step translation circuit input; 2. the step-by-step translation circuit is made up of 158 XOR gate, and each XOR gate has an input to meet Q ₁₅₉, another input meets Q successively ₁₅₈～Q ₀, step-by-step translation circuit output d ₁₅₈～d ₀Both connect the input of shifted data selector data, connect the subtraction circuit input again; 3. the shifted data selector is made up of 149 data selectors, and its address code input connects the output of μ value key circuit, and its data input connects the step-by-step translation circuit, and its output connects the subtraction circuit input, output g ₁₄₈～g ₀4. subtraction circuit is made up of 158 binary adders and inverter; The adder input connects by d ₁₅₈～d ₀With inverter output, the inverter input meets g ₁₄₈～g ₀, subtraction circuit output D ₁₅₉D ₁₅₈～D ₀Meet chaos latch Q ₁₅₉Q ₁₅₈～Q ₀D input, Q ₁₅₉Meet Q ₁₆₀D input; 5. chaos output circuit Q ₁₆₀And Q ₁₅₉～Q ₁Step-by-step XOR and Q ₁₆₀Negate is with positive negative binary number Q ₁₆₀Q ₁₅₉～Q ₀Be converted into positive binary number chaos output Y ₁₅₉～Y ₀160 chaotic signals of each clock cp output; In addition, also have initial value key circuit, μ value key circuit, lead code decision circuit and open trigger, initial value key circuit is put the number input with the initial value key for presetting several chaos latch initial values that connect, and μ value key circuit connects the input of shifted data selector address with sequence μ value; The lead code decision circuit receives and judges whether wireless receipts/signalling comes, and opens flip-flop toggle and stops foregoing circuit.

The advantage that shows in chaos sequence generation method specific implementation of the present invention and the sequencer hardware is described in detail as follows:

(1) finish with high speed high-precision chaotic function f (x) and remove the multiplication and division computing and only illustrate with the method for a subtraction:

Finite precision effect is a great problem that present chaology is moved towards application, and the Logistic chaotic function needs 2 multiplyings and 1 subtraction; The Lorenz chaotic function needs 5 multiplyings and 4 subtractions, and speed is slow, and precision is low; No matter be with software or hardware, multiplying is the major obstacle that improves precision and speed, and the present invention finishes with f (x) and removes multiplication and division, only with a subtraction.Get μ in formula one and the formula two _i〉=0, draw

| x| ∈ [0,2N-1], μ ∈ [0,2] formula three

Remove multiplication and division, only simplification and the formula three with subtraction and circuit has utmost point confidential relation, convolution three describes chaos sequence generator core circuit Figure 71 of Qian chaotic function f of the present invention (x) in detail, and describe the advantage have in detail (for intuitively, getting K=160 illustrates, K is got arbitrary value, reason is identical, as gets K=296):

1. realize subtraction with the step-by-step XOR.Establish K=160 in the formula three, N-1=2 ¹⁶⁰-1, use Q ₁₅₉Q ₁₅₈Q ₀Represent 160 bigits | x _i|, N-1 equals low 159 (bit ₁₅₈Bit ₀) all be 1.When | x _i| (Q during≤N-1 ₁₅₉=0) N-1-|x in, the execution formula three _i|, just right | x _i| in Q ₁₅₈～Q ₀Carry out the step-by-step negate, and Q ₁₅₉Constant, replace subtraction N-1-|x with the step-by-step negate _i|; When | x _i| (Q during＞N-1 ₁₅₉In=1), the execution formula three | x _i|-N, also promptly only with highest order Q ₁₅₉Subtract 1, Q ₁₅₈～Q ₀Constant; Q is merged in two kinds of computings ₁₅₉And Q ₁₅₈～Q ₀Carry out the step-by-step XOR, draw 159 XOR output d ₁₅₈～d ₀, two kinds of situation Q ₁₅₉In fact and x value _iSymbol is identical, can temporarily preserve Q ₁₅₉, not with Q ₁₅₉Subtract 1, Q when moving to left later on ₁₅₉Naturally lose.Only need t time of delay of one-level XOR gate _Pd, high more a lot of than traditional subtraction speed, data bits is many more, and this advantage is outstanding more.

2. finish data (h μ with the shifted data selector _i+ c) gt.Select for use μ to be selected in 2 (1-2 ^-50) and 2 (1-2 ^-8) between, the μ in the formula three _i* data=2 (1-2 ^{-(h μ i+c)}) * data, d and c are integer, get c=10, h=4.The μ sequence table is shown μ ₀μ ₁μ ₂μ _iμ _U-1μ _u, have in the μ value key circuit this circuit output μ in the i time iteration _i, with μ _iAs the address code of data selector, finish d ₁₅₈～d ₀(4 μ move to right _i+ 10) position promptly realizes 2 ^{-(4 μ i+10)}* data d ₁₅₈～d ₀=data selector output g ₁₄₈～g ₀Every iteration once changes the primary address sign indicating number, finishes the data multidigit with data selector and moves to right, and speed is fast.

3. replace multiplying with subtraction.Carry out subtraction 2 (1-2 with subtraction circuit ^{-(h μ i+c)}* (d ₁₅₈～d ₀)=2 ((d ₁₅₈～d ₀)-(g ₁₄₈～g ₀)); Earlier carry out (d by subtraction ₁₅₈～d ₀)-(g ₁₄₈～g ₀), be output as S ₁₅₈S ₀, must no-carry, then with S ₁₅₈S ₀Take advantage of 2, be about to S ₁₅₈S ₀Move to left 1 again.Move to left 1 and be equivalent to output line S ₁₅₈S ₀Change, promptly press D successively ₁₅₉← S ₁₅₈, D ₁← S ₀, D ₂← S ₁Connect, wherein D ₁₅₉D ₁₅₈D ₂D ₁D ₀Being subtraction circuit output, also is chaos latch Q ₁₅₉Q ₁₅₈Q ₂Q ₁Q ₀The D input, be about to S ₁₅₈S ₁₅₇S ₁S ₀Deposit Q separately ₁₅₉Q ₁₅₈Q ₂Q ₁, only change the output line, need not any gate circuit.The remaining Q in back moves to left ₀ Set 1, i.e. Q ₀← 1, be equivalent in the formula (1) ± 1; The result draws 160 bit data Q ₁₅₉Q ₁₅₈Q ₂Q ₁Q ₀, need in the shifting process temporarily to be kept at Q ₁₅₉Sign bit deposit Q in ₁₆₀, i.e. Q ₁₆₀← Q ₁₅₉This shows, high more a lot of with the multiplying in the subtraction replacement formula three than multiplying speed, increase with chaos latch figure place, leading borrow subtraction circuit is than the easy realization of mlultiplying circuit.

4. realize the output of chaos data with the step-by-step XOR.Sign bit Q ₁₆₀=0 expression positive number, Q ₁₆₀=1 expression negative because of binary number only uses 0 and 1, does not have-1, should be integer with positive and negative number conversion, subtracts above-mentioned 160 bit data Q with 2N-1 for this reason ₁₅₉Q ₁₅₈Q ₂Q ₁Q ₀If Q ₁₆₀=0, all be 1 because of 2N-1 is 160, subtract Q with 2N-1 ₁₅₉Q ₁₅₈Q ₂Q ₁Q ₀, be equivalent to Q ₁₅₉Q ₁₅₈Q ₂Q ₁Q ₀The step-by-step negate; If Q ₁₆₀=1,2N-1 Reduction of Students' Study Load Q then ₁₅₉Q ₁₅₈Q ₂Q ₁Q ₀, be 2N-1 and add Q ₁₅₉Q ₁₅₈Q ₂Q ₁Q ₀, note Q ₀=1, so Q ₀=1 with 2N-1 in-1 offset, 2N is exactly Q ₁₆₀=1, the result draws Q ₁₆₀=1, Q ₀=0, all the other Q ₁₅₉Q ₂Q ₁Constant.Because of two kinds of situation Q ₀Be 0 all, deletion Q during output ₀Use Q ₁₆₀And Q ₁₅₉Q ₂Q ₁By realizing Y for XOR ₁₅₈Y ₁Y ₀, highest order Q ₁₆₀Negate gets Y ₁₅₉, draw 160 chaos data output Y ₁₅₉Y ₁₅₈Y ₁Y ₀The output of chaos data is preferably in the later half cycle of clock.Here subtraction (2N-1 subtracts 160 bit data) is also finished with step-by-step XOR and negate, and one-level XOR gate speed is much larger than subtraction circuit speed.

(2) realization of the particular hardware of chaos sequence generator and the course of work: Figure 70 are the chaos sequence generator calcspar of high speed high-precision chaotic function of the present invention.Detailed circuit is Figure 71 in the dotted line of Figure 70, and promptly Figure 71 is the chaos sequence generator core circuit diagram of high speed high-precision chaotic function of the present invention.Make x _I+1=f (x _i), x _iBe the i time iterative value, the chaos latch is by 161 D-latch Q among Figure 71 ₁₆₀Q ₁₅₉～Q ₀Form, use Q ₁₆₀Deposit Chaos Variable x _iSymbol, Q ₁₅₉～Q ₀Absolute value | x _i|, it includes 160 and has the d type flip flop Q that clock presets several functions ₁₅₉～Q ₀, this d type flip flop structure is shown in Figure 72, and wherein control end E meets Q _SWireless receipts/send out chip to receive/send out process in data always send lead code earlier, then are only address code and data and check code, lead code is that steering signal is received/sent out to data, requisite, lead code and receipts/send out data time to determine at interval, can be used as the synchronizing signal of chaos enciphering/deciphering.

Referring to Figure 70, the lead code decision circuit judges that whether send signal comes, and before signal is come, opens trigger Q _S=0 (E=0) under the cp effect, puts initial value (as the initial value key) as going into the chaos latch, and μ value key circuit deposits μ value key in; In case the lead code decision circuit is judging that sending signal comes, and opens trigger and puts 1 immediately, be i.e. Q _S=1 (E=1), under clock cp effect, by following step 1.～5. each cp finish interative computation one time.1. the chaos latch is by 161 D-latch Q ₁₆₀Q ₁₅₉Q ₁₅₈～Q ₀Form highest order Q ₁₆₀The is-symbol position, other 160 Q ₁₅₉Q ₁₅₈～Q ₀Be the chaos data bit, Q ₁₅₉Q ₁₅₈～Q ₀Output connect step-by-step translation circuit input; 2. the step-by-step translation circuit is made up of 158 XOR gate, and each XOR gate has an input to meet Q ₁₅₉, another input meets Q successively ₁₅₈～Q ₀, step-by-step translation circuit output d ₁₅₈～d ₀Both connect the input of shifted data selector data, connect the subtraction circuit input again; 3. the shifted data selector is made up of 149 data selectors, and its address code input connects the output of μ value key circuit, and its data input connects the step-by-step translation circuit, and its output connects the subtraction circuit input, output g ₁₄₈～g ₀4. subtraction circuit is made up of 158 binary adders and inverter; The adder input connects by d ₁₅₈～d ₀With inverter output, the inverter input meets g ₁₄₈～g ₀, subtraction circuit output D ₁₅₉D ₁₅₈～D ₀Connect chaos latch D input; 5. chaos output circuit Q ₁₆₀And Q ₁₅₉～Q ₁Step-by-step XOR and Q ₁₆₀Negate is with positive negative binary number Q ₁₆₀Q ₁₅₉～Q ₀Be converted into positive binary number chaos output Y ₁₅₉～Y ₀160 chaotic signals of each clock cp output; In addition, also have initial value key circuit, μ value key circuit, lead code decision circuit and open trigger, initial value key circuit is put the number input with the initial value key for presetting several chaos latch initial values that connect, and μ value key circuit connects the input of shifted data selector address with sequence μ value; The lead code decision circuit receives and judges whether wireless receipts/signalling comes, and opens flip-flop toggle and stops foregoing circuit.Situation uses the start-up portion that sends data to replenish as lead code on demand, and lead code is to receive/send out the enabling signal of data, by the synchronizing signal that can be used as chaos sequence generator (comprising that lead code is additional).

The chaos sequence generator data output Y of circuit performance and Computer simulation results: high speed high-precision chaotic function f of the present invention (x) ₁₅₉～Y ₀Divide 5 sections demonstrations (the ∵ computer is the highest with the precision of double, but display precision is number of bits≤56), these 5 sections is Y successively ₁₅₉～Y ₁₂₈, Y ₁₂₇～Y ₉₆, Y ₉₅～Y ₆₄, Y ₆₃～Y ₆₂, Y ₃₁～Y ₀Figure 83, Figure 84, Figure 85, Figure 86, Figure 87 are 5 sections output waveforms, and every figure output amplitude is about 2 ³²=4.29 * 10 ⁹Figure 73, Figure 74, Figure 75, Figure 76, Figure 77 are 5 sections output power spectrum density curves; Figure 78, Figure 79, Figure 80, Figure 81, Figure 82 are the correlation properties curves of 5 sections outputs.Above-mentioned Figure 73～Figure 82 is near Figure 39～uniform random number sequence rand and Gaussian Profile random number sequence randn power spectral density and correlation properties curve shown in Figure 42, and power spectrum is smooth, and correlation properties are at one-period point 5 * 10 ⁴Very high very thin spike is arranged everywhere, show that autocorrelation is very strong, other their cross correlation of place's reflection shows that the amplitude of cross correlation is very little.Above-mentioned performance shows that this circuit utilizes the best section of chaotic function f (x), and randomness is best, is suitable for chaos encryption.

(3) advantage of the chaos sequence generation method of high speed high-precision chaotic function and chaos sequence generator:

1. precision height, speed height.Chaos Variable 160 bits, precision are much larger than aforementioned calculation machine double type, much larger than existing chaos encryption circuit.The potentiality that continue to increase figure place are arranged, and subtraction circuit is got key effect to speed when continuing to increase the binary number figure place.Subtraction circuit and XOR gate etc. all are combinational circuits, and each cp finishes interative computation one time, and one time iterative process is only used subtraction 1 time.To CMOS logic application-specific integrated circuit (ASIC), finish 64 ripple carry adders (RCA) and postpone to be about 30ns under 0.5 μ m technology, inverter delay is about 0.43ns, and MUX postpones to be about 2.43ns, three input NOR door triggers postpone to be about 0.85ns, and trigger postpones maximum and is about 9.5ns.160 subtraction circuits add inverter with 160 ripple carry adders to be realized, then postpones to be about 75ns+0.43ns=75.5ns.Calculate cp cycle=75.5+9.5+2.43+0.85 ≈ 88.5ns, get cp cycle=0.1 μ s, encrypting 128 plaintexts needs time=17 * 0.1 μ s=1.7 μ s.If press the middle small scale integrated circuit calculation of parameter, subtraction circuit is realized (negative becomes radix-minus-one complement+1) with 4 full binary adders 283 entirely, shared 40 full adders, then finish 160 and be subtraction needs 40 * 53ns=2.12 μ s, other gate delay＜0.08 μ s, get cp cycle=2.2 μ s, then encrypting 128 plaintexts needs time=17 * 2.2 μ s=37.4 μ s.Speed is much larger than existing chaos encryption circuit.

2. circuit is simple, is adapted at using in wireless network and the wireless sensor network.Show that average every used device is less: (i) chaos sequence generator does not have the multiplication and division computing, replaces multiplying with subtraction, with realization subtraction and output circuits such as step-by-step negates; One of the every increase of data then only needs to increase by 1 trigger, 2 XOR gate, and 1 data selector, and with 1 of subtracter increase.(ii) expressly chaos queuing-chaos XOR circuit is only used 8 data selectors (every usefulness 1/16), 40 XOR gate (every usefulness 1/3.2), 4 8D latchs (every usefulness 1/32), 16 8 bit shift register and other 128 8 bit shift register (every usefulness 1.125).128 refer to all queuing sign indicating number keys and deposit 128 8 bit shift register entirely in, if change every circulation into by 16 queuing sign indicating numbers of the parallel input of computer key, then a queuing sign indicating number key circuit only needs be made up of 88 bit shift register, can reduce 120 8 bit shift register (every usefulness 1/5.3).

3. Information Security is good.Three keys are arranged: initial value key, μ value key and queuing sign indicating number key.Note queuing code bit number is nd, and queuing sign indicating number set of cipher key number is n _Ra, the plaintext figure place $N_{\mathrm{data}}=8\×2^{n_d},$ N _XorPosition D-latch figure place N _Xor=8 * n _d, N _RaPosition ring shift right shift register figure place $N_{\mathrm{ra}}=n_{\mathrm{ra}}\×n_d\×2^{n_d},$ Chaos latch chaos output figure place K=N _Xor+ N _Data, get n _d=4, n _Ra=16, N then _Xor=8 * n _d=32, $N_{\mathrm{data}}=8\×2^{n_d}=128,$ The initial value key is K=N _Data+ N _Xor=160, initial value has 2 ¹⁶⁰≈ 1.46 * 10 ⁴⁸Plant possibility, μ value key has 32 4 system numbers, has 4 ³²≈ 1.84 * 10 ¹⁹Plant possibility μ value sequence; Every group of queuing sign indicating number key $2^{n_d}=16$ Number, total 16!=2.09 * 10 ¹³Plant and to arrange, press n _Ra=16 batch totals are calculated, queuing sign indicating number key nearly (2.09 * 10 ¹³) ¹⁶=1.3 * 10 ²¹³Plant and to arrange; Three keys need exhaustive number of times=1.46 * 10 ⁴⁸* 1.84 * 10 ¹⁹* 1.3 * 10 ²¹³≈ 3.49 * 10 ²⁸⁰, the method for exhaustion is decoded and may not; In addition, 8 input shz ₁～shz ₈Can upset natural order and meet 8 output rsh ₁～rsh ₆, the total 8! of connected mode=40320 kinds, more increase the difficulty that the method for exhaustion is decoded.

If n _d=5, n _Ra=16, then $N_{\mathrm{ra}}=n_d\×n_{\mathrm{ra}}\×2^{n_d}=5\×512,$ Queuing sign indicating number key circuit is formed MUX by 5 512 ring shift right shift registers ₍₁₎～MUX ₍₈₎Be 8 32 and select 1 data selector; N _Xor=8 * n _d=40,40 XOR gate of 40 D-latch figure places and connection thereof are arranged; The plaintext figure place $N_{\mathrm{data}}=8\×2^{n_d}=256,$ 8 32 bit shift register are arranged;

Every circulation has and 33 claps (promptly 2 ^Nd+ 1 claps), ciphering process and above-mentioned similar, the 1st claps 296 chaos output (K=N that earlier chaos sequence generator generated _Xor+ N _Data=40+256=296) insert N _Xor=40 latchs and $N_{\mathrm{data}}=8\×2^{n_d}=8$ Individual 32 bit shift register; The the 2nd～the 33rd claps generation 32 byte ciphertexts (i.e. 256 ciphertexts); The chaos output figure place K=N of chaos sequence generator _Data+ N _Xor=296, the initial value key has 2 ^K=2 ²⁹⁶≈ 1.27 * 10 ⁸⁹Kind, μ value key is the same, a queuing yard key have (32! ) ¹⁶=(2.63 * 10 ³⁵) ¹⁶=5.2 * 10 ⁵⁶⁶Kind, three keys need exhaustive number of times=1.27 * 10 ⁸⁹* 5.28 * 10 ⁵⁶⁶* 1.84 * 10 ¹⁹≈ 1.23 * 10 ⁶⁷⁵, the method for exhaustion is decoded and may not.To reset team be the chaos formula to the serial of system of Himdu logic literary composition again, the plaintext that front and back are identical, the chaos formula is reset team expressly must be inequality, and then with another chaotic signal XOR, encrypt institute draw before and after two ciphertexts more complete inequality, the effect of secondary chaos is arranged.It is short-term response that chaotic signal is reset team to plaintext serial chaos formula, and analytic approach is decoded also not possibility, and it is extremely difficult to crack.Chaos sequence has good statistical property, and it does not meet the probability statistics principle on numeric distribution, has both made traditional chaos encrypting method, to expressly not doing any processing, also thinks feasible.In addition because at a high speed, every cp iteration once, per 17 iteration are just taken out chaotic signal one time, 17 times repeatedly between output bias＞1 time repeatedly between output bias, overcome the short period response of chaos sequence; Can also improve figure place again, overcome the chaos sequence finite precision effect.

(4) description of drawings

Fig. 1 is the curve chart that doubly diverges in the cycle of the computer simulation of Qian chaotic function f of the present invention (x).

Fig. 2 is the Lyapunov index curve diagram of the computer simulation of Qian chaotic function f of the present invention (x).

Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11 are that Qian chaotic function f of the present invention (x) is at μ=2,2 (1-2 successively ^-50), 2 (1-2 ^-40), 2 (1-2 ^-30), 2 (1-2 ^-20), 2 (1-2 ^-10), 2 (1-2 ^-8), 2 (1-2 ^-6), 2 (1-2 ^-4) the power spectral density plot figure of computer simulation.

Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 20 are that Qian chaotic function f of the present invention (x) is at μ=2,2 (1-2 successively ^-50), 2 (1-2 ^-40), 2 (1-2 ^-30), 2 (1-2 ^-20), 2 (1-2 ^-10), 2 (1-2 ^-8), 2 (1-2 ^-6), 2 (1-2 ^-4) the correlation properties curve chart of computer simulation.

Figure 21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, Figure 27, Figure 28, Figure 29 be successively Qian chaotic function f of the present invention (x) in μ=1.1,1.2,1.3,1.4,1.5,1.6,1.7,1.8,1.9 computer simulation power spectral density plot figure.

Figure 30, Figure 31, Figure 32, Figure 33, Figure 34, Figure 35, Figure 36, Figure 37, Figure 38 be successively Qian chaotic function f of the present invention (x) in μ=1.1,1.2,1.3,1.4,1.5,1.6, the correlation properties curve chart of 1.7,1.8,1.9 computer simulation.

Figure 39 and Figure 41 are respectively power spectrum and the correlation properties simulation curve figure of uniform random number sequence rand.

Figure 40 and Figure 42 are respectively power spectrum and the correlation properties simulation curve figure of Gaussian Profile random number sequence randn.

Figure 43, Figure 44, Figure 45, Figure 46, Figure 47, Figure 48, Figure 49, Figure 50, Figure 51 are that the Logistic chaotic function is at μ=2,2 (1-2 successively ^-50), 2 (1-2 ^-40), 2 (1-2 ^-30), 2 (1-2 ^-20), 2 (1-2 ^-10), 2 (1-2 ^-8), 2 (1-2 ^-6), 2 (1-2 ^-4) the power spectral density plot figure of computer simulation.

Figure 52, Figure 53, Figure 54, Figure 55, Figure 56, Figure 57, Figure 58, Figure 59, Figure 60 are that the Logistic chaotic function is at μ=2,2 (1-2 successively ^-50), 2 (1-2 ^-40), 2 (1-2 ^-30), 2 (1-2 ^-20), 2 (1-2 ^-10), 2 (1-2 ^-8), 2 (1-2 ^-6), 2 (1-2 ^-4) the correlation properties curve chart of computer simulation.

Figure 61, Figure 62, Figure 63 are the power spectral density plot figure of the computer simulation of Lorenz chaotic function x, y, z successively.

Figure 64, Figure 65, Figure 66 are the correlation properties curve chart of the computer simulation of Lorenz chaotic function x, y, z successively.

Figure 67, Figure 68, Figure 69 are the phase path figure of the computer simulation of Lorenz chaotic function xy, yz, zx successively.

Figure 70 is the chaos sequence generator calcspar of high speed high-precision chaotic function of the present invention.

Figure 71 is the chaos sequence generator core circuit diagram of high speed high-precision chaotic function of the present invention.

Figure 72 presets the d type flip flop circuit diagram of several functions for tool among Figure 12.

Figure 73, Figure 74, Figure 75, Figure 76, Figure 77 are the chaos sequence generator output Y for high speed high-precision chaotic function of the present invention successively ₁₅₉～Y ₁₂₈, Y ₁₂₇～Y ₉₆, Y ₉₅～Y ₆₄, Y ₆₃～Y ₆₂, Y ₃₁～Y ₀The power spectral density plot figure of computer simulation.

Figure 78, Figure 79, Figure 80, Figure 81, Figure 82 are the chaos sequence generator output Y for high speed high-precision chaotic function of the present invention successively ₁₅₉～Y ₁₂₈, Y ₁₂₇～Y ₉₆, Y ₉₅～Y ₆₄, Y ₆₃～Y ₆₂, Y ₃₁～Y ₀The correlation properties curve chart of computer simulation.

Figure 83, Figure 84, Figure 85, Figure 86, Figure 87 are the chaos sequence generator output Y of high speed high-precision chaotic function of the present invention successively ₁₅₉～Y ₁₂₈, Y ₁₂₇～Y ₉₆, Y ₉₅～Y ₆₄, Y ₆₃～Y ₆₂, Y ₃₁～Y ₀The output curve diagram of computer simulation.

Figure 88 is the chaos encryption circuit diagram of the no multiplication and division of high speed high-precision chaotic function of the present invention.

Figure 89 is the chaos encryption circuit core partial circuit figure that the present invention mixes the no multiplication and division of the ignorant function of high-speed, high precision.

Figure 90, Figure 91, Figure 92 are that chaos encryption circuit computer simulation plaintext data waveform, the plaintext chaos of the no multiplication and division of high speed high-precision chaotic function of the present invention reset rsh waveform after the team, ciphertext z oscillogram successively.

Figure 93, Figure 94, Figure 95 be successively high speed high-precision chaotic function of the present invention no multiplication and division the computer simulation of chaos encryption circuit expressly data, expressly chaos is reset the power spectral density plot figure of rsh, ciphertext Z after the team.

Figure 96, Figure 97, Figure 98 be successively high speed high-precision chaotic function of the present invention no multiplication and division the computer simulation of chaos encryption circuit expressly data, expressly chaos is reset the correlation properties curve chart of rsh, ciphertext Z after the team.

Figure 99, Figure 100, Figure 101 are the figure figure that Figure 90, Figure 91, Figure 92 abscissa amplify successively.

Figure 102 is the chaos decode circuit core partial circuit figure of the no multiplication and division of high speed high-precision chaotic function of the present invention.

Figure 103, Figure 104, Figure 105 are that the chaos decode circuit of the no multiplication and division of high speed high-precision chaotic function of the present invention receives ciphertext z when its three keys and the full simultaneous computer simulation of encrypted circuit successively _rWaveform, z _rRecover expressly data with rsh waveform, deciphering back behind the chaotic signal XOR _rOscillogram.

Figure 106, Figure 107, Figure 108 are that the chaos decode circuit of the no multiplication and division of high speed high-precision chaotic function of the present invention expressly receives ciphertext z when its three keys and the full simultaneous computer simulation of encrypted circuit successively _r, z _rRecover expressly data with rsh, deciphering back behind the chaotic signal XOR _rPower spectral density plot figure.

Figure 109, Figure 110, Figure 111 are that the chaos decode circuit of the no multiplication and division of high speed high-precision chaotic function of the present invention receives ciphertext z when its three keys and the full simultaneous computer simulation of encrypted circuit successively _r, z _rRecover expressly data with rsh, deciphering back behind the chaotic signal XOR _rThe correlation properties curve chart.

Figure 112, Figure 113, Figure 114 be successively high speed high-precision chaotic function of the present invention no multiplication and division the chaos decode circuit when it three keys and encrypted circuit much at one, only have the simulation of minute differences computer-chronograph to receive ciphertext z _rWaveform, z _rRecover expressly data with rsh waveform, deciphering back behind the chaotic signal XOR _rOscillogram.

Figure 115, Figure 116, Figure 117 be successively high speed high-precision chaotic function of the present invention no multiplication and division the chaos decode circuit when it three keys and encrypted circuit much at one, only have the simulation of minute differences computer-chronograph expressly to receive ciphertext z _r, z _rRecover expressly data with rsh, deciphering back behind the chaotic signal XOR _rPower spectral density plot figure.

Figure 118, Figure 119, Figure 120 be successively high speed high-precision chaotic function of the present invention no multiplication and division the chaos decode circuit when it three keys and encrypted circuit much at one, only have the simulation of minute differences computer-chronograph to receive ciphertext z _r, z _rRecover expressly data with rsh, deciphering back behind the chaotic signal XOR _rThe correlation properties curve chart.

(5) embodiment

The present invention is further illustrated for following mask body:

Traditional method is mainly studied chaotic function from mathematics, then mathematical chaotic function is applied in the reality.Yet good chaotic function on the mathematics, the characteristics of not necessarily complete realistic computer hardware and software, this is the deficiency of the method for tradition research, the present invention discloses a kind of Qian chaotic function f (x) and is then undertaken by opposite method, at first press the characteristics of computer hardware and software, remove to define Qian chaotic function f (x), prove on mathematics that then it is a chaotic function.

(1) the present invention discloses a kind of Qian chaotic function f (x) that meets the computer hardware characteristics, is expressed as follows:

N=2 ^K, K=positive integer (1)

|x|∈[0，2N-1]，|μ|∈[0，2] (2)

For proof f (x) is a chaotic function, proof f (x) satisfies from mapping earlier; Be the criterion of the chaotic function used always because of the Lyapunov index, its Lyapunov index LE of then deriving proves: when 2 〉=μ＞1, and LE＞0, f (x) is a chaos state.

Proof formula (2) satisfies from mapping: when | x|≤N-1, and 0≤N-1-|x|≤N-1, promptly 0≤| g (x) |≤N-1; When N-1＜| during x|≤2N-1,0≤|| x|-N|≤N-1, promptly 0≤| g (x) |≤N～1.Cause | μ |≤2, when μ g (x) 〉=0, μ g (x)+1=| μ || g (x) |+1≤| μ | (N-1)+1≤2N-1, satisfy | f (x) |≤2N-1; When μ g (x)＜0 ,-(μ g (x)-1)=-μ g (x)+1=| μ || g (x) |+1≤| μ | (N-1)+1≤2N-1, satisfy | f (x) |≤2N-1; Promptly to arbitrarily | x| ∈ [0,2N-1], satisfy | f (x) | ∈ [0,2N-1], so f (x) satisfies from mapping.

Satisfy under the prerequisite of mapping at f (x), the criterion that can utilize Lyapunov index LE to judge as chaos state, for this reason from the derive Lyapunov index LE of f (x) of mathematics, and proof when 2 〉=| μ |＞0, LE＞0, f (x) is a chaos state:

1. establish | x|≤N-1 and | x+dx|≤N-1, perhaps | x|＞N-1 and | x+dx|＞N-1.Find out that according to formula (1) and formula (2) ∵ f (x) only gets one of μ g (x)+1 or μ g (x)-1 form, ∴ $\left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dg}\left(x\right)}\right|=\left|\mathrm{\μ}\right|;$ ∵ g (x) only get N-1-|x| or-|| one of x|-N| form, ∴ $\left|\frac{\mathrm{dg}\left(x\right)}{d\left|x\right|}\right|=1;$ In addition, $\left|\frac{d|x|}{\mathrm{dx}}\right|=1,$ So draw according to the method for asking the compound function difference quotient,

$\left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dx}}\right|=|\frac{\mathrm{df}\left(x\right)}{\mathrm{dg}\left(x\right)}\·\frac{\mathrm{dg}\left(x\right)}{d\left|x\right|}\·\frac{d\left|x\right|}{\mathrm{dx}}|=\left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dg}\left(x\right)}\right|\·\left|\frac{\mathrm{dg}\left(x\right)}{d\left|x\right|}\right|\·\left|\frac{d\left|x\right|}{\mathrm{dx}}\right|=\left|\mathrm{\μ}\right|\·1\·1=\left|\mathrm{\μ}\right|$

Nearly all data point all satisfies following formula, have only two data points (| x|=N-1 or | x+dx|=N-1) do not satisfy.

2. establish respectively | x|≤N-1 and | x+dx|＞N-1 and | x|＞N-1 and | x+dx|≤N-1, make μ 〉=0 (or making μ＜0), then can release by (3) $\left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dx}}\right|>\left|\mathrm{\μ}\right|.$

In a word, $\left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dx}}\right|\≥\left|\mathrm{\μ}\right|,$ $\mathrm{LE}=\underset{J\→\∞}{\lim }\frac{1}{J}\underset{i=1}{\overset{J}{\mathrm{\Σ}}}\ln \left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dx}}\right|\≥\underset{J\→\∞}{\lim }\frac{1}{J}\underset{i=1}{\overset{J}{\mathrm{\Σ}}}\ln \left|\mathrm{\μ}\right|=\ln \left|\mathrm{\μ}\right|.$ Judge that by LE＞0 f (x) is a chaos state, LE depends on ln| μ |, get 2 〉=| μ |＞1, ln2 〉=ln| μ then |＞0, promptly when 2 〉=| μ | in the time of＞1, LE＞0, f (x) is a chaos state, the maximum of LE is about ln2=0.69314718.

(2) performance evaluation and the Computer simulation results of Qian chaotic function f (x).

Make x _I+1=f (x _i), x wherein _iBe variable x i sub-value in the iterative process, and x _I+1The i+1 sub-value.Computer simulation chaotic function f (x _i) drawing Fig. 1 and Fig. 2, the abscissa μ of two figure is that Fig. 1 is f (x from-2 →+2 variations _i) the period of a function curve that doubly diverges, ordinate is x _iValue is got N=2 ⁵⁰, x _iMaximum is about ± and 2.25 * 10 ¹⁵, show and satisfy from mapping, consistent with mathematical proof; Fig. 2 is f (x _i) the Lyapunov exponential curve of function, ordinate is the LE value, as can be seen, absolute value as μ | μ | at 1 → 2, LE＞0, LE maximum=0.69425 (μ=-2) and 0.69453 (μ=2), near theoretical value ln2=0.69314718, and | μ |=1 place, LE=0, the result is consistent with mathematical proof; Show | μ | in 1 → 2 function f (x) is chaos state, is the realization chaos sequence, | μ | can choose at 1 and 2.Fig. 3～Figure 11 is to be μ=2,2 (1-2 successively ^-50), 2 (1-2 ^-40), 2 (1-2 ^-30), 2 (1-2 ^-20), 2 (1-2 ^-10), 2 (1-2 ^-8), 2 (1-2 ^-6), 2 (1-2 ^-4) the power spectral density PSD curve.The feature of chaotic motion is that power spectrum broad peak occurs or joins together, and except that Fig. 3, Fig. 4～Figure 11 power spectrum broad peak occurs or joins together, and the feature of chaotic motion is arranged.The feature of the chaotic motion of Fig. 3 is very little, is not suitable for using μ=2, is μ=2 (1-2 and depart from μ=2 ^-50)～2 (1-2 ^-8) feature of chaotic motion is very strong, be suitable for using.

The auto-correlation of chaotic motion is approximately the δ function; The chaos sequence cross-correlation that is produced by two different initial values is 0, and its characteristic is similar to white noise, is fit to maintain secrecy and spread spectrum communication.Figure 12～Figure 20 is μ=2,2 (1-2 successively ^-50), 2 (1-2 ^-40), 2 (1-2 ^-30), 2 (1-2 ^-20), 2 (1-2 ^-10), 2 (1-2 ^-8), 2 (1-2 ^-6), 2 (1-2 ^-4) the correlation properties xcorr curve of function f (x), except that Figure 12, the autocorrelation of Figure 13～Figure 20 function is good, at periodic point 5 * 10 ⁴There is very high very thin spike at the place, shows that autocorrelation is very strong, other their cross correlation of place's reflection, and the amplitude of cross correlation is very little, near 0.

Figure 21～Figure 29 and Figure 30～Figure 38 are μ=1.1,1.2 successively, and the power spectrum of 1.3,1.4,1.5,1.6,1.7,1.8,1.9 function f (x) and correlation properties curve can be used as the foundation of selecting μ for use.

Figure 39 and Figure 41 are respectively power spectrum and the correlation properties curves of uniform random number sequence rand, Figure 40 and Figure 42 are respectively power spectrum and the correlation properties curves of Gaussian Profile random number sequence randn, during application preferably near the characteristic of Figure 39～Figure 42, be (horizontal line) of the preferably smooth constant amplitude of power spectrum, correlation properties have very high very thin spike at one-period point place, and other is bordering on 0.Find out that by Fig. 3～Figure 38 μ is at 2 (1-2 ^-50) and 2 (1-2 ^-8) between power spectrum and correlation properties close with Figure 39～Figure 42, so parameter μ preferably is selected in 2 (1-2 ^-50) and 2 (1-2 ^-8) between.

Figure 43～Figure 51 and Figure 52～Figure 60 are respectively the power spectrum and the correlation properties curves of Logistic chaotic function commonly used, and these figure and Fig. 3～Figure 11 are similar, and μ is at 2 and 2 (1-2 ^-8) between power spectrum and correlation properties close with Figure 39～Figure 42.Figure 61～Figure 69 is the power spectrum and the correlation properties curve of Lorenz chaotic function, can be for referencial use.

Below in conjunction with specific embodiment the present invention is explained:

The no multiply and divide of chaos encrypted circuit of embodiment 1:Qian chaotic function.

Figure 88 is the chaos sequence generator calcspar of the f shown in Figure 70 (x) in the lower dotted line for the present invention does not have multiply and divide of chaos encrypted circuit calcspar, by its output chaos sequence; It in the dotted line of top the chaos of plaintext shown in Figure 89 queuing-chaos XOR part calcspar.Wherein chaos sequence has two effects: the 1. chaos conversion of queuing sign indicating number makes plaintext strings rearrangement team (chaos formula).2. the mixing of team's plaintext and chaos sequence is reset in serial.Figure 89 is the chaos encryption circuit core partial circuit figure of no multiplication and division, is described as follows:

1. N expressly _DataCircuit is exactly the clear data buffer, and the clear data that on the one hand continuous receiving computer is sent here constantly (promptly selects 1 data selector MUX for 8 16 to 8 data queued selectors on the other hand ₍₁₎～MUX ₍₈₎) 128 plaintexts of output data ₁₂₇Data ₁₂₆Data ₁Data ₀

2. queuing sign indicating number key circuit is by 4 256 ring shift right shift registers 32 * 165 ₍₁₎～32 * 165 ₍₄₎Form, deposited 16 groups of queuing sign indicating number sequences in, queuing sign indicating number key has 16 * 16 * 4=1024 position; Every group of queuing sign indicating number sequence is the sequence of 16 16 system numbers (4 bit), and this 16 number 0～F has nothing in common with each other in the group, and queuing sign indicating number key circuit has 4 output Q _H0～Q _H3

3. eight queuing sign indicating number-chaos translation circuits are made up of 32 latchs 4 * 377 and 32 XOR gate, and 32 XOR gate are 4 row, 8 row, and an input of 8 XOR gate of every row (connecting together by row) meets Q respectively _H0～Q _H3, another input of=32 XOR gate of all 4 row, 8 row meets 32 output ch of 32 latchs 4 * 377 separately ₀～ch ₃₁, 4 outputs of 4 XOR gate of every row meet MUX in order respectively ₍₁₎～MUX ₍₈₎4 address codes input ABCD.

4. beat 1, and the chaos that chaos sequence generator is generated is exported high 32 Y earlier ₁₅₉～Y ₁₂₈Insert 32 latchs 4 * 377 in the 8 queuing sign indicating number-chaos translation circuits, be output as ch ₃₁～ch ₀All the other 128 Y of chaos output ₁₂₇～Y ₀Insert 8 16 bit shift register 2 * 165 in the plaintext-chaos XOR circuit ₍₁₎～2 * 165 ₍₈₎In.

5. beat 2～17, ring shift right shift register 32 * 165 under 16 cp ₍₁₎～32 * 165 ₍₄₎Output Q _H0～Q _H3Shift out 16 queuing sign indicating numbers that have nothing in common with each other successively, Q _H0～Q _H3With 8 chaos output ch ₃₁～ch ₂₈, ch ₂₇～ch ₂₄, ch ₂₃～ch ₂₀, ch ₁₉～ch ₁₆, ch ₁₅～ch ₁₂, ch ₁₁～ch ₈, ch ₇～ch ₄, ch ₃～ch ₀Carry out the step-by-step XOR, draw 8 chaos queuings of 16 strings sign indicating number, meet 8 data queued selector MUX respectively ₍₁₎～MUX ₍₈₎Address code ABCD.

6. plaintext-chaos XOR circuit comprises 8 16 bit shift register 2 * 165 ₍₁₎～2 * 165 ₍₈₎With 8 XOR gate in the right.The output of 8 XOR gate is z ₀～z ₇, 8 input shz of 8 XOR gate ₁～shz ₈Meet MUX in order successively ₍₁₎～MUX ₍₈₎8 output rsh ₁～rsh ₈Another input of 8 XOR gate meets 8 16 bit shift register output Q respectively _H10～Q _H17Plaintext N _DataAfter 128 plaintexts, 8 rows in the circuit finish rearrangement team by data selector, the shz that draws ₁～shz ₈With 8 16 bit shift register output Q _H10～Q _H17Make XOR by 8 XOR gate, at z ₀～z ₇Form the ciphertext output of a byte, under 16 clock cp effect, finish the ciphertext (i.e. 128 ciphertexts) of 16 bytes.

7. sending into following 128 plaintexts by computer then repeats said process and encrypts.

Figure 90～Figure 98 is a chaos encryption circuit computer simulation figure of the present invention, and Figure 90 is a plaintext data waveform, and the data waveform is a triangular wave, Figure 91 is that expressly chaos is reset rsh waveform after the team, the rsh waveform is gapped fuzzy, and Figure 92 is a ciphertext z waveform, the then fuzzy a slice of ciphertext z waveform.Figure 93 is a plaintext data power spectrum waveform, and waveform has obvious spike, no chaotic characteristic; Figure 94 is that expressly chaos is reset rsh power spectrum waveform after the team, has the wave broadband waveform, and showing after chaos is reset team has certain chaotic characteristic; Figure 95 is a ciphertext z power spectrum waveform, near smooth (horizontal line) of constant amplitude fuzzy a slice waveform, promptly near the power spectrum of Figure 39～Figure 42 uniform random number sequence rand and Gaussian Profile random number sequence randn.Figure 96 is plaintext data correlation properties waveforms, middle about 1.6 * 10 ⁴Locate not highly, auto-correlation is very poor, and other place is bigger, and promptly cross-correlation is bigger; Figure 97 is that expressly chaos is reset rsh correlation properties waveform after the team, middle about 1.6 * 10 ⁴Thin narrow spike appears in the place, and auto-correlation increases, and other place is still big, and promptly cross-correlation is still bigger; Figure 98 is ciphertext z correlation properties waveforms, middle about 1.6 * 10 ⁴The place occurs high and thin narrow spike, and auto-correlation is very big, and other locates nearly 0, and promptly cross-correlation is very little, near the correlation properties curve of uniform random number sequence rand and Gaussian Profile random number sequence randn, with encrypt require consistent.Figure 99, Figure 100, Figure 101 are that Figure 90, Figure 91, Figure 92 amplify figure, are convenient to observe.

The chaos decode circuit of the no multiplication and division of embodiment 2:Qian chaotic function.

Figure 102 is the chaos decode circuit core partial circuit figure of the no multiplication and division of Qian chaotic function of the present invention, and the chaos decode circuit is identical with chaos encryption circuit major part, only needs data selector MUX ₍₁₎～MUX ₍₈₎) change data distributor DIS into ₍₁₎～DEL ₍₈₎, (i.e. 8 XOR gate z of 8 XOR gate input and output lines in the transposing plaintext-chaos XOR circuit again ₀～z ₇Output changes input into, and meets data selector MUX among Figure 89 ₍₁₎～MUX ₍₈₎Input change among Figure 102 to data distributor DIS ₍₁₎～DEL ₍₈₎Output), chaos decode is the inverse process of chaos encryption, mainly shows the process of ciphertext → plaintext, i.e. the input z of 8 XOR gate ₀～z ₇The ciphertext of a byte is then by data distributor DIS ₍₁₎～DIS ₍₈₎Heavily distribute expressly, other modular construction is identical with the encrypted circuit appropriate section with effect.

When decrypt circuit three keys and full while of transmitting terminal encrypted circuit, the chaos decode circuit of the no multiplication and division of Qian chaotic function of the present invention is carried out computer simulation draw: Figure 103 receives ciphertext z _rWaveform, waveform blurs a slice; Figure 104 is z _rWith rsh waveform behind the chaotic signal XOR, waveform is fuzzy, and is gapped; Figure 105 is that expressly data is recovered in the deciphering back _rWaveform, waveform are triangular waves, and plaintext is identical with sending.Figure 106 is z _rThe power spectrum waveform is near smooth fuzzy a slice waveform of constant amplitude; Figure 107 is a rsh power spectrum waveform, has the wave broadband waveform, and certain chaotic characteristic is arranged; Figure 108 is data _rThe power spectrum waveform has obvious spike, no chaotic characteristic.Figure 109 is z _rThe correlation properties waveform, about 1.6 * 10 ⁴The place occurs high and thin narrow spike, and auto-correlation is very big, and other locates nearly 0, and promptly cross-correlation is very little; Figure 110 is the correlation properties waveform of rsh, about 1.6 * 10 ⁴Thin narrow spike appears in the place, and auto-correlation increases, and other place is still big, and promptly cross-correlation is still bigger; Figure 111 is data _rThe correlation properties waveform, auto-correlation is very poor, promptly cross-correlation is big.As can be seen, decrypting process and ciphering process are opposite fully, and expressly data is recovered in the deciphering back _rWaveform (triangular wave).

Now insert chaos latch Q ₁₅₉Q ₁₅₈～Q ₀Initial value+1, promptly add 1 by 160 lowest order, other is constant, the chaos decode circuit that the present invention is not had multiplication and division carries out kind of a computer simulation and draws again: Figure 112, Figure 113, Figure 114 are respectively z _r, rsh, data _rWaveform, three waveforms all are fuzzy a slices, deciphering back data _rDo not recover expressly waveform (triangular wave).Figure 115, Figure 116, Figure 117 are respectively z _r, rsh, data _rThe power spectrum waveform, three waveforms all are near smooth (horizontal line) of constant amplitude fuzzy a slice; Figure 118, Figure 119, Figure 120 are respectively z _r, rsh, data _rThe correlation properties waveform, three waveforms all are that auto-correlation is very big, other locates nearly 0, promptly cross-correlation is very little.

The chaos spread spectrum circuit of the no multiplication and division of embodiment 3:Qian chaotic function.

The electromagnetic environment of modern wireless device becomes complicated unusually, disturbs more and more serious, to realize communication rapidly, accurately, secret stern challenge proposed.Spread spectrum communication realizes communication under electromagnetic environment complexity, serious interference situation smooth and easy, becomes the developing direction of future communications.The spreading code of function admirable is crucial in spread spectrum.The tradition spread spectrum communication mostly adopts linearity or nonlinear shift register to produce pseudo random sequence as frequency expansion sequence, shortcoming is that available code character sequence number order is few, sequence complexity is low, correlation function presents periodically, be decrypted easily etc., the chaos sequence of chaotic function of the present invention then has many characteristics that are better than traditional frequency expansion sequence, the precision height, speed is fast, and circuit is simple, be easy to produce, aperiodicity does not restrain but bounded, and initial value is had sensitivity etc., quantity is many, can satisfy the quantity of the chaos spread spectrum sequence of auto-correlation and cross-correlation performance fully simultaneously.

At transmitting terminal, establishing and will sending data-signal is n position binary sequence sign indicating number: d _i=± 1, i=0,1,2 ..., n, ± 1 corresponding transmitted bit is logical one and logical zero.A pseudo random sequence must be arranged as frequency expansion sequence, its code check (bit rate) is more a lot of greatly than above-mentioned digital signal code check, and former linearity or the nonlinear shift register of mostly adopting produces pseudo random sequence.Now use the chaos sequence of high speed high-precision chaotic function: c=c instead ₁c ₂c ₃C _k, c _j=0,1; Use digital signal d _iModulation chaos sequence c works as d _i=+1 o'clock, the transmit chip sequence was taken as c=c in+1 duration ₁c ₂c ₃C _kWork as d _i=-1 o'clock, the transmit chip sequence was taken as in-1 duration $c^{-1}=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="c"\; filenames="S2008100638962E00011.png,S2008100638962E00051.png"\; state="\{\{state\}\}">c</figure-callout>}}_1}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="c"\; filenames="S2008100638962E00011.png,S2008100638962E00021.png"\; state="\{\{state\}\}">c</figure-callout>}}_2}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="c"\; filenames="S2008100638962E00011.png,S2008100638962E00051.png"\; state="\{\{state\}\}">c</figure-callout>}}_3}\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\stackrel{\&OverBar;}{c_k}.$ Sending data-signal is group of chip sequence (c and a c in fact ^-1).At receiving terminal, by inner product operation (be about to receiving data sequence and reference sequences c and carry out the step-by-step modular two multiplication, and sue for peace), if receiving data sequence (being c) is identical with reference sequences c, then the inner product result is k, if receiving data sequence is c ^-1And reference sequences c step-by-step is anti-, and then the inner product result is-k.To interference sequence and reference sequences inner product result (absolute value)＜k; This is because of the chaos sequence auto-correlation is approximately the δ function, and k is a chip sequence length.

Claims (4)

1. the chaos sequence generation method of a high speed high-precision chaotic function; It is characterized in that: described high speed high-precision chaotic function is a kind of chaotic function f (x that meets the computer hardware characteristics _i), be expressed as

N=2 ^K, K=positive integer, formula one

| x _i| ∈ [0,2N-1], | μ _i| ∈ [0,2], formula two

According to described chaotic function f (x _i) the chaos sequence generation method finished is as follows:

Chaos value x _iExist in the chaos latch, the chaos latch is by K+1 D-latch Q _KQ _K-1Q _K-2～Q ₀Form, wherein Q _KDeposit x _iSymbol, Q _K-1Q _K-2～Q ₀Deposit x _iAbsolute value | x _i|; Initial value key circuit is deposited chaos latch initial value, and μ value key circuit is deposited sequence μ _iValue; The lead code decision circuit judges whether come, signal is not come, and opens trigger Q if sending signal _S=0, chaos latch initial value is inserted Q _KQ _K-1Q _K-2～Q ₀Signal is come, and puts Q immediately _S=1, start chaos sequence generator, each clock cp chaos sequence generator is carried out a chaotic function interative computation, generates a K position chaos output Y _K-1～Y ₀The concrete method that generates 1 chaos output is: 1. the step-by-step translation circuit is with Q _K-1And Q _K-2～Q ₀Make the step-by-step XOR, carry out the subtraction N-1-|x of formula one thus _i| or | x _i|-N, output d _K-2～d ₀2. the shifted data selector is with μ _iAs the address code of data selector, with data d _K-2～d ₀H μ moves to right _i+ c position carries out 2 thus ^{-(h μ i+c)}* data d _K-2～d ₀, output g _K-2-c～g ₀3. subtraction circuit carries out d earlier _K-2～d ₀Subtract g _K-2-c～g ₀=S _K-2～S ₀, the then S as a result of subtraction _K-2～S ₀With line to moving to left 1, extreme lower position 1, i.e. the input D of D-latch _K-1Meet S _K-2, D _K-2Meet S _K-3... D ₁Meet S ₀, D ₀Connect 1; Realize the multiplication μ of formula two thus with subtraction circuit _i* data ± 1=2 (1-2 ^{-(h μ i+c)}) * data and ± 1, subtraction circuit output D _K-1D _K-2～D ₀4. at the cp rising edge subtraction circuit is exported D _K-1D _K-2～D ₀Deposit chaos latch Q in _K-1Q _K-2～Q ₀, and with μ _iValue sign bit and Q _K-1XNOR is deposited Q _K5. chaos output circuit Q _KAnd Q _K-1～Q ₁Step-by-step XOR and Q _KNegate is with positive negative binary number Q _KQ _K-1～Q ₀Be converted into positive binary number chaos output Y _K-1～Y ₀After this each cp is repeated above-mentioned steps 1.～5. carry out, constantly produce chaos output Y _K-1～Y ₀, generate chaos sequence output.

2. the chaos sequence generation method of a kind of high speed high-precision chaotic function according to claim 1 is characterized in that: get K=160, N=2 ¹⁶⁰, μ _i〉=0, c=10, h=4, chaos value x _iExist in the chaos latch, the chaos latch is by 161 D-latch Q ₁₆₀Q ₁₅₉Q ₁₅₈～Q ₀Form, wherein Q ₁₆₀Deposit x _iSymbol, Q ₁₅₉Q ₁₅₈～Q ₀Deposit x _iAbsolute value | x _i|; Initial value key circuit is deposited chaos latch initial value, and μ value key circuit is deposited sequence μ _iValue; The lead code decision circuit is judging whether come, signal is not come, and opens trigger Q if sending signal _S=0, chaos latch initial value is inserted Q ₁₅₉Q ₁₅₈～Q ₀Signal is come, and puts Q immediately _S=1, chaos sequence generator is started working, and each clock cp chaos sequence generator is finished the chaotic function interative computation one time, specifically generates a K position chaos output Y ₁₅₉～Y ₀A chaos output intent that generates is that 1. the step-by-step translation circuit is with Q ₁₅₉And Q ₁₅₈～Q ₀Make the step-by-step XOR, carry out the subtraction N-1-|x of formula one thus _i| or | x _i|-N, output d ₁₅₈～d ₀2. the shifted data selector is with μ _iAs the address code of data selector, with data d ₁₅₈～d ₀4 μ move to right _i+ 10, carry out 2 thus ^{-(4 μ i+10)}* data d ₁₅₈～d ₀, output g ₁₄₈～g ₀3. subtraction circuit carries out d earlier ₁₅₈～d ₀Subtract g ₁₄₈～g ₀=S ₁₅₈～S ₀, follow S as a result with subtraction ₁₅₈～S ₀With line to moving to left 1, extreme lower position 1, i.e. D ₁₅₉Meet S ₁₅₈, D ₁₅₈Meet S ₁₅₇... D ₁Meet S ₀, D ₀Connect 1, realize the multiplication μ of formula two thus with subtraction circuit _i* data ± 1=2 (1-2 ^{-(4 μ i+10)}) * data and ± 1, subtraction circuit output D ₁₅₉D ₁₅₈～D ₀4. at the cp rising edge subtraction circuit is exported D ₁₅₉D ₁₅₈～D ₀Deposit chaos latch Q in ₁₅₉Q ₁₅₈～Q ₀, and with Q ₁₅₉Deposit Q ₁₆₀5. chaos output circuit Q _KAnd Q _K-1～Q ₁Step-by-step XOR and Q _KNegate is with positive negative binary number Q ₁₆₀Q ₁₅₉～Q ₀Be converted into positive binary number chaos output Y ₁₅₉～Y ₀After this each cp is repeated above-mentioned steps 1.～5. carry out, constantly produce chaos sequence output Y ₁₅₉～Y ₀

3. the chaos sequence generator that forms of the chaos sequence generation method of high speed high-precision chaotic function according to claim 1, it is characterized in that: the chaos sequence generator core of high speed high-precision chaotic function comprises chaos latch, step-by-step translation circuit, shifted data selector, subtraction circuit and chaos output circuit: 1. the chaos latch is by K+1 position D-latch Q _KQ _K-1Q _K-2～Q ₀Form highest order Q _KThe is-symbol position, other K position Q _K-1Q _K-2～Q ₀Be the chaos data bit, Q _K-1Q _K-2～Q ₀Output connect step-by-step translation circuit input; 2. the step-by-step translation circuit is made up of K-1 XOR gate, and each XOR gate has an input to meet Q _K-1, another input meets Q successively _K-2～Q ₀, step-by-step translation circuit output d _K-2～d ₀Both connect the input of shifted data selector data, connect the subtraction circuit input again; 3. the shifted data selector is made up of K-2-c data selector, and its address code input connects the output of μ value key circuit, and its data input connects the output of step-by-step translation circuit, and its output connects the subtraction circuit input, output g _K-2-c～g ₀4. subtraction circuit is made up of K-1 position binary adder and inverter; The adder input meets d _K-2～d ₀With inverter output, the inverter input meets g _K-2-c～g ₀, subtraction circuit output D _K-1D _K-2～D ₀Meet chaos latch Q _K-1Q _K-2～Q ₀D input, Q _K-1And μ _iSign bit is different non-or meet Q _KD input; 5. chaos output circuit Q _KAnd Q _K-1～Q ₁Step-by-step XOR and Q _KWith μ _iThe sign bit XOR is with positive negative binary number Q _KQ _K-1～Q ₀Be converted into positive binary number chaos output Y _K-1～Y ₀K position chaotic signal of each clock cp output; In addition, also have initial value key circuit, μ value key circuit, lead code decision circuit and open trigger, initial value key circuit is put the number input with the initial value key for presetting several chaos latch initial values that connect, and μ value key circuit connects the input of shifted data selector address with sequence μ value; The lead code decision circuit receives and judges whether wireless receipts/signalling comes, and opens flip-flop toggle and stops foregoing circuit.

4. the chaos sequence generator of a kind of high speed high-precision chaotic function according to claim 3 is characterized in that: get K=160, N=2 ¹⁶⁰, μ _i〉=0, c=10, h=4, the chaos sequence generator core of high speed high-precision chaotic function comprises chaos latch, step-by-step translation circuit, shifted data selector, subtraction circuit and chaos output circuit, 1. the chaos latch is by 161 D-latch Q ₁₆₀Q ₁₅₉Q ₁₅₈～Q ₀Form highest order Q ₁₆₀The is-symbol position, other 160 Q ₁₅₉Q ₁₅₈～Q ₀Be the chaos data bit, Q ₁₅₉Q ₁₅₈～Q ₀Output connect step-by-step translation circuit input; 2. the step-by-step translation circuit is made up of 158 XOR gate, and each XOR gate has an input to meet Q ₁₅₉, another input meets Q successively ₁₅₈～Q ₀, step-by-step translation circuit output d ₁₅₈～d ₀Both connect the input of shifted data selector data, connect the subtraction circuit input again; 3. the shifted data selector is made up of 149 data selectors, and its address code input connects the output of μ value key circuit, and its data input connects the step-by-step translation circuit, and its output connects the subtraction circuit input, output g ₁₄₈～g ₀4. subtraction circuit is made up of 158 binary adders and inverter; The adder input connects by d ₁₅₈～d ₀With inverter output, the inverter input meets g ₁₄₈～g ₀, subtraction circuit output D ₁₅₉D ₁₅₈～D ₀Meet chaos latch Q ₁₅₉Q ₁₅₈～Q ₀D input, Q ₁₅₉Meet Q ₁₆₀D input; 5. chaos output circuit Q ₁₆₀And Q ₁₅₉～Q ₁Step-by-step XOR and Q ₁₆₀Negate is with positive negative binary number Q ₁₆₀Q ₁₅₉～Q ₀Be converted into positive binary number chaos output Y ₁₅₉～Y ₀160 chaotic signals of each clock cp output; In addition, also have initial value key circuit, μ value key circuit, lead code decision circuit and open trigger, initial value key circuit is put the number input with the initial value key for presetting several chaos latch initial values that connect, and μ value key circuit connects the input of shifted data selector address with sequence μ value; The lead code decision circuit receives and judges whether wireless receipts/signalling comes, and opens flip-flop toggle and stops foregoing circuit.

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