CN101232367B - Chaos encrypting and decrypting method without multiply and divide of chaos function and circuit thereof - Google Patents

Abstract

The invention discloses a chaotic encryption method without multiplication and division of a high-speed high-precision chaotic function and an encryption circuit, the encryption circuit includes a plaintext chaotic queuing-chaotic XOR circuit and a chaotic sequence generator; the queuing codes and the chaotic signal are firstly carried out the XOR to be converted into the nd sites of chaotic queuing codes as the address codes, 8 data selectors select 8 from the 8 multiplied by 2<nd> sites of parallel plaintext to be taken as the 1 byte chaotic re-queuing plaintext, then the XOR with the another chaotic signal is carried out to produce 1 byte ciphertext, 2<nd> of cp can encrypt 8 multiplied 2<nd> sites of ciphertext; each cp of the chaotic sequence generator generates 8 multiplied by (2<nd> plus nd) sites of chaotic outputs, wherein, the deduction calculation of N minus 1 minus the absolute value of xi and so on are realized by using XOR, the multiplication of Mui multiplied by data isrealized by using the deduction; the invention has an queuing code key, an initial value key and a Mu value key, the safety is high; the nd is equal to 4, the encryption of 128 sites of plaintext needs about 1.7Mus; the method can be realized by using FPGA, CPLD and ASIC, which is used in the network safety technology field, in particular to a wireless network and a wireless sensor network.

Description

The no multiply and divide of chaos method for encryption/decryption and the circuit thereof of chaotic function

(1) technical field

The invention belongs to the network security technology field, specifically a kind of no multiply and divide of chaos encryption method and encrypted circuit thereof.

(2) technical background

Encryption is the important means of guaranteeing data security property now.The rise of Internet, wireless network and wireless sensor network at present makes encryption technology become and becomes more and more important.Traditional cryptographic means such as DES, though it is very extensive that RSA etc. use now, also show very strong fail safe, but all finish under the sufficient prerequisite, be not suitable for the wireless network and the wireless sensor network of resource wretched insufficiency based on resource, for example DES decodes now, slow 100 times of RSA speed than DES, the computing cost is very high, and ellipse garden curve is encrypted and is expended great amount of hardware resources, quantum cryptography is the encryption technology that is perfectly safe in theory, but is in the exploratory development stage.Occurred a kind of chaos encrypting method at present, it utilizes in the chaos system the initial value sensitivity, and is unpredictable, and characteristics such as topology dependence produce secret key, and then encrypt, and show than conventional cryptography more performance.But because of speed slower, finite precision effect, short period response, problems such as floating-point operation difficulty make it not be used widely.

Chaos system is owing to the sensitiveness to initial value, and very little initial value error just can be amplified by system, and therefore, the chronicity of system is uncertain; Because chaos sequence has good statistical property, so it can produce random number series, these characteristics are well suited for the sequential encryption technology again.

The problem that existing chaos encrypting method exists:

1. finite precision effect

Most of chaotic functions all are earlier with mathematical method research, then this chaotic function is used for practice, however actual chaos sequence always under limited precision, generate, not in full conformity with the mathematical theory requirement, make many mathematical chaos systems be difficult to realization.The scholar is arranged even thinks that finite precision effect is a great problem that occurs during present chaology is moved towards to use:

1. the generation of a lot of chaos sequences realizes with computer or programming device, for example uses computer C language and C ⁺⁺Programming, the highest with the precision of double, the double data are expressed as d * 10 ^J, wherein d is a mantissa, and J is an index, and 64 bits commonly used are represented d and J, and precision depends on the figure place of d, the number of bits of d≤56, higher accuracy computation machine is difficult for realizing.As realizing that with programming device for example Nios CPU only can be configured to 16 * 16 → 32 hardware multipliers; This shows that the precision such as the Lorenz chaos system that realizes with FPGA and dsp chip hardware multiplier and adder generally is lower than the double type.

2. also the generation of a lot of chaos sequences is to adopt modulus integrating circuit and analog to digital conversion circuit ADC, for example Lorenz chaos system.Integrating circuit is an analog circuit, and analog circuit is influenced seriously by zero drift and thermal noise, and precision is far below digital circuit; ADC cost height, ADC precision only are tens, and obviously the ADC precision is far below computer double type.

2. the difficulty of in wireless network and wireless sensor network, using.

Wireless network and wireless sensor network are current important development directions, but the wireless sensor network node volume is little, and computing capability is low, memory space is few, the resource wretched insufficiency; Because of using powered battery, also has the requirement of low energy consumption and real-time, information security method and the thinking that can not copy the sufficient legacy network of resource fully again.The very little node of volume also will be finished Routing Protocol except chaos encryption, functions such as and multiple sensor data acquisition and wireless receipts/send out are finished under resource is serious restricted, and this is the very big difficult problem of a class.For example, be about 4K byte (or big slightly) lining at the program capacity and finish these tasks, be exactly an extremely thing of difficulty.Chaos encryption is used for wireless network and wireless sensor network is brand-new problem, the new chaotic maps that research is suitable for wireless network, wireless sensor network and digital system characteristics is a top priority.

3. short period response

The research of existing chaos sequence is to be based upon in the statistical analysis for the estimation of the periodicity pseudo-randomness of institute's formation sequence, complexity, cross correlation etc., enough big (t → ∞) of the cycle that is difficult to guarantee the sequence that realizes, complexity is enough high, this shortcoming has reduced the confidentiality of chaos encryption system to a certain extent, thereby the people can not be encrypted with it relievedly.Some researchs are at present adopted very long computer simulation time T for meeting the condition of t → ∞ on the mathematics, and during as T=24 or more, the randomness of the chaos sequence that thus chaos system is described and is generated is good, and meets the mathematics requirement.Yet wireless network and wireless sensor network node powered battery require energy consumption extremely low, and the operating time must lack, and can not work in continuous 24 hours, so the short period Computer simulation results are all the better near actual.

(3) summary of the invention

The objective of the invention is to disclose the no multiply and divide of chaos encryption method and the circuit thereof of a kind of precision height, speed height, circuit is simple, Information Security is good high speed high-precision chaotic function, be expressed as follows:

The no multiply and divide of chaos encryption method of chaotic function of the present invention comprises expressly chaos queuing-chaos XOR method and chaos sequence generation method two large divisions;

Described plaintext chaos queuing-chaos XOR method is as follows: note $N_{\mathrm{ra}}=n_{\mathrm{ra}}\&times;n_d\&times;2^{n_d},$ N _xor＝8×n _d， $N_{\mathrm{data}}=8\&times;2^{n_d},$ K=N _Xor+ N _DataUnder the control circuit effect, plaintext N _DataCircuit is imported N by computer by interrupt mode _DataThe position expressly; Queuing sign indicating number key circuit is N _RaPosition ring shift right shift register, it has deposited n in _RaGroup queuing sign indicating number key, it exports n _dPosition queuing sign indicating number Q _H0～Q _{H (nd-1)}Every cycle period has 2 ^Nd+ 1 claps 1 clock cp of every bat; 1. the K position chaos output Y that chaos sequence generator is generated is clapped in every circulation the 1st _K-1～Y ₀Insert N respectively _DataBit shift register and N _XorThe position D-latch is for the step prepares down; 2. the 2nd clap, the code conversion of at first will lining up is a chaos queuing sign indicating number, and measure is: queuing sign indicating number Q _H0～Q _{H (nd-1)}Respectively with N _XorThe step-by-step XOR is made in the chaos output of position D-latch, draws 8 chaos queuing sign indicating numbers; Then carry out plaintext chaos formula by chaos queuing sign indicating number and reset team, measure is: 8 chaos queuing sign indicating numbers are received the address code input of eight data queued selectors respectively; This data selector data input meets expressly N _DataThe N of circuit _DataThe position is output expressly, and this data selector output is rsh ₁～rsh ₈So this data selector is lined up sign indicating number from N by chaos separately _DataSelect 8 in the plaintext of position as 1 plaintext rsh of byte chaos formula rearrangement team ₁～rsh ₈Produce the ciphertext of 1 byte at last, measure is: rsh ₁～rsh ₈Meet 8 XOR gate input shz ₁～shz ₈Shz ₁～shz ₈With N _DataThe output chaotic signal Q of bit shift register ₁₀～Q ₁₇Make the step-by-step XOR, at 8 XOR gate output sho ₁～sho ₈Produce 1 byte ciphertext, sho ₁～sho ₈Meet outer output Z ₀～Z ₇Prepare for going on foot down simultaneously with this, measure is: this cp makes queuing sign indicating number key circuit and N _DataBit shift register all moves to right, the output Q that each self-forming is new _H0～Q _{H (nd-1)}And Q ₁₀～Q ₁₇3. the 3rd～2 ^Nd+ 1 claps the 2nd bat process of repetition, the 2nd～2 ^Nd+ 1 claps, and produces 2 ^NdIndividual serial byte form ciphertext is finished N _DataPosition chaos encryption expressly; Press the same manner to next N _DataChaos encryption is expressly carried out in the position;

Described chaos sequence generation method is to be based upon a kind of chaotic function f (x _i) on the basis, f (x _i) be expressed as

N=2 ^K, K=positive integer, formula one

| x _i| ∈ [0,2N-1], | μ _i| ∈ [0,2], formula two

According to described chaotic function f (x _i) the chaos sequence generation method finished is as follows:

Get μ _i〉=0, c=10, h=4, storage chaos value x _iThe chaos latch by K+1 D-latch Q _KQ _K-1Q _K-2～Q ₀Form, wherein Q _kDeposit x _iSymbol, Q _K-1Q _K-2～Q ₀Deposit x _iAbsolute value | x _i|; Initial value key circuit is deposited chaos latch initial value, and μ value key circuit is deposited sequence μ _iValue; The lead code decision circuit judges whether come, signal is not come, and opens trigger Q if sending signal _S=0, the chaos latch is inserted initial value; Signal is come, and puts Q immediately _S=1, start chaos sequence generator, each clock cp finishes the chaotic function interative computation one time, generates K position chaos output Y _K-1～Y ₀Generate Y _K-1～Y ₀Method be: 1. the step-by-step translation circuit is with Q _K-1And Q _K-2～Q ₀Make the step-by-step XOR, carry out the subtraction N-1-|x of formula one thus _i| or | x _i|-N, output d _K-2～d ₀2. the shifted data selector is with μ _iAs the address code of data selector, with data d _K-2～d ₀4 μ move to right _i+ 10, carry out 2 thus ^{-(4 μ i+10)}* data d _K-2～d ₀, output g _K-12～g ₀3. subtraction circuit carries out d earlier _K-2～d ₀Subtract g _K-12～g ₀=S _K-2～S ₀, follow S as a result with subtraction _K-2～S ₀With line to moving to left 1, extreme lower position 1; Be D _K-1Meet S _K-2, D _K-2Meet S _K-3... D ₁Meet S ₀, D ₀Connect 1, realize the multiplying μ of formula two thus with subtraction circuit _i* data ± 1=2 (1-2 ^{-(4 μ i+10)}) * data ± 1, subtraction circuit output D _K-1D _K-2～D ₀4. at the cp rising edge subtraction circuit is exported D _K-1D _K-2～D ₀Deposit chaos latch Q in _K-1Q _K-2～Q ₀, and with Q _K-1Deposit Q _K5. chaos output circuit Q _KAnd Q _K-1～Q ₁Step-by-step XOR and Q _KNegate is with positive negative binary number Q _KQ _K-1～Q ₀Be converted into positive binary number chaos output Y _K-1～Y ₀After this 1.～5. each cp repetition above-mentioned steps carries out, and constantly produces chaos sequence output Y _K-1～Y ₀

The no multiply and divide of chaos encryption method of chaotic function of the present invention also has some technical characterictics like this:

1, in the plaintext chaos queuing-chaos XOR method, gets n _d=4, n _Ra=16, N then _Xor=8 * n _d=32, $N_{\mathrm{data}}=8\&times;2^{n_d}=128,$ K＝N _xor+N _date＝160， $N_{\mathrm{ra}}=n_{\mathrm{ra}}\&times;n_d\&times;2^{n_d}=1024,$ Plaintext N _DataCircuit is output as 128 plaintexts; Queuing sign indicating number key circuit is made up of 4 256 ring shift right shift registers, is output as Q _H0～Q _H3Described plaintext chaos queuing-chaos XOR method is as follows: under the control circuit effect, 1. the 1st clap 160 chaos output Y that chaos sequence generator is generated ₁₅₉～Y ₀Insert 8 16 bit shift register and 32 D-latchs; 2. the 2nd clap Q _H0～Q _H3Make the step-by-step XOR with the chaos output of 32 D-latchs respectively, draw 8 chaos queuing sign indicating numbers; 8 chaos queuing sign indicating numbers are received the address code input of eight data queued selectors respectively; This data selector data input meets expressly N _Data128 plaintext outputs of circuit are so this data selector is selected 8 as 1 plaintext rsh of byte chaos formula rearrangement team by chaos queuing sign indicating number separately from 128 plaintexts ₁～rsh ₈Rsh ₁～rsh ₈Meet 8 XOR gate input shz ₁～shz ₈Shz ₁～shz ₈Chaotic signal Q with 8 16 bit shift register outputs ₁₀～Q ₁₇Make the step-by-step XOR, XOR gate output sho ₁～sho ₈Produce the ciphertext of 1 byte; Sho ₁～sho ₈Meet outer output Z ₀～Z ₇This cp makes 4 256 ring shift right shift registers and 8 16 bit shift register move to right one, forms new output Q _H0～Q _H3And Q ₁₀～Q ₁₇3. the 3rd～17 clap the 2nd bat process of repetition, clap, produce the ciphertext of 16 serial byte forms successively, finish the chaos encryption of 128 plaintexts the 2nd～17; Following 128 plaintexts are carried out chaos encryption by the same manner;

According to described chaotic function f (x _i) the chaos sequence generation method finished is as follows: get K=160, N=2 ¹⁶⁰, μ _i〉=0, c=10, h=4, storage chaos value x _iThe chaos latch by 161 D-latch Q ₁₆₀Q ₁₅₉Q ₁₅₈～Q ₀Form; The lead code decision circuit judges that sending signal comes, and puts Q immediately _S=1, start chaos sequence generator, each clock cp of this generator generates K position chaos output Y ₁₅₉～Y ₀The generation method is that 1. the step-by-step translation circuit is with Q ₁₅₉And Q ₁₅₈～Q ₀Make the step-by-step XOR, output d ₁₅₈～d ₀2. the shifted data selector is with μ _iAs the address code of data selector, with data d ₁₅₈～d ₀4 μ move to right _i+ 10, output g ₁₄₈～g ₀3. subtraction circuit carries out d earlier ₁₅₈～d ₀Subtract g ₁₄₈～g ₀=S ₁₅₈～S ₀, follow S as a result with subtraction ₁₅₈～S ₀With line to moving to left 1, extreme lower position 1; Be D ₁₅₉Meet S ₁₅₈, D ₁₅₈Meet S ₁₅₇... D ₁Meet S ₀, D ₀Connect 1, subtraction circuit output D ₁₅₉D ₁₅₈～D ₀4. at the cp rising edge subtraction circuit is exported D ₁₅₉D ₁₅₈～D ₀Deposit low 160 Q of chaos latch in ₁₅₉Q ₁₅₈～Q ₀, and with Q ₁₅₉Deposit Q ₁₆₀5. chaos output circuit Q ₁₆₀And Q ₁₅₉～Q ₁Step-by-step XOR and Q ₁₆₀Negate is with positive negative binary number Q ₁₆₀Q ₁₅₉～Q ₀Be converted into positive binary number chaos output Y ₁₅₉～Y ₀After this each cp is repeated above-mentioned steps 1.～5. carry out, constantly produce chaos sequence output Y ₁₅₉～Y ₀

2, the chaos encryption circuit that forms according to the no multiply and divide of chaos encryption method of chaotic function, this chaos encryption circuit comprises expressly chaos queuing-chaos XOR circuit and chaos sequence generator two large divisions; First part expressly chaos queuing-chaos XOR circuit comprises: 1. plaintext N _DataCircuit, input connects computer, and the clear data that receiving computer is sent here, and storage data are exported 128 plaintexts and are met eight data queued selector MUX ₍₁₎～MUX ₍₈₎The data input; 2. queuing sign indicating number key circuit is made up of 4 256 ring shift right shift registers, and parallel input connects computer, by computer input queue sign indicating number key; Queuing sign indicating number key circuit has 4 output Q _H0～Q _H33. eight queuing sign indicating number-chaos translation circuits are made up of 32 D-latchs and 32 XOR gate, an input of every of all 32 XOR gate connects 32 outputs of 32 latchs separately, 32 XOR gate are 4 row, 8 row, and an input of 8 XOR gate of every row connects together by row, meets Q respectively _H0～Q _H3, 4 outputs of 4 XOR gate of every row meet MUX in order respectively ₍₁₎～MUX ₍₈₎4 address codes input ABCD; 4. 160 chaos outputs of chaos sequence generator generation connect the parallel input of 32 D-latchs in the eight queuing sign indicating number-chaos translation circuits and the parallel input of 8 16 bit shift register in the plaintext-chaos XOR circuit respectively; 5. plaintext-chaos XOR circuit comprises 8 16 bit shift register and 8 XOR gate; One input of 8 XOR gate meets MUX respectively ₍₁₎～MUX ₍₈₎8 outputs, another input of 8 XOR gate connects the output of 8 16 bit shift register respectively; 8 outputs of 8 XOR gate form the ciphertext output of a byte, under 16 clock cp effect, form the ciphertext of 16 bytes, i.e. 128 ciphertexts; Second largest part chaos sequence generator comprises: 1. the chaos latch is by 161 D-latch Q ₁₆₀Q ₁₅₉Q ₁₅₈～Q ₀Form highest order Q ₁₆₀The is-symbol position, other 160 Q ₁₅₉Q ₁₅₈～Q ₀Be the chaos data bit, Q ₁₅₉Q ₁₅₈～Q ₀Output connect step-by-step translation circuit input; 2. the step-by-step translation circuit is made up of 158 XOR gate, and each XOR gate has an input to meet Q ₁₅₉, another input meets Q successively ₁₅₈～Q ₀, step-by-step translation circuit output d ₁₅₈～d ₀Both connect the input of shifted data selector data, connect the subtraction circuit input again; 3. the shifted data selector is made up of 149 data selectors, and its address code input connects the output of μ value key circuit, and its data input connects the step-by-step translation circuit, and its output connects the subtraction circuit input, output g ₁₄₈～g ₀4. subtraction circuit is made up of 158 binary adders and inverter; The adder input connects by d ₁₅₈～d ₀With inverter output, the inverter input meets g ₁₄₈～g ₀, subtraction circuit output D ₁₅₉D ₁₅₈～D ₀Connect chaos latch D input; 5. the chaos output circuit is by Q ₁₆₀And Q ₁₅₉～Q1 step-by-step XOR gate and input meet Q ₁₆₀Not gate form 160 chaotic signal Y of each clock cp output ₁₅₉～Y ₀

Another object of the present invention is to provide a kind of encrypting and decrypting method without multiply and divide of chaos of chaotic function, this chaos decode method comprises that the ciphertext chaos rejoins one's unit-chaos XOR method and chaos sequence generation method two large divisions:

Described ciphertext chaos rejoins one's unit-and chaos XOR method is as follows: note N _Xor=8 * n _d, $N_{\mathrm{data}}=8\&times;2^{n_d},$ K＝N _xor+N _data， $N_{\mathrm{ra}}=n_{\mathrm{ra}}\&times;n_d\&times;2^{n_d};$ Queuing sign indicating number key circuit is N _RaPosition ring shift right shift register, it has deposited n in _RaGroup queuing sign indicating number key, it exports n _dPosition queuing sign indicating number Q _H0～Q _{H (nd-1)}Under the control circuit effect, every cycle period has 2 ^Nd+ 1 claps 1 clock cp of every bat; 1. the K position chaos output Y that chaos sequence generator is generated is clapped in every circulation the 1st _K-1～Y ₀Insert N respectively _DataBit shift register and N _XorThe position D-latch is for the step prepares down; 2. the 2nd clap, at first with 1 byte ciphertext Z _R0～Z _R7The 1 byte chaos formula that is converted to the expressly rsh that waits to rejoin one's unit ₁～rsh ₈, measure is: Z _R0～Z _R7Meet shz ₁～shz ₈, with shz ₁～shz ₈With N _DataThe output chaotic signal Q of bit shift register ₁₀～Q ₁₇Make the step-by-step XOR, at 8 XOR gate output sho ₁～sho ₈, just at rsh ₁～rsh ₈The 1 byte chaos formula that produces is waited to rejoin one's unit expressly; The code conversion of then will lining up is a chaos queuing sign indicating number, and measure is: queuing sign indicating number Q _H0～Q _{H (nd-1)}Respectively with N _XorThe step-by-step XOR is made in the chaos output of position D-latch, draws 8 chaos queuing sign indicating numbers; Carry out plaintext chaos formula by chaos queuing sign indicating number at last and return team, measure is: 8 chaos queuing sign indicating numbers are received the address code input of eight data queued distributors respectively; This data distributor data output meets expressly N _DataThe N of circuit _DataThe position is input expressly, so this data distributor be the address by separately chaos queuing sign indicating number, with the 1 byte chaos formula plaintext rsh that waits to rejoin one's unit ₁～rsh ₈Deposit expressly N in _DataIn the corresponding address storaging unit of circuit; Prepare for going on foot down simultaneously with this, measure is: this cp makes queuing sign indicating number key circuit and N _DataBit shift register all moves to right, the output Q that each self-forming is new _H0～Q _{H (nd-1)}And Q ₁₀～Q ₁₇3. the 3rd～2 ^Nd+ 1 claps the 2nd bat process of repetition; The 2nd～2 ^Nd+ 1 claps, to 2 ^NdIndividual serial byte form decrypt ciphertext is finished N _DataThe chaos decode of position ciphertext; Press the same manner to following 2 ^NdIndividual serial byte form ciphertext is carried out chaos decode; Described chaos sequence generation method is identical with claim 1.

The no multiply and divide of chaos encryption method and the encrypted circuit of high speed high-precision chaotic function of the present invention specify as follows:

(1) the hardware implementation method and the advantage of the chaos sequence generator of high-speed, high precision Qian chaotic function f (x).

Figure 43～Figure 51 and Figure 52～Figure 60 are respectively the power spectrum and the correlation properties curves of Logistic chaotic function commonly used, and Figure 61～Figure 69 is the power spectrum and the correlation properties curve of Lorenz chaotic function.Wherein the Logistic chaotic function needs 2 multiplyings and 1 subtraction; The Lorenz chaotic function needs 5 multiplyings and 4 subtractions, and speed is very slow, and precision is very low; Obviously multiplying is the major obstacle that improves precision and speed.The present invention removes the multiplication and division computing, only with a subtraction.

In Figure 70 and Figure 71, make x _I+1=f (x _i), x _iBe the i time iterative value.For directly perceived convenient, get μ with explanation _i〉=0, n _d=4, n _Ra=16, then $N_{\mathrm{ra}}=n_{\mathrm{ra}}\&times;n_d\&times;2^{n_d}=1024,$ N _xor＝8×n _d＝32， $N_{\mathrm{data}}=8\&times;2^{n_d}=128,$ K=N _Xor+ N _Date=160, Figure 71 contains 160 and has the d type flip flop Q that clock presets several functions ₁₅₉～Q ₀, this d type flip flop structure is shown in Figure 72, and wherein control end E meets Q _SWireless receipts/send out chip data a to receive/process always sends lead code earlier, then be only address code and data and check code, lead code is that data are received/steering signal, and is requisite, lead code and receipts/send out data time to determine at interval, can be used as the synchronizing signal of chaos enciphering/deciphering.The lead code decision circuit judges that whether send signal comes, and before signal is come, opens trigger Q _S=0 (E=0) under the cp effect, will put as going into the chaos latch as the initial value of initial value key, and μ value key circuit deposits μ value key in; In case the lead code decision circuit judges that sending signal comes, and opens trigger and puts 1 immediately, be i.e. Q _S=1 (E=1) under clock cp effect, finishes interative computation one time by each cp of abovementioned steps.Chaos sequence generator of the present invention, employing formula one and formula two, the simplification of circuit and two formulas have utmost point confidential relation, in conjunction with chaos sequence generator of the present invention core circuit Figure 71, and describe the method for physical circuit realization and the advantage that this method has in detail:

1. realize subtraction with the step-by-step negate.If K=160 (any K is also set up), N-1=2 ¹⁶⁰-1, use Q ₁₅₉Q ₁₅₈... ..Q ₀Represent 160 bigits | x _i|, N-1 equals low 159 (bit ₁₅₈... ..bit ₀) all be 1.When | x _i| (Q during≤N-1 ₁₅₉=0), carries out N-1-|x _i|, just right | x _i| in Q ₁₅₈～Q ₀Carry out the step-by-step negate, Q ₁₅₉Constant, replace subtraction N-1-|x with the step-by-step negate _i|; When | x _i| (Q during＞N-1 ₁₅₉=1), carry out | x _i|-N also is about to highest order Q ₁₅₉Subtract 1, Q ₁₅₈～Q ₀Constant; Q is merged in two kinds of computings ₁₅₉And Q ₁₅₈～Q ₀Carry out the step-by-step XOR, draw 159 XOR output d ₁₅₈～d ₀, two kinds of situation Q ₁₅₉In fact and x value _iSymbol is identical, can temporarily preserve Q ₁₅₉, not with Q ₁₅₉Subtract 1, Q when moving to left later on ₁₅₉Naturally lose.No matter figure place is much, only need t time of delay of one-level XOR gate or inverter _PdArithmetic speed than traditional subtracter is high a lot, and figure place is big more, and this advantage is outstanding more.

2. finish data (h μ with the shifted data selector _i+ c) gt.Select for use μ to be selected in 2 (1-2 in the practicality ^-50) and 2 (1-2 ^-8) between, μ _i* data=2 (1-2 ^{-(h μ i+c)}) * data, d and c are integer, get c=10, h=4.The μ sequence table is shown μ ₀μ ₁μ ₂... μ _i... μ _U-1μ _u, have in the μ value key circuit this circuit output μ in the i time iteration _i, with μ _iAs the address code of data selector, finish d ₁₅₈～d ₀(4 μ move to right _i+ 10) position promptly realizes 2 ^{-(4 μ i+10)}* data d ₁₅₈～d ₀=data selector output g ₁₄₈～g ₀Every iteration once changes the primary address sign indicating number, finishes the data multidigit with data selector and moves to right, than a lot of soon with the shift register speed that moves to right.

3. replace multiplying with subtraction.Carry out subtraction 2 (1-2 one time with subtraction circuit ^{-(h μ i+c)}) * (d ₁₅₈～d ₀)=2 ((d ₁₅₈～d ₀)-(g ₁₄₈～g ₀)); Earlier carry out (d by subtraction ₁₅₈～d ₀)-(g ₁₄₈～g ₀), be output as S ₁₅₈... ..S ₀, because of (d ₁₅₈～d ₀)＞(g ₁₄₈～g ₀), must there be borrow; Then with S ₁₅₈... ..S ₀Take advantage of 2, be about to S ₁₅₈... ..S ₀Move to left 1 again.Move to left 1 and be equivalent to output line S ₁₅₈... S ₀Change, promptly press D successively ₁₅₉← S ₁₅₈... D ₁← S ₀, D ₂← S ₁Deng connection, D wherein ₁₅₉D ₁₅₈... D ₂D ₁D ₀Being subtraction circuit output, also is chaos latch Q ₁₅₉Q ₁₅₈... ..Q ₂Q ₁Q ₀The D input, be about to S ₁₅₈S ₁₅₇... ..S ₁S ₀Deposit Q separately ₁₅₉Q ₁₅₈... ..Q ₂Q ₁, only change the output line, need not any gate circuit.The remaining Q in back moves to left ₀ Set 1, i.e. Q ₀← 1, be equivalent in the formula two ± 1; The result draws 160 bit data Q ₁₅₉Q ₁₅₈... ..Q ₂Q ₁Q ₀, be kept at Q originally ₁₅₉The sign bit displacement time deposit Q in ₁₆₀, i.e. Q ₁₆₀← Q ₁₅₉This shows, replace multiplying with subtraction, high more a lot of than multiplying speed, increase with chaos latch figure place, leading borrow subtraction circuit is than the easy realization of mlultiplying circuit.

4. realize the output of chaos data with the step-by-step XOR gate.Sign bit Q ₁₆₀=0 expression positive number, Q ₁₆₀=1 expression negative because of binary number only uses 0 and 1, does not have-1, should be integer with positive and negative number conversion, subtracts above-mentioned 160 bit data Q with 2N-1 for this reason ₁₅₉Q ₁₅₈... ..Q ₂Q ₁Q ₀If Q ₁₆₀=0, all be 1 because of 2N-1 is 160, subtract Q with 2N-1 ₁₅₉Q ₁₅₈... ..Q ₂Q ₁Q ₀, be equivalent to Q ₁₅₉Q ₁₅₈... ..Q ₂Q ₁Q ₀The step-by-step negate; If Q ₁₆₀=1,2N-1 Reduction of Students' Study Load Q then ₁₅₉Q ₁₅₈... ..Q ₂Q ₁Q ₀, be 2N-1 and add Q ₁₅₉Q ₁₅₈... ..Q ₂Q ₁Q ₀, note Q ₀=1, so Q ₀=1 with 2N-1 in-1 offset, 2N is exactly Q ₁₆₀=1, the result draws Q ₁₆₀=1, Q ₀=0, all the other Q ₁₅₉... Q ₂Q ₁Constant.Because of two kinds of situation Q ₀Be 0 all, deletion Q during output ₀Use Q ₁₆₀And Q ₁₅₉... ..Q ₂Q ₁By realizing Y for XOR ₁₅₈... ..Y ₁Y ₀, highest order Q ₁₆₀Negate gets Y ₁₅₉, draw 160 chaos data output Y ₁₅₉Y ₁₅₈... ..Y ₁Y ₀The later half cycle that is preferably in clock is read the output of chaos data.Here replace subtraction (2N-1 subtracts 160 bit data) with step-by-step XOR and negate, XOR gate speed is much larger than subtraction circuit speed.

Chaos sequence generator output Y ₁₅₉～Y ₀Divide 5 sections demonstrations (the ∵ computer is the highest with the precision of double precision datum type double, but display precision is number of bits≤56), 5 sections is Y successively ₁₅₉～Y ₁₂₈, Y ₁₂₇～Y ₉₆, Y ₉₅～Y ₆₄, Y ₆₃～Y ₆₂, Y ₃₁～Y ₀, these 5 sections output waveform figures are expressed as Figure 83, Figure 84, Figure 85, Figure 86, Figure 87 respectively, and every figure output amplitude is about 2 ³²=4.29 * 10 ⁹This power spectral density PSD curve of 5 sections is expressed as Figure 73, Figure 74, Figure 75, Figure 76, Figure 77 respectively; This correlation properties curve of 5 sections is expressed as respectively and is Figure 78, Figure 79, Figure 80, Figure 81, Figure 82.Above-mentioned Figure 73～Figure 82 is near Figure 39～uniform random number sequence rand and Gaussian Profile random number sequence randn power spectrum and correlation properties curve shown in Figure 42, and power spectrum is smooth, and correlation properties are at one-period point 5 * 10 ⁴There is very high very thin spike at the place, shows that autocorrelation is very strong, and other their cross correlation of place's reflection shows that the amplitude of cross correlation is very little, is applicable to encryption.

(2) no multiply and divide of chaos encryption method, encrypted circuit and the performance of high speed high-precision chaotic function.

Figure 88 is the chaos sequence generator calcspar of the high speed high-precision chaotic function shown in Figure 70 in the lower dotted line for the no multiply and divide of chaos encrypted circuit calcspar of chaotic function of the present invention, by its output chaos sequence; It in the dotted line of top the plaintext chaos queuing-chaos XOR part calcspar shown in Figure 89.Chaos encrypting method of the present invention comprises expressly chaos queuing-chaos XOR method and chaos sequence generation method two large divisions, wherein first carries out plaintext the chaos formula earlier to reset team, and then with the method for chaotic signal XOR, second portion provides the generation method of the required chaotic signal of the circuit of realizing first's method.Chaos sequence has two effects: 1. the queuing sign indicating number is done the chaos conversion and plaintext is carried out serial chaos formula rearrangement team.2. again the chaos formula is reset team's plaintext and chaos sequence XOR.

The no multiply and divide of chaos encrypted circuit core circuit diagram of high speed high-precision chaotic function of the present invention is Figure 89, is described as follows:

1. N expressly _DataCircuit is exactly the clear data buffer, and the clear data that on the one hand continuous receiving computer is sent here constantly (is got n to 8 data queued selectors on the other hand _d=4, $2^{n_d}=2^4=16,$ There are 8 16 and select 1 data selector MUX ₍₁₎～MUX ₍₈₎) 128 plaintexts of data input pin conveying data ₁₂₇Data ₁₂₆... data ₁Data ₀(∵ $N_{\mathrm{data}}=8\&times;2^{n_d}=128$ )。

2. queuing sign indicating number key circuit is by 4 256 ring shift right shift registers 32 * 165 ₍₁₎～32 * 165 ₍₄₎Form and (get n now _Ra=16, $N_{\mathrm{ra}}=n_{\mathrm{ra}}\&times;n_d\&times;2^{n_d}=16\&times;4\&times;2^4=4\&times;256$ ), deposit n by computer in to it _Ra=16 groups of queuing sign indicating number sequences are as queuing sign indicating number key (having 4 * 256); Every group of queuing sign indicating number sequence is 2 ^NdIndividual $2^{n_d}=16$ The sequence of individual 16 system numbers, in the requirement group this $2^{n_d}=16$ Number 0～F has nothing in common with each other, total 16!=2.09 * 10 ¹³Planting may arrangement mode.Queuing sign indicating number key circuit has $2^{n_d}=4$ Individual output Q _H0～Q _H3, corresponding 4 bit Q _H1～Q _H3

3. eight queuing sign indicating number-chaos translation circuits are by N _Xor=32 latchs 4 * 377 and N _Xor=32 XOR gate are formed, and 32 XOR gate are N _Xor=n _dCapable 8 row of * 8=4, an input of 8 XOR gate of every row (connecting together by row) meets Q respectively _H0～Q _H3, another input of=32 XOR gate of all 4 row, 8 row meets the N of 32 latchs 4 * 377 separately _Xor=32 output ch ₀～ch ₃₁, 4 outputs of 4 XOR gate of every row meet MUX in order respectively ₍₁₎～MUX ₍₈₎N _d=4 address code input ABCD.

4. at beat 1, elder generation is with the N of the chaos output of chaos sequence generator generation _XorThe position (is high 32 Y ₁₅₉～Y ₁₂₈) insert the N in the eight queuing sign indicating number-chaos translation circuits _Xor=32 latchs 4 * 377 are output as ch ₃₁～ch ₀All the other N of chaos output _DataPosition (i.e. 128 Y ₁₂₇～Y ₀) insert (∵ in the plaintext-chaos XOR circuit $N_{\mathrm{data}}=8\&times;2^{n_d}=8\&times;16$ ) 8 16 bit shift register 2 * 165 ₍₁₎～2 * 165 ₍₈₎

5. at beat 2～17 (2 ^Nd-1), $2^{n_d}=16$ Ring shift right shift register 32 * 165 under the individual cp ₍₁₎～32 * 165 ₍₄₎Output Q _H0～Q _H3Shift out 16 queuing sign indicating numbers that have nothing in common with each other successively, Q _H0～Q _H3With 8 chaos output ch ₃₁～ch ₂₈, ch ₂₇～ch ₂₄, ch ₂₃～ch ₂₀, ch ₁₉～ch ₁₆, ch ₁₅～ch ₁₂, ch ₁₁～ch ₈, ch ₇～ch ₄, ch ₃～ch ₀Carry out the step-by-step XOR, draw 8 chaos queuings of 16 strings sign indicating number, meet 8 data queued selector MUX respectively ₍₁₎～MUX ₍₈₎Address code ABCD.

6. plaintext-chaos XOR circuit comprises $N_{\mathrm{data}}=8\&times;2^{n_d}=8$ Individual 16 bit shift register 2 * 165 ₍₁₎～2 * 165 ₍₈₎With 8 XOR gate.The output of 8 XOR gate is z ₀～z ₇, 8 input shz of 8 XOR gate ₁～shz ₈Meet MUX in order successively ₍₁₎～MUX ₍₈₎8 output rsh ₁～rsh ₈Annotate: incoming line shz ₁～shz ₈Can upset natural order and meet output line rsh ₁～rsh ₆, as rsh ₂Meet shz ₅, rsh ₃Meet shz ₁, rsh ₄Meet shz ₈, rsh ₅Meet shz ₂, rsh ₆Meet shz ₄, rsh ₇Meet shz ₇, rsh ₈Meet shz ₃, connected mode has 8! Kind.Another input of 8 XOR gate meets 8 16 bit shift register output Q respectively _H10～Q _H17Plaintext N _DataN in the circuit _DataAfter=128 plaintext 8 rows finish rearrangement team by data selector, the shz that draws ₁～shz ₈With 8 16 bit shift register output Q _H10～Q _H17Be passed to 8 XOR gate, make XOR, XOR gate output z ₀～z ₇Form the ciphertext of a byte, under 16 clock cp effect, finish the ciphertext (i.e. 128 ciphertexts) of 16 bytes.

7. send into down N by computer then _Data=128 plaintexts repeat said process and encrypt.

8. the chaos sequence generator of every beat (1 cp) high-speed, high precision Qian chaotic function f (x) is carried out 1 interative computation, produces 1 N _Data=128 chaos outputs, each circulation $2^{n_d}+1=17$ Individual cp produces the output of 17 chaos, gets them in 17 and 1 deposits N _Xor=32 latchs 4 * 377 and N _Data=8 16 bit shift register 2 * 165 ₍₁₎～2 * 165 ₍₈₎

Figure 90～Figure 98 is the no multiply and divide of chaos encrypted circuit computer simulation figure of high speed high-precision chaotic function of the present invention, Figure 90 is a plaintext data waveform, the data waveform is a triangular wave, Figure 91 is that expressly chaos is reset rsh waveform after the team, the rsh waveform is gapped fuzzy, Figure 92 is a ciphertext z waveform, the then fuzzy a slice of ciphertext z waveform.Figure 93 is a plaintext data power spectrum waveform, and waveform has obvious spike, no chaotic characteristic; Figure 94 is that expressly chaos is reset rsh power spectrum waveform after the team, has the wave broadband waveform, and showing after chaos is reset team has certain chaotic characteristic; Figure 95 is a ciphertext z power spectrum waveform, near smooth (horizontal line) of constant amplitude fuzzy a slice waveform, promptly near the power spectrum of Figure 39～Figure 42 uniform random number sequence rand and Gaussian Profile random number sequence randn.Figure 96 is plaintext data correlation properties waveforms, middle about 1.6 * 10 ⁴Locate not highly, auto-correlation is very poor, and other place is bigger, and promptly cross-correlation is bigger; Figure 97 is that expressly chaos is reset rsh correlation properties waveform after the team, middle about 1.6 * 10 ⁴Thin narrow spike appears in the place, and auto-correlation increases, and other place is still big, and promptly cross-correlation is still bigger; Figure 98 is ciphertext z correlation properties waveforms, middle about 1.6 * 10 ⁴The place occurs high and thin narrow spike, and auto-correlation is very big, and other locates nearly 0, and promptly cross-correlation is very little, near the correlation properties curve of uniform random number sequence rand and Gaussian Profile random number sequence randn, with encrypt require consistent.Figure 99, Figure 100, Figure 101 are that Figure 90, Figure 91, Figure 92 amplify figure, are convenient to observe.

(3) encrypting and decrypting method without multiply and divide of chaos of high speed high-precision chaotic function, decrypt circuit and performance.

Figure 102 is the no multiply and divide of chaos decrypt circuit core circuit diagram of high speed high-precision chaotic function of the present invention, and it is identical with the encrypted circuit major part, only needs data selector MUX ₍₁₎～MUX ₍₈₎) change data distributor DIS into ₍₁₎～DES ₍₈₎, data distributor data input rsh ₁～rsh ₈Meet 8 XOR gate output sho ₁～sho ₈, the data output of data distributor meets expressly N _DataThe N of circuit _DataParallel-by-bit is expressly imported, again with 8 XOR gate incoming line shz ₁～shz ₈With output line sho ₁～sho ₈Location swap.Chaos decode is the inverse process of chaos encryption, mainly shows the process of ciphertext → plaintext, because of the shz of 8 XOR gate ₁～shz ₈Input meets the ciphertext z of a byte _R0～z _R7, shz at first ₁～shz ₈With the chaotic signal XOR, draw a byte chaos formula expressly rsh that waits to rejoin one's unit ₁～rsh ₈, then by data distributor DIS ₍₁₎～DIS ₍₈₎By separately chaos queuing sign indicating number be the address, with the 1 byte chaos formula plaintext rsh that waits to rejoin one's unit ₁～rsh ₈Deposit expressly N in _DataIn the corresponding address storaging unit of circuit; Other modular construction is identical with the encrypted circuit appropriate section with effect, is described as follows: 1. beat 2～17, have 16 clock cp to draw 8 chaos queuings of 16 strings sign indicating number by the same manner, control 8 data queued distributor DIS respectively with them ₍₁₎～DIS ₍₈₎2. in the plaintext-chaos XOR circuit 8 XOR gate from z _R0～z _R7The ciphertext of a byte of input, with it with deposit 8 16 bit shift register output Q in _H10～Q _H17Make XOR by 8 XOR gate, reset expressly rsh of team by the chaos formula of a byte of 8 XOR gate output ₁～rsh ₈, and the output of 8 XOR gate meets DIS respectively ₍₁₎～DIS ₍₈₎8 be input as rsh ₁～rsh ₈So, finish the chaos formula by data distributor and wait the heavily distribution expressly of rejoining one's unit, promptly by 8 DIS ₍₁₎～DIS ₍₈₎The data that delivers to _R159～data _R0The relevant position stores away; Under 16 clock cp effect, from z _R0～z _R7Import the ciphertext of 16 bytes, be converted to the plaintext (i.e. 128 plaintexts) of 16 bytes, send full datar ₁₅₉～data _R0All positions store away.3. N expressly _DataCircuit is to have the clear data buffer that the input step-by-step is stored, plaintext data after 128 deciphering of continuous on the one hand reception 8 data queued distributors output now _R127... ..data _R1Data _R0On the other hand by the clear data of interrupt mode after computer sends deciphering.

When decrypt circuit three keys and full while of transmitting terminal encrypted circuit, no multiply and divide of chaos decrypt circuit of the present invention is carried out computer simulation draw: Figure 103 receives byte ciphertext waveform z _r, waveform blurs a slice; Figure 104 is z _rWith the expressly rsh waveform of waiting to rejoin one's unit of byte chaos formula behind the chaotic signal XOR, waveform is fuzzy, and is gapped; Figure 105 is that expressly data is recovered in the deciphering back _rWaveform, waveform are triangular waves, and plaintext is identical with sending.Figure 106 is z _rThe power spectrum waveform is near smooth fuzzy a slice waveform of constant amplitude; Figure 107 is a rsh power spectrum waveform, has the wave broadband waveform, and certain chaotic characteristic is arranged; Figure 108 is data _rThe power spectrum waveform has obvious spike, no chaotic characteristic.Figure 109 is z _rThe correlation properties waveform, about 1.6 * 10 ⁴The place occurs high and thin narrow spike, and auto-correlation is very big, and other locates nearly 0, and promptly cross-correlation is very little; Figure 110 is the correlation properties waveform of rsh, about 1.6 * 10 ⁴Thin narrow spike appears in the place, and auto-correlation increases, and other place is still big, and promptly cross-correlation is still bigger; Figure 111 is data _rThe correlation properties waveform, auto-correlation is very poor, promptly cross-correlation is big.As can be seen, decrypting process and ciphering process are opposite fully, and expressly data is recovered in the deciphering back _rWaveform (triangular wave).

Now insert chaos latch Q ₁₅₉Q ₁₅₈～Q ₀Initial value+1, other is constant promptly to add 1, three key by 160 lowest order, again no multiply and divide of chaos decrypt circuit is carried out kind of a computer simulation and draw: Figure 112, Figure 113, Figure 114 are respectively z _r, rsh, data _rWaveform, three waveforms all are fuzzy a slices, deciphering back data _rDo not recover expressly waveform (triangular wave).Figure 115, Figure 116, Figure 117 are respectively z _r, rsh, data _rThe power spectrum waveform, three waveforms all are near smooth (horizontal line) of constant amplitude fuzzy a slice; Figure 118, Figure 119, Figure 120 are respectively z _r, rsh, data _rThe correlation properties waveform, three waveforms all are that auto-correlation is very big, other locates nearly 0, promptly cross-correlation is very little.

(4) the no multiply and divide of chaos encryption method of high speed high-precision chaotic function of the present invention and the advantage of chaos encryption circuit:

1. precision height, speed height.Chaos Variable 160 bits, precision are much larger than aforementioned calculation machine double type, much larger than existing chaos encryption circuit.The potentiality that continue to increase figure place are arranged, and subtraction circuit is got key effect to speed when continuing to increase the binary number figure place.Subtraction circuit and XOR gate etc. all are combinational circuits, and each cp finishes interative computation one time, and one time iterative process is only used subtraction 1 time.To CMOS logic application-specific integrated circuit (ASIC), finish 64 ripple carry adders (RCA) and postpone to be about 30ns under 0.5 μ m technology, inverter delay is about 0.43ns, and MUX postpones to be about 2.43ns, three input NOR door triggers postpone to be about 0.85ns, and trigger postpones maximum and is about 9.5ns.160 subtraction circuits add inverter with 160 ripple carry adders to be realized, then postpones to be about 75ns+0.43ns=75.5ns.Calculate cp cycle=75.5+9.5+2.43+0.85 ≈ 88.5ns, get cp cycle=0.1 μ s, encrypting 128 plaintexts needs time=17 * 0.1 μ s=1.7 μ s.If press the middle small scale integrated circuit calculation of parameter, subtraction circuit is realized (negative becomes radix-minus-one complement+1) with 4 full binary adders 283 entirely, shared 40 full adders, then finish 160 and be subtraction needs 40 * 53ns=2.12 μ s, other gate delay＜0.08 μ s, get cp cycle=2.2 μ s, then encrypting 128 plaintexts needs time=17 * 2.2 μ s=37.4 μ s.Speed is much larger than existing chaos encryption circuit.

2. circuit is simple, is adapted at using in wireless network and the wireless sensor network.Show that average every used device is less: (i) chaos sequence generator does not have the multiplication and division computing, replaces multiplying with subtraction, with realization subtraction and output circuits such as step-by-step negates; One of the every increase of data then only needs to increase by 1 trigger, 2 XOR gate, and 1 data selector, and with 1 of subtracter increase.(ii) expressly chaos queuing-chaos XOR circuit is only used 8 data selectors (every usefulness 1/16), 40 XOR gate (every usefulness 1/3.2), 4 8D latchs (every usefulness 1/32), 16 8 bit shift register and other 128 8 bit shift register (every usefulness 1.125).128 refer to all queuing sign indicating number keys and deposit 128 8 bit shift register entirely in, if change every circulation into by 16 queuing sign indicating numbers of the parallel input of computer key, then a queuing sign indicating number key circuit only needs be made up of 88 bit shift register, can reduce 120 8 bit shift register (every usefulness 1/5.3).

3. Information Security is good.Three keys are arranged: initial value key, μ value key and queuing sign indicating number key.Get n _d=4, n _Ra=16, N then _Xor=8 * n _d=32, $N_{\mathrm{data}}=8\&times;2^{n_d}=128,$ The initial value key is K=N _Data+ N _Xor=160, have 2 ¹⁶⁰≈ 1.46 * 10 ⁴⁸Plant the possibility initial value, μ value key has 32 4 system numbers, has 4 ³²≈ 1.84 * 10 ¹⁹Plant possibility μ value sequence; Every group of queuing sign indicating number key $2^{n_d}=16$ Number has 16!=2.09 * 10 ¹³Plant and to arrange, press n _Ra=16 batch totals are calculated, and are about (2.09 * 10 ¹³) ¹⁶=1.3 * 10 ²¹³Plant and to arrange; Three keys need exhaustive number of times=1.46 * 10 ⁴⁸* 1.84 * 10 ¹⁹* 1.3 * 10 ²¹³≈ 3.49 * 10 ²⁸⁰, the method for exhaustion is decoded and may not; In addition, 8 input shz ₁～shz ₈Can upset natural order and meet 8 output rsh ₁～rsh ₆, the total 8! of connected mode=40320 kinds, more increase the difficulty that the method for exhaustion is decoded.

If get n _d=5, n _Ra=16, then $N_{\mathrm{ra}}=n_d\&times;n_{\mathrm{ra}}\&times;2^{n_d}=5\&times;512,$ Queuing sign indicating number key circuit is formed MUX by 5 512 ring shift right shift registers ₍₁₎～MUX ₍₈₎Be 8 32 and select 1 data selector; N _Xor=8 * n _d=40,40 XOR gate of 40 D-latch figure places and connection thereof are arranged; The plaintext figure place $N_{\mathrm{data}}=8\&times;2^{n_d}=256,$ 8 32 bit shift register are arranged; Every circulation has and 33 claps (promptly 2 ^Nd+ 1 claps), ciphering process and above-mentioned similar, the 1st claps the K=N that earlier chaos sequence generator is generated _Xor+ N _DataN is inserted in the chaos output of=40+256=296 position _Xor=40 latchs and $N_{\mathrm{data}}=8\&times;2^{n_d}=8$ Individual 32 bit shift register; The the 2nd～the 33rd claps generation 32 byte ciphertexts (i.e. 256 ciphertexts); The chaos output figure place K=N of chaos sequence generator _Data+ N _Xor=296, the initial value key has 2 ^K=2 ²⁹⁶≈ 1.27 * 10 ⁸⁹Kind, μ value key is the same, a queuing yard key have (32! ) ¹⁶=(2.63 * 10 ³⁵) ¹⁶=5.2 * 10 ⁵⁶⁶Kind, three keys need exhaustive number of times=1.27 * 10 ⁸⁹* 5.28 * 10 ⁵⁶⁶* 1.84 * 10 ¹⁹≈ 1.23 * 10 ⁶⁷⁵, the method for exhaustion is decoded and may not.To reset team be the chaos formula to the serial of system of Himdu logic literary composition again, the plaintext that front and back are identical, the chaos formula is reset team expressly must be inequality, and then with another chaotic signal XOR, encrypt institute draw before and after two ciphertexts more complete inequality, the effect of secondary chaos is arranged.It is short-term response that chaotic signal is reset team to plaintext serial chaos formula, and analytic approach is decoded also not possibility, and it is extremely difficult to crack.In addition because at a high speed, every cp iteration once, per 17 iteration are just taken out chaotic signal one time, 17 times repeatedly between output bias＞1 time repeatedly between output bias, overcome the short period response of chaos sequence; Can also improve figure place again, overcome the chaos sequence finite precision effect.

(4) description of drawings

Fig. 1 is the curve chart that doubly diverges in the cycle of the computer simulation of Qian chaotic function f of the present invention (x).

Fig. 2 is the Lyapunov index curve diagram of the computer simulation of Qian chaotic function f of the present invention (x).

Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11 are that Qian chaotic function f of the present invention (x) is at μ=2,2 (1-2 successively ^-50), 2 (1-2 ^-40), 2 (1-2 ^-30), 2 (1-2 ^-20), 2 (1-2 ^-10), 2 (1-2 ^-8), 2 (1-2 ^-6), 2 (1-2 ^-4) the power spectral density plot figure of computer simulation.

Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 20 are that Qian chaotic function f of the present invention (x) is at μ=2,2 (1-2 successively ^-50), 2 (1-2 ^-40), 2 (1-2 ^-30), 2 (1-2 ^-20), 2 (1-2 ^-10), 2 (1-2 ^-8), 2 (1-2 ^-6), 2 (1-2 ^-4) the correlation properties curve chart of computer simulation.

Figure 21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, Figure 27, Figure 28, Figure 29 be successively Qian chaotic function f of the present invention (x) in μ=1.1,1.2,1.3,1.4,1.5,1.6,1.7,1.8,1.9 computer simulation power spectral density plot figure.

Figure 30, Figure 31, Figure 32, Figure 33, Figure 34, Figure 35, Figure 36, Figure 37, Figure 38 be successively Qian chaotic function f of the present invention (x) in μ=1.1,1.2,1.3,1.4,1.5,1.6, the correlation properties curve chart of 1.7,1.8,1.9 computer simulation.

Figure 39 and Figure 41 are respectively power spectrum and the correlation properties simulation curve figure of uniform random number sequence rand.

Figure 40 and Figure 42 are respectively power spectrum and the correlation properties simulation curve figure of Gaussian Profile random number sequence randn.

Figure 43, Figure 44, Figure 45, Figure 46, Figure 47, Figure 48, Figure 49, Figure 50, Figure 51 are that the Logistic chaotic function is at μ=2,2 (1-2 successively ^-50), 2 (1-2 ^-40), 2 (1-2 ^-30), 2 (1-2 ^-20), 2 (1-2 ^-10), 2 (1-2 ^-8), 2 (1-2 ^-6), 2 (1-2 ^-4) the power spectral density plot figure of computer simulation.

Figure 52, Figure 53, Figure 54, Figure 55, Figure 56, Figure 57, Figure 58, Figure 59, Figure 60 are that the Logistic chaotic function is at μ=2,2 (1-2 successively ^-50), 2 (1-2 ^-40), 2 (1-2 ^-30), 2 (1-2 ^-20), 2 (1-2 ^-10), 2 (1-2 ^-8), 2 (1-2 ^-6), 2 (1-2 ^-4) the correlation properties curve chart of computer simulation.

Figure 61, Figure 62, Figure 63 are the power spectral density plot figure of the computer simulation of Lorenz chaotic function x, y, z successively.

Figure 64, Figure 65, Figure 66 are the correlation properties curve chart of the computer simulation of Lorenz chaotic function x, y, z successively.

Figure 67, Figure 68, Figure 69 are the phase path figure of the computer simulation of Lorenz chaotic function x y, yz, zx successively.

Figure 70 is the chaos sequence generator calcspar of high speed high-precision chaotic function of the present invention.

Figure 71 is the chaos sequence generator core circuit diagram of high speed high-precision chaotic function of the present invention.

Figure 72 presets the d type flip flop circuit diagram of several functions for tool among Figure 12.

Figure 73, Figure 74, Figure 75, Figure 76, Figure 77 are the chaos sequence generator output Y for high speed high-precision chaotic function of the present invention successively ₁₅₉～Y ₁₂₈, Y ₁₂₇～Y ₉₆, Y ₉₅～Y ₆₄, Y ₆₃～Y ₆₂, Y ₃₁～Y ₀The power spectral density plot figure of computer simulation.

Figure 78, Figure 79, Figure 80, Figure 81, Figure 82 are the chaos sequence generator output Y for high speed high-precision chaotic function of the present invention successively ₁₅₉～Y ₁₂₈, Y ₁₂₇～Y ₉₆, Y ₉₅～Y ₆₄, Y ₆₃～Y ₆₂, Y ₃₁～Y ₀The correlation properties curve chart of computer simulation.

Figure 83, Figure 84, Figure 85, Figure 86, Figure 87 are the chaos sequence generator output Y of high speed high-precision chaotic function of the present invention successively ₁₅₉～Y ₁₂₈, Y ₁₂₇～Y ₉₆, Y ₉₅～Y ₆₄, Y ₆₃～Y ₆₂, Y ₃₁～Y ₀The output curve diagram of computer simulation.

Figure 88 is the no multiply and divide of chaos encrypted circuit structural representation of high speed high-precision chaotic function of the present invention.

Figure 89 is the no multiply and divide of chaos encrypted circuit core circuit diagram that the present invention mixes the ignorant function of high-speed, high precision.

Figure 90, Figure 91, Figure 92 are that no multiply and divide of chaos encrypted circuit computer simulation plaintext data waveform, the plaintext chaos of high speed high-precision chaotic function of the present invention reset rsh waveform after the team, ciphertext z oscillogram successively.

Figure 93, Figure 94, Figure 95 be successively high speed high-precision chaotic function of the present invention no multiply and divide of chaos encrypted circuit computer simulation expressly data, expressly chaos is reset the power spectral density plot figure of rsh, ciphertext Z after the team.

Figure 96, Figure 97, Figure 98 be successively high speed high-precision chaotic function of the present invention no multiply and divide of chaos encrypted circuit computer simulation expressly data, expressly chaos is reset the correlation properties curve chart of rsh, ciphertext Z after the team.

Figure 99, Figure 100, Figure 101 are the figure that Figure 90, Figure 91, Figure 92 abscissa amplify successively.

Figure 102 is the no multiply and divide of chaos decrypt circuit core circuit diagram of high speed high-precision chaotic function of the present invention.

Figure 103, Figure 104, Figure 105 are three key and the encrypted circuit full simultaneous computer simulation byte ciphertext z that receive of the no multiply and divide of chaos decrypt circuit of high speed high-precision chaotic function of the present invention when it successively _rWaveform, z _rWaiting to rejoin one's unit with byte chaos formula behind the chaotic signal XOR, expressly expressly data is recovered in rsh waveform, deciphering back _rOscillogram.

Figure 106, Figure 107, Figure 108 are that the no multiply and divide of chaos decrypt circuit of high speed high-precision chaotic function of the present invention expressly receives ciphertext z when its three keys and the full simultaneous computer simulation of encrypted circuit successively _r, z _rRecover expressly data with rsh, deciphering back behind the chaotic signal XOR _rPower spectral density plot figure.

Figure 109, Figure 110, Figure 111 are that the no multiply and divide of chaos decrypt circuit of high speed high-precision chaotic function of the present invention receives ciphertext z when its three keys and the full simultaneous computer simulation of encrypted circuit successively _r, z _rRecover expressly data with rsh, deciphering back behind the chaotic signal XOR _rThe correlation properties curve chart.

Figure 112, Figure 113, Figure 114 be successively high speed high-precision chaotic function of the present invention no multiply and divide of chaos decrypt circuit when it three keys and encrypted circuit much at one, only have the simulation of minute differences computer-chronograph to receive ciphertext z _rWaveform, z _rRecover expressly data with rsh waveform, deciphering back behind the chaotic signal XOR _rOscillogram.

Figure 115, Figure 116, Figure 117 be successively high speed high-precision chaotic function of the present invention no multiply and divide of chaos decrypt circuit when it three keys and encrypted circuit much at one, only have the simulation of minute differences computer-chronograph expressly to receive ciphertext z _r, z _rRecover expressly data with rsh, deciphering back behind the chaotic signal XOR _rPower spectral density plot figure.

Figure 118, Figure 119, Figure 120 be successively high speed high-precision chaotic function of the present invention no multiply and divide of chaos decrypt circuit when it three keys and encrypted circuit much at one, only have the simulation of minute differences computer-chronograph to receive ciphertext z _r, z _rRecover expressly data with rsh, deciphering back behind the chaotic signal XOR _rThe correlation properties curve chart.

(5) embodiment

Below in conjunction with accompanying drawing the present invention is described in further detail:

Traditional method is mainly studied from mathematics, is applied to then in the reality, and not necessarily realistic fully, the present invention is undertaken by opposite method, at first presses the characteristics of computer hardware, removes to define Qian chaotic function f (x), proves on mathematics then.

(1) the present invention discloses a kind of Qian chaotic function f (x) that meets the computer hardware characteristics, is expressed as follows:

N=2 ^K, K=positive integer (1)

|x|∈[0，2N-1]，|μ|∈[0，2] (2)

Proof formula (2) satisfies from mapping: when | x|≤N-1, and 0≤N-1-|x|≤N-1, promptly 0≤| g (x) |≤N-1; When N-1＜| during x|≤2N-1,0≤|| x|-N|≤N-1, promptly 0≤| g (x) |≤N-1.Cause | μ |≤2, when μ g (x) 〉=0, μ g (x)+1=| μ || g (x) |+1≤| μ | (N-1)+1≤2N-1, satisfy | f (x) |≤2N-1; When μ g (x)＜0 ,-(μ g (x)-1)=-μ g (x)+1=| μ || g (x) |+1≤| μ | (N-1)+1≤2N-1, satisfy | f (x) |≤2N-1; Promptly to arbitrarily | x| ∈ [0,2N-1], satisfy | f (x) | ∈ [0,2N-1], so f (x) satisfies from mapping.

Satisfy under the prerequisite of mapping at f (x), the criterion that can utilize Lyapunov index LE to judge as chaos state, for this reason from the derive Lyapunov index LE of f (x) of mathematics, and proof when 2 〉=| μ |＞0, LE＞0, f (x) is a chaos state:

1. establish | x|≤N-1 and | x+dx|≤N-1, perhaps | x|＞N-1 and | x+dx|＞N-1.Find out that according to formula (1) and formula (2) f (x) only gets one of μ g (x)+1 or μ g (x)-1 form, and g (x) only get N-1-|x| or-|| one of x|-N| form draws $\left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dg}\left(x\right)}\right|=\left|\mathrm{\&mu;}\right|,$ $\left|\frac{\mathrm{dg}\left(x\right)}{d\left|x\right|}\right|=1,$ $\left|\frac{d\left|x\right|}{\mathrm{dx}}\right|=1,$ Release according to the method for asking the compound function difference quotient,

$\left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dx}}\right|=|\frac{\mathrm{df}\left(x\right)}{\mathrm{dg}\left(x\right)}\&CenterDot;\frac{\mathrm{dg}\left(x\right)}{d\left|x\right|}\&CenterDot;\frac{d\left|x\right|}{\mathrm{dx}}|=\left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dg}\left(x\right)}\right|\&CenterDot;\left|\frac{\mathrm{dg}\left(x\right)}{d\left|x\right|}\right|\&CenterDot;\left|\frac{d\left|x\right|}{\mathrm{dx}}\right|=\left|\mathrm{\&mu;}\right|\&CenterDot;1\&CenterDot;1=\left|\mathrm{\&mu;}\right|$

Nearly all data point all satisfies following formula, have only two data points (| x|=N-1 or | x+dx|=N-1) do not satisfy.

2. establish | x|≤N-1 and | x+dx|＞N-1, must | x|=N-1, | x+dx|=N-1+|dx|, make μ 〉=0 and μ＜0 respectively, can prove $\left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dx}}\right|>\left|\mathrm{\&mu;}\right|.$ Establish again | x|＞N-1 and | x+dx|≤N-1, similar approach draws: $\left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dx}}\right|>\left|\mathrm{\&mu;}\right|$

In a word, $\left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dx}}\right|\&GreaterEqual;\left|\mathrm{\&mu;}\right|,$ $\mathrm{LE}=\underset{J\&RightArrow;\&infin;}{\lim }\frac{1}{J}\underset{i=1}{\overset{J}{\mathrm{\&Sigma;}}}\ln \left|\frac{\mathrm{df}\left(x\right)}{\mathrm{dx}}\right|\&GreaterEqual;\underset{J\&RightArrow;\&infin;}{\lim }\frac{1}{J}\underset{i=1}{\overset{J}{\mathrm{\&Sigma;}}}\ln \left|\mathrm{\&mu;}\right|=\ln \left|\mathrm{\&mu;}\right|.$ Judge that by LE＞0 f (x) is a chaos state, LE depends on ln| μ |, get 2 〉=| μ |＞1, ln2 〉=ln| μ |＞0, also promptly when 2 〉=| μ | in the time of＞1, LE＞0, f (x) is a chaos state, the maximum of LE is about ln2=0.69314718.

(2) Computer simulation results of Qian chaotic function f (x).

Make x _I+1=f (x _i), x _iAnd x _I+1Be respectively iterative process x the i time and i+1 sub-value.If μ _i〉=0, draw formula (3),

|x _i|∈[0，2N-1]，μ _i∈[0，2] (3)

Fig. 1 is the curve that doubly diverges in the cycle of Qian chaotic function f (x) function computer simulation, and ordinate is x _iValue is got N=2 ⁵⁰, x _iMaximum is about ± and 2.25 * 10 ¹⁵, the abscissa μ of Fig. 1 and Fig. 2 figure _i=μ is from-2 →+2 variations, shows and satisfies from mapping, and is consistent with mathematical proof; Fig. 2 is the Lyapunov exponential curve of Qian chaotic function f (x), ordinate is the LE value, absolute value as μ | μ | at 1 → 2, LE＞0, LE maximum=0.69425 (μ=-2) and 0.69453 (μ=2), near theoretical value ln2=0.69314718, and at μ=1 place, LE=0, the result is consistent with mathematical proof; Show | μ | in 1 → 2 function f (x) is chaos state, is the realization chaos sequence, | μ | can choose at 1 and 2.Fig. 3～Figure 11 is to be μ=2,2 (1-2 successively ^-50), 2 (1-2 ^-40) ... ..2 (1-2 ^-6), 2 (1-2 ^-4) the power spectral density PSD curve of chaotic function f (x).Except that Fig. 3, Fig. 4～Figure 11 power spectrum broad peak occurs or joins together, and the feature of chaotic motion is arranged.The feature of the chaotic motion of Fig. 3 is very little, is not suitable for μ=2, and be μ=2 (1 and depart from μ=2 ^-250)～2 (1-2 ^-8) feature of chaotic motion is very strong, be suitable for using.

The auto-correlation of chaotic motion is approximately the δ function; Two different chaos sequence cross-correlation of initial value are 0, and characteristic is similar to white noise.Figure 12～Figure 20 is μ=2.....2 (1-2 successively ^-4) the correlation properties xcorr curve of chaos Qian function f (x); Except that Figure 12, the autocorrelation of Figure 13～Figure 20 function is good, at periodic point 5 * 10 ⁴There is very high very thin spike at the place, shows that autocorrelation is very strong, and other place's amplitude is very little, and promptly their cross correlation is very little, near 0.

Figure 21～Figure 29 and Figure 30～Figure 38 are μ=1.1,1.2 successively, power spectrum and the correlation properties curve of 1.3,1.4,1.5,1.6,1.7,1.8,1.9 Qian chaotic function f (x), as a reference.Figure 39 and Figure 41 are respectively power spectrum and the correlation properties curves of uniform random number sequence rand, Figure 40 and Figure 42 are respectively power spectrum and the correlation properties curves of Gaussian Profile random number sequence randn, best characteristic near Figure 39～Figure 42, it is power spectrum preferably smooth constant amplitude, correlation properties have very high very thin spike at one-period point place, and other is bordering on 0.To Fig. 3～Figure 38, μ is at 2 (1-2 ^-50) and 2 (1-2 ^-8) between power spectrum and correlation properties close with Figure 39～Figure 42, so parameter μ preferably is selected in 2 (1-2 ^-50) and 2 (1-2 ^-8) between.Figure 43～Figure 51 and Figure 52～Figure 60 are respectively the power spectrum and the correlation properties curves of Logistic chaotic function commonly used, are found out that by this figure μ is at 2 and 2 (1-2 ^-8) between power spectrum and correlation properties close with Figure 39～Figure 42.Figure 61～Figure 69 is the power spectrum and the correlation properties curve of Lorenz chaotic function, as a reference.

Claims (4)

1. the no multiply and divide of chaos encryption method of a chaotic function is characterized in that: this chaos encrypting method comprises expressly chaos queuing-chaos XOR method and chaos sequence generation method two large divisions;

Described plaintext chaos queuing-chaos XOR method is as follows: note $N_{\mathrm{ra}}=n_{\mathrm{ra}}\&times;n_d\&times;2^{n_d},$ N _xor＝8×n _d， $N_{\mathrm{data}}=8\&times;2^{n_d},$ K=N _Xor+ N _DataUnder the control circuit effect, plaintext N _DataCircuit is imported N by computer by interrupt mode _DataThe position expressly; Queuing sign indicating number key circuit is N _RaPosition ring shift right shift register, it has deposited n in _RaGroup queuing sign indicating number key, it exports n _dPosition queuing sign indicating number

Every cycle period has

Clap 1 clock cp of every bat; 1. the K position chaos output Y that chaos sequence generator is generated is clapped in every circulation the 1st _K-1～Y ₀Insert N respectively _DataBit shift register and N _XorThe position D-latch is for the step prepares down; 2. the 2nd clap, the code conversion of at first will lining up is a chaos queuing sign indicating number, and measure is: the queuing sign indicating number

Respectively with N _XorThe step-by-step XOR is made in the chaos output of position D-latch, draws 8 chaos queuing sign indicating numbers; Then carry out plaintext chaos formula by chaos queuing sign indicating number and reset team, measure is: 8 chaos queuing sign indicating numbers are received the address code input of 8 data queued selectors respectively; This data selector data input meets expressly N _DataThe N of circuit _DataThe position is output expressly, and this data selector output is rsh ₁～rsh ₈So this data selector is lined up sign indicating number from N by chaos separately _DataSelect 8 in the plaintext of position as 1 plaintext rsh of byte chaos formula rearrangement team ₁～rsh ₈Produce the ciphertext of 1 byte at last, measure is: rsh ₁～rsh ₈Meet 8 XOR gate input shz ₁～shz ₈Shz ₁～shz ₈With N _DataThe output chaotic signal Q of bit shift register ₁₀～Q ₁₇Make the step-by-step XOR, at 8 XOR gate output sho ₁～sho ₈Produce 1 byte ciphertext, sho ₁～sho ₈Meet outer output Z ₀～Z ₇Prepare for going on foot down simultaneously with this, measure is: this cp makes queuing sign indicating number key circuit and N _DataBit shift register all moves to right, the output that each self-forming is new And Q ₁₀～Q ₁₇3.

Clap to repeat the 2nd bat process, the

Clap, produce

Individual serial byte form ciphertext is finished N _DataPosition chaos encryption expressly; Press the same manner to next N _DataChaos encryption is expressly carried out in the position;

Described chaos sequence generation method is to be based upon a kind of chaotic function f (x _i) on the basis, f (x _i) be expressed as

N=2 ^K, K=positive integer formula one

| x _i| ∈ [0,2N-1], | μ _i| ∈ [0,2] formula two

According to described chaotic function f (x _i) the chaos sequence generation method finished is as follows:

Get μ _i〉=0, storage chaos value x _iThe chaos latch by K+1 D-latch Q _KQ _K-1Q _K-2～Q ₀Form, wherein Q _kDeposit x _iSymbol, Q _K-1Q _K-2～Q ₀Deposit x _iAbsolute value | x _i|; Initial value key circuit is deposited chaos latch initial value, and μ value key circuit is deposited sequence μ _iValue; The lead code decision circuit judges whether come, signal is not come, and opens trigger Q if sending signal _S=0, the chaos latch is inserted initial value; Signal is come, and puts Q immediately _S=1, start chaos sequence generator, each clock cp finishes the chaotic function interative computation one time, generates K position chaos output Y _K-1～Y ₀Generate Y _K-1～Y ₀Method be: 1. the step-by-step translation circuit is with Q _K-1And Q _K-2～Q ₀Make the step-by-step XOR, carry out the subtraction N-1-|x of formula one thus _i| or | x _i|-N, output d _K-2～d ₀2. the shifted data selector is with μ _iAs the address code of data selector, with data d _K-2～d ₀4 μ move to right _i+ 10, carry out thus

Output g _K-12～g ₀3. subtraction circuit carries out d earlier _K-2～d ₀Subtract g _K-12～g ₀=S _K-2～S ₀, follow S as a result with subtraction _K-2～S ₀With line to moving to left 1, extreme lower position 1; Be D _K-1Meet S _K-2, D _K-2Meet S _K-3... D ₁Meet S ₀, D ₀Connect 1, realize the multiplying of formula two thus with subtraction circuit

Subtraction circuit output D _K-1D _K-2～D ₀4. at the cp rising edge subtraction circuit is exported D _K-1D _K-2～D ₀Deposit chaos latch Q in _K-1Q _K-2～Q ₀, and with Q _K-1Deposit Q _K5. chaos output circuit Q _KAnd Q _K-1～Q ₁Step-by-step XOR and Q _KNegate is with positive negative binary number Q _KQ _K-1～Q ₀Be converted into positive binary number chaos output Y _K-1～Y ₀After this each cp is repeated above-mentioned steps 1.～5. carry out, constantly produce chaos sequence output Y _K-1～Y ₀

2. the no multiply and divide of chaos encryption method of chaotic function according to claim 1 is characterized in that: expressly in the chaos queuing-chaos XOR method, get n _d=4, n _Ra=16, N then _Xor=8 * n _d=32, $N_{\mathrm{data}}=8\&times;2^{n_d}=128,$ K＝N _xor+N _data＝160， $N_{\mathrm{ra}}=n_{\mathrm{ra}}\&times;n_d\&times;2^{n_d}=1024,$ Plaintext N _DataCircuit is output as 128 plaintexts; Queuing sign indicating number key circuit is made up of 4 256 ring shift right shift registers, is output as Q _H0～Q _H3Described plaintext chaos queuing-chaos XOR method is as follows: under the control circuit effect, 1. the 1st clap 160 chaos output Y that chaos sequence generator is generated ₁₅₉～Y ₀Insert 8 16 bit shift register and 32 D-latchs; 2. the 2nd clap Q _H0～Q _H3Make the step-by-step XOR with the chaos output of 32 D-latchs respectively, draw 8 chaos queuing sign indicating numbers; 8 chaos queuing sign indicating numbers are received the address code input of eight data queued selectors respectively; This data selector data input meets expressly N _Data128 plaintext outputs of circuit are so this data selector is selected 8 as 1 plaintext rsh of byte chaos formula rearrangement team by chaos queuing sign indicating number separately from 128 plaintexts ₁～rsh ₈Rsh ₁～rsh ₈Meet 8 XOR gate input shz ₁～shz ₈Shz ₁～shz ₈Chaotic signal Q with 8 16 bit shift register outputs ₁₀～Q ₁₇Make the step-by-step XOR, XOR gate output sho ₁～sho ₈Produce the ciphertext of 1 byte; Sho ₁～sho ₈Meet outer output Z ₀～Z ₇This cp makes 4 256 ring shift right shift registers and 8 16 bit shift register move to right one, forms new output Q _H0～Q _H3And Q ₁₀～Q ₁₇3. the 3rd～17 clap the 2nd bat process of repetition, clap, produce the ciphertext of 16 serial byte forms successively, finish the chaos encryption of 128 plaintexts the 2nd～17; Following 128 plaintexts are carried out chaos encryption by the same manner;

According to described chaotic function f (x _i) the chaos sequence generation method finished is as follows: get K=160, N=2 ¹⁶⁰, μ _i〉=0, storage chaos value x _iThe chaos latch by 161 D-latch Q ₁₆₀Q ₁₅₉Q ₁₅₈～Q ₀Form; The lead code decision circuit judges that sending signal comes, and puts Q immediately _S=1, start chaos sequence generator, each clock cp of this generator generates K position chaos output Y ₁₅₉～Y ₀The generation method is that 1. the step-by-step translation circuit is with Q ₁₅₉And Q ₁₅₈～Q ₀Make the step-by-step XOR, output d ₁₅₈～d ₀2. the shifted data selector is with μ _iAs the address code of data selector, with data d ₁₅₈～d ₀4 μ move to right _i+ 10, output g ₁₄₈～g ₀3. subtraction circuit carries out d earlier ₁₅₈～d ₀Subtract g ₁₄₈～g ₀=S ₁₅₈～S ₀, follow S as a result with subtraction ₁₅₈～S ₀With line to moving to left 1, extreme lower position 1; Be D ₁₅₉Meet S ₁₅₈, D ₁₅₈Meet S ₁₅₇... D ₁Meet S ₀, D ₀Connect 1, subtraction circuit output D ₁₅₉D ₁₅₈～D ₀4. at the cp rising edge subtraction circuit is exported D ₁₅₉D ₁₅₈～D ₀Deposit low 160 Q of chaos latch in ₁₅₉Q ₁₅₈～Q ₀, and with Q ₁₅₉Deposit Q ₁₆₀5. chaos output circuit Q ₁₆₀And Q ₁₅₉～Q ₁Step-by-step XOR and Q ₁₆₀Negate is with positive negative binary number Q ₁₆₀Q ₁₅₉～Q ₀Be converted into positive binary number chaos output Y ₁₅₉～Y ₀After this each cp is repeated above-mentioned steps 1.～5. carry out, constantly produce chaos sequence output Y ₁₅₉～Y ₀

3. the chaos encryption circuit that generates of the no multiply and divide of chaos encryption method of chaotic function according to claim 1, it is characterized in that: the chaos encryption circuit comprises expressly chaos queuing-chaos XOR circuit and chaos sequence generator two large divisions; First part expressly chaos queuing-chaos XOR circuit comprises: 1. plaintext N _DataCircuit, input connects computer, and the clear data that receiving computer is sent here, and storage data are exported 128 plaintexts and are met 8 data queued selector MUX ₍₁₎～MUX ₍₈₎The data input; 2. queuing sign indicating number key circuit is made up of 4 256 ring shift right shift registers, and parallel input connects computer, by computer input queue sign indicating number key; Queuing sign indicating number key circuit has 4 output Q _H0～Q _H33. 8 queuing sign indicating number-chaos translation circuits are made up of 32 D-latchs and 32 XOR gate, an input of every of all 32 XOR gate connects 32 outputs of 32 latchs separately, 32 XOR gate are 4 row, 8 row, and an input of 8 XOR gate of every row connects together by row, meets Q respectively _H0～Q _H3, 4 outputs of 4 XOR gate of every row meet MUX in order respectively ₍₁₎～MUX ₍₈₎4 address codes input ABCD; 4. 160 chaos outputs of chaos sequence generator generation connect the parallel input of 32 D-latchs in the 8 queuing sign indicating number-chaos translation circuits and the parallel input of 8 16 bit shift register in the plaintext-chaos XOR circuit respectively; 5. plaintext-chaos XOR circuit comprises 8 16 bit shift register and 8 XOR gate; 1 input of 8 XOR gate meets MUX respectively ₍₁₎～MUX ₍₈₎8 outputs, another input of 8 XOR gate connects the output of 8 16 bit shift register respectively; 8 outputs of 8 XOR gate form the ciphertext output of a byte, under 16 clock cp effect, form the ciphertext of 16 bytes, i.e. 128 ciphertexts; Second largest part chaos sequence generator comprises: 1. the chaos latch is by 161 D-latch Q ₁₆₀Q ₁₅₉Q ₁₅₈～Q ₀Form highest order Q ₁₆₀The is-symbol position, other 160 Q ₁₅₉Q ₁₅₈～Q ₀Be the chaos data bit, Q ₁₅₉Q ₁₅₈～Q ₀Output connect step-by-step translation circuit input; 2. the step-by-step translation circuit is made up of 158 XOR gate, and each XOR gate has an input to meet Q ₁₅₉, another input meets Q successively ₁₅₈～Q ₀, step-by-step translation circuit output d ₁₅₈～d ₀Both connect the input of shifted data selector data, connect the subtraction circuit input again; 3. the shifted data selector is made up of 149 data selectors, and its address code input connects the output of μ value key circuit, and its data input connects the step-by-step translation circuit, and its output connects the subtraction circuit input, output g ₁₄₈～g ₀4. subtraction circuit is made up of 158 binary adders and inverter; The adder input connects by d ₁₅₈～d ₀With inverter output, the inverter input meets g ₁₄₈～g ₀, subtraction circuit output D ₁₅₉D ₁₅₈～D ₀Connect chaos latch D input; 5. the chaos output circuit is by Q ₁₆₀And Q ₁₅₉～Q ₁Step-by-step XOR gate and input meet Q ₁₆₀Not gate form 160 chaotic signal Y of each clock cp output ₁₅₉～Y ₀

4. the encrypting and decrypting method without multiply and divide of chaos of a chaotic function is characterized in that: this Chaotic Solution encryption method comprises that the ciphertext chaos rejoins one's unit-chaos XOR method and chaos sequence generation method two large divisions;

Described ciphertext chaos rejoins one's unit-and chaos XOR method is as follows: note N _Xor=8 * n _d, $N_{\mathrm{data}}=8\&times;2^{n_d},$ K＝N _xor+N _data， $N_{\mathrm{ra}}=n_{\mathrm{ra}}\&times;n_d\&times;2^{n_d};$ Queuing sign indicating number key circuit is N _RaPosition ring shift right shift register, it has deposited n in _RaGroup queuing sign indicating number key, it exports n _dPosition queuing sign indicating number Under the control circuit effect, every cycle period has

Clap 1 clock cp of every bat; 1. the K position chaos output Y that chaos sequence generator is generated is clapped in every circulation the 1st _K-1～Y ₀Insert N respectively _DataBit shift register and N _XorThe position D-latch is for the step prepares down; 2. the 2nd clap, at first with 1 byte ciphertext Z _R0～Z _R7The 1 byte chaos formula that is converted to the expressly rsh that waits to rejoin one's unit ₁～rsh ₈, measure is: Z _R0～Z _R7Meet shz ₁～shz ₈, with shz ₁～shz ₈With N _DataThe output chaotic signal Q of bit shift register ₁₀～Q ₁₇Make the step-by-step XOR, at 8 XOR gate output sho ₁～sho ₈, just at rsh ₁～rsh ₈The 1 byte chaos formula that produces is waited to rejoin one's unit expressly; The code conversion of then will lining up is a chaos queuing sign indicating number, and measure is: the queuing sign indicating number

Respectively with N _XorThe step-by-step XOR is made in the chaos output of position D-latch, draws 8 chaos queuing sign indicating numbers; Carry out plaintext chaos formula by chaos queuing sign indicating number at last and return team, measure is: 8 chaos queuing sign indicating numbers are received the address code input of eight data queued distributors respectively; This data distributor data output meets expressly N _DataThe N of circuit _DataThe position is input expressly, so this data distributor be the address by separately chaos queuing sign indicating number, with the 1 byte chaos formula plaintext rsh that waits to rejoin one's unit ₁～rsh ₈Deposit expressly N in _DataIn the address storaging unit of circuit response; Prepare for going on foot down simultaneously with this, measure is: this cp makes queuing sign indicating number key circuit and N _DataBit shift register all moves to right, the output that each self-forming is new

And Q ₁₀～Q ₁₇3.

Repeat the 2nd bat process;

Clap, right

Individual serial byte form decrypt ciphertext is finished N _DataThe chaos decode of position ciphertext; Press the same manner to following

Individual serial byte form ciphertext is carried out chaos decode;

Described chaos sequence generation method is to be based upon a kind of chaotic function f (x _i) on the basis, f (x _i) be expressed as

N=2 ^K, K=positive integer formula one

| x _i| ∈ [0,2N-1], | μ _i| ∈ [0,2] formula two

According to described chaotic function f (x _i) the chaos sequence generation method finished is as follows:

Get μ _i〉=0, storage chaos value x _iThe chaos latch K+1 D-latch Q arranged _KQ _K-1Q _K-2～Q ₀Form, wherein Q _kDeposit x _iSymbol, Q _K-1Q _K-2～Q ₀Deposit x _iAbsolute | x _i|; Initial value key circuit is deposited chaos latch initial value, and μ value key circuit is deposited sequence μ _iValue; The lead code decision circuit judges whether come, signal is not come, and opens trigger Q if sending signal _S=0, the chaos latch is inserted initial value; Signal is come, and puts Q immediately _S=1, start chaos sequence generator, each clock cp finishes the chaotic function interative computation one time, generates K position chaos output Y _K-1～Y ₀Generate Y _K-1～Y ₀Method be: 1. the step-by-step translation circuit is with Q _K-1And Q _K-2～Q ₀Make the step-by-step XOR, carry out formula one thus and get subtraction N-1-|x _i| or | x _i|-N, output d _K-2～d ₀2. the shifted data selector is with μ _iAs the address code of data selector, with data d _K-2～d ₀4 μ move to right _i+ 10, carry out thus Output g _K-12～g ₀3. subtraction circuit carries out d earlier _K-2～d ₀Subtract g _K-12～g ₀=S _K-2～S ₀, follow S as a result with subtraction _K-2～S ₀With line to moving to left 1, extreme lower position 1; Be D _K-1Meet S _K-2, D _K-2Meet S _K-3... D ₁Meet S ₀, D ₀Connect 1, realize the multiplying of formula two thus with subtraction circuit

Subtraction circuit output D _K-1D _K-2～D ₀4. at the cp rising edge subtraction circuit is exported D _K-1D _K-2～D ₀Deposit chaos latch Q in _K-1Q _K-2～Q ₀, and with Q _K-1Deposit Q _K5. chaos output circuit Q _KAnd Q _K-1～Q ₁Step-by-step XOR and Q _KNegate is with positive negative binary number Q _KQ _K-1～Q ₀Be converted into positive binary number chaos output Y _K-1～Y ₀After this 1.～5. each cp repetition above-mentioned steps carries out, and constantly produces chaos sequence output Y _K-1～Y ₀

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