CN1818691A - Cable fault positioning system and method - Google Patents

Abstract

A positioning system of cable fault is composed of signal sending and collecting module, data storage module, CPU module, CPLE module, keyboard module, display module and power supply module .Its positioning method can be realized by programming CPU module and CPLD module based on said system.

Description

A kind of cable fault positioning system and method thereof

Technical field

The present invention relates to a kind of system and method that is used for the cable fault location, the cable fault positioning system and the localization method that particularly relate to a kind of employing CPU (central processing unit) (hereinafter to be referred as CPU) and scale programmable logic device (ComplexProgrammable Logic Devices is hereinafter to be referred as CPLD) design.

Background technology

Cable is as the important transmission channel of train locomotive signal and ground signal, and can be directly connected to train safe and punctually moves; Engineering such as electric power, communication more needs to lay a large amount of cables, and the line characteristic situation of cable is to people's production, life important influence.Because cable is among the field environment throughout the year, be subjected to that surrounding environment, external force influence, the plague of rats and factor affecting such as burn into is aging year by year, line characteristic can change, so that faults such as broken string, swinging cross, ground connection occur, it not only influences safety of railway transportation on schedule, and can cause great economic loss to people's production, life.So how to get rid of cable fault with the shortest time, minimum cost is the current important topic that faces.

Shorten troubleshooting time, the position of trouble-shooting point is crucial apace.Although and existing cable fault positioning system kind is more on the market, all show stupid, big, numerous, inconvenient operation.A kind of " cable tester " disclosed among the Chinese patent ZL02286887.9, it comprises main frame, slave and the common conductor that connects them, main frame is made up of microprocessor A, voice signal processing unit A, control circuit A and AD converter, slave is made up of microprocessor B, voice signal processing unit B, control circuit B, and main frame cable connectivity port A links to each other with slave cable connectivity port B and forms the computer terminal detection system.This system constitutes loaded down with trivial details, must detect at two ends, especially under remote situation, needs the common conductor of corresponding length between main frame and the extension set, puts to no little inconvenience to use.This system also exists intelligent degree low in addition, and testing precision is difficult to deficiencies such as assurance.Disclose a kind of among the Chinese patent 9211989.X: " intelligent power cable fault tester and method of testing thereof ", it includes input circuit, the high-speed a/d interface, CPU (central processing unit) CPU, read only memory ROM, random access memory ram, display interface device, keyboard and printer interface.... wherein, input circuit is handled the high pressure echo voltage division signal of failure cable again, and the flashover that output is suitable for the computing machine requirement triggers and the sampling two paths of signals, is connected to the high-speed a/d interface circuit; The high-speed a/d interface is mainly pulled formation by the ultra-large integrated chip of 30MHz flash-mode A/D with according to a cover control circuit and storage that sequential relationship is designed; Read-only memory is solidified with manifold common cable fault waveform.Advanced design concept has been adopted in this invention, realize that an end detects, but the electric cable failure detector that this invention provided, the circuit elements device performance of its formation, integrated degree and intellectuality etc. are subjected to the limit levels of prevailing condition lower, equally also exist systems bulky, be difficult to reach outdoor detection maintenance job high-level efficiency, high-quality requirement etc.

Summary of the invention

For overcoming above-mentioned deficiency, the purpose of this invention is to provide a kind ofly carry, easy to use, low in energy consumption, detect degree of accuracy and high cable fault positioning system and the localization method of intelligent degree.

For achieving the above object, the present invention has adopted advanced " pulse reflection method " principle that Method of Cable Trouble Point is positioned.Its principle of work is: during test, inject action of low-voltage pulse on fault wire, this pulse edge cable is propagated up to the place of impedance mismatching, as short dot or open circuit point etc., all can cause wave reflection on these aspects, detected equipment received when reflected impulse was got back to test lead.The character type of fault can be by the decision of the polarity of reflected impulse, with the transponder pulse same polarity be the high resistant character fault of opening a way, with the transponder pulse opposite polarity be low-resistance short circuit character fault.Fault distance calculated out by the mistiming of measuring between pulse and the echo-pulse, promptly $S=\frac{1}{2}\mathrm{\υ}\·t.$

For this reason, cable fault positioning system provided by the present invention comprises following part:

Signal transmitting module: in order to drive by the central processing unit controls scale programmable logic device produce at least two kinds of frequencies transponder pulse, and this transponder pulse is transmitted on the tested cable;

Signal acquisition module: in order to gathering the reflected impulse on the tested cable, and be digital signal with the analog signal conversion of this reflected impulse;

Data memory module: in order to store above-mentioned signal acquisition module collection and the data behind the CPLD buffer memory by scale programmable logic device control;

CPU: in order to realize the control of above-mentioned signal transmitting module, signal acquisition module and data memory module and the processing of data by CPLD;

CPLD: in order to realize the control of above-mentioned CPU to above-mentioned signal transmitting module, signal acquisition module and data memory module;

Keysheet module:, realize man-machine interaction in order to input command;

Display module: parameter, test result information and data processing value thereof are set in order to demonstration;

Power module: in order to the system works power supply to be provided.

Above-mentioned signal acquisition module is to be made of digital-control amplifier and analog to digital converter (hereinafter to be referred as AD converter).

Above-mentioned Keysheet module comprises transmission single transponder pulse button, cursor left button and cursor right button.

Above-mentioned Keysheet module comprises that also pulse propagation speed increases button and pulse propagation speed reduces button.

Above-mentioned Keysheet module also comprises transmission continuous impulse button.

Above-mentioned power module comprises that digital circuit is with power module and mimic channel power module.

A kind of cable fault localization method is characterized in that comprising the following steps: at least

Step 1. system initialization and self check enter low-power consumption mode then, wait for entering interrupt routine;

When step 2. begins to test, press the Keysheet module button, system withdraws from low-power consumption mode and enters interrupt routine, judge above-mentioned key value, enter the respective keys handling procedure, described respective keys handling procedure comprises the step of transmission transponder pulse button and the step of cursor left button and cursor right button;

Step 3. enters and sends transponder pulse button program when key value is transmission transponder pulse button, and it further comprises:

Step 31.CPU control CPLD produces single transponder pulse, also this transponder pulse is sent on the tested cable by signal transmitting module;

Step 32. signal acquisition module is gathered the reflected impulse on the tested cable, and is digital signal with the analog signal conversion of this reflected impulse, by storing data memory module into behind the CPLD buffer memory, finishes until data storage;

Step 33.CPLD feeds back above-mentioned collection, stores the signal that data finish to CPU, and CPU reads in above-mentioned data by CPLD in batches;

Step 34.CPU carries out data processing to reading in data, the position of failure judgement point, and the information that shows test results on display module;

Step 35. is interrupted clearly, withdraws from interrupt routine, the system recovery low-power consumption mode;

Step 4 is pressed the cursor left button or is pressed the cursor right button, judges that key value goes forward side by side into the move to left step of button and cursor right button of cursor, makes display module show the data processing value of above-mentioned test result information.

The program of above-mentioned transmission transponder pulse key comprises that also the central processing unit controls scale programmable logic device produces continuous transponder pulse, and will this continuous transponder pulse sends to step on the tested cable core by signal transmitting module.

Above-mentioned respective keys handling procedure comprises that also pulse propagation speed increases the step that button/pulse propagation speed reduces button, in order to according to user's needs parameter to be set.

Above-mentioned interrupt routine also comprises eliminates the key jitter step.

The present invention is above-mentioned to be become apparent with other purpose, feature and advantage in order to make, and preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.

Description of drawings

Fig. 1 forms theory diagram for system of the present invention;

Fig. 2 is a kind of preferable signal transmitting module schematic block circuit diagram of the present invention;

Fig. 3 is the theory diagram of digital-control amplifier in a kind of preferable signal acquisition module of the present invention;

Fig. 4 is A/D convertor circuit schematic diagram in a kind of preferable signal acquisition module of the present invention;

Fig. 5 is a kind of preferable data memory module schematic block circuit diagram of the present invention;

Fig. 6 is a kind of preferable CPU modular circuit schematic diagram of the present invention;

Fig. 7 is a jtag interface pin circuitry schematic diagram in the CPU module;

Fig. 8 is a kind of preferable CPLD modular circuit schematic diagram of the present invention;

Fig. 9 is the circuit theory diagrams of a kind of preferable Keysheet module of the present invention;

Figure 10 is a kind of preferable display module power supply connection diagram of the present invention;

Figure 11 is a LCD interface circuit schematic diagram in the display module;

Figure 12 is a kind of preferable power module circuitry schematic diagram of the present invention;

Figure 13 is the inventive method main program flow chart;

Figure 14 is the inventive method interrupt routine process flow diagram;

Figure 15 is a kind of preferred embodiment process flow diagram of CPLD module.

Embodiment

As shown in Figure 1, the present invention partly is made up of signal transmitting module, signal acquisition module, data memory module, CPU module, CPLD module, Keysheet module and display module, power module etc.

Above-mentioned signal transmitting module can be made of high-voltage drive and peripheral circuit, for example open collector six high back voltage drivers, 7406 chips and resistance constitute, as shown in Figure 2, CPU module controls CPLD produces single transponder pulse, for example produce the high frequency square wave transponder pulse of single 0.5 μ s, by high-voltage drive transponder pulse is raised, for example be lifted to 9 volts, be transmitted into then on the tested cable.Also can produce continuous transponder pulse, for example produce the continuous high frequency square wave transponder pulse of 20KHz, and continuous transponder pulse be raised, for example be lifted to 9 volts, be transmitted into then on the tested cable by high-voltage drive by CPU module controls CPLD.

Above-mentioned signal acquisition module can be made of digital-control amplifier and AD converter, in order to gathering the reflected impulse on the tested cable, and the analog signal data of this reflected impulse is converted to digital signal data.Wherein digital-control amplifier can adopt variable gain amplifier, AD8369 chip for example, and the gain of acquired signal just can be controlled automatically by the CPU module like this.The gain control of AD8369 is shaped on two kinds of patterns: serial mode and parallel schema, and existing is example with the parallel schema, this moment, BT0-BT3 input control was encoded when the DENB pin is high.As shown in Figure 3, be AD8369 chip and peripheral circuit theory diagrams thereof.By CPU module input control coding, connected one electric capacity on the FILT pin, the electric capacity of 0.1 μ F for example, the cutoff frequency of Hi-pass filter is when gaining to-3dB $\frac{1}{2\mathrm{\π}\left({10}^{-7}\right)\left(100\right)}=16\mathrm{KHz}.$ Signal is exported to AD converter through after amplifying with differential mode.

AD converter can be by modulus conversion chip, and for example MAX1198 chip, and peripheral circuit constitutes.Because the velocity of propagation of current traveling wave in tested polyethylene insulated cable be 200m/ μ s, if require point on the waveform can tell the length of 2m, the sampling number that then needs is 200/2=100 time/μ s, requires sample frequency to reach 100MHz at least.The MAX1198 chip that present embodiment adopts is operated under the sample frequency of 140MHz, and its use has replaced the mode of a plurality of AD conversion chip of former usefulness parallel connection to improve the method for frequency acquisition, has improved the degree of stability of system greatly.As shown in Figure 4, the reference voltage of MAX1198 can be provided also and can be provided by the outside by inside.Present embodiment adopts internal reference voltage.Its CLK pin connects be the clock signal that provides of the active crystal oscillator by 140MHz (this active crystal oscillator for one independently parts provide clock signal for AD conversion chip and CPLD simultaneously).The input mode of simulating signal adopts the difference input.Its SLEEP, PD and OE pin be by the same pin control of CPU module, these three pins input low levels simultaneously when enabling the AD modular converter, and this three pin input high levels At All Other Times are to reduce power consumption.

Above-mentioned data memory module can be by static RAM (Static Random AccessMemory be hereinafter to be referred as SRAM), and for example CY7C1021BV33 and peripheral circuit are formed.8 bit data of above-mentioned AD converter output, be 16 bit data via the CPLD buffer memory after, store among the SRAMCY7C1021BV33, after all data storage finish, the waiting for CPU resume module.The sampling rate of present embodiment AD converter is 140MSPS, need deposit SRAM in the frequency of 70MHz behind the CPLD buffer memory.As shown in Figure 5, be the circuit theory diagrams of CY7C1021BV33.Because read-write all is 16 to chip,, can also connect together with CE so BLE, BHE link together.So these three pins are by the same pin control of CPLD in the circuit module.16 position datawires all directly link to each other with CPLD with 16 bit address lines.When the beginning acquired signal, data deposit CY7C1021BV33 in the frequency of 70MHz under the control of CPLD.Reading the line data of going forward side by side by the CPU module by CPLD again after storage finishes handles.

Above-mentioned CPU (central processing unit) can be made of 8 above single-chip microcomputers and peripheral circuit.For example select the MSP430 series monolithic of 16 in TI company, can realize super low-power consumption, this series monolithic has adopted reduced instruction set computer (RISC) structure, has abundant addressing mode (7 kinds of source operand addressing, 4 kinds of destination operand addressing), succinct 27 core instructions and a large amount of dummy instructions; Data-carrier store all can be participated in multiple computing in a large amount of registers and the sheet; The disposal route of tabling look-up efficiently in addition; Higher processing speed is arranged, and under the 8MHz crystal-driven, the instruction cycle is 125 μ s.These characteristics have guaranteed to work out out high efficiency source program.Present embodiment adopts MSP430F149 single-chip microcomputer wherein, and it has special super low-power consumption design, five kinds of low power mode of operation.Present embodiment uses the interrupt function of 8 pins of MSP430F149, and the negative edge that level on the pin is set produces and interrupts, and other pins all use as the I/O port.MSP430F149 has six kinds of mode of operations, is provided with by control bit.Under various mode of operations, the active state of three kinds of clocks that clock system produces has nothing in common with each other.Table 1 is the active state of each control bit and clock under the various mode of operations.Any one interrupt event can wake system up from various low-power consumption modes, and interrupt return instruction can turn back to system the state before interrupting.

The active state of each control bit and clock under the various mode of operations of table 1

Mode of operation	Control bit	CPU, the timely mitriform attitude of oscillator
			Activity pattern (AM)	SCG1＝0 SCG0＝0 OscOff＝0 CPUOff＝0	CPU is in the movable ACLK activity of the movable SMCLK of active state MCLK
Low-power consumption mode 0 (LPM0)	SCG1＝0 SCG0＝0 OscOff＝0 CPUOff＝1	CPU is in the illegal state MCLK movable ACLK activity of SMCLK that is under an embargo
			Low-power consumption mode 1 (LPM1)	SCG1＝0 SCG0＝1 OscOff＝0	CPU is in the illegal state MCLK SMCLK that is under an embargo and is under an embargo

	CPUOff＝1	The ACLK activity
			Low-power consumption mode 2 (LPM2)	SCG1＝1 SCG0＝0 OscOff＝0 CPUOff＝1	CPU is in the illegal state MCLK SMCLK ACLK activity that is under an embargo that is under an embargo
Low-power consumption mode 3 (LPM3)	SCG1＝1 SCG0＝1 OscOff＝0 CPUOff＝1	CPU is in the illegal state DCO ACLK activity that is under an embargo that MCLK is under an embargo, SMCLK is under an embargo
			Low-power consumption mode 4 (LPM4)	SCG1＝X SCG0＝X OscOff＝1 CPUOff＝1	CPU is in the illegal state MCLK SMCLK ACLK that is under an embargo that is under an embargo and is under an embargo

Finish system initialization in master routine, as setting, the distribution of port and the scheduling of interrupting of clock etc., and after the self check, the CPU module just can enter low-power consumption mode.Enter behind the low-power consumption mode even main system clock also can stop, at this moment system power dissipation is only in the scope of the μ A order of magnitude.In case the interrupt request of permission is arranged, the CPU module was waken up in the time of 6 μ s, entered activity pattern, carried out interrupt routine.After being finished, system turns back to the state before interrupting, and continues low-power consumption mode.That is to say that the situation of system power dissipation depends on the execution time of interrupt routine.Figure 6 shows that the circuit theory diagrams of MSP430F149.The external crystal oscillator of this chip is as the system works clock, and for example the crystal oscillator of external 4MHz is as the system works clock.Its pin uses as follows:

P1.0 LIGHT_L cursor left button (input)

P1.1 LIGHT_R cursor right button (input)

P1.2 SPEED_A velocity of wave propagation increases button (input)

P1.3 SPEED_S velocity of wave propagation reduces button (input)

P1.4 TEST sends 2MHz pulse button (input)

P1.5 POINT sends 20KHz continuous impulse button (input)

The expansion of P1.6 BEIYONG button is standby

The expansion of P1.7 BEIYONG button is standby

P2.0 AM0 AD8369 control signal (output)

P2.1 AM1 AD8369 control signal (output)

P2.2 AM2 AD8369 control signal (output)

P2.3 AM3 AD8369 control signal (output)

P2.4 ADEN AD enable signal (output)

P2.5 REDI reads SRAM clock signal (output)

P2.6 RAM_WE SRAM writes enable signal (output)

P2.7 BEIYONG is standby

It is wide that P3.0 0.5 μ s control CPLD launches 0.5 μ s pulse

The monopulse (output) of degree

The continuous arteries and veins of P3.1 20KHz control CPLD emission 20KHz

Dash (output)

P3.2 REDO CPLD deposits the SRAM signal (input) that finishes

P3.3 CS2 LCD panel choosing (output)

P3.4 LED_RS liquid crystal control signal (output)

P3.5 LED_WR liquid crystal control signal (output)

P3.6 LED_BUSY liquid crystal busy signal (input)

P3.7 LED_R (EN) liquid crystal control signal (output)

P4.0---P4.7 DATA15---DATA8 CPLD changes SRAM content (input)

P5.0---P5.7 DATA8---DATA0 CPLD changes SRAM content (input)

P6.0---P6.7 LED_DB0---LED_DB7 liquid crystal signal wire (output)

After each register of MSP430F149 initialization and the display module.Just change low power consumpting state over to, wait for look-at-me.Send the transponder pulse button if press, the exomonental button of for example single 0.5 μ s, MSP430F149 can control the monopulse that CPLD sends 0.5 μ s pulse width, waits for that then the SRAM of CPLD feedback stores the signal that data finish.Receive after this signal, it just reads in data by CPLD in batches.MSP430F149 carries out data processing to data after reading in, the automatic position of failure judgement point, and test result information shown on display module, for example, demonstration reflection configuration and position of failure point information.Press other button, for example, emission continuous impulse button, a cursor left side/button that moves right, pulse propagation speed increase/minimizing button etc., MSP430F149 also can carry out the processing of corresponding key assignments, after disposing, recovers low power consumpting state again automatically.The program download of MSP430F149 is JTAG (the Joint Test Action Group) interface pin by it: test clock input pin TCK, test pattern are selected pin TMS, test data input pin TDI and test data output pin TDO.By its jtag interface, we can carry out on-line debugging, boundary scan and fault detect to MSP430F149.Fig. 7 is the MSP430F149JTAG circuit theory diagrams.

Above-mentioned CPLD module can be made of MAX3000 family chip and peripheral circuit thereof.For example adopt CPLD EPM3256 to carry out the control of signal transmission, data acquisition and data storage.The maximum operation frequency of CPLDEPM3256 is 143MHz, so in order to improve accuracy of detection as far as possible, native system carries out data acquisition with the frequency of 140MHz.As shown in Figure 8, to launch single transmission pulse is example, the course of work of EPM3256 is: after EPM3256 receives the single exomonental instruction of transmission that CPU MSP430F149 sends, EPM3256 will send a monopulse at the 55th pin, the monopulse of 0.5 μ s pulse width for example, beginning the signal that the received signal acquisition module is gathered into simultaneously, for example is after 16 bit data with two 8 bit data buffer memorys, deposits the SRAMCY7C1021BV33 the inside and goes.Wait after all data storage finish, EPM3256 sends a signal to CPU MSP430F149, then under the sequential control of MSP430F149, the data in the SRAMCY7C1021BV33 is read in the MSP430F149 in batches handle.EPM3256 inside is divided into 3 parts by software.One is the frequency divider part, and the frequency division of the frequency of the 140MHz that active crystal oscillator is provided is 2MHz, and regulates clock signal to AD converter according to pulse propagation speed; Second is the Data Receiving storage area, promptly with certain time sequence, with Data Receiving and deposit in the CY7C1021BV33; The 3rd is data transmission part, and the data that are about in the CY7C1021BV33 are sent among the MSP430F149, also are at every turn all with 16 transmissions in this part.The 16 position datawire pins of EPM3256 and CY7C1021BV33 are made as the I/O pattern.Be the pin assignment of CPLD below:

The 1---2 sky

3 GND

4 CTDI JTAG pins

5---12 OD0---OD7 AD data-in port (input)

13 GND

The 14---16 sky

17 GND

The 18---19 sky

20 CTMS JTAG pins

The 21---23 sky

24 VCC

25 140MHz 140MHz crystal oscillator input ports (input)

26 GND

27 CLK

The 28---32 sky

33 GND

The 34---36 sky

The 37---49 sky

50---51 VCC

52 GND

53 2MHz control CPLD launches the monopulse of 0.5 μ s pulse width

54 20KHz control CPLD emission 20KHz continuous impulses (input) 0

55 TWOIN, 0.5 μ s, the emission outlet (output) of 20KHz pulse

56 skies

57 GND

58 VCC

59 GND

The 60---63 sky

64 GND

65---72 RAM A0---RAM A7 SRAM address wire (output)

73 VCC

74---75 RAM D15---RAM D14 SRAM data line (importing out)

76 VCC

77 GND

78---84 RAM D13---RAM D7 SRAM data line (importing out)

85 GND

86---88 RAM D6---RAM D4 SRAM data line (importing out)

89 CTCK JTAG pins

90---93 RAM D3---RAM D0 SRAM data line (importing out)

94 GND

95 VCC

96---103 RAM A8---RAM A15 SRAM address wire (output)

104 CTDO JTAG pins

105 GND

The 106---sky

107 RAM CE SRAM chip selection signals (output)

108 RAM OE SRAM enable signals (output)

109---113 DATA0---DATA4 and MSP430 data transmission (output)

114 GND

115 VCC

116---122 DATA5---DATA11 and MSP430 data transmission (output)

123 VCC

124 GND

The 125---128 sky

129 GND

130 VCC

131---134 DATA12---DATA15 and MSP430 data transmission (output)

135 GND

136 REDO CPLD deposit the SRAM signal (output) that finishes

137 REDI read SRAM clock signal (input)

The 138---143 sky

144 VCC 3.3V

Above-mentioned Keysheet module can comprise that cursor left button, cursor right button, pulse propagation speed increase button, pulse propagation speed reduces button, sends the individual pulse button and sends the continuous impulse button, in order to above-mentioned CPU (central processing unit) is sent interruptive command, realize man-machine interaction.Wherein send the individual pulse button, for example, send the continuous impulse button for sending the monopulse button of 0.5 μ s pulse width, for example for sending 20KHz continuous impulse button, can also comprise reset key and several standby buttons in addition, for example 1-8 spare key prepared against when function is expanded and used.Because the interrupt resources of CPUMSP430F149 is abundant, button all can adopt the interruption of work pattern.The key-press module of present embodiment is to be made in separately on a less printed wiring board (PCB) plate, is connected to mainboard by row's pin and winding displacement.As shown in Figure 9, when not pushing button, be the 3.3V high level on each button pin, when pressing certain button, be low level on this button pin, press that a cursor left side/button moves right, after pulse waveform shows, the user can moving cursor to reflected impulse waveform section start, MSP430F149 can show the data processing value of this test result information automatically on display module, for example show the data processing value of distance between reflected impulse waveform section start and the pulse transponder pulse point.Pulse propagation speed increase/minimizing button can be provided with the velocity of propagation of electromagnetic wave in cable according to user's needs, and system default pulse propagation velocity amplitude is 200m/ μ s.When the pulse propagation rapid change, the distance value of demonstration is respective change thereupon also.Four buttons such as an above cursor left side/button that moves to right, pulse propagation speed increase/minimizing button all have the function of continuous button, and MSP430F149 can detect button automatically and whether be in down state always, if will carry out the button subroutine continuously.Greatly facilitate user's use like this.Native system has all carried out disappearing dithering process to all buttons.

Above-mentioned display module is provided with parameter, test result information and data processing value thereof in order to demonstration.Described demonstration is provided with parameter, for example shows the parameters such as velocity of propagation of tested cable, and the information that shows test results for example shows the information such as reflection wave waveform collect, and the video data processing costs for example shows range information between measured point and the trouble spot etc.Display module can adopt LCD MODULE, for example, adopts the LCM240128ZK type liquid crystal of Beijing high official position Creative Company, its displaying contents 240 * 128 dot matrix.For mating with MSP430F149, LCM240128ZK uses the 3.3V supply voltage.Be operated under 8 6800 mode of operations.The inner subsidiary character library of LCM240128ZK is so generally need only numbering from Chinese character to particular register that import this character or when wanting character display or Chinese character.Will at first regulate slide rheostat as shown in figure 10 when liquid crystal uses, making the voltage difference between VDD and the VO is 18.5V, can normally show like this.Will reset to liquid crystal when powering on, the low level on the RST pin can not be less than 100ms, can Figure 11 shows that the interface catenation principle figure of LCM240128ZK by realizing as the electric capacity shown in Figure 11.After powering on, MSP430F149 at first will carry out initialization to LCM240128ZK, promptly to specific register assignment.LCM240128ZK has two kinds of display modes, and a kind of is the character type display mode; Another kind is the dot matrix type display mode.When wanting display waveform, at first should change the display mode of LCM240128ZK into the dot matrix type display mode.Under this display mode, LCM240128ZK is divided into 240*128 point.If want to light certain point, just write 1 to the register of its correspondence.

Above-mentioned power module comprises that digital circuit with working power and mimic channel working power, is separated from each other like this and can avoids interference.This two parts power supply all is to be transformed into 5V by 9V, and then be transformed into 3.3V by 5V, as shown in figure 12, power module can adopt LT1117-5 and LT1117-3.3 chip and peripheral circuit to constitute, their maximums can provide 800 milliamperes electric current, satisfy the needs of native system.Wherein use the device of digital 5V that active crystal oscillator of 140MHz and 7406 chips are arranged; Use the device of digital 3.3V that MSP430F149, LCM240128ZK, CY7C1021BV33 and CPLD are arranged; Use the device of simulation 3.3V that AD8369 and MAX1198 are arranged.

Cable fault localization method of the present invention, be on the basis of system of the present invention, to realize by programming to CPU module and CPLD module, for example by the c program programming of CPU MSP430F149 and the Very High Speed Integrated Circuit (VHSIC) hardware description language of CPLD EPM3256 (very-high-speed integrated circuit hardware description language is called for short VHDL) programming are realized.Be the master routine program flow diagram of CPU MSP430F149 as shown in figure 13, initialization is as required some registers and port to be provided with when program begins most.After CPU MSP430F149 initialization and self check finish, enter low power consumpting state, wait for the generation of interrupting.Figure 14 shows that the interrupt routine process flow diagram of the master routine of CPU MSP430F149.CPUMSP430F149 enters after the interrupt routine, judges it is the interruption which port causes earlier, judges once behind the 10ms that delays time then again, can eliminate the erroneous judgement that causes because of shake like this.CPUMSP430F149 judges above-mentioned key value, and enters correspondent button value handling procedure, and is last, and clear the interruption withdrawed from interrupt routine, the system recovery low-power consumption mode.

Top-down Design Mode is adopted in the VHDL programming of CPLD EPM3256.Bottom is divided into three modules, is encapsulated by a TOP top document at last.The VHDL program bottom of EPM3256 is divided into three modules: first is a frequency division module, because after the frequency reception data of EPM3256 with 140MHz, send to SRAM with the frequency of 70MHz, so will carry out 2 frequency divisions earlier; Second is the Data Receiving memory module, after receiving sense command, sends the monopulse of one 0.5 μ s pulse width earlier in this module, simultaneously the data of input is carried out buffer memory and exports to SRAM then; The 3rd is data transmission blocks, and this module reads out data in the SRAM and sends to CPU MSP430F149 then.The VHDL top-level module end_top.vhdl of native system is realized by the TOP file.This document gets up three module package of bottom, forms a complete module.Figure 15 shows that a kind of preferred embodiment process flow diagram of CPLD module.

System of the present invention has carried out actual test at the railway scene.Tested object is the cable of 8 known fault point positions, and wherein short trouble is 4,4 of open circuit faults.The cable model is PTYA23, i.e. polyethylene insulation composite sheath steel-tape armouring signal cable, and this model cablebreak speed is 201m/ μ s.The trouble spot of two kinds of faults all is respectively 83m, 135m, 400m, 670m apart from test point.During test, to every wireline test five times, the gained result is as shown in table 2.From test result, native system has reached the requirement at railway scene substantially.

Table 2 test result relatively

Physical fault point position (m)	Short trouble measurement result (m)	Open circuit fault measurement result (m)	Physical fault point position (m)	Short trouble measurement result (m)	Open circuit fault measurement result (m)
						83m	84	84	400m	401	402
83	83	400	400
				85	85		401	401
84	84	402	401
				83	85		402	400
135m	136	136	670m							670	672
				136	137	671	670
	136	136						671	672
				137	136	672	672
	135	135						671	671

The present invention had both solved the processing speed problem of CPU owing to adopt the control model of " CPU+ high speed CPLD ", had effectively reduced the quantity of peripheral chip again, had improved the reliability of system.The present invention adopts novel ultra high speed A chip, has replaced the mode of a plurality of AD conversion chip of former usefulness parallel connection to improve the method for frequency acquisition, has improved the degree of stability of system greatly.As long as use the present invention in the operation of cable one end, the intelligent degree height of fault test was as long as be subjected to the personnel of basic training can both find out the trouble spot smoothly.System adopts low power dissipation design, and instrument is battery-powered, has satisfied the portable requirement of field work.

Though the present invention with preferred embodiment openly as above; but be not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the scope that claim defines.

Claims (10)

1. cable fault positioning system is characterized in that comprising following part:

Signal transmitting module: in order to drive by the central processing unit controls scale programmable logic device produce at least two kinds of frequencies transponder pulse, and this transponder pulse is transmitted on the tested cable;

Signal acquisition module: in order to gathering the reflected impulse on the tested cable, and be digital signal with the analog signal conversion of this reflected impulse;

Data memory module: in order to store above-mentioned signal acquisition module collection and the data behind the CPLD buffer memory by scale programmable logic device control;

CPU (central processing unit): in order to realize the control of above-mentioned signal transmitting module, signal acquisition module and data memory module and the processing of data by scale programmable logic device;

Scale programmable logic device: in order to realize of the control of above-mentioned CPU (central processing unit) to above-mentioned signal transmitting module, signal acquisition module and data memory module;

Keysheet module:, realize man-machine interaction in order to input command;

Display module: parameter, test result information and data processing value thereof are set in order to demonstration;

Power module: in order to the system works power supply to be provided.

2. positioning system according to claim 1 is characterized in that described signal acquisition module is to be made of digital-control amplifier and analog to digital converter.

3. positioning system according to claim 2 is characterized in that described Keysheet module comprises transmission single transponder pulse button, cursor left button and cursor right button.

4. positioning system according to claim 3 is characterized in that described Keysheet module comprises that also pulse propagation speed increases button and pulse propagation speed reduces button.

5. positioning system according to claim 4 is characterized in that described Keysheet module also comprises transmission continuous impulse button.

6. according to the described positioning system of arbitrary claim in the claim 1 to 5, it is characterized in that described power module comprises that digital circuit is with power module and mimic channel power module.

7. a cable fault localization method is characterized in that comprising the following steps: at least

Step 1. system initialization and self check enter low-power consumption mode then, wait for entering interrupt routine;

When step 2. begins to test, press the Keysheet module button, system withdraws from low-power consumption mode and enters interrupt routine, judge above-mentioned key value, enter the respective keys handling procedure, described respective keys handling procedure comprises the step of transmission transponder pulse button and the step of cursor left button and cursor right button;

Step 3. enters and sends transponder pulse button program when key value is transmission transponder pulse button, and it further comprises:

Step 31 central processing unit controls scale programmable logic device produces single transponder pulse, also this transponder pulse is sent on the tested cable by signal transmitting module;

Step 32. signal acquisition module is gathered the reflected impulse on the tested cable, and is digital signal with the analog signal conversion of this reflected impulse, by storing data memory module into behind the scale programmable logic device buffer memory, finishes until data storage;

Step 33. scale programmable logic device feeds back above-mentioned collection, stores the signal that data finish to CPU (central processing unit), and CPU (central processing unit) is read in above-mentioned data by scale programmable logic device in batches;

Step 34. CPU (central processing unit) is carried out data processing to reading in data, the position of failure judgement point, and the information that shows test results on display module;

Step 35. is interrupted clearly, withdraws from interrupt routine, the system recovery low-power consumption mode;

Step 4 is pressed the cursor left button or is pressed the cursor right button, judges that key value goes forward side by side into the move to left step of button and cursor right button of cursor, makes display module show the data processing value of above-mentioned test result information.

8. localization method according to claim 7, the program that it is characterized in that above-mentioned transmission transponder pulse key comprise that also the central processing unit controls scale programmable logic device produces continuous transponder pulse, and will this continuous transponder pulse sends to step on the tested cable core by signal transmitting module.

9. according to claim 7 or 8 described localization methods, it is characterized in that above-mentioned respective keys handling procedure comprises that also pulse propagation speed increases the step that button/pulse propagation speed reduces button, in order to parameter to be set according to user's needs.

10. according to the described localization method of arbitrary claim in the claim 7 to 9, it is characterized in that above-mentioned interrupt routine also comprises elimination key jitter step.

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