CN1802569A - Pattern generator and test apparatus - Google Patents
Pattern generator and test apparatus Download PDFInfo
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- CN1802569A CN1802569A CNA2004800159351A CN200480015935A CN1802569A CN 1802569 A CN1802569 A CN 1802569A CN A2004800159351 A CNA2004800159351 A CN A2004800159351A CN 200480015935 A CN200480015935 A CN 200480015935A CN 1802569 A CN1802569 A CN 1802569A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31813—Test pattern generators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
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- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
A pattern generator includes: a main memory for storing a plurality of sequence data blocks for generating a test pattern; a first sequence cache memory for successively storing the sequence data blocks; a second sequence cache memory, a data spread section for successively executing the sequence data blocks stored in the first cache memory and generating a test pattern; and pre-read means. While the data spread section is executing a sequence data block, if a pre-read instruction for pre-reading another sequence data block is detected, the pre-read means reads out the another sequence data block from the main memory and stores it in the second sequence cache memory.
Description
Technical field
The invention relates to a kind of pattern generator and proving installation.Particularly, the invention relates to a kind of pattern generator and proving installation for testing electronic element.At the designated state of admitting to incorporate into bibliographic reference,, incorporate in the application's case, as the part of the application's case with reference to the content that following application case is put down in writing.
The special hope 2003-163461 applying date is put down on June 9th, 15
Background technology
Since known, pattern generator is used in the proving installation of testing electronic element.Pattern generator is for testing electronic element, produces the test pattern of the input signal of electronic component.Since known, pattern generator produces test pattern from pattern data and sequence data.
Pattern generator comprises memory body and gets (cache) memory body soon that memory body is that the memory cache body is to read pattern data and sequence data from memory body in regular turn with execution sequence storage pattern data group and sequence data group, and stores.Sequence data is used for producing the order group of test pattern for utilizing the order of indication output pattern data, and by being constituted in the jump of data (jump) order and loop (loop) order etc. in proper order.
Pattern generator is read pattern data and sequence data in regular turn from memory body, is stored in the memory cache body.In addition, according to the sequence data that is stored in the memory cache body, the pattern data from be stored in the memory cache body produces test pattern.
In the order group of sequence data, detect when jumping to the address that does not have the sequence data that stores and pattern data in the memory cache body, pattern generator reads out sequence data and pattern data at this address from memory body, and is stored into the memory cache body.
Therefore, when reading out sequence data and pattern data from memory body, can produce time for reading, when pattern generating, just may produce the stand-by period.In addition, when the functional test of carrying out electronic component and sweep test, functional test must be stored in continuous address space in the memory body with data and sweep test with execution sequence with data.Therefore, for example when wanting repeatedly to use sweep test to use data, must be most identical data storage in memory body, so the jumbo memory body of needs.
Summary of the invention
Purpose of the present invention promptly is that a kind of pattern generator and proving installation that can solve foregoing problems will be provided.This purpose can be made up by the feature that the independent entry of claim is put down in writing to be reached.In addition, depend on item and then stipulated more favourable object lesson of the present invention.
In order to address the above problem, implement kenel according to of the present invention first, a kind of pattern generator is provided, produce from the test data that gives in advance and be used for the test pattern of testing electronic element.Pattern generator comprises memory main body, stores most sequence data blocks in order to produce test pattern; The first sequence memory cache body stores those sequence data blocks in regular turn; The second sequence memory cache body; Data expansion portion carries out those stored sequence data blocks of the first sequence memory cache body, in regular turn to produce this test pattern; And read the unit earlier, in order to carry out in the sequence data block in data expansion portion, if when detecting the first read command that read other sequence data blocks earlier, read out other sequence data blocks from memory main body, and be stored in the second sequence memory cache body.
If data expansion portion when detecting the jump commands that carry out other sequence data blocks, reads and carries out other sequence data blocks from the second sequence memory cache body after detecting this elder generation's read command.After detecting first read command,, read and carry out the sequence data block from the first sequence memory cache body if when in a sequence data block, not detecting jump commands.
Memory main body more stores most pattern data blocks, shows should the sequence data block giving the signal of electronic component.Pattern generator more comprises the first pattern memory cache body, in order to store the pattern data blocks corresponding to the stored sequence data block of the first sequence memory cache body; And the second pattern memory cache body.Reading the unit earlier carries out in the sequence data block in data expansion portion, if when detecting the first read command that read other sequence data blocks earlier, read out the pattern data blocks corresponding from memory main body, and be stored in the second pattern memory cache body with other sequence data blocks.Data expansion portion is by carrying out the sequence data block, and pattern data blocks that will be corresponding with other sequence data blocks launches, to produce test pattern.
Elder generation's read command is an order, in order to specify the initial address at memory main body of the sequence data block that should read earlier and corresponding pattern data blocks.Read the unit earlier and use appointed initial address, from memory main body, read out sequence data block and pattern data blocks earlier.
Elder generation's read command is an order, in order to specify the sequence data block read earlier and the label of pattern data blocks.Pattern generator more comprises the reference memory body, in order to distinguish corresponding storage with label and by this label appointed sequence data blocks with the address at memory main body of pattern data blocks.Reading the unit earlier can be according to label, obtains address at memory main body from the reference memory body, and reads out sequence data block and pattern data blocks according to the address of obtaining earlier from memory main body.
The sequence data block comprises the scanning sequence data blocks of the sweep test that is used for carrying out electronic component, and the pattern data blocks comprises the scan pattern data blocks of the sweep test that is used for carrying out electronic component.Read the unit earlier and can read scanning sequence data blocks and scan pattern data blocks earlier.
Expansion portion can repeatedly carry out a scanning sequence block when producing this test pattern.Memory main body can be stored in most scanning sequence data blocks in the continuous zone.Memory main body can be stored in most scan pattern data blocks in the continuous zone.
Data expansion portion is in carrying out these other sequence data blocks, if when detecting the return command of Next Command of the jump commands that turn back to a sequence data block, can from the first sequence cache block, read out and carry out Next Command in the jump commands of a sequence data block.
According to the second enforcement kenel of the present invention, the invention provides a kind of proving installation, in order to testing electronic element.Proving installation comprises pattern generator, produces test pattern, with testing electronic element; Waveshaper is in order to the shaping test pattern; And judging part, according to the quality of output signal judgement electronic component, wherein electronic component is according to the test pattern output signal output.The aforementioned pattern generator more comprises memory main body, stores most sequence data blocks in order to produce test pattern; The first sequence memory cache body stores those sequence data blocks in regular turn; The second sequence memory cache body; Data expansion portion carries out those stored sequence data blocks of the first sequence memory cache body in regular turn, to produce test pattern; And read the unit earlier, in order to carry out in the sequence data block in data expansion portion, if when detecting the first read command that to read other sequence data blocks earlier, read out other sequence data blocks from memory main body, and be stored in the second sequence memory cache body.
In addition, above-mentioned summary of the present invention is not to list all essential feature of the present invention, and the inferior combination of these syndromes also is to constitute feature of the present invention.
According to the present invention, can produce test pattern more efficiently.In addition, testing electronic element more efficiently.In addition, can dwindle the memory body capacity of use.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is a structure example of the proving installation 100 of the demonstration embodiment of the invention.
Fig. 2 shows a structure example synoptic diagram of pattern generator 20.
Fig. 3 illustrates the synoptic diagram of the detailed construction example of memory body control part 70, pattern generating section 80 and serial device 90.
Fig. 4 illustrates the synoptic diagram in the data structure example of memory main body 60.
Fig. 5 illustrates the example of the test pattern of pattern generator 50 generations.
Fig. 6 illustrates the synoptic diagram of the action example of pattern generator 50.
Fig. 7 illustrates the synoptic diagram of other examples of the structure of proving installation 100.
Fig. 8 illustrates the synoptic diagram of the data structure example of most memory main bodies 60.
Fig. 9 illustrates the synoptic diagram of the data structure example of most memory main bodies 60.
150: test board control part 50: pattern generator
40: waveshaper 20: determining device
30: signal is exported into portion 100: proving installation
200: electronic component 60: memory main body
110: bus-bar control part 70: the memory body control part
10: inefficacy memory body 140: get control part soon
80: pattern generating section 90: serial device
120: algorithm 130: get portion soon
72: read unit 160 earlier: the reference memory body
84: the second pattern memory caches of 82: the first pattern memory cache bodies body
86: 92: the first sequence memory caches of bus-bar control part body
94: the second sequence memory cache bodies 96: sequence control part
Embodiment
Then, see through embodiments of the invention the present invention is described, but following embodiment is used for limiting the invention relevant with claim, and all combinations of illustrated in an embodiment in addition feature are not limited to the necessary important document of invention solution.
Fig. 1 is a structure example of the proving installation 100 of the demonstration embodiment of the invention.Proving installation 100 testing electronic elements 200.Proving installation 100 possesses pattern generator 50, waveshaper 40, signal and exports into portion 30 and judging part 20.At this, electronic component 200 is meant the element that moves in response to the electronic signal that is given.For example, the semiconductor circuit etc. that comprises IC wafer with semiconductor device, LSI etc.
Waveshaper 40 receives and the shaping test pattern, offers signal with desired sequential and exports into portion 30.Signal is exported into portion 30 test pattern that receives is offered electronic component 200, and electronic component 200 receives the output signal of exporting according to test pattern.
Judging part 20 is judged the quality of electronic component 200 according to the output signal that receives.For example, judging part 20 receives expectation value signals from pattern generator 50, and by the output signal of this expectation value signal and electronic component 200 relatively, the quality of judgement electronic component 200.
Fig. 2 shows a structure example synoptic diagram of pattern generator 20.Pattern generator 50 comprises memory main body 60, data expansion portion 170, serial device (sequencer) 90, bus-bar control part 110, algorithm pattern generating section 120, acquisition portion 130, acquisition control part 140 and inefficacy memory body (failmemory) 10.Data expansion portion 170 comprises memory body control part 70 and pattern generating section 80.
Memory main body 60 stores in order to produce the test data of test pattern.Test data is divided into most test data blocks and stores.For example, memory main body 60 stores a majority pattern data blocks (pattern data block) and most sequence data blocks (sequence data block) as the test data block, wherein most pattern data blocks are cut apart the pattern data that shows the signal that should give electronic component 200, and the sequence data block is should be cut apart to the pattern data sequence data of the order of electronic component 200 with being used to refer to.In addition, memory main body 60 is with the corresponding storage with the sequence data block of pattern data blocks.
Bus-bar control part 110 is from test board control part 150, reception should provide the indication information of test data block to the order of pattern generator 80 and/or serial device 90, and according to this indication information, any one pattern data blocks and/or the sequence data block that should read from memory main body 60 are indicated memory body control part 70 in regular turn.Memory body control part 70 reads pattern data blocks and sequence data block according to from the received indication of bus-bar control part 110 in regular turn from memory main body 60.The pattern data blocks of reading offers pattern generating section 80 in regular turn, and the sequence data block of reading offers serial device 90 in regular turn.
In addition, when the electronic component 200 that should test was memory body, serial device 90 can provide the indicator signal that makes the pattern data that produces memory body test usefulness to algorithm pattern generating section 120.Algorithm pattern generating section 120 according to predefined algorithm, produces memory body test pattern data when receiving the situation of this indicator signal.In this situation, pattern generating section 80 more according to memory body test pattern data, produces test pattern.
Acquisition portion 130 and acquisition control part 140 are stored in inefficacy memory body 10 with the judged result of judging part 20.The memory body test that the address of the pattern data blocks of 90 pairs of pattern generating section of acquisition portion 130 receiving sequence devices 80 indication or algorithm pattern generating section 80 produce with data both any one or all.Acquisition portion 130 provides the address of corresponding pattern data blocks or any one that data is used in corresponding memory body test in judged result, or both.Acquisition control part 140 receives from test board control part 150 and is used to refer to the indicator signal that whether judged result is stored into inefficacy memory body 10, and to should indicator signal, provides judged result to inefficacy memory body 10.
In addition, when the end of test (EOT) of a pattern data blocks, acquisition control part 140 also can be with the judged result notice bus-bar control part 110 of this pattern data blocks.In this situation, bus-bar control part 110 is with this judged result notice test board control part 150.
In addition, inefficacy memory body 10 stores the judged result of judging part 20.Test board control part 150 can be read the judged result that inefficacy memory body 10 stores, and carries out the analysis of the test result of electronic component 200, also can carry out the analysis of test result according to the judged result of each pattern data blocks.In addition, in this example, pattern generator 50 has inefficacy memory body 10, but in other examples, pattern generator 50 does not have inefficacy memory body 10, and proving installation 100 also can have inefficacy memory body 10, and test board control part 150 also can have the inefficacy memory body in addition.
Fig. 3 illustrates the synoptic diagram of the detailed construction example of memory body control part 70, pattern generating section 80 and serial device 90.Memory body control part 70 comprises reads unit 72 earlier, and pattern generator 80 comprises memory cache body 88 and pattern control part 86, and serial device 90 comprises memory cache body 98 and serial device controller 96.
Memory body control part 70 reads data according to the indication information that is received from the bus-bar control part from memory main body 60, and is stored into memory cache body 88 and memory cache body 98.Memory cache body 88 comprises the first pattern memory cache body 82 and the second pattern memory cache body 84.Memory cache body 98 comprises the row memory cache body 92 and the second sequence memory cache body 94 in regular turn.
Memory body control part 70 is stored into the first pattern memory cache body 82 to the pattern data blocks in regular turn, and the sequence data block is stored into the first sequence memory cache body 92 in regular turn according to from the received indication information of bus-bar control part 110.
Pattern control part 86 produces test pattern according to the pattern data blocks that the first pattern memory cache body 82 stores.For example, be received in the address of the first pattern memory cache body 82 in regular turn, and export the pattern data of the address that receives in regular turn, to produce test pattern from sequence control part 96.
Sequence control part 96 takes out and carries out the sequence data block that the first sequence memory cache body 92 stores in regular turn.For example, the sequence data block is the order group who comprises jump commands, loop order and return command etc., and sequence control part 96 is indicated the address of the first pattern memory cache body 82 to pattern control part 86 in regular turn according to the order at the sequence data block.
Sequence control part 96 is in carrying out a sequence data block, if when detecting the situation of the first read command that read other sequence data blocks earlier in this sequence data block, sequence control part 96 should elder generation's read command notice memory body control part 70 reads the unit earlier.For example, the sequence data block is the order group who comprises jump commands, loop order and return command etc., and sequence control part 96 is indicated the address of the first pattern memory cache body 82 to pattern control part 86 in regular turn according to the order in the sequence data district.
Sequence control part 96 is being carried out during a sequence data district determines, if detect should read the first read command of other sequence data blocks earlier the time at this sequence data block, what sequence control part 96 should elder generation's read command be notified to the memory body control part reads unit 72 earlier.For example, in the sequence data block of carrying out the main formula (main routine) that shows test pattern, when detecting the secondary formula (subroutine) of first read test pattern, just with this message notice memory body control part 70.
Read unit 72 earlier when sequence control part 96 receives the notice of first read command, read first read command appointed sequence data blocks from memory main body 60, and be stored into the second sequence memory cache body 94.In addition, read unit 72 earlier in 86 actions of pattern control part, read data earlier, be stored in the memory cache body from memory main body 60.
Sequence control part 96 is after detecting first read command, when the jump commands that detects at the stored sequence data block that should carry out of the second sequence memory cache body 94, just read out and carry out at the stored sequence data block of the second sequence memory cache body 94.Afterwards,, pattern control part 86 produces test pattern according to being stored in pattern data blocks corresponding in the second pattern memory cache body 84.When this situation, sequence control part 96 can specify in the address of the second pattern memory cache body 84.In addition, when the first pattern memory cache body 82 and the second pattern memory cache body 84 are two address spaces at identical memory cache body, also can specify the address of this memory cache body.
In addition, after detecting first read command,, just read and carry out the sequence data block that the first sequence memory cache body, the 92 stored next ones should be carried out when not when executory sequence data block detects jump commands.
At this, to read the life life earlier and can be an order, it specifies in the order of the initial address of memory main body 60 in the sequence data block that should read earlier.In addition, first read command can be the order of specifying the label (label) of the sequence data block that read earlier.At this, so-called label is for specifying the information of each sequence data block.In this situation, pattern generator 50 can more comprise reference memory body 160, is used for label and corresponding and store to the initial address at memory main body 60 of sequence data block that should label.Sequence control part 96 can be notified to this label and read unit 72 earlier, reads unit 72 earlier according to this label, extracts address at memory main body 60 from reference memory body 160, reads out sequence data block on the address that extracts from memory main body 60 again.
In addition, read unit 72 earlier from memory main body 60, read out the pattern data blocks that corresponds to the sequence data block, be stored into the second pattern memory cache body 84 again.Read unit 72 earlier in the action of other composed components of pattern generator 50,, and be stored into the second pattern memory cache body 84 and the second sequence memory cache body 94 from memory main body 60 first read test data.Therefore, if use present embodiment, the stand-by period of can the minimizing data reading, and produce test pattern continuously.In addition, memory body control part 70 is stored into the first pattern memory cache body 82 and the first sequence memory cache body 92 according to the indication information in regular turn with test data.By in memory body control part 70 also action, store test data in regular turn, so can produce test pattern continuously at other composed components of pattern generator 50.As mentioned above, according to the pattern generator 50 of present embodiment, can produce test pattern more efficiently.
The first pattern memory cache body 82 and the second pattern memory cache body 84 can be two address spaces at identical memory cache body, also can be two other memory cache bodies.In addition, also be identical in row memory cache body 92 and the second sequence memory cache body 94 in regular turn.
In addition, proving installation 100 also can carry out the sweep test of electronic component.At this, so-called sweep test is for for example comprising the test by the test specimens attitude of IEEE1149.1 decision, the test of the scanning qualifying (scan pass) of testing electronic element.In this situation, the pattern data blocks that memory main body 60 stores comprises the scan pattern data blocks that sweep test is used, and the sequence data block comprises the scanning sequence data blocks that sweep test is used.In addition, proving installation 100 also can be made up sweep test and other test and be carried out.For example, proving installation 100 can combine sweep test in the lump with the functional test of the logic section of testing electronic element and carry out.
Fig. 4 illustrates the synoptic diagram in the data structure example of memory main body 60.In the present example, proving installation 100 carries out functional test and sweep test.Memory main body 60 is stored into most sequence data blocks shown in Figure 4, most scanning sequence data blocks, most pattern data blocks and most scan pattern data blocks in the continuous zone respectively.This routine pattern generator 50 is owing to according to the initial address of being used data blocks by the specified sweep test of first read command, carry out reading of data blocks, and each can be stored in each in the memory main body by other each data blocks continuously.
In addition,, be not stored in the memory main body under each data blocks, can produce test pattern continuously yet yet with execution sequence according to this routine pattern generator.Therefore, be that the data of unit is appended, deleted and replace or the like and can easily carry out with the data blocks.
Fig. 5 illustrates the example of the test pattern of pattern generator 50 generations.In this example, pattern generator 50 produces the test test pattern that functional test and sweep test are combined.
Fig. 6 illustrates the synoptic diagram of the action example of pattern generator 50.In this example, pattern generator 50 produces test pattern shown in Figure 5.In this example, pattern generator 50 mainly carries out functional test according to the sequence data block that is stored in the first sequence scanning memory cache body 92, and according to the sequence data block that is stored in the second sequence scanning memory cache body 94, carries out sweep test.
At first, memory body control part 70 should be used in the pattern data blocks and the sequence data block of the generation of this test pattern according to the indication information, be stored in the first pattern memory cache body 82 and the first sequence memory cache body 92 in regular turn.Therefore at this, memory body control part 70 can be deleted the data blocks of having carried out, the dummy section of the memory cache body that the produces block that then stores data in regular turn.In addition, the data blocks that memory body control part 70 also can should store next time covers the data blocks of having carried out.Preferable in addition, the memory cache body has the zone that can store most data blocks.
Serial device 90 is carried out stored sequence data block in the first sequence memory cache body 92 in regular turn.If sequence data block 1 in commission detects under the situation of first read command, read unit 72 earlier and should be stored into the second sequence memory cache body 94 by the specified scanning sequence data blocks 1 of elder generation's read command.
If detect jump commands at sequence data block 1, serial device 90 is carried out the scanning sequence data blocks 1 that the second sequence memory cache body 94 stores.If serial device 90 detect turn back to when the Next Command of the jump commands of sequence data block 1, then reads and carry out the Next Command of this jump commands.In addition, when jump commands was the finish command of sequence data block 1, serial device 90 read out and carries out next sequence data block 2 from the first sequence memory cache body.
Detect first read command at next sequence data block, the scanning sequence data blocks 2 of appointment is stored into the second sequence memory cache body 94.In this case, reading unit 72 earlier can be from second sequence memory cache body deletion scanning sequence data blocks 1.
In addition, as shown in Figure 6, when data expansion portion 170 produces the situation of a test pattern again, can repeatedly carry out scanning sequence data blocks 1.According to words at this routine pattern generator 50, owing to read out the specified scanning sequence data blocks of first read command from memory main body 60, be stored into the second sequence memory cache body 94 again, the data blocks that is stored in a zone of memory main body 60 can repeatedly be carried out.Therefore, compared to data blocks is stored in situation in the memory main body 60 with execution sequence, the capacity of memory main body 60 can dwindle.
In addition, according to this routine pattern generator 50, owing to be stored in the memory cache body with data blocks by the specified sweep test of first read command, functional test and sweep test can combination in any.
In addition, though this example be the explanation about the sequence data block, pattern generator 50 also is to carry out identical processing for the pattern data blocks corresponding to the sequence data block.
Fig. 7 illustrates the synoptic diagram of other examples of the structure of proving installation 100.In this example, proving installation 100 comprises most pattern generators 50, and it corresponds to most pins (pin) of electronic component 200 respectively.In addition, also more can comprise most waveshapers 40 that correspond to each pattern generator 50.
Fig. 8 and Fig. 9 illustrate the synoptic diagram of the data structure example of most memory main bodies 60.Fig. 8 and Fig. 9 represent with the pin title in the data zone that corresponds to each memory main body 60.Memory main body 60 is identical with the memory main body 60 of Fig. 4 related description, stores most sequence data blocks (SQ), most scanning sequence data blocks (SC), most pattern data blocks (PD) and most scan pattern data blocks (SP).
When proving installation 100 carries out the situation of sweep test, do not correspond to sweep test and do not produce test pattern with the pattern generator 50 of pin.Therefore, hunt data blocks for scan pattern data blocks and the scanning preface corresponding to the pin of sweep test not, corresponding memory main body 60 does not just store.Therefore, just in address space, produce the zone of vacating in the memory main body 60.
For example in Fig. 8, pin 1 is the sweep test pin, and pin 2 to pin 4 is the pin that does not correspond to sweep test.Memory main body 60 just produces dummy section 210 and dummy section 220 owing to do not have to store corresponding to the scanning sequence data blocks and the scan pattern data blocks of pin 2 to pin 4 in address space.
This routine memory main body 5 also can be in this dummy section, is stored in the performed data blocks of other pattern generators 50.For example, as shown in Figure 9, can store the scanning sequence data blocks (SC1-n) and the scan pattern data blocks (SP1-n) of pin 1 usefulness.In this case, pattern generator 50 comprises the means that read data blocks from the memory main body of other pattern generators 50.For example, memory body control part 70 can read data blocks from the memory main body 60 of other pattern generators 50.According to this routine proving installation 100, the zone of memory main body 60 can be used more efficiently.Therefore, can dwindle the capacity of memory main body 60.
As above-mentioned explanation, know proving installation 100 according to present embodiment, test pattern can be produced more efficiently, and the memory body capacity can be lowered.
Can understand from above-mentioned explanation,, can produce test pattern more efficiently according to words of the present invention.In addition, testing electronic element more efficiently.Moreover the memory body capacity of use can dwindle.
Though the above-mentioned use embodiment of the invention illustrates that technical scope of the present invention is not limited to the record scope of the foregoing description.The above embodiments can add various change and improvement.The enforcement kenel that adds this kind change or improvement also is to be contained in technical scope of the present invention.
Claims (11)
1. a pattern generator produces a test pattern that is used for testing an electronic component from a test data that gives in advance, and this pattern generator comprises:
One memory main body stores most sequence data blocks in order to produce this test pattern;
One first sequence memory cache body stores those sequence data blocks in regular turn;
One second sequence memory cache body;
One data expansion portion carries out those stored sequence data blocks of this first sequence memory cache body, in regular turn to produce this test pattern; And
One reads the unit earlier, in order to carry out in this sequence data block in this data expansion portion, if when detecting the first read command that read other these sequence data blocks earlier, read out other this sequence data blocks from this memory main body, and be stored in this second sequence memory cache body.
2, pattern generator according to claim 1, wherein this data expansion portion is after detecting this elder generation's read command, if when detecting the jump commands that carry out other these sequence data blocks, read and carry out other this sequence data blocks from this second sequence memory cache body
After detecting this elder generation's read command,, read and carry out this sequence data block from this first sequence memory cache body if when in this sequence data block, not detecting this jump commands.
3, pattern generator according to claim 2, wherein this memory main body more stores most pattern data blocks, show should the sequence data block should giving the signal of this electronic component,
This pattern generator more comprises one first pattern memory cache body, in order to store this pattern data blocks corresponding to this stored sequence data block of this first sequence memory cache body; And one second pattern memory cache body,
Wherein this is read the unit earlier and carries out in this sequence data block in this data expansion portion, if when detecting the first read command that read other these sequence data blocks earlier, read out this pattern data blocks corresponding from this memory main body with other this sequence data blocks, and be stored in this second pattern memory cache body
This data expansion portion is by carrying out this sequence data block, and this pattern data blocks that will be corresponding with other these sequence data blocks launches, to produce this test pattern.
4, pattern generator according to claim 3 should elder generation's read command be an order wherein, in order to specifying the initial address at this memory main body of this sequence data block that should read earlier and corresponding this pattern data blocks,
This is read the unit earlier and uses appointed this initial address, reads out this sequence data block and this pattern data blocks from this memory main body earlier.
5, pattern generator according to claim 3 should elder generation's read command be an order wherein, in order to specifying this sequence data block read earlier and the label of this pattern data blocks,
This pattern generator more comprises a reference memory body, in order to this label and by of the address respectively corresponding storage at this memory main body of specified this sequence data block of this label with this pattern data blocks,
This reads the unit earlier according to this label, obtains a address at this memory main body from this reference memory body, and reads out this sequence data block and this pattern data blocks according to this address of obtaining earlier from this memory main body.
6, pattern generator according to claim 3, wherein this sequence data block comprises the one scan sequence data block of the one scan test that is used for carrying out this electronic component, this pattern data blocks comprises the one scan pattern data blocks of this sweep test that is used for carrying out this electronic component
This is read the unit earlier and reads this scanning sequence data blocks and this scan pattern data blocks earlier.
7, pattern generator according to claim 3, wherein should expansion portion when producing this test pattern, repeatedly carry out this scanning sequence block.
8, pattern generator according to claim 7, wherein this memory main body is that most scanning sequence data blocks are stored in the continuous zone.
9, pattern generator according to claim 7, wherein this memory main body is that most scan pattern data blocks are stored in the continuous zone.
10, pattern generator according to claim 2, wherein this data expansion portion is in carrying out these other sequence data blocks, if when detecting the return command of Next Command of this jump commands that turn back to this sequence data block, from this first sequence cache block, read out and carry out this Next Command in this jump commands of this sequence data block.
11, a kind of proving installation, in order to test an electronic component, this proving installation comprises:
One pattern generator produces a test pattern, to test this electronic component;
One waveshaper is in order to this test pattern that is shaped; And
One judging part, foundation one output signal is judged the quality of this electronic component, wherein this electronic component is exported this output signal according to this test pattern,
This pattern generator more comprises:
One memory main body stores most sequence data blocks in order to produce this test pattern;
One first sequence memory cache body stores those sequence data blocks in regular turn;
One second sequence memory cache body;
One data expansion portion carries out those stored sequence data blocks of this first sequence memory cache body, in regular turn to produce this test pattern; And
One reads the unit earlier, in order to carry out in this sequence data block in this data expansion portion, if when detecting the first read command that read other these sequence data blocks earlier, read out other this sequence data blocks from this memory main body, and be stored in this second sequence memory cache body.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP163461/2003 | 2003-06-09 | ||
| JP2003163461 | 2003-06-09 |
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| CN1802569A true CN1802569A (en) | 2006-07-12 |
| CN100462731C CN100462731C (en) | 2009-02-18 |
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| CNB2004800159351A Expired - Fee Related CN100462731C (en) | 2003-06-09 | 2004-05-21 | Pattern generator and test apparatus |
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| US (1) | US7472327B2 (en) |
| EP (1) | EP1640735B1 (en) |
| JP (1) | JP4378346B2 (en) |
| KR (1) | KR100882361B1 (en) |
| CN (1) | CN100462731C (en) |
| DE (1) | DE602004011614T2 (en) |
| TW (1) | TWI313755B (en) |
| WO (1) | WO2004109307A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005043204A (en) * | 2003-07-22 | 2005-02-17 | Advantest Corp | Pattern generator and testing device |
| WO2008099239A1 (en) * | 2007-02-16 | 2008-08-21 | Freescale Semiconductor, Inc. | System, computer program product and method for testing a logic circuit |
| US7743305B2 (en) | 2007-03-20 | 2010-06-22 | Advantest Corporation | Test apparatus, and electronic device |
| US7716541B2 (en) * | 2007-03-21 | 2010-05-11 | Advantest Corporation | Test apparatus and electronic device for generating test signal to a device under test |
| US7725794B2 (en) | 2007-03-21 | 2010-05-25 | Advantest Corporation | Instruction address generation for test apparatus and electrical device |
| KR102314419B1 (en) * | 2021-07-27 | 2021-10-19 | (주) 에이블리 | Apparatus and method for generating semiconductor test pattern |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02284077A (en) * | 1989-04-25 | 1990-11-21 | Nec Corp | Testing device for logic integrated circuit |
| JPH0438482A (en) * | 1990-06-04 | 1992-02-07 | Fujitsu Ltd | Apparatus for testing logical circuit |
| US5925145A (en) * | 1997-04-28 | 1999-07-20 | Credence Systems Corporation | Integrated circuit tester with cached vector memories |
| JPH11237451A (en) * | 1998-02-23 | 1999-08-31 | Advantest Corp | Pattern generator of semiconductor testing device |
| JP2000065904A (en) | 1998-08-21 | 2000-03-03 | Advantest Corp | Semiconductor tester |
| US6769083B1 (en) * | 1998-11-10 | 2004-07-27 | Advantest Corporation | Test pattern generator, a testing device, and a method of generating a plurality of test patterns |
| US6092225A (en) * | 1999-01-29 | 2000-07-18 | Credence Systems Corporation | Algorithmic pattern generator for integrated circuit tester |
| US6505137B1 (en) * | 1999-09-20 | 2003-01-07 | Radiant Technologies, Inc. | Method for operating a test system |
| US6567941B1 (en) * | 2000-04-12 | 2003-05-20 | Advantest Corp. | Event based test system storing pin calibration data in non-volatile memory |
| CA2345605A1 (en) * | 2001-04-30 | 2002-10-30 | Robert A. Abbott | Method of testing embedded memory array and embedded memory controller for use therewith |
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2004
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- 2004-05-21 WO PCT/JP2004/006933 patent/WO2004109307A1/en active IP Right Grant
- 2004-05-21 JP JP2005506738A patent/JP4378346B2/en not_active Expired - Fee Related
- 2004-05-21 EP EP04734342A patent/EP1640735B1/en not_active Expired - Fee Related
- 2004-05-21 KR KR1020057023758A patent/KR100882361B1/en not_active IP Right Cessation
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| US20060161372A1 (en) | 2006-07-20 |
| JP4378346B2 (en) | 2009-12-02 |
| EP1640735B1 (en) | 2008-01-30 |
| EP1640735A4 (en) | 2006-06-28 |
| DE602004011614T2 (en) | 2009-01-29 |
| KR20060037269A (en) | 2006-05-03 |
| EP1640735A1 (en) | 2006-03-29 |
| TW200508633A (en) | 2005-03-01 |
| JPWO2004109307A1 (en) | 2006-09-21 |
| WO2004109307A1 (en) | 2004-12-16 |
| KR100882361B1 (en) | 2009-02-05 |
| US7472327B2 (en) | 2008-12-30 |
| CN100462731C (en) | 2009-02-18 |
| DE602004011614D1 (en) | 2008-03-20 |
| TWI313755B (en) | 2009-08-21 |
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