JPH0438482A - Apparatus for testing logical circuit - Google Patents

Abstract

PURPOSE:To short the test processing time (throughput) of the whole to a large extent as compared with a conventional one by performing the storing processing of a test pattern and the execution processing thereof in parallel. CONSTITUTION:A calculator 30 successively and continuously reads a test pattern from a disk apparatus 40 at a constant cycle in the order of SI pattern PI pattern... SI pattern... as shown by a broken line. As a result, only the SI pattern is stored in an SI pattern memory 543 and only the PI pattern is stored in a PI pattern memory 541 and only a PO pattern is stored in a PO pattern memory 542 and only an SO pattern is stored in an SO pattern memory 544. A reading circuit 55 reads the SI pattern through a reading bus 53 to supply the same to a test control circuit 55 which in turn operates an object 20 to be tested.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a logic circuit testing device that performs logic function tests on logic circuit elements such as large-scale integrated circuits and printed wiring boards on which the same elements are mounted. ) and for the purpose of cost reduction, the first test pattern for testing is sequentially input to the device under test, the device under test is operated, and the signal pattern output from the device under test is changed to the expected pattern. In the logic circuit testing apparatus, the logic circuit testing apparatus performs a logic function test of the test object by comparing and comparing with a second test pattern shown in FIG.
and a pattern memory provided in a number equal to the number of each type of second test pattern, and writing for storing the first and second test patterns separately and sequentially for each type in a plurality of the pattern memories. and an execution processing means for reading a test pattern from a pattern memory different from the pattern memory in which the writing operation is being performed by the writing means among the plurality of pattern memories, and performing a test execution process for the test object. Configure it like this.

[Industrial application field]

The present invention relates to a logic circuit testing device, and more particularly to a logic circuit testing device for testing the logic functions of logic circuit elements such as large-scale integrated circuits and printed wiring boards on which the same elements are mounted.

When testing the logic function of a device under test such as a logic circuit element such as a large-scale integrated circuit (LSI) or a printed wiring board on which the same element is mounted, a logic signal pattern for testing is input to the device under test. By operating the device under test and comparing the signal pattern output from the device under test with the expected pattern, it is tested whether the device under test operates logically or not. If the test object is a high-density, large-scale printed wiring board, the number of logic signal patterns for testing will be enormous, and the test processing time will be long. There is a demand for shortening of storage processing and execution processing.

[Conventional technology]

FIG. 4 shows a configuration diagram of an example of a conventional logic circuit testing device. In the figure, a logic circuit testing device 10 includes a write circuit 11.
Data bus 12. Pattern memory 13, readout circuit 1
4 and a test control circuit 15. Data bus 12 is for writing.

The pattern memory 13 is shared for reading and stores a plurality of types of test patterns based on a scanning method.

Further, the test control circuit 15 executes a test pattern and tests the object under test 20.

Further, 30 is a computer, 40 is a disk device in which a plurality of types of test patterns based on the scan method are stored in advance, and the computer 30 reads the test patterns from the disk device 40 and inputs them to the writing circuit 11. The test patterns used in the scan method logic function test include: ■Primary input (PI) pattern, ■
There are four types: primary output (PO) pattern, ■scan input (SI) pattern, and ■scan output (S○) pattern.

Next, to explain the operation of the above configuration, the above four types of test patterns are sequentially read out from the disk device 40 under the control of the computer 30 and input to the write circuit 11, where they are processed for writing. After receiving the data, the write circuit 1 of the pattern memory 13 via the data bus 12
1 is written to the address specified.

FIG. 5 is a time chart for testing one pattern, and as shown by the broken line in the figure, Sl, PI.

The test patterns of PO and S○ are sequentially stored in the pattern memory 13.

The above-mentioned four types of test patterns stored in the pattern memory 13 are then first read out as the Sl pattern from the address specified by the readout circuit 14 as shown by the solid line in FIG. 14 to the test control circuit 15. The test control circuit 15 inputs the input Sl pattern serially to the SI terminal of the device under test 20, and inputs it to the scan latch via the test scan circuit in the device under test 20 to operate the device under test 20. . Thereafter, as shown by the solid line in FIG. 5, the PIl pattern, PO pattern, and SO pattern are sequentially read out from the address specified by the readout circuit 14 in the order of is input.

When the PIl pattern is input, the test control circuit 15 inputs it in parallel to the connector of the device under test 20, and
Operate 0. Next, when the PO pattern is input, the test control circuit 15 reads out the motion amount cover pattern of the DUT 20 based on the above Sl and PI pattern input in parallel from the connector of the DUT 20, and combines this with the input PO pattern. Comparison and verification are performed to determine whether or not it is logically normal.

When the test control circuit 15 receives the S○ pattern next,
Serially read out the operation amount cover pattern of the device under test 20 based on the above SI and PI pattern input from the special SO ground terminal of the device under test 20, and compare and check this with the input SO pattern to determine whether it is logically normal. Make a judgment.

In this way, conventionally, four types of test patterns are sequentially stored in the pattern memory 13, and after the storage is completed,
Four types of test patterns are sequentially read out from the pattern memory 13 and each test pattern is executed. Therefore, as shown in Figure 5, the test processing time for the l pattern, in which storage processing and execution processing are conventionally performed once for each of the four types of test patterns, is the same as the storage processing time for the four types of test patterns. This is the sum of the execution processing time of the four types of test patterns. Normally, several thousand patterns are required for the logical function test of the device under test 20, but conventionally, the test pattern is stored in the pattern memory 13 and read out and executed at high speed, thereby shortening the pattern execution processing time. We are trying to

[Invention or problem to be solved]

However, in the conventional logic circuit testing apparatus described above, it takes time to store the test pattern in the pattern memory 13, making it difficult to shorten the overall test processing time (improve throughput). Furthermore, the pattern memory 13 must have a large capacity, which increases the cost of the entire device.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a logic circuit testing apparatus that can shorten test processing time (improve throughput) and reduce costs.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention. In the same figure, 10
0. ~100. is a pattern memory, which is provided as many times as there are first test patterns to be input to the device under test and second test patterns to be compared and verified with the output signal pattern of the device under test.

Reference numeral 101 denotes a writing means that stores the above-mentioned first and second test patterns separately and sequentially for each type. 102 is an execution processing means, which includes pattern memories 1001 to 1002;
100. Among them, the test pattern is read from a pattern memory different from the pattern memory in which the writing operation is being performed by the writing means 101, and execution processing of the test on the test object is performed.

[Effect]

When executing patterns, even if there are multiple test patterns, they are not executed at the same time, but are executed sequentially.

The present invention has been developed with this point in mind, and the next pattern is stored in the pattern memory while the pattern is being executed. That is, pattern memories 1001 to 100. are provided individually depending on the type of test pattern.
During a period in which the test pattern formed by the writing means 101 is written into the pattern memory formed by the writing means 101, another test pattern is executed from another pattern memory by the processing means 102.
and execute the pattern for testing the test object. Therefore, in the present invention, test pattern storage processing and test pattern execution processing can be performed in parallel.

〔Example〕

FIG. 2 shows a configuration diagram of an embodiment of the present invention. In the figure, the same components as in FIGS. 1 and 4 are denoted by the same reference numerals, and their explanations will be omitted. In FIG.
．． Write bus 52° Read bus 53. PI pattern memory 54I.

Po pattern memory 542.31 pattern memory 54,
and SO pattern memory 544. It is composed of a readout circuit 55 and a test control circuit 56.

That is, this embodiment uses the pattern memory 1001 described above.
~100. The P1 pattern memory 54 corresponds to the pattern memories 1001, 1002, 100z, and 1004, in an example where the number n is "4".

Po pattern memory 542. Sl pattern memory 54,
and SO pattern memory 544 respectively store the PI pattern and
Four types of test patterns, PO pattern, SL pattern, and SO pattern, are stored separately. Further, the readout circuit 55 and the test control circuit 56 are connected to the execution processing means 102.
It consists of

Next, the operation of this embodiment will be explained with reference to FIG. The computer 30 reads test patterns from the disk drive 40 in the order of SI pattern → PI pattern → PO pattern → SO pattern → SL pattern → . This read test pattern is stored in the pattern memory 54. ~54
4, the SI pattern memo I is sequentially written by the write circuit 51 via the write circuit 51 and the write bus 52, respectively.
J54s, PI pattern memory 54. , Po pattern memory 54. and is switched and stored in the SO pattern memory 544. As a result, the Sl pattern memory 54. is Sl
Only the pattern or PI pattern memory 54. is P
Only the I pattern is stored in the Po pattern memory 542.
Only the pattern is stored in the SO pattern memory 544, and only the SO pattern is stored in the SO pattern memory 544, respectively. Therefore, each pattern memory 54. ~544 store only one test pattern and one type of test pattern, so each requires a minimum memory capacity.

On the other hand, the readout circuit 55 is connected to the Sl pattern memory 54, i
: After the Sl pattern is stored, it is read out via the readout bus 53 and supplied to the test control circuit 56. As a result, the test control circuit 56 serially inputs the Sl pattern data to the Sl terminal in the device under test 20 to operate the device under test 20, as in the conventional case. During the execution period of this Sl pattern indicated by the solid line SI in FIG. 3, the broken line P1. As indicated by PO, a PI pattern and a PO pattern are sequentially stored in the PI pattern memory 54 and the PO pattern memory 54t.

When the above Sl pattern execution process is completed, the readout circuit 55 reads out the PI pattern from the PI pattern memory 54□ via the readout bus 53 as shown by the solid line PI in FIG. 3, and supplies it to the test control circuit 56. Input the data in parallel to the connector of the test object 20,
The test object 20 is operated. When this PI pattern execution process is completed, the readout circuit 55 reads out the readout bus 5 from the <PO pattern memory 54□ as shown by the solid line P○ in FIG.
The test control circuit 56 reads out the PO pattern through the
Here, as in the conventional case, it is compared with pattern data taken out in parallel from the output connector of the test object 20 to determine whether the logical function of the test object 20 is normal or not.

After the start of the PI pattern execution process described above and until the end of the PO pattern execution process, the next SO pattern is input via the write circuit 51 and the write bus 52, as shown by the broken line SO in FIG. SO pattern memory 5
44.

When the above PO pattern execution processing is completed, the readout circuit 55 then reads out the SO pattern from the SO pattern memory 544 via the readout bus 53, as shown by the solid line SO in FIG. The test control circuit 56 compares this S○ pattern with the operation result output signal pattern data of the device under test 20 taken out serially from the So terminal of the device under test 20 to determine whether the logic function of the device under test 20 is normal. Determine whether or not. During execution of this PO pattern processing, as shown by the broken line SI in FIG.
2, the next Sl pattern is inputted to the S pattern memory 54. is stored in

Thereafter, the same operation as above is repeated.

In this way, according to this embodiment, four types of test patterns are executed sequentially, and the next different test pattern is stored during the execution processing period, so the test processing time is significantly reduced compared to the conventional method. It can be shortened to

〔Effect of the invention〕

As described above, according to the present invention, test pattern storage processing and test pattern execution processing can be performed in parallel, so the overall test processing time (throughput) can be significantly shortened compared to the conventional method. Moreover, since the pattern memory can be used in a small capacity, the cost of the entire device can be reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a time chart for explaining the operation of Fig. 2, and Fig. 4 is a block diagram of a conventional example. FIG. 5 is a time chart for explaining the operation of FIG. 4. In the figure, 0 is a logic circuit test device, 1 is a write circuit, 2 is a write bus, 3 is a read bus, 54 to 54. , 100. ~100. 55 represents a pattern memory, 55 represents a readout circuit, and 56 represents a test control circuit. Patent Applicant: Fujitsu Neinshikawa Co., Ltd./) 7 Hara Aif 5 2 Page 1 Figure 1

Claims (3)

[Claims] (1) A second test in which the first test pattern for testing is sequentially input to the device under test, the device under test is operated, and the signal pattern output from the device under test shows the expected pattern. In a logic circuit testing device that performs a logic function test of the test object by comparing and matching patterns, a pattern memory (100_1 to 100_n) provided in the number of each type of the first and second test patterns is provided.
), writing means (101) for storing the first and second test patterns separately and sequentially for each type in the plurality of pattern memories (100_1 to 100_n); 100_1 to 100_n), execution processing means (102) reads a test pattern from a pattern memory different from the pattern memory in which the write operation is being performed by the writing means (101) and executes the test on the test object; A logic circuit testing device characterized by having the following. (2) The execution processing means (102) selects a pattern memory to perform a read operation from among the plurality of pattern memories (100_1 to 100_n) and reads a desired test pattern from the selected pattern memory (55). ), and a test control circuit (56) for inputting the test pattern read out by the reading circuit (55) to the device under test or comparing it with the output signal pattern of the device under test. The logic circuit testing device according to claim 1, characterized in that: (3) The first test pattern is the PI pattern and the S
I pattern, the second test pattern is a PO pattern and an SO pattern, and the plurality of pattern memories (100_1 to 100_n) are provided with four circuits corresponding to each of these four types of patterns. 2. The logic circuit testing device according to claim 1.