CN1783500A

CN1783500A - Erasable and programmable read-only memory element and producing and operating method

Info

Publication number: CN1783500A
Application number: CN 200410096740
Authority: CN
Inventors: 王知行
Original assignee: Individual
Current assignee: Individual
Priority date: 2004-12-03
Filing date: 2004-12-03
Publication date: 2006-06-07
Anticipated expiration: 2024-12-03
Also published as: CN100373625C

Abstract

This invention relates to erasable and programmable ROM elements and their manufacturing and operation method, in which, a first layer of a semiconductor is above a matrix with a first conduction type, a first zone formed between the matrix and the first layer having a second conduction type, a groove is formed on the a surface of the first layer with a side wall and a base part, a second zone is formed on said first layer adjacent to an upper part of the groove laterally with the second conduction type, a channel zone is set on the first layer between the first zone and the second zone formed along the side wall of said groove, a conductive floating grid is adjacent to said channel zone and isolated with it, a conductive control grid, part of which is set on the floating grid and insulated with it, a conductive tunnel grid is set on part of the control grid and isolated with it, characterizing that it does not need high voltage to generate a basic structure.

Description

Can erase read-only memory element and manufacturing and method of operation with programmable

Technical field

The present invention relates to a kind of non-volatile (nonvolatile) memory, especially read-only memory (the electrically programmable read onlymemory that refers to the electronic type programmable, EPROM) and electronic type can erase read-only memory (electrically erasable and programmable read only memory, EEPROM) element with programmable.The invention particularly relates to the framework of memory cell (memory cell), the method that forms memory cell and non-volatile memory array with floating gate.The present invention specifically is the read-only memory element with programmable of can erasing, the manufacturing of element and method of operation.

Background technology

As depositing the nonvolatile storage location of electric charge and relevant memory array, all is that present industry is known with floating gate.Basically, memory cell sees through electronics is sent or send to a floating gate, reaches erasing or sequencing of electronic type.Though this floating gate electrically go up be with arround electrode insulation, with arround electrode capacity coupled effect is but arranged.Remain in the quantity of electric charge in the floating gate, determined the state of memory cell.Generally speaking, defined state may have only two states or more kinds of state (polymorphic storage).Distinguish from structure, at present known memory cell can be splitting bar (split gate) type, storehouse grid type or theirs is combined.

In the current non-volatility memorizer, in order to reach needed store status, it is very general adopting high voltage (generally being 9 to 20 volts) during operation.Therefore, for the operation of supporting memory component, it is very important that high voltage in the wafer produces foundation structure (high-voltage infrastructure), and these structures also become a very important part in non-volatility memorizer and its product.High voltage produces foundation structure and has comprised the array high voltage transistor that separates, and these high voltage transistors except general CMOS processing procedure, generally also need 5 extra road light shields on processing procedure.So high voltage produces very complicated that process technique that foundation structure can make non-volatility memorizer becomes.

It is that high voltage generation foundation structure is difficult to dwindle its area along with technology evolution that a high voltage in addition produces the problem that foundation structure produced.Because the physical principle that memory component used, high voltage can cause component size to be difficult to reduction exactly.And opposite, since the many decades in past, the operating voltage of logical circuit constantly descends always, and what follow is that the minimum dimension in the CMOS process technique is also constantly dwindled.Also therefore, predictably, the gap between the operating voltage of logical circuit and the operating voltage of memory component can constantly increase.This problem is along with the CMOS processing procedure enters epoch of 0.25 micron (micrometer), and the more obvious of change also more worsens.Therefore, in memory product of new generation, no matter be embedded or the non-volatility memorizer product of standard, often can see a fixed cost, be exactly high voltage circuit has occupied a sheet of chip area.Dimension reduction that high voltage caused restriction restriction too the minimum feature size of high voltage transistor (minimum feature size).What often can find is that follow-on product just directly prolongs has used the design specification (design rule) of catching up with the same high voltage transistor of a generation.In addition, high voltage operation also can cause the problem of the functional and reliability of product.

U.S. Patent number the 5th, 780 wants to introduce a stair-stepping raceway groove/drain electrode framework in splitting bar type or storehouse grid type element No. 341, attempts going to solve above problem.Wherein, electron charge is to see through channel hot electron effect (channel hot electron) or source terminal radiation (source-side injection, SSI) mechanism enters floating gate.Electric charge in the floating gate is to see through the Fowler-Nordheim tunneling mechanism, and leaves floating gate.Yet these mechanism all need high voltage to keep running.Stair-stepping raceway groove/drain electrode framework is to improve the efficient that electric charge penetrates really.But, even if so, in order to keep the running of element, still need be up to 10 volts voltage.High like this voltage be it is generally acknowledged, needs strict control to be centered around the floating gate quality of insulator all around.So such structure is subjected to the processing procedure factor easily and damages, and also is easy to generate the problem on the reliability.

U.S. Patent number the 6th, 372, No. 617 hope form polysilicon (polysilicon) sidewall (spacer) above seeing through and form a floating gate and the edge at that floating gate in a sunk structure, reduce high-tension demand.Such floating gate framework can significantly improve the capacitive coupling between control gate and the floating gate.Other technology is also arranged, utilize the polysilicon (hemispherical grained polysilicon) that forms hemispherical grain on the floating gate of a concavity, to increase the surface area of floating gate, reach similar purpose.Operating voltage approximately can drop to about 16 volts.Ask for an interview that Kitamura T. etc. shown " A Low Voltage Operation Flahs Cell with HighCoupling Ratio Using Horned Floating Gate with HSG ", be published in 1998, the paper of VLSI technical seminar (Symposium on VLSITechnology Dig.Technical Papers), the 104th to 105 page.But the formation of polysilicon sidewall (spacer) on the concavity floating gate has increased the complexity on the processing procedure.In addition, because the surface height of recessed floating gate changes acutely, also increased the degree of difficulty of successive process (formation of character line for example).In a word, all be that production is more bothered.In addition, the floating gate structure of concavity has caused the edge of floating gate that bigger drop is arranged.Such drop can increase the interference between floating gate and the floating gate, therefore, is unfavorable for reducing the spacing between element and the element.

Element has also limited the reduction of the size of element own for high-tension demand.For example, in order to operate under the high voltage, grid length of element (gate length) or channel length (channel length) just must be long enough to prevent that (punch through) phenomenon that penetrates of drain-to-source from taking place.So, so least limit that has just caused the size reduction of element own, just, the channel length of memory component minimum just can only be certain value.As the problem that high voltage transistor suffered from, the problem that the sort memory element is suffered from is along with processing procedure enters 0.25 micron epoch, and more apparent serious.From the viewpoint of element physical size, this problem has caused whole element heights (length of element on bit line direction just) that the limiting value of a minimum has been arranged.

Another subject matter that occurs in memory-size reduction is the thickness of oxide that floating gate is wrapped.For a pure zirconia layer, the someone to propose the theoretical value of minimum thickness be between 5～6nm, just enough keep out because the electric leakage that the Fowler-Nordheim tunneling mechanism is caused.Ask for an interview K.Naruke and equal that the 424th page to the 427th page of nineteen twenty-two IEDMTechnical Digest shown " Stress InducedLeakage Current Limiting to Scale Down EEPROM TunnelOxide Thickness ".And, after dielectric layer lives through high-tension stress, the generation that extra leakage current is also frequent.Therefore, maintain in the floating gate for the leakage current of keeping the same degree and with electric charge, reach the standard of product specification, the about 8～9nm of thickness of employed thin oxide layer is said in all very consistent report of the product in many epoch.Ask for an interview that S.Lai shown in the 971st～973 page of IEDM Technical Digest in 1998 " Flash Memories:Where We Were and Where We AreGoing ".The demand of minimum oxidated layer thickness has like this limited the reductionization of element channel width.Because element needs the electric current that reads of a minimum at least, be inversely proportional to oxidated layer thickness and read electric current, and be proportional to channel width.From the viewpoint of element physical size, this problem has caused whole element width (length of element on the character line direction just) that the limiting value of a minimum has been arranged.

The above problem of inquiring into all often comes across the non-volatile memory component that uses storehouse grid formula EEPROM framework, such as No. the 4th, 957,877, United States Patent (USP).There are many methods to be suggested, wish to overcome to reach a littler difficulty that component size met with.For example, United States Patent (USP) the 5th, 146, disclosed a memory component of the groove (trench) that is formed on an approximate contact hole (contact hole) for No. 426 with floating gate and control gate, United States Patent (USP) the 5th, 432,739 and 5, disclosed for 563, No. 083 along the sidewall in a columnar silicon zone and formed a memory component with floating gate and control gate.These elements can reach than the storehouse grid formula produced element of EEPROM technology in the general present age and have less component size.Ask for an interview D.Kuo and equal that among the Symposium on VLSI Technology Dig.Technical Papers in 1994 the 51st～52 page is shown " TEFET-A High Density, Low Erase Voltage, Trench Flash EEPROM "; H.Pein equals that among the IEDM TechnicalDigest in 1993 the 11st～14 page is shown " Performance of the 3-D SidewallFlash EPROM Cell ".But, these elements still need come the executive component data to erase up to the voltage more than 12 volts action, this still is a shortcoming that is waiting to be overcome.For example, United States Patent (USP) the 5th, 146, the element in No. 426 use the high bias source electrode (buried source) that buries to carry out the action of erasing.Near the corner of groove gate dielectric layer attenuation can produce the high electric field of a part, and then strengthens the charge transfer when erasing action.Yet even if above achievement is arranged, operating voltage is still very high, and the quality of oxide layer also needs to be subjected to strict control.In addition, for these elements, gradual change type (graded) source junction (junction) is very important, in order to be born high voltage.Such high voltage and the operation of burying source electrode have significantly caused the restriction of the minimum spacing of burying source electrode, also therefore, have stopped the further reduction of component size simultaneously.Such restriction also makes the segmentation (segmentation) of memory array and block integrate the complicated of (block integration) simultaneously, thus unfortunate increase the entire area of memory array, lowered that component size is dwindled and the advantage that obtains.In addition, at United States Patent (USP) the 5th, 146, in No. 426, the channel bottom in each element must be formed on and bury in the source electrode, and its degree of depth must strict control, in order to make the action of can both successful execution erasing of all elements.Yan Ge requirement is like this believed to have caused to produce and is gone up very large difficulty.United States Patent (USP) numbers the 5th, 432, and 739 and 5,563, the purpose of having used shaped element to reach the small components size No. 083.The violent height that this element has been produced in the time of must being dependent on floating gate and control gate formation rises and falls (large topography), because its technology has adopted polysilicon sidewall in a large number.Except high-tension shortcoming, violent height rises and falls and the strict control of the needed processing procedure of formation of polysilicon sidewall all can make processing procedure complicated, has also caused the difficulty of producing.

Summary of the invention

In view of this, main purpose of the present invention is to provide the improvement of a kind of EPROM and eeprom memory element.The invention provides the read-only memory element that can erase with programmable, the present invention also provides manufacturing and the method for operation that can erase with the read-only memory element of programmable.

In order to realize purpose of the present invention, the present invention proposes a kind of read-only memory (read only memory, ROM) element of erasing with programmable.The semiconductor of one ground floor has first conductivity type in matrix top.One first district is formed between this matrix and this ground floor, has second conductivity type.One groove (trench) is formed at a surface of this ground floor, has a sidewall and a bottom.One second district is formed in this ground floor, and side direction is adjacent to a first half of this groove, has this second conductivity type.One channel region (channel region) is in this ground floor, and between this first district and this second district, this sidewall that is roughly prolonging this groove forms.The floating gate (floatinggate) of one conduction is adjacent to this channel region, and insulate mutually with this channel region.The control gate (control gate) of one conduction, a part wherein places on this floating gate, and insulate mutually with this floating gate.The tunnel grid (tunneling gate) of one conduction place on the part of this control gate, and insulate mutually with this control gate.

Read-only memory element of erasing with programmable of the present invention, wherein, this sidewall of this groove is surperficial perpendicular with this ground floor roughly, and this bottom of this groove roughly parallels with this surface of this ground floor.

Read-only memory element of erasing with programmable of the present invention, wherein, this groove passes this second district and this ground floor, and this bottom of this groove is formed in this first district.

Read-only memory element of erasing with programmable of the present invention, wherein, this groove passes this second district, this ground floor and this first district, and this bottom of this groove is formed in this matrix.

Read-only memory element of erasing with programmable of the present invention, other includes one first insulating barrier, has a first, is located on the surface of this second district and this ground floor, and a second portion, go up this bottom of being located at this groove and side direction is attached at this sidewall of this groove.

Read-only memory element of erasing with programmable of the present invention, wherein, this control gate and this tunnel grid are in the overlapping mutually in the district that overlaps; And

At least the part of this floating gate is to be located under this overlapping district.

Read-only memory element of erasing with programmable of the present invention, wherein, this control gate has:

One first is roughly on the surface of the part of being located at this second district at least of insulation and this ground floor; And

One second portion is roughly on Jue Yuan the surface of being located at this floating gate.

Read-only memory element of erasing with programmable of the present invention, other includes an insulating barrier between these tunnel grid and this control gate, and this insulating barrier has a thickness, is enough to allow that quantum-mechanical tunneling electron passes through.

Read-only memory element of erasing with programmable of the present invention, wherein, this insulating barrier is a silicon oxynitride layer, wherein, the ratio of oxygen is between 70% to 90%.

Read-only memory element of erasing with programmable of the present invention, wherein, this control gate is a metal, and the Fermi level (Fermi-level) of its work function (work function) roughly is positioned at the central authorities of the energy interband of this insulating barrier every (energy band gap).

Read-only memory element of erasing with programmable of the present invention, wherein, the part of this control gate has allows that impacting electric charge (ballistic charge) penetrates a thickness in the past.

Read-only memory element of erasing with programmable of the present invention, wherein, these tunnel grid are the heavily doped semiconductor substance of a P type.

Read-only memory element of erasing with programmable of the present invention, wherein, this control gate is the heavily doped semiconductor substance of a P type.

For realizing purpose of the present invention, the present invention also proposes read-only memory (read only memory, the ROM) element arrays that can erase with programmable.A plurality of drain lines that this array has the semiconductor of a matrix (bulk material), a ground floor, a plurality of isolated district that separates and separates.This ground floor has first conductivity type in this matrix top.Should be formed in this ground floor in isolated district, roughly be parallel to each other, extend a first direction, per two adjacent isolated intervals have an active region.This drain line extends this first direction, and each drain line is formed at the part of this active region at least, and is adjacent to this surface of this ground floor.Each active region has a plurality of memory elements.Each memory element includes the floating gate (floating gate) of one first district, a groove (trench), one second district, a channel region (channelregion), a conduction, the control gate (control gate) of a conduction and the tunnel grid (tunneling gate) of a conduction.This first district is formed between this matrix and this ground floor, has second conductivity type.This channel shaped is formed in a surface of this ground floor, has a sidewall and a bottom.This second district is formed in this ground floor, and side direction is adjacent to a first half of this groove, has this second conductivity type.This channel region is in this ground floor, and between this first district and this second district, this sidewall that is roughly prolonging this groove forms.This floating gate is adjacent to this channel region, and insulate mutually with this channel region.The part of this control gate places on this floating gate, and insulate mutually with this floating gate.These tunnel grid are located on the part of this control gate, and insulate mutually with this control gate.

Read-only memory element array of erasing with programmable of the present invention, other includes:

A plurality of grooves are lined up the matrix with a plurality of row (row) and row (column), and these row extend this first direction, and this row extends a second direction, and this second direction is roughly vertical with this first direction.

Separate and parallel a plurality of control grid lines, every control grid line extends roughly vertical with this a first direction second direction, strides across this active region and should completely cut off the district, and be electrically connected to a plurality of control gates of this memory element.

Separate and parallel a plurality of tunnels grid line, every tunnel grid line extends this first direction, and is electrically connected to a plurality of tunnels grid of this memory element.

Read-only memory element array of erasing with programmable of the present invention, wherein, for each memory element, this control gate and this tunnel grid are in the overlapping mutually in the district that overlaps; And

Read-only memory element array of erasing with programmable of the present invention, wherein, this second district is electrically connected to the part of one of this drain line at least.

Separate and parallel multiple source polar curve a plurality of first districts that are connected to this memory element that each source electrode line is electrical.

Read-only memory element array of erasing with programmable of the present invention, wherein, for each memory element, this groove passes this second district and this ground floor, and this bottom of this groove is formed in this first district.

For realizing purpose of the present invention, the present invention also proposes a kind of read-only memory (read only memory, ROM) method of element that can erase with programmable that form.Include following steps.Form the semiconductor of a ground floor,, have one first conductivity type in matrix top.Form one first district, between this matrix and this ground floor, have one second conductivity type.Form a groove (trench),, have a sidewall and a bottom in a surface of this ground floor.Form one second district, in this ground floor, side direction is adjacent to a first half of this groove, has this second conductivity type.Form a channel region (channelregion), in this ground floor, between this first district and this second district, roughly prolonging this sidewall of this groove.Form the floating gate (floating gate) of a conduction, be adjacent to this channel region, and insulate mutually with this channel region.Form the control gate (controlgate) of a conduction, its part places on this floating gate, and insulate mutually with this floating gate.Form the tunnel grid (tunneling gate) of a conduction, on the part of this control gate, and insulate mutually with this control gate.

The formation one of the present invention method with the read-only memory element of programmable of can erasing, wherein, this sidewall of this groove is surperficial perpendicular with this ground floor roughly, and this bottom of this groove roughly parallels with this surface of this ground floor.

The formation one of the present invention method with the read-only memory element of programmable of can erasing, wherein, this groove passes this second district and this ground floor, and this bottom of this groove is formed in this first district.

The formation one of the present invention method with the read-only memory element of programmable of can erasing, wherein, this control gate and this tunnel grid are in the overlapping mutually in the district that overlaps; And

The formation one of the present invention method with the read-only memory element of programmable of can erasing, wherein, this control gate has:

The formation one of the present invention method with the read-only memory element of programmable of can erasing, wherein, other includes formation one insulating barrier between these tunnel grid and this control gate, and this insulating barrier has a thickness, is enough to allow that quantum-mechanical tunneling electron passes through.

The formation one of the present invention method with the read-only memory element of programmable of can erasing, wherein, this insulating barrier is a silicon oxynitride layer, wherein, the ratio of oxygen is between 70% to 90%.

The formation one of the present invention method with the read-only memory element of programmable of can erasing, wherein, this control gate is a metal, and the Fermi level (Fermi-level) of its work function (work function) roughly is positioned at the central authorities of the energy interband of this insulating barrier every (energy bandgap).

The formation one of the present invention method with the read-only memory element of programmable of can erasing, wherein, the part of this control gate has allows that impacting electric charge penetrates a thickness in the past.

The formation one of the present invention method with the read-only memory element of programmable of can erasing, wherein, these tunnel grid are the heavily doped semiconductor substance of a P type.

The formation one of the present invention method with the read-only memory element of programmable of can erasing, wherein, this control gate is the heavily doped semiconductor substance of a P type.

Be to realize that the object of the invention, the present invention also propose a kind of read-only memory (read only memory, ROM) method of element arrays that can erase with programmable that form.This method includes the following step.In the semiconductor of a ground floor, form a plurality of isolated district separately, this ground floor has one first conductivity type in matrix top, and this isolated district roughly is parallel to each other, and extends a first direction, and per two adjacent isolated intervals have an active region.Form a plurality of drain lines separately, extend this first direction, each drain line is formed at the part of this active region at least, and is adjacent to this surface of this ground floor.Surface in this ground floor, form a plurality of grooves (trench), be arranged in the array, the row of this array (column) extend this first direction, the row of this array (row) extends the second direction with this first direction approximate vertical, and each groove has a sidewall and a bottom.Between this matrix and this ground floor, form a plurality of first districts, have one second conductivity type.Form a plurality of second districts in this ground floor, each second district's side direction is adjacent to one of them the first half of this groove, has this second conductivity type.Form a plurality of channel regions (channel region) in this ground floor, each channel region is between one of one of this first district and this second district, and this sidewall that is roughly prolonging one of this groove forms.Form the floating gate (floating gate) of a plurality of conductions, the insulation of each floating gate be adjacent to this channel region one of them.Form the control gate (control gate) of a plurality of conductions, the insulation of the part of each control gate place this floating gate on one of them.Form the tunnel grid (tunneling gate) of a plurality of conductions, on the part of being located at this control gate of each tunnel gate insulation.

The formation one of the present invention method with the read-only memory element array of programmable of can erasing, other includes:

Form and separate and parallel a plurality of control grid lines, every control grid line extends roughly vertical with this a first direction second direction, strides across this active region and should completely cut off the district, and be electrically connected to this control gate partly.

Form and separate and parallel a plurality of tunnels grid line, every tunnel grid line extends this first direction, and is electrically connected to these tunnel grid of part.

The formation one of the present invention method with the read-only memory element array of programmable of can erasing, wherein, each this control gate tunnel grid corresponding with are in the overlapping mutually in the district that overlaps; And

The part of each floating gate is to be located at one of them time of this overlapping district.

The formation one of the present invention method with the read-only memory element array of programmable of can erasing, wherein, each this second district is electrically connected to the part of one of this drain line at least.

Form and separate and parallel multiple source polar curve, this first district that is connected to part that each source electrode line is electrical.

The formation one of the present invention method with the read-only memory element array of programmable of can erasing, wherein, each groove passes this second district one of them and this ground floor, and this bottom of each groove is formed at this first district in one of them.

For realizing purpose of the present invention, the present invention also proposes read-only memory (read only memory, ROM) method of operation of element that can erase with programmable.This element has the floating gate (floating gate) of a conduction, be formed in the groove (trench) of semiconductor substrate (semiconductor substrate), the control gate (control gate) of one conduction, have a part of placing on this floating gate of insulating, the tunnel grid (tunneling gate) of one conduction, across an insulating barrier, on the part that places this control gate of insulation, to form multilayer (multi-layers) structure, thereby allow that electronics and hole are with an about close speed, the tunnel is by (tunneling through) this insulating barrier, source electrode and drain region separately, this source area in abutting connection with but electrically isolate from a lower part of this floating gate, this drain region in abutting connection with but electrically isolate from a top of this floating gate, and a channel region, be formed between this source electrode and the drain region, extend a sidewall of this groove.Give a positive voltage for this drain region, with the positive voltage that is coupled to this floating gate.Give this tunnel grid one voltage, this voltage is negative value with respect to a voltage of this control gate, and intensity is enough to make this tunnel grid electron radiation and radiates the hole from this control gate, and make this electronics and hole in about close speed but rightabout mode, pass through this insulating barrier, and make this electronics have enough energy, pass through this control gate, impact charge carrier transfer mechanism (ballistic carrier transport mechanism) and see through, and then arrive this floating gate.

Method of operation of erasing with the read-only memory element of programmable of the present invention, other includes:

Give a negative voltage for this drain region and this wellblock, with this negative voltage of coupling unit to this floating gate; And

Give this tunnel grid one voltage, this voltage with respect to a voltage of this control gate be on the occasion of, and intensity is enough to make grid radiation hole, this tunnel and from this control gate electron radiation, and make this electronics and hole in about close speed but rightabout mode, pass through this insulating barrier, and make this hole have enough energy, pass through this control gate, impact charge carrier transfer mechanism (ballistic carrier transport mechanism) and see through, and then arrive this floating gate.

For realizing purpose of the present invention, the present invention also proposes read-only memory (read only memory, ROM) method of operation of element that can erase with programmable.This element has at least two states, this element has the floating gate (floating gate) of a conduction, be formed in the groove (trench) of semiconductor substrate (semiconductor substrate), the control gate (control gate) of one conduction, have a part of placing on this floating gate of insulating, the tunnel grid (tunneling gate) of one conduction, see through an insulating barrier, on the part that places this control gate of insulation, to form multilayer (multi-layers) structure, thereby allow electronics and hole with an about close speed, the tunnel is by (tunneling through) this insulating barrier, source electrode that separates and drain region, in abutting connection with but electrically isolate from this floating gate, and a channel region, be defined between this source electrode and the drain region, electrically isolate from this floating gate.Set up this element this state one of them, utilization is from this tunnel grid electron radiation and from this control gate radiation hole, so that but this electronics and hole are in about close speed rightabout mode, pass through this insulating barrier, and make this electronics have enough energy, pass through this control gate, impact charge carrier transfer mechanism (ballisticcarrier transport mechanism) and see through, and then arrive this floating gate.Wherein another of this state of setting up this element, utilization is from this grid radiation hole, tunnel and from this control gate electron radiation, so that but this electronics and hole are in about close speed rightabout mode, pass through this insulating barrier, and make this hole have enough energy, pass through this control gate, impact charge carrier transfer mechanism (ballistic carrier transportmechanism) and see through, and then arrive this floating gate.

Description of drawings

Figure 1A to Fig. 1 F is respectively the different single nonvolatile memory element that manufactures according to the first embodiment of the present invention;

Fig. 2 A is the energy band diagram according to impact electronics of the present invention;

Fig. 2 B is the energy band diagram according to impact of the present invention hole;

Fig. 2 C is an energy band diagram, in order to show that contrary tunnel(l)ing is for impacting the negative effect that the hole radiation is caused;

Shown electronic carrier and the holoe carrier in valency electricity band and conductive strips in the semiconductor among Fig. 3, with respect to a kind of insulator, the energy rank barrier height of being seen;

Fig. 4 A is, impacts electronics and just begun to take place, and the partially conductive band of floating gate when being in initial condition;

Fig. 4 B is, floating gate has been impacted the electronics charging and finished, and the energy band diagram when producing self limit sequencing mechanism;

Fig. 4 C is, impacts the hole and just begun to take place, and the partial valence electricity band of floating gate when being in initial condition;

Fig. 4 D is, floating gate has been impacted the hole charging and finished, and the energy band diagram when producing the self limit erasing mechanism;

Fig. 5 A has shown the top view of a matrix;

Fig. 5 B is along the profile of CC ' line among Fig. 5 A;

Fig. 6 A-6J forms memory component of the present invention in regular turn, the structure top view in different phase;

Fig. 7 A-7J is respectively the profile of Fig. 6 A-6J along AA ' line;

Fig. 8 A-8J is respectively the profile of Fig. 6 A-6J along BB ' line;

Fig. 9 A-9J is respectively the profile of Fig. 6 A-6J along CC ' line.

Embodiment

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:

Memory component

See also Figure 1A to Fig. 1 F, its single nonvolatile memory element for manufacturing according to embodiments of the invention.Memory component among Figure 1A includes a matrix (bulkmaterial) 50.Matrix 50 can be semiconductor substance (silicon for example) or insulator (such as silica, silicon sulfide or the known dielectric medium of other industry).In a preferred embodiment, matrix 50 can be the silicon of one first conductivity type (hereinafter referred to as the P type), and its doping content approximately arrives 5E17 atom/cm-3 between 1E15.The semiconductor layer 40 that one first conductivity type is arranged above matrix 50, its doping content approximately arrive 5E18 atom/cm-3 between 5E15 than matrix 50 height.The thickness of semiconductor layer 40 can approximately be between 0.2 to 0.4 micron.Matrix 50 and semiconductor layer are referred to as the substrate (substrate) 51 of memory component below 40.One first heavy doping (heavily-doped) district 24 of second conductivity type (hereinafter referred to as the N type) is embedded between matrix 50 and the semiconductor layer 40.The major part of first heavily doped region 24 can be located in matrix 50 or the semiconductor layer 40.The doping content of first heavily doped region 24 can be between 1E18 to 5E21 atom/cm-3, and its thickness can be between about 0.2 to 2 micron.First heavily doped region 24 is as the source area (source region) of memory component, and semiconductor layer 40 is then as the memory wellblock at each memory component place.In the memory wellblock, just in the semiconductor layer 40, one second heavy doping (heavily-doped) district 22 of second conductivity type is formed at the position that is adjacent to semiconductor layer 40 surfaces, its doping content can arrive 5E21 atom/cm-3 between 1E19 approximately, and its thickness can be between about 0.05 to 0.15 micron.Second heavily doped region 22 is as the drain region (drain region) of memory component.Trench holes with trenched side-wall 31 is passed drain region 22 and memory wellblock 40, and the channel bottom 33 of trench holes is located in the source area 24 then.Source area 24 and drain region 22 have defined a channel region (channel region) 21 together, are prolonging trenched side-wall 31 and are forming, between source area 24 and drain region 22.On memory wellblock 40, drain region 22, channel region 21, source area 24 and channel bottom 33, be formed with one first insulating barrier 44.First insulating barrier 44 can be silicon dioxide (silicon dioxide, to call silica in the following text), silicon nitride (siliconnitride), silicon oxynitride (silicon oxynitride) or the material of high-k (such as aluminium oxide (aluminum oxide), hafnium oxide (hafnium oxide), zirconia (zirconium oxide) etc.).First insulating barrier 44 has a first 43 to place the top of memory wellblock 40 and drain region 22, and the placing trenched side-wall 31 and place on the channel bottom 33 an of second portion 45 adjacency.The thickness of the first 43 of first insulating barrier 44 can be between about 80 to 2000 dusts (), and the thickness of its second portion 43 can be between about 50 to 500 dusts ().Floating gate 20 is placed in the trench holes, sees through first insulating barrier 44, insulate mutually with memory wellblock 40, drain region 22, channel region 21 and source area 24.Floating gate 20 roughly is a rectangle, and its width can be between about 0.03 to 0.8 micron, and its thickness can be between about 0.2 to 4 micron.One second insulating barrier 29 is arranged on floating gate 20, its thickness can be between about 50 to 400 dusts (), its material can be silica, silicon nitride, silicon oxynitride, aluminium oxide, hafnium oxide, zirconia or above combination, for example composite bed of a silicon oxide/silicon nitride/silicon oxide.On first insulating barrier 44 and second insulating barrier 29 control gate 15 is arranged, it can be the intraconnections thing (such as metal silicide (silicide)) or the refractory metal (refractory metal) of heavily doped polysilicon (polycrystalline silicon), low-resistance.In one embodiment, control gate 15 can have two parts: first 16 roughly is positioned in the first 43 of first insulating barrier 44, and thickness is between about 400 to 4000 dusts (); Second portion 17 roughly is positioned on second insulating barrier 29, and thickness is approximately between about 50 to 1000 dusts ().May changing of the shape of some control gates will be described after a while.The 3rd insulating barrier 36 has first 35 in the first 16 of control gate 15, and second portion 34 is on the second portion 17 of control gate 15.The first 35 of the 3rd insulating barrier 36 can be silica, silicon nitride, silicon oxynitride, aluminium oxide, hafnium oxide, zirconia or above combination, and thickness is approximately between about 100 to 1000 dusts.The second portion 34 of the 3rd insulating barrier 36 can be silica, silicon nitride, silicon oxynitride, aluminium oxide, hafnium oxide, zirconia or above combination, and thickness is approximately between about 30 to 200 dusts.On the second portion 34 of the 3rd insulating barrier 36 tunnel grid 10.Tunnel grid 10 can be the intraconnections thing (such as metal silicide) or the refractory metals of a heavily doped polysilicon, low-resistance, and its thickness is between about 1000 to 4000 dusts.Being the 4th insulating barrier 12 in the first 35 of the 3rd insulating barrier 36, can be silica, silicon nitride or silicon oxynitride, and its thickness is between about 500 to 10000 dusts.

Figure 1A-1,1A-2 and 1A-3 have shown the partial enlarged drawing of three kinds of variations of control gate 15.Among the embodiment of Figure 1A-1 and 1A-2, its objective is to make control gate 15 have a second portion 17 thinner, thereby strengthen and impact charge carrier (ballisticcarrier), in the time of element program or erase operation for use, penetrate probability in the past than first 16.In the embodiment of Figure 1A-1, this purpose is to see through to form a recessed downward surperficial 17a on the second portion 17 of control gate 15, that is to say that surperficial 17a has a recessed structure haply.In the embodiment of Figure 1A-2, the recessed downward surperficial 17a in second portion 17 tops is exactly the flute surfaces 13a that is formed at a hemisection (semi-recessed) groove 13 of control gate 15, and the trenched side-wall 13b of groove 13 is roughly vertical with substrate surface.Second portion 17 thin degree can be decided by the material and the desirable performance of element operation of control gate 15.Haply, between 10%～90% of the thickness that the thickness of second portion 17 can first 16.Figure 1A-3 has shown an embodiment with control gate of fairly simple structure.In Figure 1A-3, the thickness of the second portion 17 of control gate 15 is roughly the same with first 16.The main benefit of Figure 1A-3 is that the processing procedure that forms control gate 15 can relatively be simplified.

The structure of memory component 100b among Figure 1B haply with Figure 1A in memory component 100a similar, and main difference is the shape of floating gate 20.The floating gate 20 of memory component 100a is a rectangle haply; Yet the floating gate 20 of memory component 100b is a V-type or the V-type of brachymemma haply.The floating gate of V-type has two parts like this: the width of top 20a can be between about 0.2 to 2 micron; The width of bottom 20b can be between tens of approximately dusts arrive to 0.1 micron.The V-structure of floating gate has effectively reduced the coupling capacitance between floating gate 20 and the source area 24 like this, therefore, can increase the capacitance coupling effect between control gate 15 and the floating gate 20.

The structure of memory component 100c among Fig. 1 C haply with Figure 1A and Figure 1B in

memory component

100a and 100b similar, and main difference is the degree of depth of floating gate 20.The groove at floating gate 20 places of

memory component

100a and 100b, its bottom 33 is to be arranged in source area 24; Yet the floating gate 20 of memory component 100c penetrated source area 24, thereby channel bottom 33 is to be arranged in matrix 50.

The structure of memory component 100d among Fig. 1 D haply with Figure 1A in memory component 100a similar, and main difference is the shape of floating gate 20.The floating gate 20 of memory component 100a is a rectangle haply, and its surface roughly trims with the surface of substrate; Yet the floating gate 20 of memory component 100d is a T type haply, and it has on the part that is positioned over substrate surface of a top insulation.In other words, protuberance 20c makes the surface of floating gate 20 be higher than substrate surface.The floating gate of T type roughly can be divided into three parts like this: the width of protuberance 20c can be between about 0.15 to 2 micron; Pars intermedia 20e is adjacent to trenched side-wall 31, and its width can be between about 0.1 to 1.5 micron; And the width of bottom 20d can be between about 0.05 to 1.5 micron.The benefit of such T type floating gate 20 is between floating gate and the control gate stronger capacitive coupling to be arranged.In addition, the second portion 17 of control gate 15 has above the protuberance 20c of floating gate 20 and can form a bulge-structure.In the process of processing procedure, therefore the relatively thinner thickness of one of formation that the second portion 17 of control gate 15 will nature, can be aimed at automatically with the protuberance 20c of beneath floating gate 20.And thin second portion 17 can provide preferable result for the transmission of impacting charge carrier (ballistic carrier).

Fig. 1 E has shown the profile according to a single non-volatile memory component of the invention process, the structure of memory component 100e wherein haply with Figure 1A in memory component 100a similar, and main difference is itself and the part that is connected of contiguous memory component.See through known shallow ridges insulation procedure (shallow trench isolation, STI) or the selective oxidation processing procedure (memory component 100e has defined active region 4 for 1ocal isolation, LOCOS) formed isolated district 5.Isolated district 5 makes with the STI processing procedure can be relatively good, because the design specification of STI (design rule) can allow smaller live width line-spacing.Generally speaking, STI is a rectangular shape haply, and thickness approximately is 0.2 micron, and width approximately is 0.1 micron, and, constituted with insulant, for example silica or other known dielectric medium.The main purpose of Fig. 1 E be can reduce control gate 15 first partly 16 and memory wellblock 40 between the parasitic capacitance that produced.The benefit that reduces such parasitic capacitance is to reduce the capacitance of being seen from control gate 15, has just reduced the load that control gate 15 is seen, thereby reduces memory component needed accessing the time (access time) when read operation.Contiguous memory component has been cut apart in isolated district 5, and the benefit that it provided can more obviously be found out from the profile Fig. 1 F.In Fig. 1 F, shown the memory component 2 among Fig. 1 E, also have two memory components 1 and 3 of both sides adjacency.Memory component is to be seated in the active region 4, and active region 4 is with the staggered settings in isolated district 5, and has formed a memory array 100f one section (segment).Emphasize at this, only shown a bit of among the memory array 100f at this, and memory array 100f can expand to any size memory array.The control gate 15 of each memory component is connected, and has constituted a control grid line 18.The length of control grid line 18 can be grown the whole array that strides across memory component.For example, suppose that an array has isolated district of staggered multiple row and active region, and be formed with a plurality of memory components in each active region, part in the memory component, similarly be control gate, just can connect together, just can stride across a full line or the memory component of a permutation then.So in fact the capacitive load effect of control grid line 18 is exactly the equivalent capacitance value summation that is positioned at the control gate 15 of each online memory component of same control gate.If under the condition that other state or variable remain unchanged, if reduced the equivalent capacitance value 50% of the control gate 15 of each memory component, that just can reduce the load 50% of control grid line, has also therefore improved the time of accessing 50%.

Figure 1A shown memory component in Fig. 1 E all has following characteristic haply.They each a control gate and tunnel grid are arranged, control gate and tunnel grid overlap on overlapping the district at one, and the floating gate that has part at least is to be positioned at the below, district that overlaps.

Certain, the size of the memory component among the present invention is the design specification (design rule) that depends in the process technique.Therefore, the memory component described above or the size in various kinds zone all only illustrate.Need benly be, the size of memory cell, must be enough to electric charge that tunnel grid 10 are emitted, pass through tunneling mechanism, for example generally occur in 3.3 volts or following direct tunnel (directtunneling), or occur in the Fowler-Nordheim tunneling mechanism of high voltage, pass the second portion of the 3rd insulating barrier 34.And, the size of the second portion 17 of control gate 15, should be to allow a part of electric charge of coming, can arrive and be received by impacting charge carrier transfer mechanism (ballistic carriertransport mechanism) by floating gate 20 from the second portion 34 of the 3rd insulating barrier 36.And the quantity that receives can be 1% to tens of % in the electric charge launched of tunnel grid 10.The physical principle of the mechanism of element operation and transmission can be explained after a while in detail like this.

Impact charge carrier transfer mechanism (ballistic carrier transport Mechanism)

What impact the representative of charge carrier transfer mechanism is electric charge carrier when advancing in conductor, does not suffer from the physical phenomenon of scattering events (scattering event).In semiconductor or other kind conductor, such scattering occurs phon scattering (carrier-to-phonon scattering) and the charge carrier form to impurity scattering (carrier-to-impurity scattering) carrier scattering (carrier-to-carrier scattering), charge carrier with charge carrier usually.And the result of these phenomenon representatives is exactly the change (having represented the change of moving direction simultaneously) of charge carrier momentum and the loss of energy.For the electric charge carrier in moving through impact transmission (ballistic transport), the residing material of electric charge carrier is stealthy relatively, and therefore, electric charge carrier can be kept its moving direction and energy in their transport process.

Impact electric charge (electronics or hole) and passed through conductor and insulator, arrive the physical phenomenon of floating gate 20 then, will explain in detail with Fig. 2 A and Fig. 2 B.Impact electric charge among Fig. 2 A is an electronics; Impact electric charge among Fig. 2 B is the hole.In the energy band diagram in Fig. 2 A and Fig. 2 B (band diagram), grid region, tunnel 52 all is a semiconductor (can be highly doped p type island region) with impacting transmission grid region 62.Select P type or N type polysilicon, due in theory consideration will be in explaining after a while.

See also Fig. 2 A, energy band diagram has wherein shown the impact electronics that is applied in the memory component of the present invention.When impacting electronics and will inject floating gate polar region 72, to transmit grid region 62 are back bias voltages to tunnel gate regions 52 with respect to impacting.Electronics 76 on the valency electricity band (valence band) of tunnel gate regions 52 will see through quantum mechanics tunneling mechanism (may be Fowler-Nordheim or direct tunnel), radiated away, and the insulator 56 that passes through tunnel.The electronics 76 of a part, classify as scattered electron (scatteredelectrons) 76b, transmit in the process in grid region 62 through overbump at them, suffer from scattering events, therefore, lost some energy, the mixed and disorderly electronics (thermal electrons) of just as heat is the same then, is impacted transmission grid region 62 and takes away.And remaining electronics classifies as impact electronics (ballistic electrons) 76b, does not meet with scattering events in passing through the process of impacting transmission grid region 62, so just the direction according to seeking script is always advanced.Apply the suitable floating gate polar region 72 that is biased in, the conductive strips that the impact electronics 76b with enough energy is overcome pin down insulating barrier (retention insulator) 67 can rank barrier height (conduction band barrier height).Such charge carrier just can enter the conductive strips 68 that pin down insulating barrier 67, keeps its direction, and is collected by floating gate 72 at last.

The energy band diagram of Fig. 2 B has shown the impact hole that is applied in the memory component of the present invention.Utilize floating grid 52 bias voltages to reach the purpose of impacting the hole ejaculation among Fig. 2 B with opposite polarity among Fig. 2 A.When tunnel gate regions 52 is positive biases with respect to impacting transmission grid 62, valency electricity band (valence band) hole 80, exactly at the valency electricity of the tunnel gate regions 52 hole electric charge on 54, will see through quantum mechanics tunneling mechanism (may be Fowler-Nordheim or direct tunnel), radiated away, and the insulator 56 that passes through tunnel is just as previous described.The hole of a part, classify as scattering hole (scattered holes) 80b, transmit in the process of grid 62 through overbump at them, suffer from scattering events, therefore, lost some energy, the mixed and disorderly hole (thermal holes) of just as heat is the same then, is impacted transmission grid 62 and takes away.And remaining hole, classify as and impact hole (ballistic holes) 80a, in passing through the process of impacting transmission grid 62, do not meet with scattering events, so just the direction according to seeking script is always advanced, up to impacting transmission grid 62 and the border that pins down insulating barrier 67.When impact hole 80a have enough energy overcome the valency electricity band that pins down insulating barrier 67 can rank barrier height (valence band barrier height) time, such charge carrier just can enter the valency electricity that pins down insulating barrier 67 and be with 69, keep its direction, collected by floating gate 72 at last.

Except show to impact theory that electric charge transmits with and in the present invention utilization, Fig. 2 A and Fig. 2 B have also shown and have used an identical tunnel grid 52, utilize the quantum mechanical tunnel principle, and the method for two kinds impact electric charge is provided.For the application of non-volatility memorizer, it is very attracting providing two kinds of impact electric charges with a tunnel grid 52, because can cause a component structure of relatively simplifying like this, also is the array of relatively simplifying simultaneously, relative, also can be fairly simple on the processing procedure.But, reach such purpose, the difficulty that but has needs to overcome, that is exactly the contrary tunnel(l)ing (reverse tunneling phenomenon) that is produced about the hot charge carrier in a jumble that transmits in the grid region 62, follow the opposite charge of impacting charge carrier in impact.Fig. 2 C has discussed this difficulty, has wherein shown the radiation of impact hole.In the energy band diagram of Fig. 2 C, tunnel grid 52 are respectively the semiconductors of P type and N type with impacting transmission grid region 62, for example are polysilicons.This explains aforesaid difficulty as an example.When impacting hole radiation generation, impact the conductive strips electronics that transmits in the grid region 62, will follow the same quantum mechanical tunnel mechanism, radiated away.But the direction of transfer of such conductive strips electronics just is to be that positive valency electricity band holoe carrier 80 is opposite with direction of transfer, shown in Fig. 2 C.The whole electric current of tunnel grid 52 in fact is to have comprised the electric current (tunnel segment of forward is provided) that valency electricity band holoe carrier 80 is contributed, and adds the electric current (reverse tunnel segment is provided) that conductive strips electronic carrier 83 is contributed.The tunnel segment of forward is to be used to impact the electric charge radiation.And when storage operation need be used impact electric charge radiation mechanism, the tunnel segment of this forward was exactly a carrier flow that needs (carrier flow).But reverse tunnel segment then is unwanted, because it does not a bit all have contribution for impacting the electric charge radiation.Another does not wish that the effect that occurs is, reverse tunnel segment can limit the maximum of forward tunnel segment, also limited simultaneously the forward tunnel segment whether can be greatly to using needed magnitude of current when impacting the electric charge radiation.For an impact hole radiation events, reverse tunnel has often accounted for the overwhelming majority of whole tunneling process, also therefore, has often limited impact transmission hole current and whether can arrive enough sizes.The reason that this phenomenon takes place is that the energy rank barrier height 59 that conductive strips electronics 83 is seen be lower than the energy rank barrier height 60 that valency electricity band hole 80 is seen in fact, thereby the electric current of tunnel grid 52 is contributed by electronic carrier.Especially, when tunnel insulation layer 56 is when constituting with silica, this phenomenon can be more obvious, because, the electric current that conductive strips electronics 83 is contributed, big appointment is 1,000 times to 1,000,000 times of the electric current that provided of valency electricity band hole 80.Just because of this phenomenon, this powerful electron stream has in fact just limited tunnel grid 52 and has impacted and transmit operable cross-pressure between the grid region 62.Therefore, also whether restriction can use a lower voltage simultaneously, just can effectively utilize the impact transfer mechanism, uses holoe carrier 80a to cause the possibility of floating gate 72.For example because tunnel grid 52 with impact to transmit grid region 62 be limited in lower than the voltage of hope, therefore, impact the energy that holoe carrier had, to be not enough to overcome energy rank barrier height 71, and be stopped so just pin down insulating barrier 67, and can't reach floating gate polar region 72.Certainly, the silicon nitride layer of zero defect (trap-free) perhaps exists, and a just opposite state is provided.But, impact electronic emission and also still can be limited, because the conductive strips that conductive strips electronics 83 is seen energy rank barrier height 59 is higher than the valency electricity band energy rank barrier height of being seen in valency electricity band hole 80 60 by reverse tunnel holoe carrier.No matter all can having stoped, the difference of phenomenon, two states see through the possibility that same tunnel grid 52 provides impact electric charge radiation not of the same race, shown in Fig. 2 C.

These phenomenons all are the natural phenomenas owing to contrary tunnel, and a large amount of contrary tunnel currents will cause the puzzlement of using single tunnel grid to produce the method for impacting charge carrier when the opposite polarity bias voltage.This puzzlement but can select for use P type semiconductor to overcome as impacting the material that transmits grid 62.Such conception has been presented among Fig. 2 B.Can find among the figure to contribute to the charge carrier of the contrary tunnel segment electronics 83 of conductive strips from Fig. 2 C, changing becomes valency electricity charged sub 82 among Fig. 2 B.What change Just because of this, contrary tunneling electron charge carrier 82 were seen can will increase by rank barrier height, and the amount of increase approximately is exactly to impact the band gap 61 (band gap) that transmits grid 62 employed materials.For example, if impacting transmission grid 62 employed materials is polysilicons of heavy doping N type, and the material of tunnel insulation layer 56 is silica, transmit the polysilicon that grid 62 change the P type in case impact, what that electron institute was seen can just can be increased to 4.22eV from 3.1 electron-volts (eV) by rank barrier height.According to employed material in this example, what the valency electricity band holoe carrier 60 in the tunnel grid 52 was seen can rank barrier height 60 approximately be 4.5eV.Therefore, contrary tunnel charge carrier is seen can rank barrier height with forward tunnel charge carrier seen similar.Also therefore, in the total current in the tunnel grid 52, only about half ofly contributed, and approximately second half is contributed by reverse tunnel segment exactly by the forward tunnel segment.So reverse tunnel just can significantly reduce for the negative effect of impacting the electric charge transmission.

According to the present invention, use the semiconductor of P type, for example the polysilicon of P type comes while so structure as tunnel grid 52 and impact transmission grid 62, can cause two kinds of characteristics.The first, such structure can allow to impact electronics and impact the hole and emit from same electrode.The second, such structure has reduced contrary tunnel(l)ing for the negative effect of impacting the electric charge radiation.When the data among Fig. 3 provide selection band gap that can be suitable and can rank barrier height have made identical grid place, a tunnel and opposite polarity bias voltage, all provide the method for the impact charge current of similar ratio.Shown electronic carrier and the holoe carrier of semiconductor (such as polysilicon or pure silicon) in valency electricity band and conductive strips among Fig. 3, with respect to a kind of insulator, that is seen can rank barrier height.Energy rank barrier height among the figure can be expressed as the function of the ratio (being exactly x) of oxygen in the silicon oxynitride system (SiOxN1-x).Because outstanding factory's processing procedure control and membrane quality are selected the representative of silicon oxynitride system as insulating barrier here for use.In silicon oxynitride system (SiOxN1-x), x represents the ratio of oxygen, the representative that is equal in a silicon oxynitride film contained oxygen percentage.For example, x=1 means that this thin film is a silica purely just; Identical reason, x=0 means that this thin film has been a silicon nitride purely just.Along with the change of x, band gap (energy gap) can become the 5.1eV of pure silicon nitride from the 8.7eV of pure silica.At this, in order to selecting reasonable dielectric medium, and the notion of reasonable structure, mainly be to find out a plurality of charge carriers (electronics and hole) that meet two conditions.The first, these charge carriers roughly can be seen identical energy rank barrier height.The second, these charge carriers are identical being with (therefore, the material of same conductivity just, for example: N type or P type).Use above notion, just can only find a state to meet above condition among Fig. 3.Can find among Fig. 3 that what the hole in the valency electricity band was seen can rank barrier height, oxygen ratio approximately slightly 82% o'clock, roughly with the electron institute in the valency electricity band see can rank barrier height equally high.Therefore, proposing a reasonable three-tier architecture at this, is exactly two-layer heavily doped polysilicon layer, and middle interior folder one deck oxygen ratio is about 82% silicon oxynitride film.Three-decker makes and is impacting the electric charge radiation like this, and when suitable bias voltage put on two polysilicon electrodes, electronics was worn flow or the speed of satisfying silicon oxynitride with the hole, roughly is with identical.In addition, such result also has a benefit, and contrary exactly tunnel current can impact suitable approaching of hole or the positive tunnel current of electronics with being used for doing producing haply.For example, the ratio of contrary tunnel current and positive tunnel current can be approximately between 0.1 to 5.It is noted that, perhaps, electronics in SiOxN1-x can have influence on the electric current that passes through wherein with the quadratic effect that fine difference caused (second order effect) on the equivalent mass (effective mass) in hole, and can't meet the condition that previous electric current equates.Under this situation, the oxygen ratio among the possible SiOxN1-x just needs slightly to adjust, and makes electric current wherein meet the condition that previous electric current equates.

It is noted that, present disclosed three-decker and find out the roughly the same method of electric current, be not to apply to polysilicon or semi-conductive tunnel grid 52 and impact transmission grid 62, person skilled in the art scholar can apply to it on material of other type.For example, the method among Fig. 3 just can apply to metallic conductor, as long as the curve that is relevant to conductive strips and valency electricity band among the figure, change into about the curve of metal Fermi level (Fermilevel) just passable.In addition, be the characteristic (ratio of oxygen) that changes insulating barrier at the basic idea of the method for this exposure, meet aforesaid two conditions.Certain, in addition expansion or adjust the method that person skilled in the art scholar also can be suitable the same meets identical condition.For example, can be under the condition of the characteristic that does not change insulating barrier 56, grid 52 change to the proper metal material with impacting transmission grid 62 wearing then, also may be able to meet the same condition, reach the same effect.For example, can select a metal, Fermi level (Fermi level) in its work function (work function) approximately is positioned at the centre of the band gap (band gap) of insulating barrier, and therefore, what electronics or hole were seen can rank barrier height can be equal probably just.In addition, in the three-decker of this exposure, insulating barrier is a single layer structure.Person skilled in the art scholar also can be suitable expansion or adjustment in addition, the composite bed (compositelayer) that this insulating barrier is become have multilayer.That is to say that insulating barrier is not limited to homogenous material, also can have multiple material, the same desirable effect of the present invention that reaches.

For person skilled in the art scholar, phenomenon described above and principle can be identified as the fact haply, and some do not discuss phenomenon, and are unlikely and significantly influence the present invention.For example, in the present invention, impact electronics 76a and impact hole 80a perhaps can in some place (perhaps being to pin down insulating barrier 67), suffer from scattering events.And such phenomenon, should not influence the present invention the scope that should comprise.

The memory component operation

Memory component operation described below will be with the memory component among Figure 1A as a reference.

1, sequencing (program)

When a memory component that is chosen to was wanted executive program, the impact electric charge of one first kenel (electronics for example) must be launched into floating gate 20.The method that reaches is as described below.At first, apply a small voltage (such as 2V) on the control gate 15.Apply a negative voltage on the tunnel grid 10.This negative voltage with respect to the voltage difference of control gate 15, must overcome the conductive strips barrier height of second layer insulating barrier 29 even as big as making electric charge.For Fig. 2 A for the disclosed energy band diagram of Fig. 3, the voltage of tunnel grid 10 can be approximately between-2.1V between-the 2.5V.One positive voltage approximately between 0 to 0.9V, can see through capacitance coupling effect, via drain region 22, memory wellblock 40, is applied on the floating gate 20.The electronics that is come out by tunnel grid 10 radiation will advance towards the direction of the second portion 17 of control gate 15.So the impact that the second portion 17 of control gate 15 has just constituted among Fig. 2 A transmits grid region 62.When electronics arrives the second portion 17 of control gate 15, they will have the energy of great number, and major part wherein, will see through and impact transfer mechanism (ballistictransport mechanism), under the situation that does not have off-energy and momentum, penetrate the second portion 17 of control gate 15, arrived the interface (interface) of the second portion 17 and second insulating barrier 29.If the energy of electronics is high to enough making themselves energy rank barrier height that strides across second insulating barrier 29, electronics just can enter second insulating barrier 29, move, arrives at last floating gate 20 therein.Impact the thickness that transfer mechanism can see through the second portion 17 of adjusting control gate 15, make its easy generation.Such thickness should be approximately less than or equal the average free footpath (mean-free-path) of electronics in that zone.For not chosen the memory component of wanting executive programization, if they are not sharing identical drain region and source area (or being positioned at listing of not chosen) with the memory component of being chosen, their drain region 22 and source area 24 are ground connection.Do not share the memory component (or being positioned on the row of not chosen) of identical control grid line with the memory component of being chosen, its control gate 15 also is a ground connection.The memory component that like this, only is positioned on the intervening portion of the row chosen and row can be by sequencing.

Be transmitted electronically to the process of floating gate 20, can continue always, begin to take place up to the blocking effect that impacts electronics.This blocking effect be floating gate 20 can be with the result who is raised, just floating gate 20 has been collected the result that the current potential that electron charge caused descends.So, just formed on second insulating barrier 29 one leg-of-mutton can rank barrier, and the increasing of the impact electron charge that this triangle can rank barrier can be collected along with floating gate 20, and uprising.In case this triangle is can rank barrier high to a certain degree, can't cross at the electronics of floating gate 20 radiation from tunnel grid 10 its etc. during usefulness rank barrier height, the electronics of transmission will be blocked in outside the floating gate 20 completely.This blocking effect is determined by voltage.That is to say that electric current wherein is different with the viewed phenomenon in the Fowler-Nordheim tunneling mechanism, is to be controlled by voltage basically.And second insulating barrier 29 generally is 80 dusts or thicker.The second so thick insulating barrier 29 times, more the electric charge tunnel of influence by voltage (just directly tunnel) is not almost impossible.Therefore, such blocking effect provides self limit (self-limiting) method of the electronics of injecting floating gate that can be accurate.As long as adjust the voltage in the zone (for example the drain region 22) around the coupling floating gate, just can predictorization the due magnitude of voltage of floating gate afterwards.Such mechanism is highly suitable for polymorphic storage (multi-levelmemory).

2, (erase) erases

Basically, will be carried out by the memory component chosen and to erase, be that the bias voltage that sees through in the time of will applying to sequencing is opposite, just can reach.More particularly, exactly the impact electric charge (hole for example) of one second kenel is injected floating gate 20.The method that reaches is as described below.At first, apply a small voltage on the control gate 15 (for example-2V).Apply a positive voltage on the tunnel grid 10.This positive voltage with respect to the voltage difference of control gate 15, must overcome the valency electricity band barrier height of second insulating barrier 29 even as big as making electric charge.For Fig. 2 A for the disclosed energy band diagram of Fig. 3, the voltage of tunnel grid 10 can be approximately between 2.1V between the 2.5V.One negative voltage approximately between 0 to-0.9V, can see through capacitance coupling effect, via drain region 22, memory wellblock 40, is applied on the floating gate 20.Under such bias voltage, according to the hole that quantum mechanics radiated out, can pass the second portion 34 of the 3rd insulating barrier 36 by tunnel grid 10, advance towards the direction of the second portion 17 of control gate 15 then.So the impact that the second portion 17 of control gate 15 has just constituted among Fig. 2 A transmits grid region 62.When the hole arrives the second portion 17 of control gate 15, they will have the energy of great number, and major part wherein, will see through and impact transfer mechanism (ballistictransport mechanism), under the situation that does not have off-energy and momentum, penetrate the second portion 17 of control gate 15, arrived the interface (interface) of the second portion 17 and second insulating barrier 29.If the energy in hole is high to enough making them oneself stride across the energy rank barrier height of second insulating barrier 29, the hole just can enter second insulating barrier 29, move, arrives at last floating gate 20 therein.The carrying out that such impact holoe carrier will continue constantly to floating gate 20 chargings, begins to take place up to self limit (self-limiting) mechanism.The electronics self-limiting mechanism of discussing when the hole self-limiting mechanism is followed sequencing is similar.Arrive hole shared ratio in the hole that tunnel grid 20 radiated out of floating gate 20, be defined herein as and impact hole transmission efficiency (ballistic holetransport efficiency), the thickness that can see through the second portion 17 of adjusting control gate 15 improves.Such thickness should be approximately less than or equal the average free footpath (mean-free-path) of hole in that zone.To do not carried out for the memory component of erasing for choosing, if they are not sharing identical drain region and source area (or being positioned on the row or column of not chosen) with the memory component of being chosen, their drain region 22 and source area 24 are ground connection.Do not share the memory component (or being positioned on the row of not chosen) of identical control grid line with the memory component of being chosen, its control gate 15 also is a ground connection.The memory component that like this, only is positioned on the intervening portion of the row chosen and row can be erased.

It is noted that, according to the present invention, the voltage of required usefulness when sequencing and erase operation for use, its absolute value all is not more than 2.5V.And such erasing mechanism and element architectural features make possibility that erasing of individual elements becomes, and this is very desirable for periodically needing data storing of change.Certainly, such feature also can apply to a small set of memory component of once erasing simultaneously, and for example, 8 memory components of once erasing simultaneously are used for depositing one " word (digital word) ".Certainly, also can apply to large numbers of memory component of once erasing simultaneously.For example, the memory component of once erase simultaneously one page (page) or multipage, each page or leaf has 2048 memory components.

3, read (read)

Read the storage element line that a quilt is chosen, grant its drain region 22 about 1V, and grant about 2.5V (this depends on the operating voltage of internal logic element) to control gate 15, voltage all can be described as and reads voltage like this.Other zone, for example source area 24 and memory wellblock 40 all are ground connection.

If the electric charge that fills in the floating gate 20 is positive, or say that the electronics in the floating gate 20 has been bled off, that channel region 21, just in abutting connection with the zone of floating gate 20 along trenched side-wall 31, will conducting.That electronic current will flow to drain region 22 from source area 24.Here it is logical one state.

Opposite, if the electric charge that fills in the floating gate 20 is born, that channel region 21 may be faint conducting, or even closes completely.Although control gate 15 all rises to drain region 22 and reads voltage,, electronic current seldom or or even do not have electronic current can flow fully through channel region 21.Under this situation, the electronic current of electronic current at this moment when the one state is very little in comparison, perhaps can be considered as not existing.Therefore, a such memory component will be regarded as being turned to the logical zero state by program.

For the row of not chosen, its control gate is a ground connection; The row of not chosen, its drain region is a ground connection.No matter be the memory component of choosing or not choosing, its memory wellblock 40 all is a ground connection.

Such memory component, can be formed in the memory array, be accompanied by traditional row-address decoder circuit (row address decodingcircuitry) that everybody knows, column address decoder circuit (column address decodingcircuitry), detecting amplifying circuit (sense amplifier circuitry), output buffer (output buffer circuitry) and input buffer circuit (input buffercircuitry) etc.

Memory component framework of the present invention and element operation mode have very large benefit, because, element operation without any need for high voltage (being higher than 2.5V), so the high voltage generation foundation structure of being mentioned with regard to no longer needing in the prior art (high-voltageinfrastructure) does not just have high voltage to produce the problem that foundation structure (high-voltageinfrastructure) is derived yet.The important feature of another the present invention be tunnel grid 10 storehouses on the second portion 17 of control gate 15, and floating gate 20 is placed on so framework of the below, zone that second portion 17 and tunnel grid 10 overlap.This framework makes electronics or the hole that tunnel grid 10 radiation on the silicon base are come out, can be straight downwards, be conveyed into the floating gate 20 of below.

The radiation framework of this " from top to bottom " of the present invention compared with prior art, has many benefits.The first, sequencing efficient (program efficiency) can significantly improve, and radiates away because impact electric charge carrier to aim at floating gate 20.Formerly in the sequencing framework of technology, the electronics that moves in raceway groove all is to prolong to follow the parallel direction of floating gate to move basically.Therefore, in the prior art, also only there is the electronics of considerably less part to be heated to and has enough energy, and be launched in the floating gate.The chances are between 1/1,000 to 1/1,000, between 000 for sequencing efficient in the prior art (being defined as the ratio value of the quantity of electric charge of injecting and the quantity of electric charge of always supplying).But, in the present invention, because the radiation framework of this " from top to bottom ", high energy carriers is that straight aligning floating gate radiation (or emission) is gone out, its sequencing efficient is estimated and can be that is to say near 1/10, has very most electric charge to be launched in the floating gate.The second, from the element operation mode as can be known, ceiling voltage (2.5V) only appears at the top (for example control gate 15 and tunnel grid 10) of silicon face.In other words, metallurgy connects face (metallurgicaljunction) (source area 24 and the drain region 22 formed faces that connect) place silicon face, when element operation, can not be exposed to that ceiling voltage.According to the present invention, when reading, source area 24 and drain region 22 have been played the part of main role really, but also are to operate under the low-voltage environment.When sequencing or erase operation for use, the part of source area 24 and drain region 22 is also as long as 20 1 slight voltages of floating gate (～0 to 1V) are given in coupling, therefore, compare with need producing hot carrier (hot carrier) necessary high voltages, also can be little many.

Because the relevant range that can allow metallurgy connect face maintains under the low relatively voltage, thus the invention provides following prior art the advantage that can't reach.The first, the dimension reduction restriction on the element heights of speaking of in the prior art has been eliminated, and therefore, can create littler component size with tighter design specification (design rule).The size reduction of memory component can reach 50%, because floating gate 20 is to be embedded in the substrate 50, and 22 of drain regions can receive low-voltage.If use 0.18 and 0.13 micron present process technique, memory component area respectively about 0.21 and 0.11 micron square.Certainly, the element area is possible can be littler.The second, connect the hot carrier's effect (hot carrier effect) of face and insulating barrier 45 qualities that hot carrier's effect is derived descend or the variety of problems of damage has also all disappeared together about metallurgy.This is all different fully with prior art just, add high voltage and connecing on the face because the sequencing in the prior art all is utilization, reach the purpose that adds hot carrier, so inevasible meeting produces very strong electric field stress to being positioned at oneself with the insulating barrier in the middle of the contiguous floating gate, thereby generation insulation quality descends or the result of damage.And in the present invention because floating gate 20 follow arround the cross-pressure in zone (for example the drain region 22) all be very little, so the electric field stress on the insulating barrier 45 also is very little, therefore has what damage situation hardly and take place.This feature for the reliability and electric charge lasting (charge retention) degree of non-volatile memory component, is very very important.

4, element disturbs (cell disturb)

Just because of memory component 100a is placed in the environment of an array, so may be because of the sequencing or the erase operation for use of other memory component in the same array, or the reading of any memory component, thereby the interference (disturbance) of q.s, just accidental also unfortunate being changed of the logic state of memory component 100a have then been accumulated.And memory component provided by the present invention can be avoided such problem.For example, in order to make electronics or cavity energy have enough energy, cross over be right after floating gate 20 with the insulating barrier 45 between the drain region 22 can rank barrier height (electronics about 3.1eV, the hole seen see be 4.6eV), charge carrier must quicken through near the face that the connects electric fields the drain region 22 and heat, to obtain sufficiently high energy, interference just can occur like this.Just because of the voltage of drain region 22 is for the voltage difference in other zone, all metallurgy connect the cross-pressure of face in other words conj.or perhaps, therefore very low (about 2 to 2.5V) that all always keep, can prevent effectively that electronics and hole from obtaining to be higher than the energy of those energy rank barrier height.In other words, if from connecing the angle of the interference that the face electric field produced, such bias voltage framework provided by the present invention can be ignored the memory component of not choosing at all, their sequencing, erase or read the interference that may cause.

In addition, impact electric charge radiation framework provided by the present invention also can significantly reduce the element disturbing effect.There are many situations that this effect can be described.The first, the poorest situation in the interference of reading is to occur in floating gate 20 to be in erased status (just floating gate 20 is electric neutrality or positive charge a little).Under this situation, the impact electronics that is brought out by control gate 15 may pass through the second portion 17 of control gate 15, and arrive the connect face of second portion 17 with insulating barrier 29 on a small quantity.But these electronics will have no idea to stride across energy rank barrier height (nearly 4eV), because their energy constraint is followed low cross-pressure (about 2V when reading) between the tunnel grid 10 in control gate 15, approximately just have only 2eV.So predictable, electronics will be blocked in outside the floating gate 20, therefore, the state of charge of floating gate 20 oneself just can not be affected.The second, the poorest situation of erasing in disturbing is to occur in floating gate 20 to be in sequencing state (just floating gate 20 has negative electrical charge).Under this situation, the impact hole of being brought out by control gate 15 may be passed through the second portion 17 of control gate 15, and arrive the connect face of second portion 17 with insulating barrier 29 on a small quantity.But, as described in first situation, energy rank barrier height (nearly 4eV) will be had no idea to stride across in these holes, because the low cross-pressure (about 2V when erasing) that their energy constraint is followed between the tunnel grid 10 in the control gate 15 of the element of not chosen approximately just has only 2eV.So predictable, the hole will be blocked in outside the floating gate 20, therefore, the state of charge of floating gate 20 oneself just can not be affected.

In addition, memory component of the present invention also can effectively reduce because of capacitance coupling effect, and the element that cross-pressure caused that produces on insulating barrier 29 disturbs.The poorest situation that comes from the element interference of this effect is that the floating gate 20 that occurs in when memory component is to be positioned at sequencing state (just floating gate has negative electrical charge).Because, the floating gate of memory component 100a can have capacitance coupling effect with all other electrode (source electrode 24, drain electrode 22 and memory wellblock 40 etc.) all around, can suppose reasonably that the capacitive coupling rate (capacitive coupling) of 15 pairs of floating gates 20 of control gate is 20%.Such capacitive coupling rate, add the low-voltage (2.5V) that is applied with when reading on the control gate 15 outward, the cross-pressure that may on the insulating barrier 29 between floating gate 20 and the control gate 15, be produced, but be near the 1.5V to 2.5, so the issuable electric current of Fowler-Nordheim tunnel effect just can be ignored at all.

Take a broad view of above-described disturbing effect and mechanism, no matter be element operation or element capacitive coupling, all by appropriate design and be controlled under the very good condition, so, in the middle of whole useful life of memory product process, can effectively prevent the non-expectation of memory component, accidental be transformed into " 0 " state from one state, or from " 0 " state exchange to one state.

Self limit (self-limiting) during the memory component operation is impacted the electric charge radiation (ballistic charge injection)

Below will explain that self limit radiation mechanism and it are in the application of element design with operation the time with a simple capacitive.The voltage of floating gate 20 probably can be used following formulate:

V _FG＝(Q _FG+∑C _iV _i)/C _total

And

∑C _iV _i＝C _FG-S*V _S+C _FG-D*V _D+C _FG-CG*V _CG+C _FG-W*V _W

C _total＝C _FG-S+C _FG-D+C _FG-CG+C _FG-W

Wherein,

Q _FGIt is the total charge dosage in the floating gate 20;

C _FG-SIt is the capacitance between floating gate 20 and the source area 24;

C _FG-DIt is the capacitance between floating gate 20 and the drain region 22;

C _FG-CGIt is the capacitance between second district 17 of floating gate 20 and control gate 15; And C _FG-WIt is the capacitance between floating gate 20 and the memory wellblock 40.

When initial condition (initial condition), can suppose does not have electric charge or electroneutral in the floating gate 20, and the voltage of that floating gate 20 just approximately is

V _{FG_i}＝∑C _iVi/C _total

1, programming operations

Below with programming operations, as impacting charge carrier, explain self limit radiation mechanism with first kind of electric charge (electronics).Fig. 4 A is in Fig. 2 A energy band diagram, just begun to take place impacting electronics, and the partially conductive band of floating gate 20 when being in initial condition.In Fig. 4 A, the impact that the second portion 17 of control gate 15 is used for being used as among Fig. 2 A transmits grid 62.Floating grid 72 among Fig. 2 A then can be used as the floating gate 20 in the memory component of the present invention.The kinetic energy 90 that impact electronics 76a in the transmission has, being enough to make it oneself stride across the conductive strips that pin down insulating barrier 29 can rank barrier height 70.In the drawings as seen, the kinetic energy 90 that impact electronics 76a is had exceeds represented as symbol 90a approximately amount than the conductive strips energy rank barrier height 70 of insulating barrier 29.Such charge carrier enters the conductive strips 68 in the insulating barrier 29 with that, just is subjected to electrical field draw then, drops to floating gate 20 at last and is collected.See through such radiative process, negative electrical charge can be among floating gate 20 gradually accumulation, and change gradually the own current potential of floating gate 20, the while has also changed the electric field in the insulating barrier 29.Along with the lasting generation of radiative process, such effect just can be impacted the direction (Fig. 4 A) of electric charge to floating gate 20 from assisting to transmit with the electric field in the insulating barrier 29, becomes to resist to transmit and impacts electric charge (Fig. 4 B).

Fig. 4 B follows Fig. 4 category-A seemingly, and main difference is in the current potential in floating gate.Here, the current potential of floating gate 20, from original initial condition, the negative electrical charge that is collected into changes.Along with the lasting generation of radiative process, at this moment have the impact electronics of the same kinetic energy 90, will be reflected, and get back to the second portion 17 of control gate 15, just as hot spuious charge carrier equally is pulled away then.In figure, more particularly point out, though electronics 76a can enter the conductive strips 68 in insulating barrier 29 subregions, but can't overcome conductive strips energy rank barrier height 70a in the insulating barrier 29.Shown also among the figure that very small amount of charge carrier can see through the quantum-mechanical mechanism that penetrates, passed through certain distance 70b, become electronic carrier 76d at last, arrived and treat in floating gate 20.But the probability that electronic carrier 76d takes place is very low-down (for example, about 1,000,000/), and, can explain that after a while very fast being lowered of expected meeting of probability takes place for this.According to the phenomenon of above description, the electric charge that floating gate 20 is collected can form a kind of mechanism, stop limits to go to the impact charge carrier of floating gate 20.Fig. 4 B just provides the basic theories of such self limit.The electron stream that electron stream 76d follows the FOWLER-Norheim tunnel to be caused is different to be that electron stream 76d can be more responsive for voltage.This has many kinds of reasons.The first, the thickness that pins down insulating barrier 29 approximately is 60 dusts or thicker, so can be considered as a Fowler-Nordheim tunnel dielectric medium.If do not consider other effect, the flow of electronic carrier 76d is with the correlation of voltage, just should be described similar with the Fowler-Nordheim tunneling characteristics, and in the Fowler-Nordheim tunneling characteristics, electric current is that very big dependence is arranged with voltage, especially when low-voltage, generally be every rising 100mV, the just big appointment of electric current increases by 10 times.The second, along with being collected by floating gate 20 that electric charge continues, therefore just always constantly being enhanced by rank barrier height of insulating barrier 29 also set up a reverse electric field E, so with regard to the more effective impact charge carrier 76a that wants to enter floating gate 20 that keeps out.Reverse electric field E like this can be expressed as generally

E＝(Q _FG-Q _{FG_fb})/(T _insulatorC _total)

Wherein

Q _{FG_fb}Electric charge when being in flat rubber belting state (flat band condition) when insulating barrier 29 in the floating gate;

T _InsulatorBe the thickness of insulating barrier 29;

Stopping can rank barrier height Φ _e, impacting the conductive strips energy rank barrier height that electronics is seen exactly in insulating barrier 29, can be expressed as

Φ _e＝q(Q _FG-Q _{FG_fb})/C _total-ΔK _e

Wherein

Δ K _eBe electronic carrier kinetic energy 90 with second insulating barrier 29 at the interface can rank barrier height poor 90a, the initial kinetic energy in the time of also can being considered as electronic carrier 76a and just having entered insulating barrier 29; And

Q is the quantity of electric charge of an electronics.

Therefore, work as Φ _eWhen being lower than zero, Δ K just _eGreater than q (Q _FG-Q _{FG_fb})/C _TotalThe time, the impact electronics can transmit and pass through insulating barrier 29, and reverse electric field roughly can be ignored for the influence that the impact electric charge that comes is caused.Along with the carrying out that radiation continues, Φ _eCan equal zero, just Δ K _eEqual q (Q _FG-Q _{FG_fb})/C _Total, the influence that reverse electric field is caused for the impact electric charge that comes just begins to occur.When more lasting the carrying out of radiation, impacting the conductive strips that electronic carrier seen in insulating barrier 29 can just begin to form by rank barrier height 70a, and, along with electric charge by floating gate 20 collect many more, the height that its conductive strips can rank barrier height 70a is just high more.Will increase the quantity of the impact charge carrier 76a that can equal to come at last fast so can be contemplated that the quantity of the charge carrier 76c that bounce-back is gone back.Also therefore, reduce the charge carrier quantity that can participate in the Fowler-Nordheim tunnel, also reduced the electronic carrier 76d quantity that has arrived floating gate 20.This mechanism has more highlighted and has suppressed the voltage effects that electric charge is sent to floating gate 20.

When radiating the sequencing element with the impact electric charge, aforesaid two kinds of effects all constitute self limit radiation mechanism simultaneously.When sequencing is incipient, can stride across energy rank barrier height 70 as long as impact electronic carrier, such electronic carrier just allows by insulating barrier 29, arrives at floating gate 20 then.Along with the carrying out of sequencing, electron charge will be deposited in floating gate 20 gradually, and in case the voltage of floating gate 20 being lowered slowly just then is low to certain value V _{FG_P}The time, will produce one new can rank barrier height 70a, and stoped all follow-up impact electronic carriers that come, make them can't arrive floating gate 20.Like this, along with the mechanism generation of self limit, sequencing just finishes, thereby has finished the flow process of whole procedureization.

When sequencing was finished, the total charge dosage in floating gate 20 can be estimated with following simple formula:

Q _FG＝C _total(V _{FG_P}-V _{FG_i})

Total charge dosage also can be estimated with another simple formula:

Q _FG＝C _{FG_fb}+(C _total/q)*ΔK _e

Hence one can see that, and after the flow process of sequencing finished, the total charge dosage that is deposited in the floating gate 20 depended on two main parameters.First parameter is impacted electronics 76a specific energy rank barrier height 70 additional additional energy 90a exactly.Because this additional energy 90a can see through tunnel grid 10 and follow the voltage difference of the second portion 17 of control gate 15 to determine, so as long as 15 bias value is followed in suitable selection or control area 10, that just can determine to leave in the total charge dosage of floating gate 20.Total capacitance Ctotal can see through the effect that element design is assisted or reinforcement is such as a fine setting parameter.For example, less total capacitance C _TotalWith causing the bias value that needs a bigger zone 10 to follow between 15, radiate the equivalent electric charge to floating gate 20.The parameter of the total charge dosage of second decision in the floating gate relates to and causes the required floating gate electric weight of insulating barrier 29 flat rubber belting states (flat bandcondition).And such electric weight is determined by memory component all electrode and corresponding coupling capacitance.Therefore, as long as selected one group of such parameter, programmed memory element to a specific state accurately just.Q _FGWith Δ K _eLinear relationship between (additional energy 90a just) more makes memory component of the present invention have the advantage of multimode storage capacity.

2, erase operation for use

Below with erase operation for use, as impacting charge carrier, explain self limit radiation mechanism with second kind of electric charge (hole).Fig. 4 C is in Fig. 2 B energy band diagram, just begun to take place impacting the hole, and the partial valence electricity band of floating gate 20 when being in initial condition.Be some negative electron charges to be arranged therein in the floating gate 20 during at this moment initial condition.In Fig. 4 C, the impact that the second portion 17 of control gate 15 is used for being used as among Fig. 2 B transmits grid 62.Floating grid 72 among Fig. 2 A figure then can be used as the floating gate 20 in the memory component of the present invention.The kinetic energy 92 that impact hole 80a in the transmission has, being enough to make it oneself stride across the valency electricity band that pins down insulating barrier 29 can rank barrier height 71.In the drawings as seen, the kinetic energy 92 that impact hole 80a is had exceeds represented as symbol 92a approximately amount than the valency electricity band energy rank barrier height 71 of insulating barrier 29.The valency electricity that such charge carrier enters in the insulating barrier 29 with that is with 69, just is subjected to electrical field draw then, drops to floating gate 20 at last and is collected.See through such radiative process, positive charge can be among floating gate 20 gradually accumulation, and change gradually the own current potential of floating gate 20, the while has also changed the electric field in the insulating barrier 29.Along with the lasting generation of radiative process, such effect just can be impacted the direction (Fig. 4 C) of electric charge to floating gate 20 from assisting to transmit with the electric field in the insulating barrier 29, becomes to resist to transmit and impacts electric charge (Fig. 4 D).

Fig. 4 D is similar with Fig. 4 C, and main difference is in the current potential in floating gate.Here, the current potential of floating gate 20, from original initial condition, the positive charge that is collected into changes.Along with the lasting generation of radiative process, at this moment have the impact hole of the same kinetic energy 92, will be reflected, and get back to the second portion 17 of control gate 15, just as hot spuious charge carrier equally is pulled away then.In figure, more particularly point out, though the valency electricity that hole 80a can enter in insulating barrier 29 subregions is with 69, but can't overcome valency electricity band energy rank barrier height 71a in the insulating barrier 29.Shown also among the figure that very small amount of charge carrier can see through the quantum-mechanical mechanism that penetrates, passed through certain distance 71b, become holoe carrier 80d at last, arrived and treat in floating gate 20.But the probability that holoe carrier 76d takes place is very low-down, and, can explain that after a while very fast being lowered of expected meeting of probability takes place for this.According to the phenomenon of above description, the electric charge that floating gate 20 is collected can form a kind of mechanism, stop limits to go to the impact charge carrier of floating gate 20.The basic theories of the self limit when Fig. 4 D just provides such erasing.The electron stream that hole stream 80d follows the FOWLER-Norheim tunnel to be caused is different to be, hole stream 80d can be more responsive for voltage.This has many kinds of reasons.The first, the thickness that pins down insulating barrier 29 approximately is 60 dusts or thicker, so can be considered as a Fowler-Nordheim tunnel dielectric medium.If do not consider other effect, the flow of holoe carrier 80d just should be described similar with the Fowler-Nordheim tunneling characteristics with the correlation of voltage.The second, along with being collected by floating gate 20 that electric charge continues, therefore just always constantly being enhanced by rank barrier height of insulating barrier 29 also set up a reverse electric field E, so with regard to the more effective impact charge carrier 80a that wants to enter floating gate 20 that keeps out.Reverse electric field E like this can be expressed as generally

E＝(Q _FG-Q _{FG_fb})/(T _insulatorC _total)

Wherein

T _InsulatorBe the thickness of insulating barrier 29;

Stopping can rank barrier height Φ _h, impacting the valency electricity band energy rank barrier height of in insulating barrier 29, being seen in the hole exactly, can be expressed as

Φ _h＝q(Q _FG-Q _{FG_fb})/C _total-ΔK _h

Wherein

Δ K _hBe holoe carrier kinetic energy 92 with insulating barrier 29 at the interface can rank barrier height poor 92a, the initial kinetic energy in the time of also can being considered as holoe carrier 80a and just having entered insulating barrier 29; And

Q is the quantity of electric charge of an electronics.

Therefore, work as Φ _hWhen being lower than zero, Δ K just _hGreater than q (Q _FG-Q _{FG_fb})/C _TotalThe time, the impact hole can be transmitted and be passed through insulating barrier 29, and reverse electric field roughly can be ignored for the influence that the impact electric charge that comes is caused.Along with the carrying out that radiation continues, Φ _hCan equal zero, just Δ K _hEqual q (Q _FG-Q _{FG_fb})/C _Total, the influence that reverse electric field is caused for the impact electric charge that comes just begins to occur.When more lasting the carrying out of radiation, impacting the valency electricity band that holoe carrier seen in insulating barrier 29 can just begin to form by rank barrier height 71a, and, along with electric charge by floating gate 20 collect many more, the height that its valency electricity band can rank barrier height 71a is just high more.Will increase the quantity of the impact charge carrier 80a that can equal to come at last fast so can be contemplated that the quantity of the charge carrier 80c that bounce-back is gone back.Also therefore, reduce the charge carrier quantity that can participate in the Fowler-Nordheim tunnel, also reduced the holoe carrier 80d quantity that has arrived floating gate 20.This mechanism has more highlighted and has suppressed the voltage effects that electric charge is sent to floating gate 20.

When radiating the data of erasing memory element with the impact electric charge, aforesaid two kinds of effects all constitute self limit radiation mechanism simultaneously.Erasing incipient the time, as long as impacting that holoe carrier can stride across can rank barrier height 71, such holoe carrier just allows by insulating barrier 29, arrives at floating gate 20 then.Along with the carrying out of erasing, hole charge will be deposited in floating gate 20 gradually, and in case the voltage of floating gate 20 being raised slowly just then is high to certain value V _{FG_E}The time, will produce one new can rank barrier height 71a, and stoped all follow-up impact holoe carriers of coming, make them can't arrive floating gate 20.Like this, along with the mechanism generation of self limit, erase and just finish, thereby finished whole flow process of erasing.

Erase finish in, the total charge dosage in floating gate 20 can be estimated with following simple formula:

Q _FG＝C _total(V _{FG_E}-V _{FG_i})

Total charge dosage also can be estimated with another simple formula:

Q _FG＝C _{FG_fb}+(C _total/q)*ΔK _h

Hence one can see that, and after the flow process of erasing finished, the total charge dosage that is deposited in the floating gate 20 depended on two main parameters.First parameter is impacted 80a specific energy rank, hole barrier height 71 additional additional energy 92a exactly.Because this additional energy 92a can see through tunnel grid 10 and follow the voltage difference of the second portion 17 of control gate 15 to determine, so as long as 15 bias value is followed in suitable selection or control area 10, that just can determine to leave in the total charge dosage of floating gate 20.Total capacitance C _TotalCan see through the effect that element design is assisted or reinforcement is such as a fine setting parameter.For example, bigger total capacitance C _TotalWith causing the bias value that needs a less zone 10 to follow between 15, radiate the equivalent electric charge to floating gate 20.The parameter of the total charge dosage of second decision in the floating gate relates to and causes the required floating gate electric weight of insulating barrier 29 flat rubber belting states (flat band condition).And such electric weight is determined by memory component all electrode and corresponding coupling capacitance.Therefore, as long as selected one group of such parameter, erasing memory element to a specific state accurately just.Q _FGWith Δ K _hLinear relationship between (additional energy 92a just) more makes the memory component of the present invention can be by accurately to a specific state.And these effects can prevent in the prior art, the problem that non-volatile memory component is excessively erased easily.

Can understand for the personage who is familiar with this technical field, more than for the description of self-limiting mechanism, no matter the charge carrier that is used is just or negative, all be feasible haply.Certain, the hole also can be selected and carry out the sequencing action, and electronics also can select the action of erasing.

3, manufacture method

Fig. 5 A has shown the top view of a matrix 50.Matrix 50 can be selected first conductivity type generally known (below select the P type for use) silicon for use.First semiconductor layer 40 of first conductivity type, its doping content is higher than the doping content of matrix 50, is formed on the matrix 50, shown in Fig. 5 B.First semiconductor layer 40 will be placed memory component as the memory wellblock, and the technology that it can be familiar with many industries in the method for 50 li formation of matrix for example, is gone into doping impurity in the matrix 50 and formed.The Chief Technology Officer that first semiconductor layer or semiconductor wellblock 40 also can be familiar with industry is on matrix 50, for example, with epitaxial deposition (epitaxial deposition) (just a kind of chemical vapour deposition (CVD) (chemical vapor deposition, CVD)) method.Epitaxial deposition method can deposit on matrix 50 and form the monocrystalline silicon that one deck mixes in advance.Afterwards, heavily doped first district 25 of second conductivity type (below select the N type for use) is formed between the matrix 50 and first semiconductor layer 40, the technology that the method for formation can be familiar with any industry, such as implanting ions (ion implantation).Though do not show on the figure,, before implanting ions, can select a photoresist layer for use, be used as light shield, define one or a plurality of first district 25, the zone that will implant as ion.First district 25 has like this formed the buried source polar curve of memory array, and the source area 24 of each memory component is connected to one first district at least.First district 25 can major part be seated in the matrix 50, or is seated in first semiconductor layer 40.Also can half be seated in the matrix 50, second half is seated in first semiconductor layer 40.Form buried source polar curve 25 (being exactly first district) and the order that forms semiconductor wellblock 40 (being exactly first semiconductor layer), also can exchange mutually.

After semiconductor wellblock 40 formed with buried source polar curve 25, the heavily doped strip region of N type and then formed.Such strip region towards a direction (hereinafter referred to as the Y direction), be the drain line 23 as memory array basically, and the drain region 22 of each memory component all is connected to a drain line 23 at least roughly.Strip region can be made of the technology that general industry is familiar with, and for example, little shadow (photo-lithography) adds implanting ions.For example.The strip region of N type like this, photoresist (photo-resistant) material of selecting for use that can be earlier suitable is coated on the silicon face, then, and with (masking) mode of shielding, optionally remove photoresist, and then form a plurality of strip openings towards first direction.Then, select N type impurity (N-typeimpurity) (such as arsenic for use, Arsenic), with general implanting ions technology, under the condition of low-yield (such as 5keV) and highly doped (such as 5E15cm-3), the silicon face that is not covered with for photoresist carries out cloth plants, and then has formed drain line 23.Then, remove photoresist, then, (such as boron, boron) concentration is that (such as 1E14cm-3) forms field reversal terminator (field-inversion stopper region) 26 under the medium or light degree approximately with p type impurity (P-type impurity).The maximum concentration point of field reversal terminator 26 preferably falls near the silicon face, and should be than the drain region 22 of drain line 23 shallow.Now, substrate 51 just has the drain region 22 and the field reversal terminator 26 of staggered strip.The drain region 22 of strip has defined the active region 4 of each memory component, and the field reversal terminator 26 of strip has then defined and has been used for the isolated district 5 of memory component of isolated different lines.The width of drain line 23 and line-spacing each other can be can accomplish minimum feature and line-spacing in the micro-photographing process.Then, with general oxidizing process or sedimentation (CVD for example), form an oxide layer 30 (can be 500-1, the silica of 000 dust).Such structure is shown in Fig. 6 A to Fig. 9 A.

Photoresist layer 7 then is formed on the insulating barrier 30, the subregion of optionally removing the photoresist layer then with a light shield, on photoresist layer 7, define a plurality of circular opens (opening) 32a, wherein expose the surface of insulating barrier 30.Each row at opening 32a place are preferably followed the central alignment of each drain line 23.And then carry out the oxide etching step one, remove 7 partial insulative layer that does not cover 30 of photoresist layer.Then with same photoresist layer 7 as etch mask, carry out silicon etch steps, a plurality of grooves 32 of formation in substrate 51.The operable general known etching (reactive ion etching (reactive ion etch, RIE)) for example, of silicon etch steps.Therefore, the pattern of photoresist upper shed 32a just duplicate or the substrate of videoing on go, and defined the pattern of groove opening 32b.Because the characteristic of dry ecthing, photoresist opening 32a is the same with groove opening 32b haply, the overlapping that their border roughly can be mutual.The carrying out that the action of etching substrate continues is in order to the degree of depth of definition groove 32.Groove 32 is dark in being enough to pass memory wellblock 40, forms a channel bottom 33 then and is parked in the buried source polar region 25.In this step because the characteristic of dry ecthing, the original photoresist opening 32a on the photoresist layer 7 may be extended Δ W, become photoresist opening 32c.When photoresist layer 7 also in, can carry out a processing procedure of automatically aiming at (self-align), N type impurity (such as arsenic) implanting ions is carried out in the sidewall 31 and the bottom 33 of groove 32.Suitable angled ion cloth is planted, and just can be used for forming the drain region 22 around groove opening 32b, so just formed self-aligning drain region 22.Such benefit is, even if the central point of groove opening 32b, because the skew on the processing procedure with the justified of drain line 23, can not determine that the drain region 22 of each memory component all is bound to be connected to the drain line 23 of memory array yet.Near the low-angle implanting ions zone the sidewall 31 of groove 32 that can be used for mixing, and then adjust the critical voltage (threshold voltage) of channel region 21 in the memory component.Such structure is shown in Fig. 6 B to Fig. 9 B.Trenched side-wall 31 can be as memory component 100a, and is vertical completely with silicon face, or as memory component 100b, with silicon face some a little inclinations arranged.In Fig. 6 B, what groove opening 32b showed is circular, still, also can be other kind of pattern (such as square or rectangle), and this depends on photoresist pattern 32a.

Remaining photoresist layer 7 just causes the resist method with general delustering and removes.Then, structurally, form a high-quality liner oxidation (liner oxide) layer 28.Lining oxide layer 28 in this is contiguous to the part of trenched side-wall 31, as a channel insulation thing 45, corresponds to memory component of the present invention, is exactly the second portion of first insulating barrier 45 wherein.Interior lining oxide layer 28 is thermal oxidation method silica, or the HTO silica, and its thickness can about 80 to 200 dusts.In this same step, interior lining oxide layer 28 also can be formed on insulating oxide 30 above.Then, with general known processing procedure, such as low pressure (low pressure) CVD, on interior lining oxide layer 28, form a polysilicon layer 19.This polysilicon layer 19 can be with regard to built-in doping (in-Situ) or mix with implanting ions subsequently in the process of deposition.The thickness of polysilicon layer 19 need fill up groove 32 completely, and possible thickness is between 400 to 2000 dusts, and end is seen the size of groove and process technique and decided.The structure of this moment is shown in Fig. 6 C in Fig. 9 C.

Then, optionally remove polysilicon layer 19, only stay and be positioned at groove 32 or near polysilicon.Preferable structure is that the polysilicon surface 19a that exposes follows the surface of the interior lining oxide layer 28 on the insulating oxide 30 to trim.The processing procedure of implementing, can use cmp (chemical-mechanical polishing earlier, CMP) polish the surface of polysilicon layer 19, then, with RIE processing procedure optionally, as stopping layer (a stop layer), remove polysilicon partly with interior lining oxide layer 28 or insulating oxide 30.If, thoroughly remove the polysilicon on the lining oxide layer 28 in may remaining in, can implement one and cross etching (over-etch) step.So polysilicon layer 19 has just only stayed block polysilicon in groove 32 after going through processing procedure, aim at groove opening automatically.Certainly, the technology that does not line up that is to say to have other little shadow and etch process, defines polysilicon layer, also can reach same purpose.Generally speaking self-aligning technology is to select preferably, because can reach smaller component size.Polysilicon in the groove 32 is the floating gate 20 that is used for being used as memory component.The structure of this moment is shown in Fig. 6 D to Fig. 9 D.

Then, on the floating gate 20 of polysilicon, form a high-quality zoneofoxidation 29, thickness is between 50 to 2000 dusts.Oxide layer in this zoneofoxidation is preferably in the mode of thermal oxidation, the oxide that grows up on the polysilicon (floating gate 20) that exposes.Zoneofoxidation 29 is connected together with oxide layer 28, has constituted the insulating barrier of a whole layer, whole cover floating gate 20 around with the top.Another can be used for forming the method selection of high quality oxide, is with general deposition technique (for example, LPCVD).Afterwards, with general deposition technique, form a polysilicon layer 14, about 1000 to 2000 dusts of thickness are on total.This polysilicon layer 14 can be P type (such as boron) heavy doping.The mode of mixing can be used implanting ions or built-in technology.Then, form an insulating barrier 35, about 40 to 100 dusts are on polysilicon layer 14.The structure of this moment is shown in Fig. 6 E to Fig. 9 E.

Then, on total, form along many photoresist bars of second direction (directions X or line direction) with one micro-photographing process.Then, between the photoresist bar, the insulating barrier 35 and polysilicon layer 14 under the bar area 18a that is covered by the photoresist bar not is just with general etch process removal, shown in Fig. 6 F.And the insulating barrier 35 under the photoresist bar position just still keeps with polysilicon layer 14.Left polysilicon layer 14 has just become many control grid line 18.The center line of each bar control grid line 18 is preferably followed the central point alignment of the groove 32 of delegation.It is little that the live width of control grid line 18 and line-spacing can be tried one's best, and end is seen the limit of micro-photographing process.Then, the photoresist bar method that just causes resist generally to deluster is removed.The structure of this moment is shown in Fig. 6 F to Fig. 9 F, wherein, and control grid line 18 and the staggered appearance of bar area 18a.

Then, the 4th insulating barrier 12 (such as silicon nitride) of formation one thicker relatively (about 1500 dusts) is on total.Then, on total, form along many photoresist bars of first direction (Y direction or column direction) with one micro-photographing process.Then, between the photoresist bar, the 4th insulating barrier 12 and the insulating barrier 35 under the bar area that is covered by the photoresist bar not, just remove with general etch process, therefore formed hemisection chase bar (semi-recessed trenchstripe) 11a, shown in Fig. 6 G along Y or column direction.And the 4th insulating barrier 12 under the photoresist bar position and insulating barrier 35 just still keep.The 4th left insulating barrier 12 has just become many silicon nitride line 11.It is little that the live width of silicon nitride line 11 and line-spacing can be tried one's best, and end is seen the limit of micro-photographing process.Then, the photoresist bar method that just causes resist generally to deluster is removed.The structure of this moment is shown in Fig. 6 G to Fig. 9 G, wherein, and silicon nitride line 11 and the staggered appearance of hemisection chase bar 11a.

Then can optionally, carry out the silicon etch process one with general anisotropic (anisotropic) etching technique.For control grid line 18, this road silicon etch process has been removed the part surface zone of control grid line 18, on the control grid line 18 between the silicon nitride line 11, has stayed oblique cone shape (taper) or concave surface.Therefore, be exposed to the second portion 17 that control grid line 18 among the hemisection chase bar 11a has just formed control grid line 18, and be positioned at the first 16 that control grid line 18 under the silicon nitride line 11 has just formed control grid line 18.First 16 all links together with second portion 17.And also as can be seen, control grid line 18 is across crossing active region 4 and isolated district 5, linked in the active region 4 memory component with the memory component in another active region 4.

Then, on exposed control grid line 18, formation one is the insulating barrier 34 of thin (about 40 to 100 dusts) relatively.The present invention for embodiment in, this insulating barrier 34 is that the oxygen ratio is about a silicon oxynitride layer of 82%.The method that forms for example, can use thermal oxidation method (thermal oxidation) then and then with hot nitriding (thermalnitridation) earlier.Known technology has downstream electrical slurry nitriding (Remote-Plasma-Nitridation) etc. at present, can be used for forming the insulating barrier 34 that coats exposed part any in the control grid line 18.Insulating barrier 34 links together with 35, has formed a whole insulating barrier, covers the upper surface of control grid line 18.The structure of this moment is shown in Fig. 6 H to Fig. 9 H.

Then, in the total top, form a polysilicon layer 8.This polysilicon layer 8 can be P type (such as boron) heavy doping.Deposition and the method that forms can be used general LPCVD.The mode of mixing can be used implanting ions or built-in technology.Polysilicon layer 8 thickness need to fill up hemisection chase bar 11a completely, can be 400 to 2000 dusts approximately, decide with the processing procedure ability on the width of hemisection chase bar 11a.Polysilicon layer 8 then is flattened (planarize), and etch-back (etch-back) makes polysilicon surface 8a preferably trim with the surface of silicon nitride line 11 then.Actual processing procedure can be to carry out planarization with CMP, carries out etch-back with RIE then, and silicon nitride line 11 is treated as etch stop layer.If will thoroughly remove the polysilicon that may remain on the silicon nitride line 11, can carry out one more and cross etching step.Therefore, polysilicon layer 8 only can remain among the hemisection chase bar 11a, and has formed the polysilicon lines 9 that is prolonging first (Y) direction.Each polysilicon lines 9 has linked the tunnel grid 10 that are positioned at the same memory component that lists.The structure of this moment is shown in Fig. 6 I to Fig. 9 I.

Then, with general metal silicide (silicide) formation method, can exposed polysilicon lines 9 surfaces be formed and aim at metal silicide automatically.For example, structurally deposit earlier a metal level (can be tungsten (tungsten), cobalt (cobalt), titanium (titanium), nickel (nickel), platinum (platinum) or molybdenum (molybdenum)), annealing (anneal) just can form the conductive layer that alloy silicon 38 constitutes so that metal can flow and infiltrate the top exposed part of polysilicon lines 9 then.Alloy silicon 38 can be called automatic aligning alloy silicon (selfaligned silicide, salicide) because its is aimed at polysilicon lines 9 and any exposed silicon face (may be the source transistor drain region) automatically.Unnecessary metal can remove with general metal etch process, and the structure that forms is shown in Fig. 6 J to Fig. 9 J.

Total can then be carried out back segment (backend) processing procedure.Back-end process may include and forms insulant (BPTEOS for example) and cover total, form the contact hole and come the electrode of suitable electrical connection memory component, insert metal in the contact hole and form metal wire to connect as the circuit of needs.At last, can on total, form sheath (passivation), and form weld pad (bondingpad) in needed position.

The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.

For example, though manufacture method of being mentioned or memory component are to use the polysilicon of an amount of doping to be used as the control gate and the tunnel grid of memory component before, but, should understand for the personage who is familiar with this technical field, any electric conducting material all should use.So, " conduction " thing in the scope that claims defined has been contained all materials that can conduct electricity, such as polysilicon, polysilicon metal (polycide), aluminium (aluminum) molybdenum (molybdenum) copper (copper) titanium nitride (titaniumnitride) and tantalum nitride (tantalum nitride) or the like.And, any suitable insulant, for example aluminium oxide (aluminum oxide), hafnium oxide (hafnium oxide), zirconium nitride (zirconium nitride) and tantalum pentoxide (tantalumpentoxide) etc. all may be used for replacing silica, silicon oxynitride or silicon nitride.In addition, material behavior is with silica or the different material of polysilicon, also may be used for replacing silicon nitride.In addition, shown in the scope that claims defined, be not that steps all in the method item is limited at and must carries out according to listed order fully, but can carry out, as long as can produce memory component among the present invention with any order.Control grid line, tunnel grid line, drain line and buried source polar curve are not limited to a fixing width or a shape, if do not limit a straight line yet, it must be rectangle that their profile does not limit yet, but any size or shape, as long as it is all right with the memory component that lists effectively to link row.It is rectangle that the profile of floating gate does not limit, it is circular that the top view of floating gate does not limit yet, its profile or top view can be any size or shape, as long as can effectively deposit electric charge and effectively control the connection of drain region and source area just passable.In addition, the upper surface of floating gate does not limit and will trim with substrate surface, floating gate also can be higher than or be lower than substrate surface, as long as can effectively be deposited electric charge, effectively to be coupled, effectively to control the connection of drain region and source area with control gate just passable.In addition, the bottom of floating gate does not limit and will be arranged in the buried source polar region, also can be in matrix, as long as floating gate can effectively be deposited electric charge, effectively to be coupled, effectively to control the connection of drain region and source area with control gate just passable.In addition, source area and drain region, source electrode line and drain line can be exchanged.Though, matrix among the figure is uniform doping, but should understand for the personage who is familiar with this technical field, the formed all doped regions of matrix (source area, drain region, channel region and memory wellblock 40 etc.) also can be formed in one or the wellblock of a plurality of conductivity types that are different from the memory wellblock.In addition, if tunnel insulation layer, trench dielectric layer, pin down insulating barrier and do not limit silica, silicon nitride or silicon oxynitride, also can be with any appropriate insulation thing, such as aluminium oxide, hafnium oxide, zirconium nitride and tantalum pentoxide etc., or can be any composite bed, for example, silicon oxide layer with the combination of alumina layer or with silicon oxide layer with the combination of zirconia layer etc.At last, isolated district is not limited to a fixing width or a shape, if do not limit a straight line yet, do not limit and to be constituted with field oxide (STI or LOCOS), do not limit and will be constituted to connect the isolated technology of face, but any isolated framework that can effectively separate the active region of the memory component that is positioned at different lines.

Being simply described as follows of symbol in the accompanying drawing:

1～3: memory component

4: active region

5: isolated district

7: the photoresist layer

8: polysilicon layer

9: polysilicon lines

10: the tunnel grid

11: the silicon nitride line

11a: hemisection chase bar

12: the four insulating barriers

13: the hemisection groove

14: polysilicon layer

15: control gate

16: first

17: second portion

18: the control grid line

18a: bar area

19: polysilicon layer

20: floating gate

21: channel region

22: drain region, second heavily doped region

23: drain line

24: source area, first heavily doped region

25: the first districts, buried source polar curve

26: the field reversal terminator

28: interior lining oxide layer

29: the second insulating barriers

30: insulating barrier

31: trenched side-wall

32: groove

32a: opening

32b: groove opening

32c: photoresist opening

33: channel bottom

34: second portion

35: first

36: the three insulating barriers

38: alloy silicon

40: memory wellblock, semiconductor layer

43: first

44: the first insulating barriers

45: second portion, channel insulation thing

50: matrix

51: substrate

52: the grid region, tunnel

56: tunnel insulation layer

59: can rank barrier height

60: can rank barrier height

62: impact and transmit the grid region

67: pin down insulating barrier

68: conductive strips

69: valency electricity band

70: can rank barrier height

70a: can rank barrier height

70b: distance

71: can rank barrier height

71a: can rank barrier height

71b: distance

72: the floating gate polar region

76: electronics

80: the hole

82: contrary tunneling electron charge carrier

83: the conductive strips electronics

90: kinetic energy

90a: additional energy

92: kinetic energy

92a: additional energy

100a～100e: memory component

100f: memory array

Claims

1, a kind of read-only memory element of erasing with programmable is characterized in that described read-only memory element includes:

One matrix;

The semiconductor of one ground floor in this matrix top, has one first conductivity type;

One first district is formed between this matrix and this ground floor, has one second conductivity type;

One channel shaped is formed in a surface of this ground floor, has a sidewall and a bottom;

One second district is formed in this ground floor, and side direction is adjacent to a first half of this groove, has this second conductivity type;

One channel region is in this ground floor, and between this first district and this second district, this sidewall that is prolonging this groove forms;

The floating gate of one conduction is adjacent to this channel region, and insulate mutually with this channel region;

The control gate of one conduction, a part wherein places on this floating gate, and insulate mutually with this floating gate; And

The tunnel grid of one conduction place on the part of this control gate, and insulate mutually with this control gate.

2, can erase according to claim 1 read-only memory element with programmable is characterized in that:

This sidewall of this groove and this ground floor surperficial perpendicular, and this bottom of this groove parallels with this surface of this ground floor.

3, can erase according to claim 1 read-only memory element with programmable is characterized in that:

This groove passes this second district and this ground floor, and this bottom of this groove is formed in this first district.

4, can erase according to claim 1 read-only memory element with programmable is characterized in that:

This groove passes this second district, this ground floor and this first district, and this bottom of this groove is formed in this matrix.

5, can erase according to claim 1 read-only memory element with programmable is characterized in that:

Other includes one first insulating barrier, has a first, is located on the surface of this second district and this ground floor, and a second portion, and go up this bottom of being located at this groove and side direction is attached at this sidewall of this groove.

6, can erase according to claim 1 read-only memory element with programmable is characterized in that:

This control gate and this tunnel grid overlap in an overlapping district mutually; And

7, can erase according to claim 1 read-only memory element with programmable is characterized in that this control gate has:

One first is on the part of being located at this second district at least of insulation and the surface of this ground floor; And

One second portion is on the surface of being located at this floating gate of insulation.

8, the read-only memory element as erasing as described in the claim 7 with programmable is characterized in that:

Other includes an insulating barrier between these tunnel grid and this control gate, and this insulating barrier has a thickness, is enough to allow that quantum-mechanical tunneling electron passes through.

9, the read-only memory element as erasing as described in the claim 8 with programmable is characterized in that:

This insulating barrier is a silicon oxynitride layer, and wherein, the ratio of oxygen is between 70% to 90%.

10, the read-only memory element as erasing as described in the claim 8 with programmable is characterized in that:

This control gate is a metal, the Fermi level of its work function be positioned at this insulating barrier can interband every central authorities.

11, can erase according to claim 1 read-only memory element with programmable is characterized in that:

The part of this control gate has allows that impacting electric charge penetrates a thickness in the past.

12, can erase according to claim 1 read-only memory element with programmable is characterized in that:

These tunnel grid are the heavily doped semiconductor substance of a P type.

13, can erase according to claim 1 read-only memory element with programmable is characterized in that:

This control gate is the heavily doped semiconductor substance of a P type.

14, the read-only memory element array that can erase with programmable is characterized in that including:

One matrix;

A plurality of isolated district separately is formed in this ground floor, is parallel to each other, and extends a first direction, and per two adjacent isolated intervals have an active region; And

A plurality of drain lines separately extend this first direction, and each drain line is formed at the part of this active region at least, and is adjacent to this surface of this ground floor;

Each active region has a plurality of memory elements, and each memory element includes:

One groove is formed at a surface of this ground floor, has a sidewall and a bottom;

The tunnel grid of one conduction are located on the part of this control gate, and are insulated mutually with this control gate.

15, the read-only memory element array as erasing as described in the claim 14 with programmable is characterized in that including in addition:

A plurality of grooves are lined up the matrix with a plurality of row and row, and these row extend this first direction, and this row extends a second direction, and this second direction is vertical with this first direction.

16, the read-only memory element array as erasing as described in the claim 14 with programmable is characterized in that including in addition:

Separate and parallel a plurality of control grid lines, every control grid line extends a second direction vertical with this first direction, strides across this active region and should completely cut off the district, and be electrically connected to a plurality of control gates of this memory element.

17, the read-only memory element array as erasing as described in the claim 14 with programmable is characterized in that including in addition:

18, the read-only memory element array as erasing as described in the claim 14 with programmable is characterized in that:

For each memory element, this control gate and this tunnel grid overlap in an overlapping district mutually; And

19, the read-only memory element array as erasing as described in the claim 14 with programmable is characterized in that:

This second district is electrically connected to the part of one of this drain line at least.

20, the read-only memory element array as erasing as described in the claim 14 with programmable is characterized in that including in addition:

21, the read-only memory element array as erasing as described in the claim 14 with programmable is characterized in that:

For each memory element, this groove passes this second district and this ground floor, and this bottom of this groove is formed in this first district.

22, a kind of method that can erase with the read-only memory element of programmable that forms is characterized in that including the following step:

Form the semiconductor of a ground floor,, have one first conductivity type in matrix top;

Form one first district, between this matrix and this ground floor, have one second conductivity type;

Form a groove,, have a sidewall and a bottom in a surface of this ground floor;

Form one second district, in this ground floor, side direction is adjacent to a first half of this groove, has this second conductivity type;

Form a channel region, in this ground floor, between this first district and this second district, prolonging this sidewall of this groove;

Form the floating gate of a conduction, be adjacent to this channel region, and insulate mutually with this channel region;

Form the control gate of a conduction, its part places on this floating gate, and insulate mutually with this floating gate; And

Form the tunnel grid of a conduction, on the part of this control gate, and insulate mutually with this control gate.

23, as can erase method with the read-only memory element of programmable of formation one as described in the claim 22, it is characterized in that:

24, as can erase method with the read-only memory element of programmable of formation one as described in the claim 22, it is characterized in that:

25, as can erase method with the read-only memory element of programmable of formation one as described in the claim 22, it is characterized in that:

26, as can erase method with the read-only memory element of programmable of formation one as described in the claim 22, it is characterized in that this control gate has:

27, as can erase method with the read-only memory element of programmable of formation one as described in the claim 26, it is characterized in that:

Other includes formation one insulating barrier between these tunnel grid and this control gate, and this insulating barrier has a thickness, is enough to allow that quantum-mechanical tunneling electron passes through.

28, as can erase method with the read-only memory element of programmable of formation one as described in the claim 27, it is characterized in that:

29, as can erase method with the read-only memory element of programmable of formation one as described in the claim 27, it is characterized in that:

30, as can erase method with the read-only memory element of programmable of formation one as described in the claim 22, it is characterized in that:

31, as can erase method with the read-only memory element of programmable of formation one as described in the claim 22, it is characterized in that:

These tunnel grid are the heavily doped semiconductor substance of a P type.

32, as can erase method with the read-only memory element of programmable of formation one as described in the claim 22, it is characterized in that:

This control gate is the heavily doped semiconductor substance of a P type.

33, a kind of method that can erase with the read-only memory element array of programmable that forms is characterized in that including:

In the semiconductor of a ground floor, form a plurality of isolated district separately, this ground floor has one first conductivity type in matrix top, and this isolated district is parallel to each other, and extends a first direction, and per two adjacent isolated intervals have an active region;

Form a plurality of drain lines separately, extend this first direction, each drain line is formed at the part of this active region at least, and is adjacent to this surface of this ground floor;

In the surface of this ground floor, form a plurality of grooves, be arranged in the array, the row of this array extend this first direction, and the row of this array extends a second direction vertical with this first direction, and each groove has a sidewall and a bottom;

Between this matrix and this ground floor, form a plurality of first districts, have one second conductivity type;

Form a plurality of second districts in this ground floor, each second district's side direction is adjacent to one of them the first half of this groove, has this second conductivity type;

Form a plurality of channel regions in this ground floor, each channel region is between one of one of this first district and this second district, and this sidewall that is prolonging one of this groove forms;

Form the floating gate of a plurality of conductions, the insulation of each floating gate be adjacent to this channel region one of them;

Form a plurality of conductive control grids, the insulation of the part of each control gate place this floating gate on one of them; And

Form a plurality of conductions tunnel grid, on the part of being located at this control gate of each tunnel gate insulation.

34, form the method that can erase with the read-only memory element array of programmable as claim 33, it is characterized in that including in addition:

Form and separate and parallel a plurality of control grid lines, every control grid line extends a second direction vertical with this first direction, strides across this active region and should completely cut off the district, and be electrically connected to this control gate partly.

35, form the method that can erase with the read-only memory element array of programmable as claim 33, it is characterized in that including in addition:

36, form the method that can erase with the read-only memory element array of programmable as claim 33, it is characterized in that:

The tunnel grid that each this control gate is corresponding with one overlap in an overlapping district mutually; And

37, form the method that can erase with the read-only memory element array of programmable as claim 33, it is characterized in that:

Each this second district is electrically connected to the part of one of this drain line at least.

38, form the method that can erase with the read-only memory element array of programmable as claim 33, it is characterized in that including in addition:

39, form the method that can erase with the read-only memory element array of programmable as claim 33, it is characterized in that:

Each groove passes this second district one of them and this ground floor, and this bottom of each groove is formed at this first district in one of them.

40, the method for operation that can erase with the read-only memory element of programmable is characterized in that described method of operation of erasing with the read-only memory element of programmable includes:

This element has the floating gate of a conduction, is formed in the groove of the semiconductor substrate with first conductivity type; The control gate of one conduction has a part of placing on this floating gate of insulating; The tunnel grid of one conduction across an insulating barrier, on the part that places this control gate of insulation, with the formation sandwich construction, thereby are allowed electronics and hole with a close speed, and the tunnel is by this insulating barrier; Separately source electrode and drain region are second conductivity type, this source area in abutting connection with but electrically isolate from a lower part of this floating gate, this drain region in abutting connection with but electrically isolate from a top of this floating gate; And a channel region, be formed in the wellblock with this first conductivity type between, extend a sidewall of this groove,

Give a positive voltage for this drain region, with the positive voltage that is coupled to this floating gate; And

Give this tunnel grid one voltage, this voltage is negative value with respect to a voltage of this control gate, and intensity is enough to make this tunnel grid electron radiation and radiates the hole from this control gate, and make this electronics and hole in close speed but rightabout mode, pass through this insulating barrier, and make this electronics have enough energy, pass through this control gate, impact the charge carrier transfer mechanism and see through, and then arrive this floating gate.

41, as can erase method of operation with the read-only memory element of programmable of claim 40, it is characterized in that including in addition:

Give this tunnel grid one voltage, this voltage with respect to a voltage of this control gate be on the occasion of, and intensity is enough to make grid radiation hole, this tunnel and from this control gate electron radiation, and make this electronics and hole in close speed but rightabout mode, pass through this insulating barrier, and make this electricity hole have enough energy, pass through this control gate, impact the charge carrier transfer mechanism and see through, and then arrive this floating gate.

42, the method for operation that can erase with the read-only memory element of programmable is characterized in that described method of operation of erasing with the read-only memory element of programmable includes:

This element has at least two states, and this element has a conductive floating gate, is formed in the groove of semiconductor substrate; The control gate of one conduction has a part of placing on this floating gate of insulating; The tunnel grid of one conduction see through an insulating barrier, on the part that places this control gate of insulation, with the formation sandwich construction, thereby allow electronics and hole with a close speed, and the tunnel is by this insulating barrier; Separately source electrode and drain region, in abutting connection with but electrically isolate from this floating gate; And a channel region, be defined between this source electrode and the drain region, electrically isolate from this floating gate,

Set up this element this state one of them, utilization is from this tunnel grid electron radiation and from this control gate radiation hole, so that but this electronics and hole are in close speed rightabout mode, pass through this insulating barrier, and make this electronics have enough energy, pass through this control gate, impact the charge carrier transfer mechanism and see through, and then arrive this floating gate; And

Wherein another of this state of setting up this element, utilization is from this grid radiation hole, tunnel and from this control gate electron radiation, so that but this electronics and hole are in close speed rightabout mode, pass through this insulating barrier, and make this hole have enough energy, pass through this control gate, impact the charge carrier transfer mechanism and see through, and then arrive this floating gate.