CN100373625C

CN100373625C - Erasable and programmable read-only memory element and producing and operating method

Info

Publication number: CN100373625C
Application number: CNB2004100967406A
Authority: CN
Inventors: 王知行
Original assignee: Individual
Current assignee: Individual
Priority date: 2004-12-03
Filing date: 2004-12-03
Publication date: 2008-03-05
Anticipated expiration: 2024-12-03
Also published as: CN1783500A

Abstract

The present invention relates to an erasable and programmable read-only memory element and a producing and operating method. A semiconductor at a first layer is provided with a first conductive type above a base body; a first region is formed between the base body and the first layer and is provided with a second conductive type. A groove is formed on the surface of the first layer and is provided with a side wall and a bottom part. A second region formed in the first layer is in sideways and adjacent connection with the upper-semi part of the groove and is provided with the second conductive type. A channel region approximately extending along the side wall of the channel is formed between the first region and the second region in the first layer. A conductive floating grid is in adjacent connection with the channel region and is insulated from the channel region; a conductive control grid, part of which is arranged on the floating grid, is insulated from the floating grid; a conductive tunnel grid is arranged on part of the control grid and is insulated from the control grid. The obvious effect is that the present invention does not need a high-voltage generation basic structure in the prior technique.

Description

Erasable and programmable read-only memory element and manufacturing and operating method

Technical Field

The present invention relates to a nonvolatile memory, and more particularly, to an Electrically Programmable Read Only Memory (EPROM) and an Electrically Erasable and Programmable Read Only Memory (EEPROM) device. More particularly, the present invention relates to the architecture of memory cells, methods of forming memory cells, and non-volatile memory arrays having floating gates. The invention relates to an erasable and programmable read-only memory element, a manufacturing method of the element and an operation method of the element.

Background

The use of floating gates as charge storing nonvolatile memory cells and related memory arrays is now well known in the art. Basically, memory cells are electrically erased or programmed by sending electrons into or out of a floating gate. The floating gate is electrically insulated from the surrounding electrodes, but has a capacitive coupling effect with the surrounding electrodes. The amount of charge remaining in the floating gate determines the state of the memory cell. Generally, a defined state may have only two states or more states (multi-state storage). In structural distinction, presently known memory cells may be of the split gate (split gate) type, the stacked gate type, or a combination thereof.

In today's non-volatile memories, it is common to operate with high voltages (typically 9 to 20 volts) in order to achieve the desired memory state. Therefore, high-voltage in-chip infrastructure (high-voltage in-chip) is very important for supporting the operation of memory devices, and these structures are also an important part of non-volatile memories and their products. The high voltage generation infrastructure includes separate arrays of high voltage transistors that typically require 5 additional masks in processing in addition to the typical CMOS process. Therefore, the high voltage generation infrastructure complicates the process technology of the non-volatile memory.

Another problem with high voltage generating infrastructures is that they are difficult to scale down with technology evolution. The high voltage results in a difficult device size reduction due to the physical principles employed by the memory device. In contrast, the operating voltage of logic circuits has been decreasing since the past decades, with the attendant reduction in minimum size in CMOS process technology. Therefore, it is expected that the difference between the operating voltage of the logic circuit and the operating voltage of the memory device will increase. This problem is exacerbated as CMOS processes enter the 0.25 micron (micrometer) era, becoming more significant. Therefore, in the new generation of memory products, whether embedded or standard, nonvolatile memory products, a fixed cost is often observed, i.e., the high voltage circuits occupy a large chip area. The size reduction limitations caused by high voltages also limit the minimum feature size (minimum feature size) of high voltage transistors. It is often found that the next generation of products directly follows the design rule (design rule) of the high voltage transistors of the previous generation. In addition, high voltage operation also causes problems with the functionality and reliability of the product.

Us 5,780,341 attempts to solve the above problem by introducing a stepped channel/drain structure in a split gate or stacked gate device. Wherein the electron charges enter the floating gate by channel hot electron (channel hot electron) or source-side injection (SSI) mechanism. The charge in the floating gate is driven off the floating gate by Fowler-Nordheim tunneling mechanism. However, these mechanisms require high voltages to maintain operation. The stepped channel/drain structure indeed improves the efficiency of charge ejection. However, even so, voltages as high as 10 volts are required to maintain the device in operation. Such high voltages are believed to require tight control of the quality of the insulator surrounding the floating gate. Therefore, such a structure is easily damaged by process factors and also easily causes a problem in reliability.

U.S. patent No. 6,372,617 seeks to reduce the need for high voltages by forming a floating gate in a recessed structure and forming a polysilicon (polysilicon) spacer over the edge of that floating gate. The floating gate structure can greatly improve the capacitance coupling between the control gate and the floating gate. There are other techniques for increasing the surface area of a concave floating gate by forming hemispherical-grained polysilicon (polysilicon) on the floating gate. The operating voltage may be reduced to approximately 16 volts or so. See "A Low Voltage Operation Flahs Cell with high connected routing Using traveling Gate with HSG" by Kitamura T. et al, published in 1998, the paper of the VLSI technical workshop (Symposium on VLSI technology dig. technical Papers), pages 104 to 105. However, the formation of polysilicon spacers (spacers) over recessed floating gates adds complexity to the process. In addition, the surface height of the recessed floating gate varies greatly, which increases the difficulty of subsequent processes (such as the formation of word lines). All in all, it makes the production more cumbersome. In addition, the concave floating gate structure causes a large step at the edges of the floating gate. Such a drop increases the interference between the floating gate and the floating gate, and thus, is not favorable for reducing the device-to-device distance.

The requirement of high voltage for the device also limits the size reduction of the device itself. For example, in order to operate at high voltages, the gate length (gate length) or channel length (channel length) of the device must be long enough to prevent the drain-to-source punch-through (punch-through) phenomenon. This, in turn, creates a minimum limit for the size reduction of the device itself, i.e., the minimum channel length of the memory device can only be a certain value. As with the high voltage transistors, the problems encountered with such memory devices are exacerbated as the manufacturing processes move into the 0.25 micron era. This problem results in a minimum limit to the overall element height (i.e., the length of the element in the bit line direction) from the physical size of the element point of view.

Another major problem that occurs with the shrinking memory size is the thickness of the oxide that encases the floating gate. For a pure oxide layer, it has been proposed that the theoretical minimum thickness is between 5 and 6nm, which is sufficient to withstand leakage due to Fowler-Nordheim tunneling mechanism. Naruke is equivalent to "Stress induced leakage Current Limiting to Scale Down EEPROM Tunnel oxide Thick", 1922, IEDMtechnical Digest, pages 424 to 427. Moreover, additional leakage currents often occur after the dielectric layer is subjected to excessive voltage stress. Therefore, in order to maintain the same level of leakage current and charge in the floating gate to meet the specifications of the product, the thinnest oxide layer used has been reported to be about 8-9 nm thick for many generations of products. See "Flash Memories" by s.lai in 1998 IEDM Technical Digest, pages 971-973: where We Were and Where We Arego ". Such a requirement of minimum oxide thickness limits the reduction of the channel width of the device. Since the device requires at least a minimum read current, which is inversely proportional to the oxide thickness and directly proportional to the channel width. This problem results in a minimum limit to the overall element width (i.e., the length of the element in the direction of the word line) from the physical size of the element point of view.

The problems discussed above are often found in non-volatile memory devices that use a stacked gate EEPROM architecture, such as that of U.S. patent No. 4,957,877. There are many ways to overcome the difficulties encountered in achieving a smaller device size. For example, U.S. Pat. No. 5,146,426 discloses a memory device having a floating gate and a control gate formed in a trench (trench) that approximates a contact hole (contact hole), and U.S. Pat. nos. 5,432,739 and 5,563,083 disclose a memory device having a floating gate and a control gate formed along the sidewall of a pillar-shaped silicon region. These devices can achieve smaller device sizes than those fabricated by typical contemporary stacked gate EEPROM technology. Please see d.kuo, entitled "TEFET-a High sensitivity, Low Erase Voltage, Trench Flash EEPROM" written on pages 51-52 of Symposium on VLSI Technology dig. technical Papers, 1994; pein equals "Performance of the 3-D Sidewall flash EPROM Cell" on pages 11-14 of IEDM technical digest, 1993. However, these devices still require voltages of up to 12 volts or more to perform the data erase operation, which is still a drawback to be overcome. For example, the device of U.S. patent No. 5,146,426 uses a high-biased buried source (buried source) to perform the erase operation. The thinning of the gate dielectric near the corners of the trench may create a localized high electric field, thereby enhancing charge transport during erase operations. However, in spite of the above results, the operating voltage is still high and the quality of the oxide layer needs to be strictly controlled. In addition, for these devices, the graded source junction (junction) is very important in order to withstand high voltages. Such high voltage and buried source operation significantly limits the minimum spacing of the buried source, and thus, prevents further device size reduction. Such limitations also complicate the segmentation and block integration of the memory array, which unfortunately increases the overall area of the memory array and reduces the advantages of the reduced device size. Furthermore, in us 5,146,426, the bottom of the trench in each cell must be formed in the buried source and its depth must be tightly controlled in order for all cells to successfully perform the erase operation. Such stringent requirements are believed to create significant manufacturing difficulties. U.S. patent nos. 5,432,739 and 5,563,083 use cylindrical elements for small element size. Such devices must rely on the formation of a floating gate and the severe topography of the control gate because of the large number of polysilicon spacers used in their technology. In addition to the disadvantages of high voltage, the severe topography and the tight control of the process required for the formation of the polysilicon spacers complicate the process and also lead to manufacturing difficulties.

Disclosure of Invention

Accordingly, the present invention is directed to an improved EPROM and EEPROM memory device. The invention provides an erasable and programmable read-only memory element, and also provides a manufacturing and operating method of the erasable and programmable read-only memory element.

To achieve the object of the present invention, the present invention proposes an erasable and programmable Read Only Memory (ROM) element. A first layer of semiconductor is over a substrate and has a first conductivity type. A first region is formed between the substrate and the first layer and has a second conductivity type. A trench (trench) is formed in a surface of the first layer, having a sidewall and a bottom. A second region of the second conductivity type is formed in the first layer laterally adjacent to an upper half of the trench. A channel region is formed in the first layer between the first region and the second region substantially along the sidewall of the trench. A conductive floating gate (floating gate) is adjacent to and insulated from the channel region. A conductive control gate (control gate), a portion of which is disposed over and insulated from the floating gate. A conductive tunneling gate is disposed over a portion of the control gate and is insulated therefrom.

In the erasable and programmable read-only memory element of the present invention, the sidewall of the trench is substantially perpendicular to the surface of the first layer, and the bottom of the trench is substantially parallel to the surface of the first layer.

In the erasable and programmable read-only memory element of the present invention, the trench penetrates the second region and the first layer, and the bottom of the trench is formed in the first region.

In the erasable and programmable read-only memory element, the groove passes through the second area, the first layer and the first area, and the bottom of the groove is formed in the substrate.

The erasable and programmable read-only memory element further comprises a first insulating layer which is provided with a first part and a second part, wherein the first part is arranged on the second area and one surface of the first layer, and the second part is arranged on the bottom of the groove and is attached to the side wall of the groove in the lateral direction.

In the erasable and programmable read-only memory element of the invention, the control gate and the tunnel gate are mutually overlapped in an overlapping region; and

at least a portion of the floating gate is disposed below the overlap region.

The erasable and programmable read-only memory element of the invention is characterized in that the control gate is provided with:

a first portion substantially insulated from at least a portion of the second region and a surface of the first layer; and

a second portion is provided substantially insulated from a surface of the floating gate.

The erasable and programmable read-only memory element further comprises an insulating layer between the tunnel gate and the control gate, wherein the insulating layer has a thickness enough to allow quantum mechanical tunnel electrons to pass through.

The erasable and programmable read-only memory element is characterized in that the insulating layer is a silicon oxynitride layer, wherein the proportion of oxygen in nitrogen is between 70 and 90 percent.

In the erasable and programmable read-only memory element, the control gate is a metal, and the Fermi-level of the work function is approximately located at the center of the energy band gap of the insulating layer.

The invention relates to an erasable and programmable read-only memory element, wherein, a part of the control gate has a thickness allowing impact charge (ballisticcharge) to penetrate through.

In the erasable and programmable read-only memory element, the tunnel gate is a P-type heavily doped semiconductor substance.

In the erasable and programmable read-only memory element, the control grid is a P-type heavily doped semiconductor substance.

To achieve the object of the present invention, the present invention also provides an erasable and programmable Read Only Memory (ROM) device array. The array has a substrate (bulk material), a first layer of semiconductor, separate isolation regions, and separate drain lines. The first layer is over the substrate and has a first conductivity type. The isolation regions are formed in the first layer, are substantially parallel to each other, extend in a first direction, and each two adjacent isolation regions have an active region. The drain lines extend in the first direction, and each drain line is formed on at least a portion of the active region and adjacent to the surface of the first layer. Each active region has a plurality of storage elements. Each memory element includes a first region, a trench (trench), a second region, a channel region (channel region), a conductive floating gate (floating gate), a conductive control gate (control gate), and a conductive tunneling gate (tunneling gate). The first region is formed between the substrate and the first layer and has a second conductivity type. The trench is formed on a surface of the first layer and has a sidewall and a bottom. The second region is formed in the first layer laterally adjacent to an upper half of the trench and has the second conductivity type. The channel region is formed in the first layer between the first region and the second region substantially along the sidewall of the trench. The floating gate is adjacent to and insulated from the channel region. A portion of the control gate is disposed over and insulated from the floating gate. The tunnel gate is disposed over a portion of the control gate and is insulated from the control gate.

The erasable and programmable read-only memory element array of the invention further comprises:

the trenches are arranged in a matrix having a plurality of rows extending in the first direction and columns extending in a second direction substantially perpendicular to the first direction.

a plurality of spaced-apart and parallel control gate lines, each control gate line extending in a second direction substantially perpendicular to the first direction, crossing over the active region and the isolation region, and electrically connected to the control gates of the memory device.

and a plurality of separated and parallel tunnel grid lines, each tunnel grid line extending in the first direction and electrically connected to the plurality of tunnel grids of the memory element.

The erasable and programmable read-only memory element array of the invention, wherein, for each memory element, the control grid and the tunnel grid are mutually overlapped in an overlapping region; and

at least a portion of the floating gate is disposed below the overlap region.

The invention relates to an erasable and programmable read-only memory element array, wherein, the second area is electrically connected to at least one part of one of the drain lines.

a plurality of spaced apart and parallel source lines, each source line electrically connected to a plurality of first regions of the memory device.

The invention provides an array of erasable and programmable read-only memory elements, wherein, for each memory element, the trench passes through the second region and the first layer, and the bottom of the trench is formed in the first region.

To achieve the above objects, the present invention further provides a method of forming an erasable and programmable Read Only Memory (ROM) device. Comprises the following steps. A first layer of semiconductor is formed over a substrate having a first conductivity type. A first region of a second conductivity type is formed between the substrate and the first layer. A trench (trench) is formed on a surface of the first layer, having a sidewall and a bottom. A second region of the second conductivity type is formed in the first layer laterally adjacent to an upper portion of the trench. A channel region is formed in the first layer between the first region and the second region substantially along the sidewall of the trench. A conductive floating gate is formed adjacent to and insulated from the channel region. A conductive control gate (control gate) is formed, a portion of which is disposed over and insulated from the floating gate. A conductive tunneling gate is formed over a portion of the control gate and is insulated from the control gate.

The invention discloses a method for forming an erasable and programmable read-only memory element, wherein the side wall of the groove is approximately vertical to the surface of the first layer, and the bottom of the groove is approximately parallel to the surface of the first layer.

In the method of forming an erasable and programmable read-only memory element of the present invention, the trench penetrates the second region and the first layer, and the bottom of the trench is formed in the first region.

The invention discloses a method for forming an erasable and programmable read-only memory element, wherein the control grid and the tunnel grid are mutually overlapped in an overlapping region; and

at least a portion of the floating gate is disposed below the overlap region.

The invention discloses a method for forming an erasable and programmable read-only memory element, wherein, the control grid is provided with:

The method of forming an erasable and programmable read-only memory element further comprises forming an insulating layer between the tunnel gate and the control gate, wherein the insulating layer has a thickness sufficient to allow quantum mechanical tunnel electrons to pass through.

The invention discloses a method for forming an erasable and programmable read-only memory element, wherein the insulating layer is a silicon oxynitride layer, and the proportion of oxygen in nitrogen is between 70% and 90%.

The invention discloses a method for forming an erasable and programmable read-only memory element, wherein, the control gate is a metal, the Fermi-level of the work function (work function) is approximately positioned at the center of the energy band gap of the insulating layer.

The invention discloses a method for forming an erasable and programmable read-only memory element, wherein a part of a control gate has a thickness which allows impact charges to penetrate through.

The invention discloses a method for forming an erasable and programmable read-only memory element, wherein a tunnel gate is a P-type heavily doped semiconductor substance.

The invention discloses a method for forming an erasable and programmable read-only memory element, wherein a control grid is a P-type heavily doped semiconductor substance.

To achieve the above objects, the present invention further provides a method of forming an array of erasable and programmable Read Only Memory (ROM) elements. The method comprises the following steps. In a semiconductor of a first layer having a first conductivity type over a substrate, a plurality of spaced apart isolation regions are formed, the isolation regions extending substantially parallel to one another in a first direction, each two adjacent isolation regions having an active region. A plurality of separate drain lines are formed extending in the first direction, each drain line being formed in at least a portion of the active region and adjacent to the surface of the first layer. Trenches (trenches) are formed in the surface of the first layer and arranged in an array with columns extending in the first direction and rows extending in a second direction substantially perpendicular to the first direction, each trench having a sidewall and a bottom. A plurality of first regions of a second conductivity type are formed between the substrate and the first layer. A plurality of second regions of the second conductivity type are formed in the first layer, each second region being laterally adjacent to an upper half of one of the trenches. Channel regions are formed in the first layer, each channel region being between one of the first regions and one of the second regions, formed substantially along the sidewall of one of the trenches. A plurality of conductive floating gates (floating gates) are formed, each floating gate being insulatively adjacent to one of the channel regions. A plurality of conductive control gates (control gates) are formed, a portion of each control gate being disposed on one of the floating gates in an insulated manner. A plurality of conductive tunnel gates (tunneling gates) are formed, each of which is disposed over a portion of the control gate in an insulated manner.

The method of forming an array of erasable and programmable read-only memory elements of the present invention further comprises:

forming a plurality of separated and parallel control gate lines, each control gate line extending in a second direction substantially perpendicular to the first direction, crossing over the active region and the isolation region, and electrically connected to a portion of the control gates.

and forming a plurality of separated and parallel tunnel grid lines, wherein each tunnel grid line extends in the first direction and is electrically connected to part of the tunnel grids.

The invention discloses a method for forming an erasable and programmable read-only memory element array, wherein each control grid and a corresponding tunnel grid are mutually overlapped in an overlapping region; and

a portion of each floating gate is disposed below one of the overlapping regions.

The invention discloses a method for forming an erasable and programmable read-only memory element array, wherein each second area is electrically connected to at least one part of one drain line.

a plurality of spaced apart and parallel source lines are formed, each source line being electrically connected to a portion of the first region.

In the method for forming an array of erasable and programmable read-only memory elements according to the present invention, each trench penetrates through one of the second regions and the first layer, and the bottom of each trench is formed in one of the first regions.

To achieve the object of the present invention, the present invention also provides a method for operating an erasable and programmable Read Only Memory (ROM) device. The device has a conductive floating gate formed in a trench (trench) in a semiconductor substrate, a conductive control gate having a portion of insulation disposed on the floating gate, a conductive tunneling gate disposed on a portion of the control gate with an insulating layer therebetween to form a multi-layer structure, thereby allowing electrons and holes to tunnel through the insulating layer at an approximately similar rate, separate source and drain regions adjacent to but insulated from a lower portion of the floating gate, a drain region adjacent to but insulated from an upper portion of the floating gate, and a channel region formed between the source and drain regions, extending along a sidewall of the trench. A positive voltage is given to the drain region to couple a positive voltage to the floating gate. The tunnel gate is given a voltage which is negative with respect to a voltage of the control gate and strong enough to cause the tunnel gate to emit electrons and holes from the control gate and to cause the electrons and holes to cross the insulating layer at approximately similar rates but in opposite directions and to have sufficient energy to cross the control gate and reach the floating gate via a ballistic carrier transport mechanism.

The operation method of the erasable and programmable read-only memory element of the invention further comprises:

applying a negative voltage to the drain region and the well region to couple a portion of the negative voltage to the floating gate; and

the tunnel gate is given a voltage which is positive with respect to a voltage of the control gate and strong enough to cause the tunnel gate to emit holes and electrons from the control gate and to cause the electrons and holes to cross the insulating layer at approximately similar rates but in opposite directions and to have sufficient energy to cross the control gate and reach the floating gate via a ballistic carrier transport mechanism.

To achieve the object of the present invention, the present invention also provides a method for operating an erasable and programmable Read Only Memory (ROM) device. The device has at least two states, the device has a conductive floating gate (floating gate) formed in a trench (trench) in a semiconductor substrate (semiconductor substrate), a conductive control gate (control gate) having a portion of insulation disposed on the floating gate, a conductive tunneling gate (tunneling gate) disposed on a portion of the control gate through an insulating layer to form a multi-layer structure, thereby allowing electrons and holes to tunnel through the insulating layer, separated source and drain regions adjacent but insulated from the floating gate, and a channel region defined between the source and drain regions and insulated from the floating gate at an approximately similar rate. One of the states of the element is established by emitting electrons from the tunnel gate and holes from the control gate so that the electrons and holes traverse the insulating layer at approximately the same rate but in opposite directions and have sufficient energy to traverse the control gate to reach the floating gate via a ballistic carrier transport mechanism. The other of the states of the cell is established by emitting holes from the tunnel gate and electrons from the control gate so that the electrons and holes cross the insulating layer at approximately similar rates but in opposite directions and so that the holes have sufficient energy to cross the control gate to reach the floating gate via a ballistic carrier transport mechanism.

Drawings

FIGS. 1A-1F illustrate different single non-volatile memory devices fabricated according to a first embodiment of the present invention;

FIG. 2A is an energy band diagram of impinging electrons in accordance with the present invention;

FIG. 2B is a band diagram of the impingement cavity in accordance with the present invention;

FIG. 2C is a band diagram illustrating the negative effects of back-tunneling on impinging hole emission;

the barrier heights seen for electron and hole carriers in the valence and conduction bands of a semiconductor are shown in fig. 3, relative to an insulator;

FIG. 4A is a portion of the conductive strip when the impinging electrons have just begun to occur while the floating gate is in the initial state;

FIG. 4B is a band diagram of the floating gate after being charged by the ballistic electrons to produce a self-limiting process programming scheme;

FIG. 4C is a partial valence band for the floating gate in its initial state, when the impact holes have just begun to occur;

FIG. 4D is a band diagram of the floating gate after it has been charged by the impact holes, resulting in a self-limiting erase mechanism;

FIG. 5A shows a top view of a substrate;

FIG. 5B is a cross-sectional view taken along line CC' of FIG. 5A;

FIGS. 6A-6J are structural top views in different stages of sequentially forming a memory element of the present invention;

FIGS. 7A-7J are cross-sectional views taken along line AA' of FIGS. 6A-6J, respectively;

FIGS. 8A-8J are cross-sectional views taken along line BB' of FIGS. 6A-6J, respectively;

fig. 9A-9J are cross-sectional views taken along line CC' of fig. 6A-6J, respectively.

Detailed Description

In order to make the aforementioned and other objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below:

memory element

Referring to fig. 1A-1F, a single non-volatile memory device is fabricated in accordance with an embodiment of the present invention. The memory device of fig. 1A includes a body (bulk) 50. The substrate 50 may be a semiconductor material such as silicon or an insulator such as silicon oxide, silicon sulfide or other dielectrics known in the art. In a preferred embodiment, the substrate 50 may be silicon of a first conductivity type (hereinafter P-type) with a doping concentration of about 1E15 to 5E17 atoms/cm-3. Above the substrate 50 is a semiconductor layer 40 of the first conductivity type doped at a concentration higher than that of the substrate 50, about 5E15 to 5E18 atoms/cm-3. The thickness of the semiconductor layer 40 may be approximately between 0.2 and 0.4 microns. The base 50 and the semiconductor layer 40 are hereinafter collectively referred to as a substrate (substrate)51 of the memory element. A first heavily-doped (heavily-doped) region 24 of the second conductivity type (hereinafter referred to as N-type) is buried between the substrate 50 and the semiconductor layer 40. A substantial portion of the first heavily doped region 24 may be located in the substrate 50 or the semiconductor layer 40. The first heavily doped region 24 may have a doping concentration of between 1E18 and 5E21 atoms/cm "3 and a thickness of between about 0.2 and 2 microns. The first heavily doped region 24 serves as a source region (source region) of the memory element, and the semiconductor layer 40 serves as a memory well region in which each memory element is located. In the memory well region, i.e., in the semiconductor layer 40, a second heavily-doped (heavily-doped) region 22 of the second conductivity type is formed adjacent to the surface of the semiconductor layer 40, and has a doping concentration of about 1E 19-5E 21 atoms/cm 3 and a thickness of about 0.05-0.15 μm. The second heavily doped region 22 serves as a drain region (drain region) of the memory element. A trench hole having trench sidewalls 31 passes through the drain region 22 and the memory well region 40, and then the trench bottom 33 of the trench hole is seated in the source region 24. The source region 24 and the drain region 22 together define a channel region 21 formed along the trench sidewall 31 between the source region 24 and the drain region 22. A first insulating layer 44 is formed on the memory well region 40, the drain region 22, the channel region 21, the source region 24, and the trench bottom 33. The first insulating layer 44 may be silicon dioxide (silicon dioxide, silicon nitride), silicon oxynitride (silicon oxynitride), or a high-k material (such as aluminum oxide, hafnium oxide, zirconium oxide, etc.). The first insulating layer 44 has a first portion 43 disposed over the memory well region 40 and the drain region 22, and a second portion 45 disposed adjacent to the trench sidewalls 31 and on the trench bottom 33. First portion 43 of first insulating layer 44 may have a thickness between about 80 and 2000 angstroms (Å) and second portion 43 may have a thickness between about 50 and 500 angstroms (Å). Floating gate 20 is placed in the trench hole and is insulated from memory well region 40, drain region 22, channel region 21, and source region 24 by first insulating layer 44. The floating gate 20 is generally rectangular, and may be between about 0.03 and 0.8 microns wide and between about 0.2 and 4 microns thick. A second insulating layer 29, which may be between about 50 and 400 angstroms thick (Å), may be formed over the floating gate 20, and may be formed of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, or combinations thereof, such as a silicon oxide/silicon nitride/silicon oxide composite layer. Over the first insulating layer 44 and the second insulating layer 29 is a control gate 15, which may be a heavily doped polysilicon (po polysilicon), a low resistance interconnect such as a metal silicide (silicide), or a refractory metal. In one embodiment, control gate 15 may have two portions: first portion 16 is substantially over first portion 43 of first insulating layer 44 and has a thickness of between about 400 and 4000 angstroms (Å); second portion 17 is substantially over second insulating layer 29 and is between about 50 and 1000 angstroms thick (Å). Some possible variations of the shape of the control gates will be described later. The third insulating layer 36 has a first portion 35 on the first portion 16 of the control gate 15 and a second portion 34 on the second portion 17 of the control gate 15. The first portion 35 of the third insulating layer 36 may be silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, or combinations thereof, and may have a thickness of between about 100 and 1000 angstroms. The second portion 34 of the third insulating layer 36 may be silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, or combinations thereof, and may have a thickness of between about 30 and 200 angstroms. On the second portion 34 of the third insulating layer 36 is a tunnel gate 10. The tunnel gate 10 may be a heavily doped polysilicon, a low resistance interconnect (e.g., metal silicide), or a refractory metal having a thickness of about 1000 to 4000 angstroms. On the first portion 35 of the third insulating layer 36 is the fourth insulating layer 12, which may be silicon oxide, silicon nitride, or silicon oxynitride, having a thickness of about 500 to 10000 angstroms.

Fig. 1A-1, 1A-2, and 1A-3 show partial enlarged views of three variations of control gate 15. In the embodiments of FIGS. 1A-1 and 1A-2, the purpose is to make the control gate 15 have a second portion 17 thinner than the first portion 16, thereby enhancing the probability of ballistic carriers (ballisticcarriers) penetrating past during the programming or erasing operation of the device. In the embodiment of fig. 1A-1, this is achieved by forming a concave surface 17a on the second portion 17 of the control gate 15, i.e. the surface 17a has a substantially concave configuration. In the embodiment of fig. 1A-2, the recessed surface 17a above the second portion 17 is the trench surface 13a of a half-cut (semi-received) trench 13 formed in the control gate 15, and the trench sidewall 13b of the trench 13 is substantially perpendicular to the substrate surface. The degree to which second portion 17 is thin may be determined by the material of control gate 15 and the desired performance of the device operation. Generally, the thickness of the second portion 17 may be between 10% and 90% of the thickness of the first portion 16. Fig. 1A-3 show an embodiment of a control gate with a relatively simple structure. In fig. 1A-3, the second portion 17 of the control gate 15 is approximately the same thickness as the first portion 16. The main benefit of fig. 1A-3 is that the process of forming the control gate 15 can be simplified.

The structure of the memory element 100B in fig. 1B is substantially similar to the memory element 100a in fig. 1A, with the main difference being the shape of the floating gate 20. The floating gate 20 of the memory element 100a is substantially rectangular; however, the floating gate 20 of the memory element 100b is generally a V-shape or a truncated V-shape. Thus the floating gate of the V-shape has two parts: the width of the upper portion 20a may be between about 0.2 to 2 microns; the width of the lower portion 20b may be between about tens of angstroms to 0.1 microns. The V-shaped configuration of the floating gate effectively reduces the coupling capacitance between the floating gate 20 and the source region 24, and thus, the capacitive coupling effect between the control gate 15 and the floating gate 20 can be increased.

The structure of the memory element 100C of fig. 1C is substantially similar to the memory elements 100a and 100B of fig. 1A and 1B, with the primary difference being the depth of the floating gate 20. The floating gates 20 of the memory elements 100a and 100b are in trenches having bottoms 33 in the source regions 24; however, the floating gate 20 of the memory element 100c penetrates through the source region 24, and thus the trench bottom 33 is located in the body 50.

The structure of the memory element 100D in fig. 1D is substantially similar to the memory element 100a in fig. 1A, with the main difference being the shape of the floating gate 20. The floating gate 20 of the memory element 100a is substantially rectangular with a surface substantially flush with the surface of the substrate; the floating gate 20 of memory element 100d, however, is generally T-shaped with an upper portion of insulation disposed on a portion of the substrate surface. In other words, the protrusion 20c makes the surface of the floating gate 20 higher than the substrate surface. Thus, the T-shaped floating gate can be roughly divided into three parts: the width of the projections 20c may be between about 0.15 to 2 microns; the middle portion 20e is adjacent to the trench sidewalls 31 and may have a width of between about 0.1 and 1.5 microns; and the width of the bottom 20d may be between about 0.05 to 1.5 microns. The benefit of such a T-shaped floating gate 20 is that there can be a strong capacitive coupling between the floating gate and the control gate. In addition, the second portion 17 of the control gate 15 may form a raised structure above the protrusion 20c of the floating gate 20. During the process, the second portion 17 of the control gate 15 will naturally be formed to a relatively thin thickness and thus will be self-aligned with the protruding portion 20c of the underlying floating gate 20. While a thinner second portion 17 provides better results for the transport of impact carriers (ballistic carriers).

FIG. 1E illustrates a cross-sectional view of a single non-volatile memory device implemented in accordance with the present invention, wherein the memory device 100E has a structure substantially similar to the memory device 100a of FIG. 1A, with the primary difference being the junction with the adjacent memory device. The memory element 100e defines an active region 4 by an isolation region 5 formed by a conventional Shallow Trench Isolation (STI) process or a local oxidation (LOCOS) process. Isolation regions 5 are preferably fabricated by STI processes because STI design rules (design rule) may allow for smaller line widths and line spacings. Generally, an STI is generally rectangular in shape, having a thickness of about 0.2 microns and a width of about 0.1 microns, and is generally formed of an insulator, such as silicon oxide or other known dielectric. The main purpose of fig. 1E is to reduce the parasitic capacitance generated between the first portion 16 of the control gate 15 and the memory well region 40. The benefit of reducing such parasitic capacitance is that the capacitance seen by control gate 15, i.e., the load seen by control gate 15, is reduced, thereby reducing the access time (access time) required for the memory element to operate during a read operation. The exclusion zone 5 separates adjacent memory elements and the benefits it provides are more evident from the cross-sectional view of fig. 1F. In fig. 1F, one memory element 2 of fig. 1E is shown, as well as two

memory elements

1 and 3 adjacent on both sides. The memory elements are located in the active region 4, and the active region 4 is interleaved with the isolation region 5 to form a segment (segment) of the memory array 100 f. It is emphasized that only a small segment of the memory array 100f is shown here, and that the memory array 100f can be extended to any size memory array. The control gate 15 of each memory element is connected to form a control gate line 18. The length of the control gate lines 18 can be as long as across the entire array of memory elements. For example, assuming an array having alternating columns of isolation regions and active regions, each of which has a plurality of memory elements formed therein, the components of the memory elements, such as control gates, may be connected together and then may span an entire row or column of memory elements. Therefore, the capacitive loading effect of the control gate line 18 is actually the sum of the equivalent capacitance values of the control gates 15 of each memory element on the same control gate line. If the equivalent capacitance of the control gate 15 of each memory element is reduced by 50%, the loading on the control gate lines can be reduced by 50%, and the access time can be increased by 50%, provided that the other states or variables remain unchanged.

The memory devices shown in FIGS. 1A-1E generally have the following characteristics. Each having a control gate and a tunnel gate, the control gate and tunnel gate overlapping at an overlap region, and at least a portion of the floating gate being located below the overlap region.

Of course, the size of the memory device in the present invention depends on the design rule in the process technology. Accordingly, the dimensions of the memory elements or regions described above are merely exemplary. It is particularly emphasized that the dimensions of the memory cell must be sufficient to cause the charge emitted by the tunnel gate 10 to tunnel through the second portion of the third insulating layer 34 by a tunneling mechanism, such as direct tunneling (direct tunneling) which typically occurs at 3.3 volts or less, or Fowler-Nordheim tunneling which occurs at higher voltages. Furthermore, the size of the second portion 17 of the control gate 15 should be such as to allow a portion of the charge coming from the second portion 34 of the third insulating layer 36 to reach and be received by the floating gate 20 by means of a ballistic carrier transport mechanism (ballistic carrier mechanism). And the received amount may be 1% to several tens% of the electric charges emitted from the tunnel gate 10. The mechanism by which such elements operate and the physical principles of transmission will be explained in more detail later.

Impact carrier transport mechanism (ballistic carrier transport) mechanism)

The impact carrier transport mechanism represents a physical phenomenon in which charge carriers travel in a conductor without encountering a scattering event. In semiconductors or other conductors, such scattering is typically carrier-to-carrier (carrier)^-to^-carrier scattering), carrier-to-phonon scattering (carrier scattering)^-to^-phonon scattering), and carrier scattering for impurities (carrier)^-to^-impurity scratching) occurs. These phenomena represent the result of a change in the momentum of the carriers (which at the same time represents a change in the direction of movement) and a loss of energy. For charge carriers moving through ballistic transport (ballistic transport), the material in which the charge carriers are located is relatively invisible, and therefore, the charge carriers are inDuring their transfer, their direction of movement and energy can be maintained.

The physical phenomenon of charge (electrons or holes) traveling through conductors and insulators and then to the floating gate 20 is explained in more detail with reference to fig. 2A and 2B. The impact charges in fig. 2A are electrons; the impact charges in fig. 2B are holes. In the band diagrams (band diagram) of fig. 2A and 2B, the tunnel gate 52 and the ballistic transfer gate 62 are both a semiconductor (which may be a highly doped P-type region). The choice of P-type or N-type polysilicon should theoretically be considered as explained later.

Referring to FIG. 2A, a band diagram is shown illustrating impact electrons applied to a memory device of the present invention. When the ballistic electrons are to be injected into the floating gate region 72, the tunnel gate region 52 is negatively biased with respect to the ballistic transfer gate region 62. Electrons 76 in the valence band (valance band) of tunnel gate region 52 are emitted through a quantum mechanical tunneling mechanism (which may be Fowler-Nordheim or direct tunneling), and through tunnel insulator 56. A portion of the electrons 76, classified as scattered electrons (scattered electrons)76b, encounter scattering events as they pass through the impingement transfer grid 62, thus losing some energy, and then being carried away by the impingement transfer grid 62 as typical thermal electrons (thermal electrons). The remaining electrons, classified as ballistic electrons 76b, do not encounter scattering events during their passage through the ballistic transfer gate 62, and therefore continue to follow the original direction. Applying an appropriate bias to the floating gate region 72 allows impinging electrons 76b of sufficient energy to overcome the barrier height (conduction band barrier height) of the conduction band of the pinning insulator 67. Such carriers can enter the conductive strips 68 of the pinned insulating layer 67, maintain their orientation, and are eventually collected by the floating gates 72.

The band diagram of fig. 2B shows the impact holes applied in the memory element of the present invention. In fig. 2B, the floating gate 52 is biased with an opposite polarity as in fig. 2A to achieve ballistic hole injection. When tunnel gate region 52 is positively biased with respect to impact transfer gate 62, valence band (valance band) holes 80, which are holes in valence band 54 of tunnel gate region 52, will be emitted through the quantum mechanical tunneling mechanism (which may be Fowler-Nordheim or direct tunneling), and through tunnel insulator 56, as previously described. A portion of the holes, classified as scattering holes 80b, encounter scattering events as they pass through the impinging transfer gate 62, and thus lose some energy, and are then carried away by the impinging transfer gate 62 as are typical thermal holes. The remaining holes, classified as ballistic holes 80a, do not experience scattering events in traversing the strike transfer gate 62, and therefore continue to follow the original direction until they strike the boundary between the strike transfer gate 62 and the pinning insulating layer 67. When the impact holes 80a have sufficient energy to overcome the barrier height (valance band barrier height) of the valence band of the pinned insulating layer 67, such carriers can enter the valence band 69 of the pinned insulating layer 67, maintain its orientation, and are finally collected by the floating gate 72.

In addition to showing the theory of impulse charge transport and its use in the present invention, fig. 2A and 2B also show the use of the same tunnel gate 52 to provide two methods of impulse charge using quantum mechanical tunneling. For non-volatile memory applications, it is attractive to use a tunnel gate 52 to provide both charge impulses, which results in a simpler cell structure and a simpler array, and is relatively simple to process. However, one difficulty to overcome for this purpose is the reverse tunneling phenomenon (reverse tunneling phenomenon) caused by thermally disordered carriers opposite to the charge of the impinging carriers in the impinging transfer gate region 62. This difficulty is discussed in fig. 2C, which shows the impinging hole emission. In the band diagram of fig. 2C, the tunnel gate 52 and the shock transfer gate region 62 are P-type and N-type semiconductors, such as polysilicon, respectively. This is an example to explain the aforementioned difficulties. When the impact hole emission occurs, the conduction band electrons in the impact transfer gate region 62 will follow the same quantum mechanical tunneling mechanism and be emitted. However, the transport direction of such conduction band electrons is just opposite to the transport direction of positive valence band hole carriers 80, as shown in fig. 2C. The entire current of tunnel gate 52 is effectively the current that includes the contribution of valence band hole carriers 80 (providing the forward tunneling portion), plus the contribution of conduction band electron carriers 83 (providing the reverse tunneling portion). The forward tunnel portion is used to impinge charge emissions. Furthermore, when the memory operation requires a charge-impact emission mechanism, the forward tunneling portion is a carrier flow (carrier flow) that is needed. However, the tunnel portion in the reverse direction is not required, since it does not contribute to the emission of the impinging charge at all. Another undesirable effect is that the reverse tunneling section limits the maximum of the forward tunneling section and also limits whether the forward tunneling section can be large enough to handle the amount of current required for ballistic charge emission. Reverse tunneling tends to account for a significant portion of the entire tunneling process for a ballistic hole emission event, and thus, tends to limit the amount of ballistic transport hole current that can be adequately sized. This occurs because the barrier height 59 seen by the conduction band electrons 83 is substantially lower than the barrier height 60 seen by the valence band holes 80, and the current of the tunnel gate 52 is substantially contributed by the electron carriers. This phenomenon is particularly pronounced when tunnel insulator layer 56 is formed of silicon oxide, since conduction band electrons 83 contribute about 1,000 to 1,000,000 times as much current as valence band holes 80. Because of this phenomenon, this strong electron flow substantially limits the voltage potential that can be used between the tunnel gate 52 and the ballistic transfer gate region 62. Thus, while limiting the ability to use a lower voltage, the possibility of using hole carriers 80a to the floating gate 72 can be effectively exploited by the ballistic transport mechanism. For example, because the tunnel gate 52 and the ballistic transfer gate region 62 are limited to a voltage lower than desired, the energy of the ballistic hole carriers is not sufficient to overcome the barrier height 71 and are therefore blocked by the pinning insulating layer 67 from reaching the floating gate region 72. Of course, a silicon nitride layer without defects (trap-free) may be present, providing a just opposite state. However, the impinging electron emission is still limited by the reverse tunneling hole carriers because the conduction band barrier height 59 seen by conduction band electrons 83 is higher than the valence band barrier height 60 seen by valence band holes 80. Both states prevent the possibility of providing different types of impinging charge emissions through the same tunnel gate 52, as shown in fig. 2C, despite the differences in phenomena.

These phenomena are due to the natural phenomenon of reverse tunneling, and the large amount of reverse tunneling current will cause the trouble of using a single tunnel gate to generate impact carriers when biased in opposite polarity. This problem can be overcome by using P-type semiconductors as the material for the ballistic transfer gate 62. Such a concept has been shown in fig. 2B. It can be seen that the carriers contributing to the reverse tunneling section have changed from electrons 83 of the conduction band in fig. 2C to valence band electrons 82 in fig. 2B. As a result of this change, the barrier height seen by the reverse tunneling electron carriers 82 will increase by an amount approximately equal to the band gap 61(band gap) of the material used to impact the transfer gate 62. For example, if the material used for the shock transfer gate 62 is heavily doped N-type polysilicon and the material of the tunnel insulator layer 56 is silicon oxide, the barrier height seen by electrons can be increased from 3.1 electron volts (eV) to 4.22eV once the shock transfer gate 62 is replaced with P-type polysilicon. The barrier height 60 seen by the valence band hole carriers 60 in the tunnel gate 52 is about 4.5eV, depending on the material used in this example. Therefore, the barrier height seen by the reverse tunnel carriers is comparable to that seen by the forward tunnel carriers. And thus about half of the total current in tunnel gate 52 is contributed by the forward tunneling portion and about the other half is contributed by the reverse tunneling portion. Therefore, the negative impact of reverse tunneling on impact charge transport can be greatly reduced.

In accordance with the present invention, the use of a P-type semiconductor, such as P-type polysilicon, as such a structure for both the tunnel gate 52 and the ballistic transfer gate 62 results in two features. First, such a structure may allow the impinging electrons as well as the impinging holes to be emitted from the same electrode. Second, such a structure reduces the negative impact of reverse tunneling on ballistic charge emission. The data in fig. 3 provides a method by which the band gap and barrier height can be appropriately selected to provide nearly proportional impulse charge current at the same one tunnel gate when biased with opposite polarity. The barrier height of electron and hole carriers seen by a semiconductor (such as polysilicon or pure silicon) in the valence and conduction bands is shown in fig. 3, relative to an insulator. The barrier height in the figure can be expressed as a function of the proportion of oxygen (i.e., x) in a silicon oxynitride system (SiOxN 1-x). The silicon oxynitride system is selected as a representative of the insulating layer because of excellent factory process control and film quality. In the SiOxN system (SiOxN1-x), x represents the proportion of oxygen, and equivalently represents the percentage of oxygen contained in a SiOxN film. For example, x ═ 1 means that the film is purely silicon oxide; for the same reason, x ═ 0 means that this film is purely silicon nitride. With x changed, the energy band gap (energy gap) can change from 8.7eV for pure silicon oxide to 5.1eV for pure silicon nitride. The concept of selecting a better dielectric and a better structure is to find out a plurality of carriers (electrons and holes) satisfying two conditions. First, these carriers see approximately the same barrier height. Second, the carriers are in the same energy band (i.e., the same conductivity type, such as N-type or P-type). Using the above concept, only one state can be found in fig. 3 to meet the above condition. In fig. 3, it can be seen that the barrier height seen by holes in the valence band is approximately as high as the barrier height seen by electrons in the valence band at an oxygen ratio of approximately 82%. Therefore, a preferred three-layer structure is proposed, namely two heavily doped polysilicon layers sandwiching a silicon oxynitride film with an oxygen ratio of about 82%. The tri-layer structure is such that when a suitable bias is applied to the two polysilicon electrodes during impact charge emission, the flow or rate of electrons and holes through the SiON is substantially the same. In addition, the result is that the reverse tunneling current is substantially similar to the forward tunneling current used to generate the impinging holes or electrons. For example, the ratio of reverse tunneling current to forward tunneling current may be approximately between 0.1 and 5. It should be noted that the second order effect (second order effect) caused by the slight difference in the equivalent mass of electrons and holes in SiOxN1-x may affect the current passing therethrough and fail to meet the condition of equal current. In this case, it is likely that the oxygen ratio in SiOxN1-x will need to be slightly adjusted to match the current in the SiOxN1-x with the current in the prior art.

It is noted that the presently disclosed tri-layer structure and method of finding the current substantially the same is not applicable to polysilicon or semiconductor tunnel gate 52 and ballistic transfer gate 62, but can be applied to other types of materials by those skilled in the art. For example, the method of fig. 3 can be applied to a metal conductor by changing the curve relating to the conduction band and the valence band in the figure to a curve relating to the metal fermi level (fermlevel). In addition, the basic idea of the method disclosed herein is to change the characteristics (oxygen ratio) of the insulating layer to meet the two aforementioned conditions. Of course, those skilled in the art can also appropriately expand or adjust the method to meet the same requirements. For example, tunnel barrier 52 and shock transfer barrier 62 may be changed to appropriate metal materials without changing the characteristics of insulating layer 56, and may be formed under the same conditions to achieve the same results. For example, a metal may be selected whose work function (work) Fermi level is approximately in the middle of the band gap of the insulating layer, so that the barrier heights seen by electrons or holes are approximately equal. In addition, in the three-layer structure disclosed herein, the insulating layer is a single-layer structure. Those skilled in the art can also appropriately expand or adjust the insulating layer to be a composite layer (composite layer) with multiple layers. That is, the insulating layer is not limited to a single material, and may have a plurality of materials to achieve the desired effects of the present invention.

It will be appreciated by those skilled in the art that the above-described phenomena and principles may be generally considered to be true, while others may not have discussed the phenomena, and do not significantly affect the present invention. For example, in the present invention, the impinging electrons 76a and the impinging holes 80a may encounter scattering events in some places (perhaps the pinning insulating layer 67). Such phenomena should not affect the scope of the present invention.

Memory element operation

The memory element operation described below will be referenced to the memory element in fig. 1A.

1. Programming (program)

When a selected memory device is to be programmed, a first type of charge (e.g., electrons) must be injected into the floating gate 20. The method achieved is as follows. First, a small voltage (e.g., 2V) is applied to control gate 15. A negative voltage is applied to the tunnel gate 10. This negative voltage and the voltage difference with respect to control gate 15 must be large enough for the charge to overcome the conduction band barrier height of second insulating layer 29. For the band diagrams disclosed in fig. 2A to 3, the voltage of the tunnel gate 10 may be approximately between-2.1V to-2.5V. A positive voltage, approximately between 0 and 0.9V, may be applied to the floating gate 20 via the drain region 22 and the memory well region 40 by capacitive coupling. Electrons emitted by tunnel gate 10 will travel towards second portion 17 of control gate 15. The second portion 17 of the control gate 15 constitutes the impact transfer gate region 62 in fig. 2A. When the electrons reach the second portion 17 of the control gate 15 they will have a high energy, and most of them will penetrate through the second portion 17 of the control gate 15 to the interface of the second portion 17 with the second insulating layer 29 without loss of energy and momentum through the ballistic transport mechanism (ballistic mechanism). Electrons can enter the second insulating layer 29, travel therein, and finally reach the floating gate 20 if their energy is high enough to cause themselves to cross the barrier height of the second insulating layer 29. The impact transfer mechanism can be facilitated by adjusting the thickness of the second portion 17 of the control gate 15. Such a thickness should be about less than or equal to the mean-free-path of the electrons in that region. For memory elements that are not selected for programming, their drain regions 22 and source regions 24 are grounded if they do not share the same drain and source regions as the selected memory element (or are on a column that is not selected). Memory elements that do not share the same control gate line as the selected memory element (or are on an unselected row) have their control gate 15 also grounded. Thus, only the memory elements at the selected row and column interleaving locations will be programmed.

The transfer of electrons to the floating gate 20 continues until the blocking effect of the impinging electrons begins to occur. This blocking effect is a result of the band of the floating gate 20 being raised, i.e., a result of the potential drop caused by the floating gate 20 collecting electron charge. Therefore, a triangular barrier is formed over the second insulating layer 29, and the triangular barrier becomes higher as the amount of the impact electron charges collected by the floating gate 20 increases. Once this triangular barrier is high to a certain extent, electrons emitted from the tunnel gate 10 against the floating gate 20 cannot cross its equivalent barrier height, and the transferred electrons are completely blocked outside the floating gate 20. This blocking effect is determined by the voltage. That is, the current therein is not the same as the observed phenomenon in Fowler-Nordheim tunneling mechanism, and is essentially controlled by voltage. Also, the second insulating layer 29 is typically 80 angstroms or thicker. With such a thick second insulating layer 29, charge tunneling that is relatively unaffected by voltage (i.e., direct tunneling) hardly occurs. Thus, such a blocking effect provides a self-limiting (self-limiting) method of electrons that can be injected into the floating gate with precision. The voltage level that the floating gate should have after programming can be predicted by simply adjusting the voltage coupled to the area surrounding the floating gate, such as drain region 22. Such a mechanism is well suited for multi-level memory.

2. Erasing (erase)

Basically, the selected memory device is erased by reversing the bias voltages applied for programming. More specifically, a second type of impact charge (e.g., holes) is injected into the floating gate 20. The method achieved is as follows. First, a small voltage (e.g., -2V) is applied to control gate 15. A positive voltage is applied to the tunnel gate 10. This positive voltage and the voltage difference with respect to control gate 15 must be large enough for the charge to overcome the valence band barrier height of second insulating layer 29. For the band diagrams disclosed in fig. 2A to 3, the voltage of the tunnel gate 10 may be approximately between 2.1V to 2.5V. A negative voltage, between about 0 and-0.9V, is applied to the floating gate 20 via the drain region 22 and the memory well region 40 by capacitive coupling. Under such bias, holes emitted by the tunnel gate 10 according to quantum mechanics will travel through the second portion 34 of the third insulating layer 36 and then towards the second portion 17 of the control gate 15. The second portion 17 of the control gate 15 constitutes the impact transfer gate region 62 in fig. 2A. When the cavities reach the second portion 17 of the control gate 15 they will have a high energy content, and most of them will penetrate through the second portion 17 of the control gate 15 without loss of energy and momentum through the ballistic transport mechanism (interface) to the second portion 17 to the second insulating layer 29. If the energy of the holes is high enough to make themselves cross the barrier height of the second insulating layer 29, the holes can enter the second insulating layer 29, travel in it, and finally reach the floating gate 20. Such a surge of hole carriers will continue to charge the floating gate 20 until a self-limiting mechanism begins to occur. The hole self-confinement mechanism is similar to the electron self-confinement mechanism discussed at the time of programming. The proportion of holes reaching the floating gate 20 among holes emitted from the tunnel gate 20, defined herein as the ballistic hole transport efficiency (ballistic hole transport efficiency), can be improved by adjusting the thickness of the second portion 17 of the control gate 15. Such thickness should be about less than or equal to the mean-free-path of the holes in that region. For memory elements that are not selected to be erased, their drain regions 22 and source regions 24 are grounded if they do not share the same drain and source regions as the selected memory element (or are located in a row or column that is not selected). Memory elements that do not share the same control gate line as the selected memory element (or are on an unselected row) have their control gate 15 also grounded. Thus, only the memory elements at the selected row and column interleaving locations are erased.

It is noted that, according to the present invention, the absolute values of the voltages required for the program and erase operations are not greater than 2.5V. Moreover, such erase mechanisms and device architecture features make erase of individual devices possible, which is ideal for periodically requiring more data storage. Of course, such a feature may also be applied to simultaneously erase a small group of memory elements at a time, for example, 8 memory elements at a time for storing a "word". Of course, it is also possible to apply to erasing a large group of memory elements simultaneously at one time. For example, one page (page) or multiple pages of memory elements, each page having 2048 memory elements, are erased at a time.

3. Reading (read)

To read a selected memory line, about 1V is applied to its drain region 22 and about 2.5V (depending on the operating voltage of the internal logic element) is applied to the control gate 15, and the voltage is referred to as the read voltage. Other regions, such as source regions 24 and memory well regions 40, are grounded.

If the charge in the floating gate 20 is positive or electrons in the floating gate 20 are removed, the channel region 21, i.e., the region adjacent to the floating gate 20 along the trench sidewall 31, will conduct. The electron current will flow from the source region 24 to the drain region 22. This is a logic "1" state.

Conversely, if the charge in the floating gate 20 is negative, the channel region 21 may be weakly conductive or even completely off. Although both the control gate 15 and the drain region 22 are raised to the read voltage, little or no electron current can flow through the channel region 21. In this case, the electron current is very small compared to the electron current in the "1" state, or can be considered to be absent. Thus, such a memory element would be considered to have been programmed to a logic "0" state.

For unselected rows, its control gate is grounded; the drain region of the unselected column is grounded. The memory well region 40 is grounded, whether selected or not selected memory elements.

Such a memory element may be formed in a memory array, accompanied by conventionally known row address decoder circuits (row address decoding circuits), column address decoder circuits (column address decoding circuits), sense amplifier circuits (sense amplifier circuits), output buffer circuits (output buffer circuits), input buffer circuits (input buffer circuits), and the like.

The memory device architecture and the device operation method of the present invention are advantageous because the device operation does not require any high voltage (higher than 2.5V), so that the high-voltage generating infrastructure (high-voltage generating infrastructure) mentioned in the prior art is not required, and the problem derived from the high-voltage generating infrastructure is not caused. Another important feature of the present invention is an architecture in which the tunnel gate 10 is stacked on the second portion 17 of the control gate 15, and the floating gate 20 is placed under the region where the second portion 17 overlaps the tunnel gate 10. This architecture allows electrons or holes emitted from the tunnel gate 10 on the silicon substrate to be transported straight down into the floating gate 20 underneath.

The "top-down" radial architecture of the present invention provides a number of advantages over the prior art. First, the programming efficiency (programming efficiency) can be greatly improved because the impact charge carriers are emitted in alignment with the floating gate 20. In prior art programming architectures, electrons moving in the channel move substantially parallel to the floating gate. Thus, also in the prior art, only a very small fraction of the electrons can be heated to have sufficient energy and be injected into the floating gate. The programming efficiency (defined as the ratio of the injected charge to the total supplied charge) in the prior art is roughly between 1/1,000 and 1/1,000,000. However, in the present invention, because of the "top-to-bottom" emission scheme, the energetic carriers are emitted (or emitted) directly in alignment with the floating gate, and the programming efficiency is predicted to be close to 1/10, i.e., a significant portion of the charge is injected into the floating gate. Second, as can be seen from the device operation, the highest voltage (2.5V) is only present above the silicon surface (e.g., control gate 15 and tunnel gate 10). In other words, the silicon surface at which the metallurgical junctions (junctions formed by the source region 24 and the drain region 22) are located does not experience the highest voltage during device operation. According to the present invention, the source region 24 and the drain region 22 do play a major role during reading, but operate in a low voltage environment. The footprint of the source region 24 and the drain region 22 is also coupled to the floating gate 20 at a small voltage (-0 to 1V) during programming or erase operations, and therefore much smaller than the high voltage required to generate hot carriers (hot carriers).

The present invention provides advantages over the prior art because the relevant area of the metallurgical junction can be maintained at a relatively low voltage. First, the size reduction limitation on the height of the device mentioned in the prior art has been eliminated, and thus, a tighter design rule (de sign rule) can be used to create a smaller device size. The size reduction of the memory element can be as much as 50% because the floating gate 20 is buried in the substrate 50 and the drain region 22 will only receive a low voltage. If current 0.18 and 0.13 micron process technologies are used, the memory device areas are approximately 0.21 and 0.11 microns squared, respectively. Of course, the element area may be smaller. Second, the hot carrier effect (hot carrier effect) of the metallurgical junction and the degradation or damage of the insulating layer 45 caused by the hot carrier effect are all eliminated. This is quite different from the prior art, in which programming is performed by applying a high voltage to the junction to heat the carriers, so that it is inevitable that a very strong electric field stress is applied to the insulating layer located between itself and the adjacent floating gate, and as a result, the insulating quality is degraded or damaged. In the present invention, since the voltage across the floating gate 20 and the surrounding region (e.g., the drain region 22) is very small, the electric field stress on the insulating layer 45 is also very small, and thus, almost no damage occurs. This feature is very important for reliability and charge retention of the nonvolatile memory element.

4. Component interference (cell disturb)

Just as the memory element 100a is placed in an array environment, a sufficient amount of disturb (disturb) may accumulate as a result of program or erase operations on individual memory elements in the same array, or reads of any memory element, and the logic state of the memory element 100a is then accidentally and unfortunately changed. The memory element provided by the invention can avoid the problem. For example, in order for electrons or holes to have sufficient energy to cross the barrier height of the insulating layer 45 between the floating gate 20 and the drain region 22 (approximately 3.1eV for electrons and 4.6eV for holes), the carriers must be accelerated and heated by the junction electric field near the drain region 22 to obtain high enough energy so that the interference does not occur. Because the voltage difference of the drain region 22 to other regions, or the cross-over voltage of all metallurgical junctions, is kept low (about 2 to 2.5V), electrons and holes are effectively prevented from gaining energy above those barrier heights. In other words, if the bias structure provided by the present invention is viewed from the disturbance caused by junction electric field, the disturbance caused by programming, erasing or reading of unselected memory devices can be ignored.

In addition, the impact charge radiation structure provided by the invention can also obviously reduce the interference effect of elements. There are many situations that can be used to illustrate this effect. First, the worst case in read disturb occurs when the floating gate 20 is in the erased state (i.e., the floating gate 20 is electrically neutral or has a little positive charge). In this situation, a small number of impinging electrons induced by control gate 15 may pass through second portion 17 of control gate 15 to the junction of second portion 17 and insulating layer 29. But these electrons will have no way to cross the barrier height (about 4eV) because their energy is limited by the low voltage (about 2V when read) between the control gate 15 and the tunnel gate 10, which is only about 2 eV. It is therefore anticipated that electrons will be blocked from the floating gate 20 and therefore the charge state of the floating gate 20 itself will not be affected. Second, the worst case in erase disturb is when the floating gate 20 is in a programmed state (i.e., the floating gate 20 has a negative charge). In this situation, a small number of impact holes induced by control gate 15 may cross over second portion 17 of control gate 15 to the junction of second portion 17 and insulating layer 29. However, as described in the first case, these holes will have no way of crossing the barrier height (about 4eV) because their energy is limited by the low voltage (about 2V when erased) between the control gate 15 and the tunnel gate 10 of the unselected cell, which is only about 2 eV. It is therefore anticipated that holes will be blocked from the floating gate 20 and therefore the charge state of the floating gate 20 itself will not be affected.

In addition, the memory element of the present invention can also effectively reduce the element interference caused by the voltage generated on the insulating layer 29 due to the capacitive coupling effect. The worst case of cell disturb resulting from this effect occurs when the floating gate 20 of the memory cell is in a programmed state (i.e., the floating gate has a negative charge). Since the floating gate of the memory element 100a will have a capacitive coupling effect with all other surrounding electrodes (source 24, drain 22, and memory well region 40, etc.), it is reasonable to assume that the capacitive coupling ratio (capacitive coupling) of the control gate 15 to the floating gate 20 is 20%. Such a capacitive coupling ratio, coupled with the low voltage (2.5V) applied to the control gate 15 during reading, may produce a voltage across the insulating layer 29 between the floating gate 20 and the control gate 15 of, but in the vicinity of 1.5V to 2.5V, so that the current that may be produced by Fowler-Nordheim tunneling is negligible at all.

By considering the above-mentioned interference effect and mechanism, whether the device operates or the device is capacitively coupled, the device is properly designed and controlled under very good conditions, so that the memory device can be effectively prevented from unexpected and accidental switching from "1" state to "0" state or from "0" state to "1" state during the whole service life of the memory product.

Self-limiting (self-limiting) impact charge emission during operation of memory devices (ballistic charge iniection)

The self-limiting emission mechanism and its application in device design and operation will be explained in a simple capacitive mode. The voltage of the floating gate 20 can be approximated by the following equation:

V_FG＝(Q_FG+∑C_iV_i)/C_total

and

∑C_iV_i＝C_FG-s*V_s+C_FG-D*V_D+C_FG-cG*V_CG+C_FG-w*V_w

C_total＝C_FG-S+C_FG-D+C_FG-CG+C_FG-w

wherein,

Q_FGis the total amount of charge in the floating gate 20;

C_FGsis the capacitance between the floating gate 20 and the source region 24;

C_FG-Dis the capacitance between the floating gate 20 and the drain region 22;

C_FG-CGis the capacitance between the floating gate 20 and the second region 17 of the control gate 15; and C_FG-wIs the capacitance between floating gate 20 and memory well region 40.

In the initial state (initial condition), it can be assumed that the floating gate 20 has no charge or is electrically neutral, and that the voltage of the floating gate 20 is about

V_{FG_i}＝∑C_ivi/C_total

1. Programming operation

The self-limiting emission mechanism is explained below in terms of a programming operation, using the first charge (electrons) as the impact carrier. Fig. 4A is a portion of the conductive strip in the band diagram of fig. 2A, just after the onset of the impact electrons, with the floating gate 20 in its initial state. In fig. 4A, the second portion 17 of the control gate 15 is used as the strike pass gate 62 in fig. 2A. While the floating gate 72 of figure 2A may be considered the floating gate 20 in the memory element of the present invention. The propagating strike electron 76a has a kinetic energy 90 sufficient to cross the conductive band barrier height 70 of the pinning insulation layer 29 on its own. It can be seen that the impinging electron 76a has a kinetic energy 90 that is higher than the conductive band barrier height 70 of the insulating layer 29 by an amount approximately as indicated by the symbol 90 a. Such carriers then enter the conductive strips 68 in the insulating layer 29, are then drawn by the electric field and eventually fall to the floating gates 20 where they are collected. Through such emission, negative charges are gradually accumulated in the floating gate 20, and the potential of the floating gate 20 itself is gradually changed, and the electric field in the insulating layer 29 is also changed. As the emission process continues, this effect changes the electric field in the insulating layer 29 from assisting in the transfer of the shock charges to the floating gate 20 (fig. 4A) to repelling the transfer of the shock charges (fig. 4B).

FIG. 4B is similar to FIG. 4A, with the primary difference being the potential of the floating gate. Here, the potential of the floating gate 20 has been changed by the collected negative charges from the original initial state. As the emission process continues, the impinging electrons, now having the same kinetic energy 90, will be reflected back to the second portion 17 of the control gate 15 and then carried away as normal thermal stray carriers. In the figure, it is more particularly noted that although electrons 76a are able to enter conductive strip 68 in a region of a portion of insulating layer 29, they are unable to overcome conductive strip barrier height 70a in insulating layer 29. It is also shown that a very small number of carriers can travel a certain distance 70b through the quantum mechanical penetration mechanism and eventually become electron carriers 76d to and remain in the floating gate 20. The probability of occurrence of the electron carriers 76d is very low (e.g., on the order of parts per million), and, as will be explained later, is expected to be reduced very quickly. According to the phenomena described above, the charge collected by the floating gate 20 forms a mechanism to block impact carriers that limit their travel to the floating gate 20. Fig. 4B provides a basic theory of such self-limiting. Unlike the electron flow caused by FOWLER-Norheim tunneling, electron flow 76d is more sensitive to voltage. This is for a number of reasons. First, the pinned insulating layer 29 is about 60 angstroms thick or thicker and thus can be considered a Fowler-Nordheim tunnel dielectric. The flow rate of electron carriers 76d should be similar to that described for Fowler-Nordheim tunneling, if not for other effects, whereas in Fowler-Nordheim tunneling the current depends strongly on the voltage, and in particular at low voltages the current increases by a factor of about 10 per 100mV increase. Second, as charge continues to be collected by the floating gate 20, the barrier height of the insulating layer 29 is constantly increased, and thus a reverse electric field E is established, so that impinging carriers 76a intended to enter the floating gate 20 are more effectively resisted. Such a reverse electric field E can be roughly represented as

E＝(Q_FG-Q_{FG_fb})/(T_insulatorC_total)

Wherein

Q_{FG_fb}Is the charge in the floating gate when the insulating layer 29 is in the flat band condition (flat band condition);

T_insulatoris the thickness of the insulating layer 29;

barrier height phi_eThat is, the height of the conduction band barrier seen by the impinging electrons in insulating layer 29, can be expressed as

Φ_e＝＝q(Q_FG-Q_{FG_fb})/C_tota1-△K_e

Wherein

ΔK_eIs the difference 90a between the kinetic energy 90 of the electron carrier and the barrier height at the interface of the second insulating layer 29, and can also be regarded as the initial kinetic energy of the electron carrier 76a just entering the insulating layer 29; and

q is the charge amount of one electron.

Therefore, when Φ_eBelow zero, i.e. Δ K_eGreater than Q (Q)_FG-Q_{FG_fb})/C_totalWhile the impinging electrons can travel through the insulating layer 29, the reverse electric field is opposite to that of the previous oneThe effect of the impact charge is roughly negligible. As the radiation continues, phi_eWill be equal to zero, i.e. Δ K_eIs equal to Q (Q)_FG-Q_{FG_fb})/C_totalThe effect of the reverse electric field on the incoming impact charge begins to appear. As the emission proceeds more continuously, the conduction band barrier height 70a seen by impinging electron carriers in the insulating layer 29 begins to form and, as charge is collected by the floating gate 20, the higher its conduction band barrier height 70 a. It is expected that the number of bouncing back carriers 76c will increase rapidly and will eventually equal the number of previous impact carriers 76 a. Thus, the number of carriers that can participate in Fowler-Nordheim tunneling is reduced, and the number of electron carriers 76d that reach the floating gate 20 is also reduced. This mechanism further highlights the voltage effect of inhibiting charge transfer to the floating gate 20.

Both of the aforementioned effects constitute a self-limiting emission mechanism when programming a device with impinging charge emission. At the very beginning of programming, as long as impinging electron carriers can cross the barrier height 70, such electron carriers are allowed to pass through the insulating layer 29 and then reach the floating gate 20. As programming progresses, electron charges are gradually accumulated in the floating gate 20, and then the voltage of the floating gate 20 is gradually lowered to a certain value V_{FG_P}A new barrier height 70a is created that blocks all subsequent incoming impinging electron carriers from reaching the floating gate 20. Thus, as the self-limiting mechanism occurs, the programming is completed, and the whole programming flow is completed.

At the completion of programming, the total amount of charge in the floating gate 20 can be estimated by the following simple formula:

Q_FG＝C_total(V_{FG_P}-V_{FG_i})

the total charge can also be estimated using another simple formula:

Q_FG＝C_{FG_fb}+(C_total/q)*ΔK_e

it follows that the total amount of charge accumulated in the floating gate 20 after the programming process is completed depends on two main parameters. The first parameter is the extra energy 90a of the impinging electron 76a that is more than the barrier height 70. Since the extra energy 90a can be determined by the voltage difference between the tunnel gate 10 and the second portion 17 of the control gate 15, the total charge stored in the floating gate 20 can be determined by properly selecting or controlling the bias voltage of the

regions

10 and 15. The total capacitance Ctotal can be used as a tuning parameter to assist or enhance the effect through the device design. For example, a smaller total capacitance Ctotal will result in a larger bias value between

regions

10 and 15 being required to deliver an equal amount of charge to floating gate 20. The second parameter that determines the total charge in the floating gate is related to the amount of floating gate charge required to cause the flat band condition of insulating layer 29. The amount of such charge is determined by all the electrodes of the memory element and the corresponding coupling capacitance. Thus, once a set of such parameters is selected, the memory element can be accurately programmed to a particular state. Q_FGAnd Δ K_eThe linear relationship between (i.e., the additional energy 90a) further provides the advantage of multi-state storage capability for the memory device of the present invention.

2. Erase operation

The self-limiting emission mechanism is explained below in terms of an erase operation, using the second charge (holes) as the impact carrier. Fig. 4C is a portion of the valence band in the band diagram of fig. 2B, when the impact holes just start to occur, and the floating gate 20 is in the initial state. This initial state is when the floating gate 20 has some negative electronic charge in it. In fig. 4C, the second portion 17 of the control gate 15 is used as the impact transfer gate 62 in fig. 2B. While the floating gate 72 of figure 2A may be considered to be the floating gate 20 in the memory element of the present invention. The transporting impinging hole 80a has a kinetic energy 92 sufficient to cause itself to cross the valence band barrier height 71 of the pinning insulating layer 29. It can be seen that the impinging holes 80a have kinetic energy 92 that is higher than the valence band barrier height 71 of the insulating layer 29 by an amount approximately as indicated by symbol 92 a. Such carriers then enter the valence band 69 in the insulating layer 29, are then drawn by the electric field, and finally fall to the floating gate 20 to be collected. Through such emission, positive charges are gradually accumulated in the floating gate 20, and the potential of the floating gate 20 itself is gradually changed, and the electric field in the insulating layer 29 is also changed. As the emission process continues, this effect changes the electric field in the insulating layer 29 from assisting in the transfer of the shock charges to the floating gate 20 (fig. 4C) to repelling the transfer of the shock charges (fig. 4D).

FIG. 4D is similar to FIG. 4C, with the primary difference being the potential of the floating gate. Here, the potential of the floating gate 20 has been changed by the collected positive charge from the original initial state. As the emission process continues, the impinging holes, now having the same kinetic energy 92, will be reflected back to the second portion 17 of the control gate 15 and then carried away as normal thermal stray carriers. In the figure, it is more particularly pointed out that, although holes 80a are able to enter the valence band 69 in a partial region of insulating layer 29, the valence band barrier height 71a in insulating layer 29 is not overcome. It is also shown that a very small number of carriers can travel a certain distance 71b through the quantum mechanical penetration mechanism and eventually become hole carriers 80d to and remain in the floating gate 20. The probability of occurrence of hole carriers 76d is very low and, as will be explained later, is expected to be reduced very quickly. According to the phenomena described above, the charge collected by the floating gate 20 forms a mechanism to block impact carriers that limit their travel to the floating gate 20. Fig. 4D provides a basic theory of self-limiting in such erasure. Unlike the electron flow caused by FOWLER-Norheim tunneling, the hole flow 80d is more sensitive to voltage. This is for a number of reasons. First, the pinned insulating layer 29 is about 60 angstroms thick or thicker and thus can be considered a Fowler-Nordheim tunnel dielectric. The flow rate of hole carriers 80d as a function of voltage should be similar to that described for Fowler-Nordheim tunneling, if not for other effects. Second, as charge continues to be collected by the floating gate 20, the barrier height of the insulating layer 29 is constantly increased, and thus a reverse electric field E is established, so that impinging carriers 80a intended to enter the floating gate 20 are more effectively resisted. Such a reverse electric field E can be roughly represented as

E＝(Q_FG-Q_{FG_fb})/(T_insulatorC_total)

Wherein

T_insulatoris the thickness of the insulating layer 29;

barrier height phi_hThat is, the valence band barrier height as seen by the impinging holes in insulating layer 29, can be expressed as

Φ_h＝q(Q_FG-Q_{FG_fb})/C_tota1-△K_h

Wherein

ΔK_hThe difference 92a between the kinetic energy 92 of the hole carriers and the barrier height at the interface of the insulating layer 29, which can also be regarded as the initial kinetic energy of the hole carriers 80a just entering the insulating layer 29; and

q is the charge amount of one electron.

Therefore, when Φ_hBelow zero, i.e. Δ K_hGreater than Q (Q)_FG-Q_{FG_fb})/C_totalWhile the impact holes can be transported through the insulating layer 29, the effect of the reverse electric field on the previous impact charges is substantially negligible. As the radiation continues, phi_hWill be equal to zero, i.e. Δ K_hIs equal to Q (Q)_FG-Q_{FG_fb})/C_totalReverse electric field for the previous oneThe effect of the impact charge of (a) starts to appear. As emission proceeds more continuously, the valence band barrier height 71a of impinging hole carriers seen in the insulating layer 29 begins to form, and as charge is collected by the floating gate 20 more, the height of its valence band barrier height 71a is higher. It is expected that the number of bouncing back carriers 80c will increase rapidly and will eventually equal the number of previous impact carriers 80 a. Thus, the number of carriers that can participate in Fowler-Nordheim tunneling is reduced, and the number of hole carriers 80d that reach the floating gate 20 is also reduced. This mechanism further highlights the voltage effect of inhibiting charge transfer to the floating gate 20.

Both of the aforementioned effects constitute a self-limiting emission mechanism when erasing data from a memory element with impinging charge emissions. At the very beginning of the erase, so long as impinging hole carriers can cross the barrier height 71, such hole carriers are allowed to pass through the insulating layer 29 and then reach the floating gate 20. As the erase proceeds, hole charges are gradually accumulated on the floating gate 20, and then the voltage of the floating gate 20 is gradually raised to a certain value V_{FG_E}A new barrier height 71a is created which prevents all subsequent incoming impinging hole carriers from reaching the floating gate 20. Thus, as the self-limiting mechanism occurs, the erase is completed, thereby completing the entire erase process.

The total amount of charge in the floating gate 20 at the time of erase completion can be estimated by the following simple formula:

Q_FG＝C_total(V_{FG_E}-V_{FG_i})

the total charge can also be estimated using another simple formula:

Q_FG＝C_{FG_fb}+(C_total/q)^*ΔK_h

it can be seen that after the erase flow is completed, the floating gate 20 is accumulatedThe total charge depends on two main parameters. The first parameter is the extra energy 92a that impacts the hole 80a more than the barrier height 71. Since the extra energy 92a can be determined by the voltage difference between the tunnel gate 10 and the second portion 17 of the control gate 15, the total charge stored in the floating gate 20 can be determined by properly selecting or controlling the bias voltage of the

regions

10 and 15. Total capacitance C_totalCan be used as a fine tuning parameter to assist or enhance the effect through the device design. For example, a larger total capacitance C_totalThis results in a smaller bias between

regions

10 and 15 being required to deliver an equal amount of charge to floating gate 20. The second parameter that determines the total charge in the floating gate is related to the amount of floating gate charge required to cause the flat band condition of insulating layer 29. The amount of such charge is determined by all the electrodes of the memory element and the corresponding coupling capacitance. Thus, once a set of such parameters is selected, the memory element can be accurately erased to a particular state. Q_FGAnd Δ K_hThe linear relationship between (i.e., the additional energy 92a) further allows the memory element of the present invention to be accurately brought to a particular state. These effects can prevent the problem that the prior art nonvolatile memory element is easy to be over-erased.

It will be appreciated by those skilled in the art that the above description of the self-limiting mechanism is generally applicable regardless of whether the carriers being used are positive or negative. Of course, holes may be selected for programming, and electrons may be selected for erasing.

3. Manufacturing method

Fig. 5A shows a top view of a substrate 50. The substrate 50 may be formed of silicon of a generally known first conductivity type (hereinafter P-type). A first semiconductor layer 40 of the first conductivity type, which has a doping concentration higher than that of the substrate 50, is formed on the substrate 50, as shown in fig. 5B. The first semiconductor layer 40 will serve as a memory well region for the placement of memory devices and may be formed in the body 50 by any number of techniques known in the art, such as doping the body 50 with impurities. The first semiconductor layer or semiconductor well 40 may also be grown on the substrate 50 by techniques well known in the art, such as epitaxial deposition (i.e., Chemical Vapor Deposition (CVD)). The epitaxial deposition process may deposit a layer of pre-doped monocrystalline silicon on the substrate 50. Thereafter, a heavily doped first region 25 of a second conductivity type (N-type is selected below) is formed between the substrate 50 and the first semiconductor layer 40 by any technique known in the art, such as ion implantation. Although not shown, a photoresist layer may optionally be used as a mask to define one or more first regions 25 as regions where ions are to be implanted prior to ion implantation. Such first regions 25 form buried source lines of the memory array, while the source region 24 of each memory element is connected to at least one first region. The first region 25 may be mostly located in the substrate 50 or in the first semiconductor layer 40. Or one half may be located in the base 50 and the other half may be located in the first semiconductor layer 40. The order of forming the buried source line 25 (i.e., the first region) and forming the semiconductor well region 40 (i.e., the first semiconductor layer) may be reversed.

After formation of the semiconductor well region 40 and the buried source line 25, heavily N-doped stripe regions are formed. Such stripe regions are substantially oriented in one direction (hereinafter referred to as Y direction) as drain lines 23 of the memory array, and the drain region 22 of each memory element is connected to at least one of the drain lines 23. The stripe regions may be formed by techniques well known in the art, such as photo-lithography (photo-lithography) plus ion implantation. By way of example. The N-type stripe regions can be formed by appropriately selecting a photo-resist material to be coated on the silicon surface, and then selectively removing the photo-resist material by masking to form a plurality of stripe openings facing the first direction. Then, an N-type impurity (e.g., Arsenic) is selected to implant the silicon surface not covered by the photoresist by a conventional ion implantation technique under a low energy (e.g., 5keV) and a high doping (e.g., 5E15cm-3), thereby forming the drain line 23. The photoresist is then removed and a field-inversion stop region (field-inversion stop region)26 is formed with a P-type impurity (e.g., boron) concentration of about a medium or a light level (e.g., 1E14 cm-3). The highest concentration point of the field inversion termination region 26 preferably falls near the silicon surface and should be shallower than the drain region 22 of the drain line 23. The substrate 51 now has interleaved strip-shaped drain regions 22 and field inversion termination regions 26. The strip-shaped drain region 22 defines the active region 4 of each memory element, and the strip-shaped field inversion stop region 26 defines the isolation region 5 for isolating the memory elements in different columns. The width of the drain lines 23 and the line distance between them may be the minimum line width and line distance that can be achieved in a photolithography process. An oxide layer 30 (which may be 500-1,000 angstroms of silicon oxide) is then formed by conventional oxidation or deposition methods (e.g., CVD). Such a structure is shown in fig. 6A to 9A.

A photoresist layer 7 is then formed on the insulating layer 30, and then a mask is used to selectively remove a portion of the photoresist layer, so as to define a plurality of circular openings (openings) 32a on the photoresist layer 7, wherein the surface of the insulating layer 30 is exposed. Each column in which the opening 32a is located is preferably aligned with the center of each drain line 23. An oxide etch step is then performed to remove the portion of the insulating layer 30 not covered by the photoresist layer 7. Then, a silicon etching step is performed using the same photoresist layer 7 as an etching mask to form a plurality of trenches 32 in the substrate 51. A generally known etch such as Reactive Ion Etch (RIE) may be used for the silicon etching step. Thus, the pattern of the opening 32a in the photoresist is replicated or imaged onto the substrate to define the pattern of the trench opening 32 b. Because of the nature of the dry etch, the photoresist opening 32a and the trench opening 32b are substantially identical, and their boundaries substantially overlap each other. The act of etching the substrate continues to define the depth of the trench 32. Trench 32 is deep enough to pass through memory well region 40 and then forms a trench bottom 33 to stop in buried source region 25. In this step, the original photoresist opening 32a on the photoresist layer 7 may be enlarged by Δ W to become a photoresist opening 32c due to the nature of the dry etching. While the photoresist layer 7 is still in place, a self-alignment process may be performed to implant N-type impurities (e.g., arsenic) into the sidewalls 31 and bottom 33 of the trench 32. Appropriate high angle ion implantation may be used to form the drain region 22 surrounding the trench opening 32b, so that a self-aligned drain region 22 is formed. This has the advantage that it is ensured that the drain region 22 of each memory element must be connected to the drain line 23 of the memory array, even if the centre point of the trench opening 32b is not aligned with the middle of the drain line 23 due to process offset. A small angle ion implantation may be used to dope the region near the sidewalls 31 of the trench 32, thereby adjusting the threshold voltage (threshold voltage) of the channel region 21 in the memory device. Such a structure is shown in fig. 6B to 9B. The trench sidewalls 31 may be perfectly vertical to the silicon surface, as in memory element 100a, or somewhat sloped to the silicon surface, as in memory element 100 b. In fig. 6B, the trench opening 32B is shown as circular, but may be of another pattern (e.g., square or rectangular) depending on the photoresist pattern 32 a.

The remaining photoresist layer 7 is removed by a general photoresist stripping method. Next, a high quality liner oxide (liner oxide) layer 28 is formed over the structure. The portion of the liner oxide layer 28 adjacent to the trench sidewall 31 serves as a trench insulator 45, which corresponds to the memory device of the present invention, i.e., the second portion of the first insulating layer 45. Liner oxide layer 28 is a thermal oxide silicon oxide, or HTO silicon oxide, which may be about 80 to 200 angstroms thick. In the same step, a liner oxide layer 28 may also be formed over the insulating oxide layer 30. Next, a polysilicon layer 19 is formed on the liner oxide layer 28 by a generally known process, such as low pressure CVD. This polysilicon layer 19 may be doped in-Situ (in-Situ) during deposition or may be subsequently doped by ion implantation. The thickness of polysilicon layer 19 needs to completely fill trench 32, and may be between 400 and 2000 angstroms depending on the size of the trench and the process technology. The structure at this time is shown in fig. 6C to 9C.

The polysilicon layer 19 is then selectively removed, leaving only the polysilicon in or near the trenches 32. Preferably, the exposed polysilicon surface 19a is substantially aligned with the surface of the liner oxide 28 on the insulating oxide 30. The process may be performed by first polishing the surface of the polysilicon layer 19 by chemical-mechanical polishing (CMP), and then removing a portion of the polysilicon layer by a selective RIE process using the liner oxide layer 28 or the insulating oxide layer 30 as a stop layer (stop layer). If the polysilicon that may remain on the liner oxide layer 28 is to be completely removed, an over-etch step may be performed. Thus, the polysilicon layer 19, after processing, leaves only the bulk polysilicon in the trench 32, automatically aligned with the trench opening. Of course, non-aligned techniques, i.e., having additional lithography and etching processes to define the polysilicon layer, may also serve the same purpose. The technique of automatic alignment is generally a better choice because of the relatively small component sizes that can be achieved. The polysilicon in the trenches 32 is used as the floating gate 20 for the memory element. The structure at this time is shown in fig. 6D to 9D.

Next, a high quality oxide region 29 is formed over the polysilicon floating gate 20 to a thickness of between 50 and 2000 angstroms. The oxide layer in this oxide region is preferably an oxide grown on the exposed polysilicon (floating gate 20) by thermal oxidation. The oxide region 29 is connected to the oxide layer 28 to form an integral insulating layer that entirely covers the periphery and top of the floating gate 20. Another method option that may be used to form high quality oxide is to use a general deposition technique (e.g., LPCVD). Thereafter, a polysilicon layer 14 is formed, by conventional deposition techniques, to a thickness of about 1000 to 2000 angstroms over the entire structure. This polysilicon layer 14 may be heavily doped P-type (e.g., boron). The doping may be performed by ion implantation or by a build-up technique. Next, an insulating layer 35, about 40 to 100 angstroms, is formed over the polysilicon layer 14. The structure at this time is shown in fig. 6E to 9E.

Then, a photolithography process is used to form a plurality of photoresist bars along the second direction (X direction or row direction) on the whole structure. Then, the insulating layer 35 and the polysilicon layer 14 under the stripe regions 18a, which are located between the photoresist stripes and not covered by the photoresist stripes, are removed by a general etching process, as shown in fig. 6F. While the insulating layer 35 and the polysilicon layer 14 remain where the photoresist strips are located. The remaining polysilicon layer 14 becomes a plurality of control gate lines 18. The centerline of each control gate line 18 is preferably aligned with the center point of a row of trenches 32. The line width and line spacing of the control gate lines 18 may be as small as possible, depending on the limits of the photolithography process. The photoresist strips are then removed in a conventional photoresist stripping process. The structure is shown in fig. 6F to 9F, in which the control gate lines 18 and the stripe regions 18a are staggered.

Next, a fourth insulating layer 12 (e.g., silicon nitride) of relatively high thickness (about 1500 angstroms) is formed over the entire structure. Then, a plurality of photoresist bars along the first direction (Y direction or column direction) are formed on the whole structure by a photolithography process. Then, the fourth insulating layer 12 and the insulating layer 35 under the stripe regions between the photoresist stripes, which are not covered by the photoresist stripes, are removed by a general etching process, thereby forming semi-cut grooves (semi-cut trenches) 11a along the Y or column direction, as shown in fig. 6G. While the fourth insulating layer 12 and the insulating layer 35 remain under the photoresist strips. The remaining fourth insulating layer 12 becomes a plurality of silicon nitride lines 11. The line width and line spacing of the silicon nitride lines 11 can be as small as possible, depending on the limits of the photolithography process. The photoresist strips are then removed in a conventional photoresist stripping process. The structure at this time is shown in fig. 6G to 9G, in which the silicon nitride lines 11 and the half-cut groove stripes 11a appear alternately.

A silicon etch process may then be performed, optionally, with a general anisotropic (anistropic) etch technique. For the control gate lines 18, the silicon etch process removes portions of the surface area of the control gate lines 18, leaving tapered or concave surfaces on the control gate lines 18 between the silicon nitride lines 11. Thus, the control gate lines 18 exposed in the half-cut groove 11a form the second portions 17 of the control gate lines 18, and the control gate lines 18 underlying the silicon nitride lines 11 form the first portions 16 of the control gate lines 18. The first portion 16 and the second portion 17 are both connected together. Also, it can be seen that the control gate line 18 crosses over the active region 4 and the isolation region 5, connecting a memory element in one active region 4 with a memory element in another active region 4.

A relatively thin (about 40 to 100 angstroms) insulating layer 34 is then formed on the exposed control gate line 18. In the illustrated embodiment, the insulating layer 34 is a silicon oxynitride layer having an oxygen ratio of about 82%. The formation may be performed, for example, by thermal oxidation followed by thermal nitridation. A known technique is a Plasma-Nitridation (Remote-Nitridation) technique, etc., which may be used to form the insulating layer 34 covering any exposed portion of the control gate line 18. The insulating layers 34 and 35 are connected together to form an overall insulating layer that covers the upper surface of the control gate line 18. The structure at this time is shown in fig. 6H to 9H.

Next, a polysilicon layer 8 is formed over the entire structure. This polysilicon layer 8 may be heavily doped P-type (e.g. boron). The deposition and formation method may use general LPCVD. The doping may be performed by ion implantation or by a build-up technique. The thickness of the polysilicon layer 8 is required to completely fill the half-cut trench 11a, and may be about 400 to 2000 angstroms, depending on the width of the half-cut trench 11a and the process capability. The polysilicon layer 8 is then planarized and then etched back (etch-back) so that the polysilicon surface 8a is preferably aligned with the surface of the silicon nitride line 11. In practice, planarization may be performed by CMP and then etch back by RIE, using the silicon nitride line 11 as an etch stop. An over-etch step may be performed to completely remove polysilicon that may remain on the silicon nitride line 11. Therefore, the polysilicon layer 8 remains only in the half-cut groove 11a, and the polysilicon line 9 extending in the first (Y) direction is formed. Each polysilicon line 9 connects the tunnel gates 10 of memory elements located in the same column. The structure at this time is shown in fig. 6I to 9I.

Then, a general metal silicide (silicide) forming method is used to form a self-aligned metal silicide on the exposed surface of the polysilicon line 9. For example, the conductive layer of silicide 38 may be formed by depositing a metal layer (e.g., tungsten, cobalt, titanium, nickel, platinum, or molybdenum) on the structure, and then annealing (annealing) the metal layer to flow and penetrate into the exposed upper portion of the polysilicon line 9. Silicide 38 may be referred to as a self-aligned silicide (salicide) because it is automatically aligned with poly line 9 and any exposed silicon surface (possibly transistor source drain). The excess metal may be removed by a conventional metal etch process and the resulting structure is shown in fig. 6J through 9J.

The entire structure may be followed by a back end (back) process. The back-end processes may include forming an insulator (e.g., BPTEOS) to cover the entire structure, forming contact holes to appropriately electrically connect the electrodes of the memory elements, filling metal into the contact holes, and forming metal lines as required circuit connections. Finally, a passivation layer (passivation) may be formed on the entire structure, and a bonding pad (bonding pad) may be formed at a desired position.

The above description is only for the preferred embodiment of the present invention, and it is not intended to limit the scope of the present invention, and any person skilled in the art can make further modifications and variations without departing from the spirit and scope of the present invention, therefore, the scope of the present invention should be determined by the claims of the present application.

For example, although the above-mentioned fabrication methods or memory devices use appropriately doped polysilicon as the control gate and tunnel gate of the memory device, it should be understood by those skilled in the art that any conductive material may be used. Therefore, the term "conductive" in the scope of the appended claims covers all substances that can conduct electricity, such as polysilicon, polysilicon metal (polycide), aluminum (aluminum) molybdenum (molybdenum) copper (copper) titanium nitride (titanium nitride), tantalum nitride (tantalum nitride), and the like. Furthermore, any suitable insulator, such as aluminum oxide (alumina oxide), hafnium oxide (hafnium oxide), zirconium nitride (zirconia nitride), tantalum pentoxide (tantlumpnent oxide), etc., may be used in place of silicon oxide, silicon oxynitride or silicon nitride. In addition, materials with different material properties than silicon oxide or polysilicon may be used instead of silicon nitride. Furthermore, not all steps in a method claim must be performed in exactly the order listed, but may be performed in any order as long as the memory device of the present invention can be manufactured, as defined by the scope of the claims. The control gate lines, tunnel gate lines, drain lines, and buried source lines are not limited to a fixed width or shape, nor are they limited to a straight line, and their cross-sectional views are not limited to rectangles, but rather any sizes or shapes, as long as they can effectively connect the memory elements in the rows and columns. The cross-sectional view of the floating gate is not limited to a rectangle, the top view of the floating gate is not limited to a circle, and the cross-sectional view or the top view can be any size or shape as long as the floating gate can effectively store charges and effectively control the connection of the drain region and the source region. In addition, the upper surface of the floating gate is not limited to be flush with the substrate surface, but may be higher or lower than the substrate surface as long as the floating gate can effectively store charges, effectively couple with the control gate, and effectively control the connection of the drain region and the source region. The bottom of the floating gate is not limited to be located in the buried source region, but may be located in the body as long as the floating gate can effectively store charges, effectively couple with the control gate, and effectively control the connection of the drain region and the source region. In addition, the source and drain regions, the source and drain lines may be reversed. Although the body is shown as being uniformly doped, it should be understood by those skilled in the art that the various doped regions (source, drain, channel, and memory well regions 40, etc.) formed in the body may be formed in one or more well regions of a different conductivity type than the memory well regions. In addition, the tunnel insulating layer, the trench insulating layer and the pinning insulating layer are not limited to silicon oxide, silicon nitride or silicon oxynitride, and any suitable insulating material may be used, such as aluminum oxide, hafnium oxide, zirconium nitride, tantalum pentoxide, etc., or any composite layer may be used, such as a combination of a silicon oxide layer and an aluminum oxide layer, or a combination of a silicon oxide layer and a zirconium oxide layer, etc. Finally, the isolation region is not limited to a constant width or shape, is not limited to a straight line, is not limited to field oxide (STI or LOCOS), is not limited to junction isolation technology, but any isolation structure that can effectively separate the active regions of memory cells in different rows.

The symbols in the drawings are briefly described as follows:

1-3: memory element

4: active region

5: isolation zone

7: photoresist layer

8: polycrystalline silicon layer

9: polysilicon line

10: tunnel grating

11: silicon nitride line

11 a: half-cut groove strip

12: a fourth insulating layer

13: half-cut groove

14: polycrystalline silicon layer

15: control grid

16: the first part

17: the second part

18: control grid line

18 a: strip-shaped area

19: polycrystalline silicon layer

20: floating gate

21: channel region

22: drain region and second heavily doped region

23: drain line

24: source region, first heavily doped region

25: first region, buried source line

26: field inversion termination region

28: liner oxide layer

29: a second insulating layer

30: insulating layer

31: trench sidewall

32: groove

32 a: opening of the container

32 b: trench opening

32c, the ratio of: photoresist opening

33: bottom of the groove

34: the second part

35: the first part

36: a third insulating layer

38: silicide

40: memory well region and semiconductor layer

43: the first part

44: a first insulating layer

45: second portion, trench insulator

50: basic rest

51: substrate

52: tunnel gate region

56: tunnel insulating layer

59: barrier height

60: barrier height

62: impact transfer gate region

67: pinned insulating layer

68: conductive tape

69: price electricity belt

70: barrier height

70 a: barrier height

70 b: distance between two adjacent plates

71: barrier height

71 a: barrier height

71 b: distance between two adjacent plates

72: floating gate region

76: electronic device

80: cavities of the wafer

82: reverse tunneling electron carriers

83: conduction band electron

90: kinetic energy

90 a: additional energy

92: kinetic energy

92 a: additional energy

100a to 100 e: memory element

100 f: memory array

Claims

1. An erasable and programmable read-only memory device, said read-only memory device comprising:

a substrate;

a first layer of semiconductor of a first conductivity type over the substrate;

a first region formed between the substrate and the first layer and having a second conductivity type;

a trench formed on a surface of the first layer and having a sidewall and a bottom;

a second region of the second conductivity type formed in the first layer and laterally adjacent to an upper half of the trench;

a trench region in the first layer between the first region and the second region formed along the sidewall of the trench;

a conductive floating gate adjacent to and insulated from the channel region;

a conductive control gate, a portion of which is disposed over and insulated from the floating gate; and

a conductive tunnel gate is disposed over a portion of the control gate and is insulated from the control gate.

2. The erasable and programmable read-only memory element of claim 1, wherein:

the sidewall of the trench is perpendicular to the surface of the first layer, and the bottom of the trench is parallel to the surface of the first layer.

3. The erasable and programmable read-only memory element of claim 1, wherein:

the trench penetrates the second region and the first layer, and the bottom of the trench is formed in the first region.

4. The erasable and programmable read-only memory element of claim 1, wherein:

the trench penetrates the second region, the first layer and the first region, and the bottom of the trench is formed in the substrate.

5. The erasable and programmable read-only memory element of claim 1, wherein:

the first insulating layer has a first part set on the second area and the first layer and a second part set on the bottom of the groove and adhered to the side wall of the groove.

6. The erasable and programmable read-only memory element of claim 1, wherein:

the control gate and the tunnel gate are mutually overlapped in an overlapping region; and

at least a portion of the floating gate is disposed below the overlap region.

7. The erasable and programmable read-only memory element of claim 1, wherein said control gate has:

a first portion, insulated on at least a portion of the second region and a surface of the first layer; and

and a second portion, which is insulated from a surface of the floating gate.

8. The erasable and programmable read-only memory element of claim 7, wherein:

an insulating layer is interposed between the tunnel gate and the control gate, the insulating layer having a thickness sufficient to allow quantum-mechanical tunneling electrons to pass therethrough.

9. The erasable and programmable read-only memory element of claim 8, wherein:

the insulating layer is a silicon oxynitride layer, wherein the proportion of oxygen in nitrogen is between 70% and 90%.

10. The erasable and programmable read-only memory element of claim 8, wherein:

the control gate is a metal having a work function with a fermi level centered in the band gap of the insulating layer.

11. The erasable and programmable read-only memory element of claim 1, wherein:

a portion of the control gate has a thickness that allows the passage of the impinging charge therethrough.

12. The erasable and programmable read-only memory element of claim 1, wherein:

the tunnel gate is a heavily P-doped semiconductor material.

13. The erasable and programmable read-only memory element of claim 1, wherein:

the control gate is a P-type heavily doped semiconductor material.

14. An array of erasable and programmable read-only memory cells, comprising:

a substrate;

a first layer of semiconductor of a first conductivity type over the substrate;

a plurality of separated isolation regions formed in the first layer, parallel to each other, extending in a first direction, each two adjacent isolation regions having an active region; and

a plurality of spaced apart drain lines extending in the first direction, each drain line formed in at least a portion of the active region and adjacent to the surface of the first layer;

each active region has a plurality of memory elements, each memory element comprising:

a conductive floating gate adjacent to and insulated from the channel region;

and the conductive tunnel gate is arranged on one part of the control gate and is insulated from the control gate.

15. The array of erasable and programmable read only memory cells of claim 14, further comprising:

the array of trenches includes a plurality of rows extending in a first direction and columns extending in a second direction perpendicular to the first direction.

16. The array of erasable and programmable read only memory cells of claim 14, further comprising:

and a plurality of control gate lines spaced apart and parallel to each other, each extending in a second direction perpendicular to the first direction, crossing over the active region and the isolation region, and electrically connected to the control gates of the memory device.

17. The array of erasable and programmable read only memory cells of claim 14, further comprising:

18. The array of erasable and programmable read-only memory elements of claim 14, wherein:

for each memory element, the control gate and the tunnel gate overlap each other in an overlap region; and

at least a portion of the floating gate is disposed below the overlap region.

19. The array of erasable and programmable read-only memory elements of claim 14, wherein:

the second region is electrically connected to at least a portion of one of the drain lines.

20. The array of erasable and programmable read only memory cells of claim 14, further comprising:

21. The array of erasable and programmable read-only memory elements of claim 14, wherein:

for each memory element, the trench passes through the second region and the first layer, and the bottom of the trench is formed in the first region.

22. A method of forming an erasable and programmable read only memory device, comprising the steps of:

forming a first layer of semiconductor over a substrate having a first conductivity type;

forming a first region of a second conductivity type between the substrate and the first layer;

forming a trench on a surface of the first layer, the trench having a sidewall and a bottom;

forming a second region of the second conductivity type in the first layer laterally adjacent to an upper half of the trench;

forming a trench region in the first layer between the first region and the second region along the sidewall of the trench;

forming a conductive floating gate adjacent to and insulated from the channel region;

forming a conductive control gate, a portion of which is disposed over and insulated from the floating gate; and

a conductive tunnel gate is formed over a portion of the control gate and insulated from the control gate.

23. The method of claim 22, further comprising:

24. The method of claim 22, further comprising:

25. The method of claim 22, further comprising:

at least a portion of the floating gate is disposed below the overlap region.

26. The method of claim 22 wherein said control gate has:

and a second portion, which is insulated from a surface of the floating gate.

27. The method of claim 26, further comprising:

an insulating layer is formed between the tunnel gate and the control gate, the insulating layer having a thickness sufficient to allow quantum-mechanical tunneling electrons to pass through.

28. The method of claim 27, further comprising:

29. The method of claim 27, further comprising:

30. The method of claim 22, further comprising:

31. The method of claim 22, further comprising:

the tunnel gate is a heavily P-doped semiconductor material.

32. The method of claim 22, further comprising:

the control gate is a P-type heavily doped semiconductor material.

33. A method of forming an array of erasable and programmable read only memory cells, comprising:

forming a plurality of spaced-apart isolation regions in a first layer of semiconductor, the first layer being of a first conductivity type overlying a substrate, the isolation regions being parallel to one another and extending in a first direction, each two adjacent isolation regions having an active region;

forming a plurality of separate drain lines extending in the first direction, each drain line being formed in at least a portion of the active region and adjacent to the surface of the first layer;

forming a plurality of trenches in the surface of the first layer, the trenches being arranged in an array, the columns of the array extending in the first direction, the rows of the array extending in a second direction perpendicular to the first direction, each trench having a sidewall and a bottom;

forming a plurality of first regions of a second conductivity type between the substrate and the first layer;

forming a plurality of second regions in the first layer, each second region laterally adjacent to an upper half of one of the trenches and having the second conductivity type;

forming a plurality of channel regions in the first layer, each channel region being between one of the first regions and one of the second regions and formed along the sidewall of one of the trenches;

forming a plurality of conductive floating gates, each floating gate being insulated adjacent to one of the channel regions;

forming a plurality of conductive control gates, a portion of each control gate being disposed on one of the floating gates in an insulated manner; and

a plurality of conductive tunnel gates are formed, each tunnel gate being insulated over a portion of the control gate.

34. The method of claim 33 further comprising:

and forming a plurality of separated and parallel control grid lines, wherein each control grid line extends in a second direction perpendicular to the first direction, crosses the active region and the isolation region and is electrically connected to part of the control grid.

35. The method of claim 33 further comprising:

36. The method of claim 33 for forming an array of erasable and programmable read only memory cells, wherein:

each control grid and a corresponding tunnel grid are mutually overlapped in an overlapping region; and

37. The method of claim 33 for forming an array of erasable and programmable read only memory cells, wherein:

each of the second regions is electrically connected to at least a portion of one of the drain lines.

38. The method of claim 33 further comprising:

39. The method of claim 33 for forming an array of erasable and programmable read only memory cells, wherein:

each trench penetrates through one of the second regions and the first layer, and the bottom of each trench is formed in one of the first regions.

40. An operating method of an erasable and programmable read only memory (EEPROM) device, the operating method comprising:

the device has a conductive floating gate formed in a trench in a semiconductor substrate of a first conductivity type; a conductive control gate having a portion thereof disposed over the floating gate; a conductive tunnel gate, which is disposed on a portion of the control gate with an insulating layer therebetween, to form a multi-layered structure, thereby allowing electrons and holes to tunnel through the insulating layer at a similar rate; separate source and drain regions of a second conductivity type, the source region being adjacent to but insulated from a lower portion of the floating gate and the drain region being adjacent to but insulated from an upper portion of the floating gate; and a channel region formed between a well region of the first conductivity type and extending to a sidewall of the trench,

imparting a positive voltage to the drain region to couple a positive voltage to the floating gate; and

the tunnel gate is given a voltage which is negative with respect to a voltage of the control gate and strong enough to cause the tunnel gate to emit electrons and holes from the control gate and to cause the electrons and holes to cross the insulating layer at similar rates but in opposite directions and to have sufficient energy to cross the control gate through an impinging carrier transport mechanism to the floating gate.

41. The method of claim 40 further comprising:

the tunnel gate is given a voltage which is positive with respect to a voltage of the control gate and strong enough to cause the tunnel gate to emit holes and electrons from the control gate and to cause the electrons and holes to cross the insulating layer at a similar rate but in opposite directions and to cause the holes to have sufficient energy to cross the control gate through an impinging carrier transport mechanism to the floating gate.

42. An operating method of an erasable and programmable read only memory (EEPROM) device, the operating method comprising:

the device has at least two states, the device has a conductive floating gate formed in a trench of a semiconductor substrate; a conductive control gate having a portion thereof disposed over the floating gate; a conductive tunnel gate, which is disposed on a portion of the control gate through an insulating layer to form a multi-layered structure, thereby allowing electrons and holes to tunnel through the insulating layer at a similar rate; separate source and drain regions adjacent to but insulated from the floating gate; and a channel region defined between the source and drain regions, insulated from the floating gate,

establishing one of the states of the device by emitting electrons from the tunnel gate and holes from the control gate such that the electrons and holes traverse the insulating layer at a similar rate but in opposite directions and have sufficient energy to traverse the control gate through an impinging carrier transport mechanism to the floating gate; and

the other of the states of the device is established by emitting holes from the tunnel gate and electrons from the control gate so that the electrons and holes cross the insulating layer at a similar rate but in opposite directions and so that the holes have sufficient energy to cross the control gate through an impinging carrier transport mechanism to the floating gate.