KR100594384B1 - Non-volatile memory device - Google Patents

Abstract

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device having an injection gate having excellent durability and retention characteristics.

The object of the invention is a plurality of active regions disposed side by side on a semiconductor substrate; A plurality of control gates across the active region; A floating gate formed between the respective active regions and the respective control gates; An injection gate formed below one side of the floating gate; A block oxide film interposed between the control gate and the floating gate; A source region formed under one side of the floating gate; A drain region formed under one side of the injection gate; And a bit line contact formed in the drain region.

Accordingly, in the nonvolatile memory device of the present invention, the floating gate has an injection gate having a self-converging erase characteristic, thereby effectively configuring and operating a multi-level bit-nor flash array, thereby achieving various effects.

NOR Flash Array, Injection Gate, Self-Convergence, Floating Gate, Hot Electron Injection, Endurance, Retention

Description

Non-volatile memory device             

1 is a cross-sectional view of a flash memory cell according to the prior art.

2 to 6 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

7 is a cell array of a nonvolatile memory device in accordance with the present invention.

8 is a cell layout of a nonvolatile memory device according to the present invention.

FIG. 9 is a cross-sectional view taken along the line AA ′ of FIG. 8; FIG.

10 is a cross-sectional view when cutting in the direction BB ′ of FIG. 8.

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device having an injection gate having excellent durability and retention characteristics.

In general, semiconductor memory devices are classified into volatile memory and non-volatile memory. Most of volatile memory is occupied by RAM such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and data can be input and stored when power is applied, but data cannot be saved because of volatilization when power is removed. Has On the other hand, nonvolatile memory, which is mostly occupied by ROM (Read Only Memory), is characterized in that data is preserved even when power is not applied.

At present, in terms of process technology, a nonvolatile memory device is classified into a floating gate series and a metal insulator semiconductor (MIS) series in which two or more kinds of dielectric layers are stacked in a double or triple layer.

Floating gate series memory devices use potential wells to implement memory characteristics, and the simple stack-type EPROM Tunnel Oxide (ETOX), which is currently widely used as a flash electrically erasable programmable read only memory (EEPROM). And a split gate structure in which one transistor includes two transistors.

On the other hand, the MIS series performs a memory function by using traps present at the dielectric bulk, the dielectric film-dielectric film interface, and the dielectric film-semiconductor interface. A typical example is the MONOS / SONOS (Metal / Silicon ONO Semiconductor) structure, which is mainly used as a flash EEPROM.

Referring to FIG. 1, a method of manufacturing a flash memory cell of the prior art is briefly described. Is used as a floating gate. A dielectric layer 15 and a second polysilicon layer 16 are formed on the floating gate 13 to use the second polysilicon layer 16 as a control gate. The metal layer 17 and the nitride film 18 are formed on the control gate 16 and patterned in a cell structure to form a flash memory cell.

In the conventional flash memory cell as described above, the floating gate and the control gate are formed in the form of a flat plate. However, in the flash memory, it is very important to improve the erase and program characteristics of the device that the potential of the control gate is well transferred to the floating gate. In the program operation using the hot carrier of the flash memory, 0 V is applied to the source, 5 V is applied to the drain, and 9 V is applied to the control gate, and the voltage applied to the control gate is applied to the gate oxide layer as it is through the floating gate. Creating an electric field allows hot electrons to be injected into the floating gate more quickly. On the contrary, during the erase operation, -7V is applied to the control gate and about 5V to the source, and electrons in the floating gate are released to the source by Fowler-Nordheim (FN) tunneling, and the capacitance between the control gate and the floating gate is large and If the capacitance between the substrates is small, the floating gate can be kept at a lower voltage, which can release more electrons toward the source, which can speed up the erase operation. As a result, the operation becomes faster as the voltage of the floating gate becomes closer to the voltage of the control gate during the program operation or the erase operation.

As a method of improving program and erase characteristics of a semiconductor device, there is a method of using a high dielectric constant material as a dielectric layer between a floating gate and a control gate. However, these methods have a lot of technical areas to be developed.

In the conventional nonvolatile device, as the programming process is performed by hot electron injection, hot electrons trap the interface between the tunnel oxide film and the silicon substrate, the tunnel oxide film, or between the tunnel oxide film and the floating gate interface. Sites are created and these trap sites cause threshold voltages to change. In addition, the trap site serves as a passage through which the stored charges are discharged, and thus the stored charge is quickly lost. That is, there is a problem in endurance characteristics and retention characteristics.

Accordingly, the present invention is to solve the problems of the prior art as described above, using an injection gate having excellent durability characteristics and retention characteristics and having a self-converging erasure characteristic capable of converging an erasure threshold voltage to a predetermined value. Accordingly, an object of the present invention is to provide a non-volatile memory device for effectively implementing a program, erase, and read operation by configuring a NOR flash cell array.

The object of the invention is a plurality of active regions disposed side by side on a semiconductor substrate; A plurality of control gates across the active region; A floating gate formed between the respective active regions and the respective control gates; An injection gate formed below one side of the floating gate; A block oxide film interposed between the control gate and the floating gate; A source region formed under one side of the floating gate; A drain region formed under one side of the injection gate; And a bit line contact formed in the drain region.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

2 to 6 are process cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

First, as shown in FIG. 2, the pad oxide film 102 and the nitride film 103 are sequentially grown or deposited on the P-type silicon substrate 101, and then the nitride film is patterned. When the nitride layer is patterned, the nitride layer is left only in the drain region of the nonvolatile memory device and all nitride layers in the remaining region are removed. The nitride film may be replaced with an oxide film or another insulating film, and the nitride film is preferably deposited to a thickness of 500 to 2500 kPa.

Next, as shown in FIG. 3, an injection gate is formed. After removing all of the pad oxide film remaining in the nitride-etched region, the tunnel oxide film 105 is grown to a thickness of 50 kPa to 120 kPa through an oxidation process. Subsequently, in order to form the injection gate, an injection gate film having a band gap larger than that of the silicon substrate and smaller than the tunnel oxide layer (SiO ₂ ) is deposited to a thickness of 100 μs to 1000 μs on the entire surface of the substrate. The injection gate film is deposited on the entire surface of the wafer, and an injection gate 104 in the form of a sidewall is formed on the sidewall of the nitride film by anisotropic blanket etching. The injection gate film may be used as long as the band gap is larger than 1.1 eV and smaller than 9.0 eV, and more preferably Al ₂ O ₃ , Y ₂ O ₃ , HfO ₂ , ZrO ₂ , BaZrO ₂ , and BaTiO _3. , Ta ₂ O ₅ , CaO, SrO, BaO, La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O _3, or an oxide film such as Lu ₂ O ₃ and SiC, AlP, AlAs, AlSb, GaP, Compound semiconductors such as GaAs, InP, ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe and the like can be used.

Next, as shown in FIG. 4, the first polysilicon, the block oxide film, and the second polysilicon are deposited. A floating gate polysilicon 106 is deposited on the entire surface of the wafer, and a block oxide layer 107 is formed on the polysilicon. Subsequently, poly silicon 108 for the control gate is deposited on the block oxide layer. The polysilicon for the floating gate and the polysilicon for the control gate are both polysilicon doped with N-type impurities or doped into N-type after deposition. Since the tunnel oxide film may be damaged when the injection gate is formed, the remaining tunnel oxide film may be removed and deposited again before depositing the polysilicon for the floating gate. The block oxide film is composed of a first block oxide film 107a and a second block oxide film 107b, wherein the first block oxide film is Al ₂ O ₃ or Y ₂ O ₃ , and the second block oxide film is SiO _2. Use The thickness of the block oxide film is determined by the threshold voltage of the erase to be converged and the thickness of the tunnel oxide film. Preferably, the first block oxide film is deposited to a thickness of 50 to 250 kW and the second block oxide film is 20 to 150 kW.

Next, as shown in FIG. 5, the second polysilicon, the block oxide film, the first polysilicon, and the nitride film are etched to form a source / drain extension region. After the photoresist is coated and patterned on the control silicon polysilicon, the control gate polysilicon, the block oxide film and the floating gate polysilicon are etched using the patterned photoresist as an etch mask to form a floating gate and a control gate. Form. Next, the nitride film remaining between the injection gates is removed. The nitride film is removed by dry etching or wet etching using phosphoric acid. Subsequently, an N-type impurity is implanted into the substrate to form a source / drain extension region 109.

Next, as shown in FIG. 6, sidewall spacers and source / drain regions are formed. The oxide layer 110 and the nitride layer 111 are sequentially deposited on the substrate to form sidewall spacers, and then sidewall spacers are formed through anisotropic etching. Subsequently, the source and drain regions 112 are formed by implanting N-type impurities into the gate and sidewall spacers using an ion implantation mask.

FIG. 7 illustrates a multi-level bit NOR type nonvolatile memory cell array using a nonvolatile memory device having a self-convergence erase function.

Table 1 shows the voltages applied to each word line (control gate), bit line, common source, and body in the case of selectively programming and reading the cell indicated by 201 in the figure and erasing by block unit.

division WL1 WL2 WL3 WL4 BL1 BL2 BL3 BL4 Source Body Program 0 Vwlp 0 0 0 0 Vblp 0 0 0 Erase1 -Vwle -Vwle -Vwle -Vwle F F F F F 0, Vb Erase2 -Vwle -Vwle -Vwle -Vwle F F F F 0, Vs F Read 0 Vref 0 0 0 0 Vblr 0 0 0

In the case of selectively programming, the word line applies Vwlp [V] only to WL2 and 0 [V] to the remaining word lines WL1, WL3, and WL4. The bit line applies Vblp [V] only to BL3 and 0 [V] to the remaining bit lines BL1, BL2, and BL4. 0 [V] is applied to both common source and body. The bit line voltage applied to the drain under the program bias condition is all drains to which BL3 is contacted, and the word line voltage applied to the control gate is formed along the WL2 line, so only 201 cells are simultaneously applied to the drain and the control gate. When the current flows from the drain of the 201 cell to the common source, electrons are injected into the injection gate by hot electron injection, and electrons injected into the injection gate move to the potential well of the floating gate, thereby increasing the threshold voltage. . Here, Vblp and Vwlp respectively applied to the bit line and the word line during the program operation are thermal electron injection efficiency, drain junction breakdown, gate disturb, program voltage, and drain stub ( The figures are optimized by various factors such as disturb.

There are two methods of erasing: F / N tunneling electrons from the floating gate toward the channel and F / N tunneling electrons from the floating gate toward the source.

Ease 1 in Table 1 shows a bias condition when electrons are tunneled out of the floating gate toward the channel. Apply -Vwle [V] to the word lines WL1, WL2, WL3, and WL4, apply 0 [V] or Vb [V] to the body, and float the remaining bit lines BL1, BL2, BL3, BL4, and all common sources. Let's do it. Therefore, a strong electric field is applied from the channel to the control gate, and the electrons trapped in the potential well of the floating gate are exited to the silicon substrate by F / N tunneling by the strong electric field applied to the control gate, thereby reducing the threshold voltage. In addition, electrons are MFN tunneled from the control gate to the floating gate in the second half of the erasure operation through the structure of the first block oxide film and the second block oxide film so that electrons can escape from the floating gate to the P-type substrate or holes from the P-type substrate to the floating gate. By compensating for the injection, the threshold voltage in the erased state converges to a constant value.

Erase 2 of Table 2 shows a bias condition when the electrons are F / N tunneled out from the floating gate toward the source. -Vwle [V] is applied to the word lines WL1, WL2, WL3, and WL4, 0 [V] or Vs [V] is applied to the common source, and the remaining bit lines BL1, BL2, BL3, and BL4 are all floating. Let's do it. Therefore, a strong electric field is applied from the source to the control gate, and the electrons trapped in the potential well of the floating gate are exited to the source by F / N tunneling by the strong electric field applied thereto, thereby reducing the threshold voltage. In this case as well, electrons are MFN tunneled from the control gate to the floating gate through the first block oxide film and the second block oxide structure in the second half of the erasure operation, and electrons are ejected from the floating gate to the source or holes are injected from the source to the floating gate. By compensating for this, the threshold voltage in the erased state is converged to a constant value.

The read applies Vref to WL2, Vblr to BL3, and applies 0 [V] to all the remaining word lines WL1, WL3, and WL4, the bit lines BL1, BL2, and BL4, the common source, and the body. If the 201 cell is erased under the read bias condition, current flows from the BL3 to the common source, and if the program state is current, the current does not flow from the BL3 to the common source to detect each program / erase state. Vref applied to WL2 during a read operation usually selects a voltage that is halfway between the highest voltage of the erased threshold voltage and the lowest voltage of the programmed voltage threshold. In the case of the voltage applied to the bit line during the read operation, if the voltage of the bit line is too high, the program operation may proceed to the cell to be read. In this case, a voltage that is low enough so that the program operation does not proceed is applied.

8 illustrates a cell layout of a nonvolatile memory device according to the present invention. A plurality of parallel active regions 301 are disposed on the semiconductor substrate. The active regions are separated by the device isolation layer 302. A plurality of control gate electrodes 303 cross over the active regions. A floating gate 305 is provided between each active region and each control gate. An injection gate 304 is provided between one side lower portion of each floating gate and the active region. A drain region exists in the semiconductor substrate between each injection gate, and a bit line contact 307 exists in a predetermined portion of the drain region. The injection gate is adjacent to the bit line contact. A bit line is disposed over the active region with an interlayer insulating layer interposed therebetween. A block oxide film is interposed between the floating gate and the control gate electrode, and a tunnel oxide film is interposed between the floating gate and the active region. The structure formed as described above is configured in a symmetrical form with respect to the drain region. The block oxide film is composed of a first block oxide film and a second block oxide film.

FIG. 9 is a cross-sectional view when the unit cell 308 of FIG. 8 is cut in the bit line direction A-A '. On the silicon substrate 401 is a tunnel oxide film 402, a floating gate 404, an injection gate 403, a block oxide film 405 and a control gate 406. The common source region 408 and the drain region 407 are formed in the semiconductor substrates on both lower sides of the control gate. Bit line contacts 409 are formed in the drain region, and the bit line contacts are all connected by one metal bit line 410.

FIG. 10 is a cross-sectional view when the unit cell 308 of FIG. 8 is cut in the word line direction B-B '. The tunnel oxide layer 503, the floating gate 504, and the block oxide layer 505 are disposed on the silicon substrate active region 501, and the active region is separated by the device isolation layer 502. The block oxide film and the word line 506 surround the separated tunnel oxide film and the floating gate.

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Accordingly, in the nonvolatile memory device of the present invention, the floating gate includes an injection gate having self-convergence erase characteristics, thereby effectively configuring and operating a multi-level bit-nor flash array.

First, unlike a conventional floating gate device, an injection gate is used to inject hot electrons through a tunnel oxide film positioned below the injection gate to inject electrons into the conduction band of the injection gate through the tunnel oxide film under the injection gate. It effectively improves the durability and retention characteristics of the device by separating the tunnel oxide film into which the thermal energy is injected and the tunnel oxide film which stores real electrons and flows into the potential well of the floating gate, which is a stable energy level. You can.

Second, electrons escape from the floating gate to the P-type substrate by MFN tunneling from the control gate to the floating gate at the end of the erasure operation using the first block oxide film and the second block oxide film instead of ONO of the conventional floating gate device. Or by compensating for the injection of holes from the P-type substrate into the floating gate, the threshold voltage in the erased state is converged to a constant value to prevent the overlaid problem and the distribution of the erased state threshold voltage is narrowed, thereby making the wide erase threshold The problem that the threshold voltage window is reduced by the voltage distribution can be improved.

Since the dielectric constants of Al ₂ O ₃ and Y ₂ O ₃ used as the third block oxide film are 9 and 17, respectively, larger than the nitride film (SiN) of about 7.5, the first block oxide film and the second block than the ONO layer are used. Using an oxide film has a higher coupling ratio, which effectively reduces the voltage applied to the control gate.

Claims (10)

A plurality of active regions disposed side by side on the semiconductor substrate; A plurality of control gates across the active region; A floating gate formed between the respective active regions and the respective control gates; An injection gate formed below one side of the floating gate; A block oxide film interposed between the control gate and the floating gate; A source region formed under one side of the floating gate; A drain region formed under one side of the injection gate; And A bit line contact formed in the drain region Non-volatile memory device comprising a. The method of claim 1, And a tunnel oxide layer between the floating gate and the active region. The method of claim 1, The nonvolatile memory device may be symmetrical with respect to the drain region. The method of claim 2, The tunnel oxide film is a nonvolatile memory device, characterized in that the SiO ₂ having a thickness of 60 ~ 120Å. delete The method of claim 1, The injection gate is Al ₂ O ₃ , Y ₂ O ₃ , HfO ₂ , ZrO ₂ , BaZrO ₂ , BaTiO ₃ , Ta ₂ O ₅ , CaO, SrO, BaO, La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ and Lu ₂ O ₃ A non-volatile memory device, characterized in that the material. The method of claim 1, The injection gate is a non-volatile memory device, characterized in that any one of SiC, AlP, AlAs, AlSb, GaP, GaAs, InP, ZnS, ZnSe, ZnTe, CdS, CdSe and CdTe. The method of claim 1, And the block oxide film comprises a first block oxide film and a second block oxide film. The method of claim 8, And the first block oxide layer is Al ₂ O ₃ or Y ₂ O ₃ having a thickness of 50 to 250 microns. The method of claim 8, And the second block oxide layer is SiO ₂ having a thickness of 20 to 150 GPa.

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