CN116913976A - Low-voltage durable high-retention feedback type floating gate transistor and preparation method thereof - Google Patents
Low-voltage durable high-retention feedback type floating gate transistor and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
The invention discloses a low-voltage durable high-retention feedback type floating gate transistor and a preparation method thereof, and belongs to the technical field of integrated circuit manufacturing. In the floating gate transistor, the floating gate layer forms an FBFET in the horizontal plane along the direction of the vertical channel, and the barrier type can be p + ‑n + ‑i(p ‑ )‑n + Or n + ‑p + ‑i(n ‑ )‑p + The floating gate layer is used as one end of the floating gate layer and is led out of i (p ‑ ) Terminal or i (n) ‑ ) The terminal performs gate control of the FBFET; may also be p + ‑i‑n + Or n + ‑i‑p + At this time, the two ends of the i region need to be led out to gate the FBFET. The invention utilizes repeated reduction of junction potential barrier to form positive feedback to realize transverse charge injection and release, reduces operation voltage and improves writing speed; the programming and erasing paths do not pass through the dielectric layer between the floating gate and the channel, and the durability is improvedSex; low leakage and high retention characteristics of data can be achieved with the double barrier of FBFETs. Based on the characteristics, the feedback type floating gate transistor has the potential of being applied to a large-scale low-power-consumption high-speed high-reliability nonvolatile memory.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a feedback type floating gate transistor with low-voltage injection, high durability and high charge holding capacity and a preparation method thereof, wherein the feedback type floating gate transistor is applied to a low-power consumption high-speed high-reliability nonvolatile memory.
Background
Memory devices are one of three major pillars in the semiconductor industry, and can be divided into Volatile (Volatile) memory and Non-Volatile (Non-Volatile) memory. The Flash Memory (Flash Memory) is also called as Flash Memory, has the advantages of low cost, high integration level, large capacity and the like, and is one of the most widely applied nonvolatile memories at present.
The flash memory device can be divided into a floating gate type flash memory (Floating Gate Flash) and a charge trapping type flash memory (Charge Trap Flash) according to the cell structure, wherein the cell structure of the floating gate type flash memory is a floating gate field effect transistor (Floating Gate Field-effect Transistor). Conventional floating gate transistors are based on FN (Fowler-Nordheim) tunneling injection mechanisms, which change channel current by applying a voltage at the control gate terminal to excite carriers in the channel to inject into the floating gate, thereby implementing the programming function of the memory. The injection current of FN tunneling depends on the electric field on the tunneling oxide layer, so that the traditional floating gate transistor has high operation voltage (about 10V) and slow writing speed (about 1 ms). During the cyclic program erase process, defects and damages are generated in the tunnel oxide layer and its interface, which results in the degradation of the endurance of the floating gate transistor (10 4 -10 6 Secondary). As process dimensions continue to shrink, thinning of the tunnel oxide layer also directly affects the charge retention characteristics.
In recent years, industry technology is continuously innovated, the application demands of the market on low voltage, high speed and high reliability are also higher and higher, and new memories are continuously emerging, but various problems exist. Accordingly, there is a need to develop and research floating gate memory devices with high injection efficiency, high endurance, and high charge retention.
Disclosure of Invention
In view of the above problems, the present invention provides a low-voltage durable high-retention feedback type floating gate transistor. The floating gate layer of the transistor forms FBFET (Feedback FET) in its horizontal plane along the direction of the vertical channel, and the barrier type of the FBFET can be p + -n + -i(p - )-n + The floating gate layer is used as one end of the floating gate layer and is led out of i (p - ) The terminal performs gate control of the FBFET; may also be p + -i-n + At this time, the two ends of the region i need to be led out for carrying outGating of FBFETs. The existence of double potential barrier under no bias blocks the injection of carriers to p + -n + -i-n + For example, when a voltage is applied to the control gate terminal of a floating gate transistor, the floating gate terminal (e.g., p + ) And adjacent n + The energy of the conduction band and the valence band of the region is reduced, holes in the floating gate are injected into the potential well and accumulated, the height of an electric potential barrier in the conduction band of the gate control region (i region) of the FBFET is further reduced, electrons are injected into the potential well, positive feedback is formed by repeatedly reducing the potential barrier to finish injection, and after writing is finished, the stored charges are pulled up through the energy band of the gate control region (i region) of the FBFET. Compared with the traditional mode that channel carriers are vertically injected into the floating gate through FN tunneling, the method and the device realize transverse charge injection and release by repeatedly reducing the junction barrier, and have low junction starting voltage, low operation voltage and high writing speed; the operation does not pass through a tunneling oxide layer (namely a dielectric layer of a floating gate and a channel), so that the durability is improved; the double potential barrier of the FBFET is utilized for charge storage, so that low leakage is realized, and the retention characteristics of data are enhanced.
The invention provides a low-voltage durable high-retention feedback type floating gate transistor, which comprises a semiconductor substrate, a source region, a drain region, a channel region, a floating gate dielectric layer, a floating gate blocking layer, a control gate, isolation layers and metal lead-out layers at all ends, wherein the floating gate layer forms an FBFET barrier region in the horizontal plane along the direction perpendicular to the channel, and the barrier type of the FBFET can be p from the floating gate to the outside + -n + -i(p - )-n + Region or n + -p + -i(n - )-p + A region, a floating gate layer as one end of the FBFET, and led out of i (p - ) Terminal or i (n) - ) An end; the barrier type of the FBFET can also be p-type from floating gate to floating gate + -i-n + Region or n + -i-p + Region i needs to be led out from two ends, one of which is close to p + Region with the other end near n + A zone.
Forming a conventional shallow trench isolation (Shallow Trench Isolation, STI) and an active region on a semiconductor substrate, and then forming a source region and a drain region within the active region, and a lightly doped channel region connecting the two; a floating gate dielectric layer, a floating gate blocking layer and a control gate are sequentially arranged on the channel region; the floating gate layer forms an FBFET barrier region along the direction of the vertical channel in the horizontal plane and forms a gate end of the FBFET, and the floating gate layer is used as a drain end of the FBFET; the FBFET (drain terminal, i.e., except floating gate) is not on the channel region, independent of the control gate and source and drain regions of the semiconductor substrate active region; the isolation layer covers the surface of the transistor device, and the metal lead-out layer passes through the isolation layer through the through holes to form metal lead-out wires connected to the source region, the drain region, the control gate and the gate end of the FBFET of the semiconductor substrate active region respectively.
In the feedback type floating gate transistor, a floating gate layer forms an FBFET barrier region on a floating gate dielectric layer along the direction of a vertical channel in the horizontal plane, wherein the barrier type of the FBFET is p + -n + -i(p - )-n + Or n + -p + -i(n - )-p + The floating gate layer is used as one end of the floating gate layer and is led out of i (p - ) Terminal or i (n) - ) The terminal performs gate control of the FBFET; may also be p + -i-n + Or n + -i-p + At this time, the two ends of the i region need to be led out to gate the FBFET.
In the feedback floating gate transistor, the floating gate dielectric layer is preferably made of silicon oxide (SiO 2 ) And the like, the thickness is preferably 2-5 nm because the tunneling injection mechanism is not considered, and the control gate voltage and the reliability of the device are comprehensively considered.
In the feedback floating gate transistor, the material of the barrier region (including the floating gate) of the FBFET is preferably polysilicon, and in order to ensure the charge storage amount, the thickness is preferably 5-10 nm, and the different types of the barrier region are realized by doping.
In the feedback floating gate transistor, the material of the floating gate blocking layer is preferably aluminum oxide (Al 2 O 3 ) Silicon oxide (SiO) 2 ) Etc., the thickness is preferably 5 to 15nm in consideration of the coupling efficiency of the control gate to the floating gate and the reliability of the device.
In the feedback floating gate transistor, the material of the control gate is preferably titanium nitride (TiN), tantalum nitride (TaN), or the like, and the thickness is preferably 50 to 100nm.
In the feedback floating gate transistor, the metal extraction layer is preferably made of titanium (Ti)/aluminum (Al), and the thickness is preferably 20nm/800nm to 70nm/1 μm.
The invention also provides a preparation method of the feedback floating gate transistor, which comprises the following steps:
1) Forming a conventional shallow trench isolation (Shallow Trench Isolation, STI) and an active region on a semiconductor substrate;
2) Forming a floating gate dielectric layer on the surface of a semiconductor substrate, and depositing a polysilicon layer (i type);
3) Defining an i region in the barrier region of the FBFET on the polysilicon layer through a photoetching technology, and doping the rest region to form first doping type polysilicon;
4) Defining a floating gate region in the polysilicon layer through a photoetching technology, doping a second doping type in the region to form second doping type polysilicon-first doping type polysilicon-i-type polysilicon-first doping type polysilicon or second doping type polysilicon-i-type polysilicon-first doping type polysilicon, and rapidly annealing to activate impurities;
5) Defining and etching to form an FBFET barrier region by a photoetching technology, then forming a source region and a drain region of an active region of a semiconductor substrate by self-aligned doping, and rapidly annealing to activate impurities;
6) Sequentially depositing a floating gate barrier layer and a control gate electrode layer on the surface of the FBFET barrier region;
7) Defining a control gate region by a photoetching technology and etching the control gate electrode layer and the floating gate barrier layer to the surface of the FBFET barrier region;
8) An isolation layer is deposited and the surface planarized, and then metal extraction of the source region, drain region, control gate and i region of the FBFET is made.
The step 1) specifically includes:
1a) Forming a silicon oxide buffer layer on a substrate by dry oxygen oxidation, and depositing a silicon nitride hard mask layer;
1b) Spin-coating organic positive photoresist, patterning an active region by a photolithography technique, and taking a silicon nitride hard mask as an active region mask;
1c) Forming shallow grooves through etching, backfilling silicon oxide through deposition, carrying out surface planarization, and removing a silicon nitride hard mask and a silicon oxide buffer layer of an active region through wet etching;
1d) And carrying out low-dose doping and rapid annealing on the active region to activate impurities, thereby forming a lightly doped channel region.
The step 8) specifically includes:
8a) After depositing a silicon oxide isolation layer and carrying out surface planarization, defining and etching through holes of a source region, a drain region, a control grid electrode and an i region of the FBFET through a photoetching technology;
8b) Sequentially depositing a metal adhesion layer titanium and a metal interconnection layer aluminum;
8c) Defining interconnection lines by photoetching technology, etching the metal layer to the isolation layer, and performing alloy annealing to form metal lead-out.
The deposition/deposition methods in the above steps 1 a), 1 c) and 8 a) may be low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD).
The floating gate dielectric layer in the step 2) is preferably formed by dry oxygen oxidation, and the polysilicon is preferably deposited by low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD).
The floating gate barrier layer deposition in step 6) is preferably atomic layer deposition (Atomic Layer Deposition, ALD).
The metal material in the above steps 6) and 8 b) may be deposited by physical vapor deposition (Physical Vapor Deposition, PVD) such as magnetron sputtering (Magnetron Sputtering) and metal vapor deposition (Metal Evaporation).
Further, the planarization method in the above preparation method is preferably chemical mechanical polishing (Chemical Mechanical Polishing, CMP).
Further, in the above preparation method, one of rapid thermal Annealing (Rapid Thermal Annealing, RTA), laser Annealing (Laser Annealing), flash Annealing (Flash Annealing), and Spike Annealing (Spike Annealing) may be used as the Annealing mode.
Further, the photolithography technique used in the above preparation method is a photolithography technique capable of defining a nano-scale such as 193nm ultraviolet lithography.
Further, the etching technique used in the above preparation method may be a method such as reactive ion etching (Reactive Ion Etching, RIE) and inductively coupled plasma etching (Inductively Coupled Plasma Etching, ICPE).
The invention has the following advantages and positive effects:
1) According to the feedback type floating gate transistor provided by the invention, the junction barrier is repeatedly reduced to realize the transverse charge injection and release, the junction starting voltage is low, the operation voltage is further reduced, and the writing speed is improved;
2) Based on the injection mechanism, the feedback type floating gate transistor provided by the invention has the advantages that the programming and erasing paths do not pass through the floating gate dielectric layer, the defect and damage of an oxide layer are avoided, and the durability of the device is further improved;
3) Charge storage is performed using the double barrier of the FBFET, thus achieving low leakage and high retention characteristics of charge;
4) The control gate end, the source and drain ends and the charge injection end (the gate end of the FBFET) of the floating gate device are mutually independent, and the operation is simple and has no interference;
5) The preparation process is simple and the structure is easy to realize.
Based on the characteristics, the feedback type floating gate transistor has the potential of being applied to a large-scale low-power-consumption high-speed high-reliability nonvolatile memory.
Drawings
Fig. 1-11 are schematic diagrams of key process steps of the feedback floating gate transistor of the present invention. In each figure, (a) is a top view of the device, (B) is a cross-sectional view of the device along the A-A 'direction (channel), and (c) is a cross-sectional view of the device along the B-B' direction (FBFET barrier). Wherein:
figure 1 is a step of forming STI isolation and lightly doped active areas on a bulk silicon substrate;
FIG. 2 shows the steps of forming a floating gate dielectric layer and depositing a polysilicon layer on the surface of a bulk silicon substrate by dry oxygen oxidation;
FIG. 3 is a step of protecting the i-region and doping the remaining region with a first doping type impurity by a photolithographic technique;
FIG. 4 is a step of defining a floating gate region and re-doping the region with a second doping type impurity by photolithographic techniques;
FIG. 5 is a step of defining and etching a barrier region of an FBFET by photolithographic techniques;
FIG. 6 shows a step of performing source-drain doping for a channel;
FIG. 7 is a step of depositing a floating gate barrier layer and a metal control gate electrode layer in sequence;
FIG. 8 is a step of patterning the control gate region by photolithographic techniques and etching the metal control gate electrode layer and floating gate barrier layer to the surface of the barrier region of the FBFET;
FIG. 9 is a step of depositing a silicon oxide isolation layer and performing surface planarization;
FIG. 10 is a step of defining and etching vias over the i-regions of the source, drain, control gate and FBFET by photolithographic techniques;
FIG. 11 is a step of depositing a metal conductive layer and patterning a metal interconnect line;
FIG. 12 shows that the barrier type of the FBFET is p + -i-n + Is a schematic diagram of the device structure;
fig. 13 is a graphical illustration of the materials used in fig. 1-12.
Detailed Description
The invention will now be described in detail by way of specific examples with reference to the accompanying drawings.
Example 1
As shown in fig. 1 to 11, a feedback type floating gate transistor (p is the barrier type of FBFET) was prepared according to the following procedure + -n + -i-n + Examples):
1) Forming an STI isolation and lightly doped active region on a bulk silicon substrate, specifically performing dry oxygen oxidation on a P-type silicon substrate to form a silicon oxide buffer layer, and then performing LPCVD deposition on a silicon nitride hard mask layer; spin-coating organic positive photoresist, patterning an active region by a photoetching technology, etching to form a shallow groove, backfilling silicon oxide by LPCVD, removing a silicon nitride hard mask of the active region and a BOE solution by hot phosphoric acid after CMP to remove a silicon oxide buffer layer; for activeRegion implantation of impurity P + The implantation dose is 5×10 12 cm -2 The implantation energy is 45keV, and the impurity is activated by rapid annealing at 1000 ℃ for 5s to form a lightly doped channel, as shown in figure 1;
2) Forming a 3nm floating gate dielectric layer on the surface of a silicon substrate in a dry oxygen oxidation mode, and depositing a 5nm polycrystalline silicon layer on the surface of the floating gate dielectric layer by LPCVD (low pressure chemical vapor deposition), as shown in figure 2;
3) Spin-on organic positive photoresist, defining p by photolithographic techniques + -n + -i-n + The i region in (a) is protected by using photoresist As a mask, the other regions are doped, and impurity As is injected + The implantation dose is 2×10 13 cm -2 The implantation energy is 2keV, and n is formed along the direction (B-B') of the vertical channel in the horizontal plane + -i-n + ", as shown in fig. 3;
4) Spin-coating organic positive photoresist again after photoresist removal, defining p by photolithography + -n + -i-n + P in (b) + A region (floating gate region) for compensation doping, protecting the rest region with photoresist as mask, and injecting impurity P + The implantation dose is 2×10 15
cm -2 The implantation energy is 2keV, forming a p + -n + -i-n + ", after photoresist removal, the impurities are activated by rapid annealing at 900 ℃ for 5 seconds, as shown in fig. 4;
5) Spin-coating organic positive photoresist, patterning an FBFET region extending from the floating gate region by a photoetching technology, and etching a polysilicon layer to the surface of the floating gate dielectric layer by ICP (inductively coupled plasma), as shown in FIG. 5;
6) Impurity As is injected by self-aligning to carry out source-drain heavy doping of the channel + The implantation dose is 5×10 15 cm -2 The implantation energy is 33keV, the impurities are activated by rapid annealing after photoresist removal, the annealing temperature is 900 ℃, and the time is 5s, as shown in figure 6;
7) Depositing an 8nm aluminum oxide barrier layer by ALD and a 50nm titanium nitride metal control gate by PVD, as shown in FIG. 7;
8) Spin-coating organic positive photoresist, performing metal control gate patterning by a photoetching technology, and etching the control gate electrode layer and the floating gate barrier layer to the surface of the FBFET region, as shown in FIG. 8;
9) Depositing a 300nm silicon oxide isolation layer by PECVD and carrying out surface planarization, as shown in figure 9;
10 Spin-coating an organic positive photoresist, defining the source, drain, control gate and i region through holes of the FBFET by photolithography, and etching to form the through holes at each end, as shown in fig. 10;
11 A metal film is formed by sequentially depositing 20nm of metal titanium (an adhesion layer) and 800nm of metal aluminum to fill the through holes by magnetron sputtering, surface planarization is performed by CMP, then metal lead-out wires are defined by photolithography, and metal interconnect wires are formed and alloyed by ICP etching, as shown in fig. 11.
Example two
The barrier type of the prepared FBFET is p + -i-n + The preparation process of the feedback floating gate transistor is similar to that of the first embodiment, and the operation difference is that: defining p in step 3) lithography + -i-n + Is doped to form an n in the horizontal plane along the direction (B-B') of the vertical channel + -i-n + "; defining p lithographically at step 4) + -i-n + P in (b) + A region (floating gate region) for forming p after compensation doping + -i-n + "; in steps 10) and 11) etching to form the via holes and fill metal at each end, both ends need to be pulled out in the i-region of the FBFET, as shown in fig. 12.
The examples of the present invention are not intended to limit the present invention. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present invention or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present invention. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (10)
1. The low-voltage durable high-retention feedback type floating gate transistor comprises a semiconductor substrate, a source region, a drain region, a channel region, a floating gate dielectric layer, a floating gate blocking layer, a control gate, an isolation layer, and metal leading-out layers at each end of the source region, the drain region and the control gate, wherein the source region and the drain region are positioned in the active region of the semiconductor substrate, the lightly doped channel region is connected with the source region and the drain region, the floating gate dielectric layer, the floating gate blocking layer and the control gate are sequentially arranged above the channel region, and the low-voltage durable high-retention feedback type floating gate transistor is characterized in that the floating gate layer forms an FBFET barrier region in a horizontal plane along a direction perpendicular to the channel, and the FBFET barrier region is selected from one of the following types (I) and (II):
(I) P is formed from floating gate to outside + -n + -i-n + Region or n + -p + -i-p + The floating gate layer is used as one end of the FBFET, and one end led out from the i region is used for gate control of the FBFET;
(II) forming p from the floating gate + -i-n + Region or n + -i-p + A region in which the i region is gated at its leading-out ends, one of which is near p + Region with the other end near n + A zone.
2. The low voltage, durable, high retention feedback floating gate transistor of claim 1, wherein said spacer covers the device surface, and wherein said metal lead-out layer forms metal lead-out lines through the spacer to connect to the source region, drain region, control gate and gate terminal of the FBFET, respectively, of the semiconductor substrate active region through the via.
3. The low-voltage durable high-retention feedback type floating gate transistor of claim 1, wherein the floating gate dielectric layer is made of silicon oxide and has a thickness of 2-5 nm.
4. The low voltage, durable, high retention feedback floating gate transistor of claim 1 wherein the barrier region of said FBFET is polysilicon and has a thickness of 5-10 nm.
5. The low voltage durable high-retention feedback type floating gate transistor of claim 1, wherein the floating gate blocking layer is made of alumina or silica with a thickness of 5-15 nm.
6. The low voltage durable high-retention feedback type floating gate transistor of claim 1, wherein the control gate is made of titanium nitride or tantalum nitride and has a thickness of 50-100 nm; the thickness of the material Ti/Al of the metal extraction layer is 20nm/800 nm-70 nm/1 mu m.
7. The method for preparing the low-voltage durable high-retention feedback type floating gate transistor according to any one of claims 1 to 6, comprising the following steps:
1) Forming a conventional shallow trench isolation and active region on a semiconductor substrate;
2) Forming a floating gate dielectric layer on the surface of a semiconductor substrate, and depositing a polysilicon layer;
3) Defining an i region in the barrier region of the FBFET on the polysilicon layer through a photoetching technology, and doping the rest region to form first doping type polysilicon;
4) Defining a floating gate region in the polysilicon layer through a photoetching technology, doping a second doping type in the region to form second doping type polysilicon-first doping type polysilicon-i-type polysilicon-first doping type polysilicon or second doping type polysilicon-i-type polysilicon-first doping type polysilicon, and rapidly annealing to activate impurities;
5) Defining and etching to form an FBFET barrier region by a photoetching technology, then forming a source region and a drain region of an active region of a semiconductor substrate by self-aligned doping, and rapidly annealing to activate impurities;
6) Sequentially depositing a floating gate barrier layer and a control gate electrode layer on the surface of the FBFET barrier region;
7) Defining a control gate region by a photoetching technology and etching the control gate electrode layer and the floating gate barrier layer to the surface of the FBFET barrier region;
8) An isolation layer is deposited and the surface planarized, and then metal extraction of the source region, drain region, control gate and i region of the FBFET is made.
8. The method of claim 7, wherein step 1) comprises:
1a) Forming a silicon oxide buffer layer on a semiconductor substrate by dry oxygen oxidation, and depositing a silicon nitride hard mask layer;
1b) Spin-coating organic positive photoresist, patterning an active region by a photolithography technique, and taking a silicon nitride hard mask as an active region mask;
1c) Forming shallow grooves through etching, backfilling silicon oxide through deposition, carrying out surface planarization, and removing a silicon nitride hard mask and a silicon oxide buffer layer of an active region through wet etching;
1d) And carrying out low-dose doping and rapid annealing on the active region to activate impurities, thereby forming a lightly doped channel region.
9. The method of claim 7, wherein step 8) comprises:
8a) Depositing a silicon oxide isolation layer, carrying out surface planarization, and defining and etching through holes for forming a source region, a drain region, a control grid and an i region of the FBFET by a photoetching technology;
8b) Sequentially depositing a metal adhesion layer titanium and a metal interconnection layer aluminum;
8c) Defining interconnection lines by photoetching technology, etching the metal layer to the isolation layer, and performing alloy annealing to form metal lead-out.
10. The method of claim 7 wherein the semiconductor substrate is a silicon substrate, and in step 2) a floating gate dielectric layer is formed by dry oxygen oxidation, followed by low pressure chemical vapor deposition of a polysilicon layer; in step 6), an atomic layer deposition is adopted to prepare a floating gate barrier layer, and a physical vapor deposition is adopted to prepare a control gate electrode layer.
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