CN1770434A - Integrated circuit chip packaging and manufacturing method thereof - Google Patents
Integrated circuit chip packaging and manufacturing method thereof Download PDFInfo
- Publication number
- CN1770434A CN1770434A CNA2004100521645A CN200410052164A CN1770434A CN 1770434 A CN1770434 A CN 1770434A CN A2004100521645 A CNA2004100521645 A CN A2004100521645A CN 200410052164 A CN200410052164 A CN 200410052164A CN 1770434 A CN1770434 A CN 1770434A
- Authority
- CN
- China
- Prior art keywords
- supporting body
- wafer
- integrated circuit
- weld pad
- framework
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000004806 packaging method and process Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000005538 encapsulation Methods 0.000 claims description 25
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 229920000297 Rayon Polymers 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 abstract 5
- 239000000853 adhesive Substances 0.000 abstract 3
- 230000001070 adhesive effect Effects 0.000 abstract 3
- 239000013078 crystal Substances 0.000 abstract 3
- 239000003990 capacitor Substances 0.000 abstract 2
- 230000010354 integration Effects 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 abstract 1
- 238000007789 sealing Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 32
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
This invention relates to one integration circuit crystal sealing and process method, which comprises one load part, one crystal slice, multiple welding lines, one cover, one first adhesive part and second one, wherein, the load one has one capacitor with one open on top of load with its top and bottom set with multiple pads and multiple blind holes set to connection load top and bottom; the crystal slice is set on bottom of capacitor with its top set with multiple welding pads with one end connected to welding pad and another end connected to top; the first adhesive covers protective welding line and welding pad; the cover located on top of load part with its size less than those of load part; the second adhesive subject on the bonding place of cover and load part.
Description
[technical field]
The invention relates to a kind of integrated circuit (IC) wafer encapsulation and manufacture method thereof, especially about a kind of small-scale integrated circuit wafer package and manufacture method thereof.
[background technology]
See also shown in Figure 1, it is a State Intellectual Property Office in the cutaway view of structure dress of No. 01200424.8 integrated circuit (IC) wafer of utility model patent of Granted publication on the 31st in October calendar year 2001, the structure dress of this integrated circuit (IC) wafer mainly comprises a supporting body 10, one wafer 12, one hides 13 and one adhesion 14, wherein this supporting body 10 has an end face 101 and a room 102, have an opening on this end face 101 and connect with room 102, be laid with a plurality of weld pads on this end face 101, this supporting body 10 further comprises a plurality of perforations 103, it is opened in supporting body 10 peripheries, in order to the weld pad that electrically connects this supporting body 10 bottom surface to this supporting body 10; This wafer 12 is fixedly arranged in this room 102, and it also has a plurality of weld pads, and is connected with the weld pad of this supporting body 10 respectively by many bonding wires 15; This adhesion 14 is laid in the joining place of each bonding wire 15 and these supporting body 10 weld pads; And this covering 13 and this adhesion 14 are affixed and can seal the opening of this room 102.Yet the consumption of this adhesion 14 is wayward, and consumption hides 13 more at least and easily gets loose, and may pull apart being connected of bonding wire 15 and supporting body 10 weld pads; Because the structure of this integrated circuit (IC) wafer is adorned it and is electrically connected by this perforation 103 and other circuit boards, if the consumption of adhesion 14 is more, when covering 13 was pressed on the supporting body 10, the perforation 103 of these adhesion 14 easily suitable supporting body 10 peripheries or its sidewall flowed down and cause it to cause product rejection in other circuit boards connections.
In view of this, provide higher integrated circuit (IC) wafer encapsulation of a kind of quality and manufacture method thereof real for necessary.
[summary of the invention]
The object of the present invention is to provide the higher integrated circuit (IC) wafer encapsulation of a kind of quality.
Another object of the present invention is to provide the manufacture method of the higher integrated circuit (IC) wafer encapsulation of a kind of quality.
For realizing purpose of the present invention, a kind of integrated circuit (IC) wafer encapsulation is provided, comprise a supporting body, a wafer, many bonding wires, a covering, one first adhesion and one second adhesions, wherein, this supporting body has a room, this room has an opening on the supporting body end face, this supporting body top and bottom part ring are around being laid with a plurality of weld pads, and its inside is provided with in order to electrically connect a plurality of blind holes of supporting body top and bottom weld pad; This wafer is fixedly arranged on the room bottom, and its top is around being laid with a plurality of weld pads; The weld pad at this each bonding wire one end connecting wafer top, the other end connects the weld pad at supporting body top; The described bonding wire of this first adhesion covering protection; This covering is positioned at the supporting body top, and its size is less than the supporting body top; This second adhesion is coated this covering and supporting body top joint.
For realizing purpose of the present invention, a kind of manufacture method of integrated circuit (IC) wafer encapsulation is provided, may further comprise the steps: a supporting body is provided, and this supporting body has a room, and this room has an opening in supporting body one end face; In bottom of wafer coating viscose glue, this wafer is placed to the room bottom by the supporting body open top; Adopt many bonding wires, respectively each bonding wire one end is connected with chip bonding pads, the other end is connected with supporting body top weld pad; One first adhesion is coated on each bonding wire; Hide one afterwards and be positioned over the supporting body top, this covering and first adhesion bonding are positioned on the supporting body with predetermined; One second adhesion is coated covering also to be solidified with the junction at supporting body top all around.
Compare known technology, when its covering of the encapsulation of integrated circuit (IC) wafer of the present invention is positioned over the supporting body top and first adhesion bonding, coat with second adhesion more afterwards and hide periphery and the joint reinforcement of supporting body top, because masked area is slightly less than supporting body, make that the adhesion consumption of coating the covering periphery is more easy to control, can avoid adhesion to overflow polluting causing product rejection, and improve processing yield; Moreover, owing to hide via two place's adhesion bondings, so it is more firm with being connected of supporting body.
[description of drawings]
Fig. 1 is the cutaway view of known integrated circuit (IC) wafer;
Fig. 2 is the cutaway view of integrated circuit (IC) wafer encapsulation of the present invention.
[embodiment]
Please refer to shown in Figure 2, integrated circuit (IC) wafer encapsulation of the present invention comprises: a supporting body 2, it has a room 23, this room 23 has an opening in the top of supporting body 2, the top of supporting body 2 and bottom peripheral edge are around being laid with a plurality of weld pads 24, and its inside is provided with a plurality of in order to electrically connect the blind hole 25 of supporting body 2 top and bottom weld pads 24; One wafer 3, it is fixedly arranged on room 23 bottoms, and its top periphery is provided with a plurality of weld pads; Many bonding wires 32, the weld pad at one end connecting wafer 3 tops (figure does not show), the other end connects the weld pad 24 at supporting body 2 tops; One hides 5, and it is fixedly arranged on supporting body 2 tops; One first adhesion 4, its covering protection bonding wire 32 and bonding hide 5; One second adhesion 6, its bonding covering 5 and supporting body 2 top joints.
This supporting body 2 is to be made by pottery, fiber composite plate and other material, and it is one or two story frame structure, comprises a framework 21 and a plate body 22.The frame of the outer rim of framework 21 and plate body 22 is measure-alike, and the justified margin of the outward flange of framework 21 and plate body 22 also closely is pressed on formation supporting body 2 on the plate body 21.Form room 23 in the supporting body 2, this room 23 is used to place wafer 3 or other electronic components.Weld pad 24 comprises top weld pad 241 and bottom weld pad 242, and this top weld pad 241 is around framework 21 tops that are laid in supporting body 2, and its outward flange apart from framework 21 has certain distance, makes the end face of framework 21 keep a space and manipulates for other; This bottom weld pad 242 is around plate body 22 bottoms that are laid in supporting body 2, and the position is corresponding with top weld pad 241, and it is used for the electric connection of this integrated circuit (IC) wafer and other circuit boards.Blind hole 4 is arranged at the inside of supporting body 2, is used to electrically connect the top weld pad 241 and bottom weld pad 242 of this supporting body 2.This blind hole 25 is made up of last blind hole 251 and following blind hole 252, and wherein, last blind hole 251 is arranged in the framework 21, and the groove that through hole that it is offered by 241 times direction framework 21 bottoms of top weld pad and framework 21 bottoms are offered is connected to form; Following blind hole 252 is arranged at plate body 22 inside, and it is offered a through hole by plate body 22 tops and is connected with bottom weld pad 242.After framework 21 and plate body 22 pressings, last blind hole 41 also is connected perforation with following blind hole 42, and its inside is provided with conductor or conductor coating, with being electrically connected of realization top weld pad 241 and bottom weld pad 242.
This wafer 3 is fixed in the bottom of room 23 by a viscose glue 31.The weld pad of these bonding wire 32 1 end connecting wafers 3, the other end are then put down on the top weld pad 241 of stretching in supporting body 2 and are connected with it.
This first adhesion 4 is coated on the bonding wire 32, with protection bonding wire 32.
This covering 5 is plate bodys, its size is less than the size of framework 21, and its periphery can cover the space to top weld pad 241 edges, when this covering 5 is when being positioned over these framework 21 tops, hide 5 and first adhesion, 4 bondings, hide 5 on supporting body 2 to pre-fix, around it, be coated with second adhesion 6 afterwards, to fix this covering 5 and to seal room 23 with framework 21 joints.At this moment, room 23 forms an enclosure space, can protect wafer 3 not to be subjected to external damage or pollution, improves life of product.Other because this hides 5 size less than framework 21, makes that the consumption of coating covering 5 second adhesion 6 all around is more easy to control, scraps when making and be unlikely to cause, and can improve process rate.
The manufacture method such as the following steps of this integrated circuit (IC) wafer encapsulation: a supporting body 2 is provided, which is provided with room 23; In a wafer 3 bottoms coating viscose glue 31, again wafer 3 is put into room 23 bottoms by supporting body 2 open tops; Adopt many bonding wires 32, respectively each bonding wire 32 1 end is connected on the chip bonding pads, the other end is connected on the supporting body 2 top weld pads 241; First adhesion 4 is coated the joint that reaches bonding wire 32 and chip bonding pads and supporting body 2 top weld pads 241 on the bonding wire 32; To hide 5 tops that are positioned over supporting body 2 afterwards, hide 5 and first adhesion 4 bonding with pre-determined bit should covering 5 on supporting body 2; Again second adhesion 6 is coated and hidden around 5 with the joint at supporting body 2 tops and solidify.
Claims (13)
1. an integrated circuit (IC) wafer encapsulation comprises a supporting body, and this supporting body has a room, and this room has an opening on the supporting body end face; One wafer, it is fixedly arranged on the room bottom, and its top is around being laid with a plurality of weld pads; Many bonding wires, the weld pad at this bonding wire one end connecting wafer top respectively, the other end is connected with the weld pad at supporting body top; One hides, and it is arranged at the supporting body top; And one first adhesion, it is characterized in that: this supporting body top and bottom part ring are around being laid with a plurality of weld pads, and its inside is provided with in order to electrically connect a plurality of blind holes of supporting body top and bottom weld pad; The described bonding wire of this first adhesion covering protection; This hides size less than the supporting body top dimension; The encapsulation of this integrated circuit (IC) wafer further comprises one second adhesion, around it is coated and hides with supporting body top joint.
2. integrated circuit (IC) wafer encapsulation as claimed in claim 1, it is characterized in that: described supporting body is one or two story frame structure, comprises a framework and a plate body, the outer rim of framework and the frame of plate body are measure-alike.
3. integrated circuit (IC) wafer encapsulation as claimed in claim 2 is characterized in that: the outward flange of described framework and the justified margin of plate body and tight pressing form above-mentioned supporting body.
4. integrated circuit (IC) wafer encapsulation as claimed in claim 2, it is characterized in that: described this blind hole is made up of last blind hole and following blind hole, wherein, last blind hole is arranged in the framework, and the groove that through hole that it is offered bottom direction framework under the weld pad at top and framework bottom are offered is connected to form; Following blind hole is arranged at plate body inside, and it is offered a through hole by the plate body top and is connected with the weld pad of bottom.
5. integrated circuit (IC) wafer as claimed in claim 1 encapsulation, it is characterized in that: described weld pad comprises top weld pad and bottom weld pad, this top weld pad is around being laid in the supporting body top, and has certain distance apart from the supporting body top outer edge.
6. integrated circuit (IC) wafer encapsulation as claimed in claim 1, it is characterized in that: the described covering and first adhesion are bonding.
7. the manufacture method of an integrated circuit (IC) wafer as claimed in claim 1 encapsulation is characterized in that may further comprise the steps:
One supporting body is provided, and this supporting body has a room, and this room has an opening in the supporting body end face;
In bottom of wafer coating viscose glue, described wafer is placed to the room bottom by the supporting body open top;
Many bonding wires are provided, respectively each bonding wire one end are connected with chip bonding pads, the other end is connected with supporting body top weld pad;
One first adhesion is provided, it is coated on each bonding wire;
One covering is provided, covering is positioned over the supporting body top, wherein said covering size is less than the supporting body top dimension;
One second adhesion is provided, around it is coated and hides with the joint at supporting body top.
8. the manufacture method of integrated circuit (IC) wafer as claimed in claim 7 encapsulation is characterized in that: described top weld pad is around being laid in the supporting body top, and has certain distance apart from the supporting body top outer edge.
9. the manufacture method of integrated circuit (IC) wafer encapsulation as claimed in claim 7, it is characterized in that: described supporting body further comprises a plurality of bottoms weld pad, and it is around being laid in supporting body bottom and corresponding with the top bond pad locations.
10. the manufacture method of integrated circuit (IC) wafer encapsulation as claimed in claim 9, it is characterized in that: described supporting body supporting body is one or two story frame structure, comprise a framework and a plate body, the outer rim of framework and the frame of plate body are measure-alike, and the outward flange of described framework and the justified margin of plate body and tight pressing form above-mentioned supporting body.
11. the manufacture method of integrated circuit (IC) wafer encapsulation as claimed in claim 10, it is characterized in that: described supporting body advances one one and comprises a plurality of blind holes, is provided with conductor or conductor coating in this blind hole in order to electrically connect this top weld pad and this bottom weld pad.
12. the manufacture method of integrated circuit (IC) wafer encapsulation as claimed in claim 11, it is characterized in that: described blind hole is made up of last blind hole and following blind hole, wherein, last blind hole is arranged in the framework, and it is to be connected to form by the groove that the through hole that direction framework bottom under the weld pad of top is offered is offered bottom framework; Following blind hole is arranged at plate body inside, and it is offered a through hole by the plate body top and is connected with the bottom weld pad.
13. the manufacture method of integrated circuit (IC) wafer encapsulation as claimed in claim 7, it is characterized in that: described covering is bonding with first adhesion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100521645A CN100454523C (en) | 2004-11-06 | 2004-11-06 | Integrated circuit chip packaging and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100521645A CN100454523C (en) | 2004-11-06 | 2004-11-06 | Integrated circuit chip packaging and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1770434A true CN1770434A (en) | 2006-05-10 |
| CN100454523C CN100454523C (en) | 2009-01-21 |
Family
ID=36751585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100521645A Expired - Fee Related CN100454523C (en) | 2004-11-06 | 2004-11-06 | Integrated circuit chip packaging and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100454523C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103166104A (en) * | 2011-12-13 | 2013-06-19 | 鸿富锦精密工业（深圳）有限公司 | Chip packaging structure and packaging method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278429A (en) * | 1989-12-19 | 1994-01-11 | Fujitsu Limited | Semiconductor device having improved adhesive structure and method of producing same |
| JP2766920B2 (en) * | 1992-01-07 | 1998-06-18 | 三菱電機株式会社 | IC package and its mounting method |
| TW575949B (en) * | 2001-02-06 | 2004-02-11 | Hitachi Ltd | Mixed integrated circuit device, its manufacturing method and electronic apparatus |
| FR2824953B1 (en) * | 2001-05-18 | 2004-07-16 | St Microelectronics Sa | OPTICAL SEMICONDUCTOR PACKAGE WITH INCORPORATED LENS AND SHIELDING |
-
2004
- 2004-11-06 CN CNB2004100521645A patent/CN100454523C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103166104A (en) * | 2011-12-13 | 2013-06-19 | 鸿富锦精密工业（深圳）有限公司 | Chip packaging structure and packaging method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100454523C (en) | 2009-01-21 |
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| Date | Code | Title | Description |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: HON HAI PRECISION INDUSTRY CO., LTD. Free format text: FORMER OWNER: YANGXIN TECHNOLOGY CO., LTD. Effective date: 20121214 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20121214 Address after: Guangdong province Shenzhen city Baoan District town Longhua tenth Industrial Zone tabulaeformis East Ring Road No. 2 two Patentee after: HONG FU JIN PRECISION INDUSTRY (SHENZHEN) Co.,Ltd. Patentee after: HON HAI PRECISION INDUSTRY Co.,Ltd. Address before: 518109 Guangdong city of Shenzhen province Baoan District Longhua Town Industrial Zone tabulaeformis tenth East Ring Road No. 2 two Patentee before: HONG FU JIN PRECISION INDUSTRY (SHENZHEN) Co.,Ltd. Patentee before: Yangxin Technology Co.,Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090121 |
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| CF01 | Termination of patent right due to non-payment of annual fee |