CN1755466A - Method for making electronic apparatus - Google Patents
Method for making electronic apparatus Download PDFInfo
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- CN1755466A CN1755466A CN 200410080290 CN200410080290A CN1755466A CN 1755466 A CN1755466 A CN 1755466A CN 200410080290 CN200410080290 CN 200410080290 CN 200410080290 A CN200410080290 A CN 200410080290A CN 1755466 A CN1755466 A CN 1755466A
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- rectangular
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- electronic installation
- making electronic
- polymer composite
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- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to a method for making an electric device which comprises the following steps: providing a base plate, forming a first long strip on the base plate, coating and covering an insulating layer material on the first long strip and the base plate, forming a second long strip on the base plate, forming a conductive macro mole material on the insulating layer and covering the second long strip, etching the conductive macro mole material by electroetching type so as to move the conductive macro mole material of the second long strip, forming a semi-conducting layer material on the second long strip and the conductive macro mole material.
Description
Technical field
The present invention relates to a kind of method of making electronic installation, particularly relate to a kind of method that insulating layer patternization and the dry ecthing mode of arranging in pairs or groups are made thin film transistor (TFT).
Background technology
Lcd products is used on the various forms of IT products with as user's interface device, as personal computer product, portable computers machine product etc.Generally in making lcd products, use a continuous films transistor arrangement as a continuous exchange component, it makes pixel electrode move, so that the operation of lcd products to be provided.
Therefore, thin film transistor (TFT) is of crucial importance for the manufacturing of LCD.General thin film transistor (TFT), especially descend contact (bottom contact) OTFT, it is to be made by gold-tinted to finish that its electrode is made, though gold-tinted is made the length (channel length) that can define channel easily, the making of electrode must be through multiple tracks steps such as overexposure, development, etching, removing photoresistances.Therefore, how to reduce making step, become industry institute urgent problem to produce the thin film transistor (TFT) that display is used.
A kind of solution of the problems referred to above is for using patterning materials collocation electric paste etching, for example No. the 518682nd, the Taiwan patent announcement, it discloses a kind of method for making of thin-film transistor structure, and shown in Figure 1A to Fig. 1 C, the method for making of this thin-film transistor structure comprises the following steps:
A) provide a substrate 10, and in this substrate 10, form a gate electrode 12;
B) on this substrate 10 and this gate electrode 12, cover one first dielectric layer 14 fully, on this first dielectric layer 14, cover a backfill dielectric layer 16 then;
C) utilize electricity slurry 18 etch-back (etch back), the backfill dielectric layer 16 on this gate electrode 12 is removed fully, and forms a pair of patterning covering backfill dielectric layer 16a and 16b simultaneously;
D) on the expose portion of first dielectric layer 14 and a pair of patterning cover backfill dielectric layer 16a and 16b, form a patterning the 3rd dielectric layer 20 and aim at the patterning active semiconductor layer 22 of this patterning the 3rd dielectric layer 20; And
E) initiatively form contacted a pair of patterning ohmic contact layer 24a and 24b on a pair of end points of semiconductor layer 22 and aim at a pair of patterned conductive layer 26a and 26b on it at patterning, this patterned conductive layer 26a and 26b are as electrode (drawing/source electrode).
Though Using such method can be produced the thin-film transistor structure with reliability, but still need the loaded down with trivial details gold-tinted making step (exposure, development, etching, removing photoresistance) of multiple tracks, simultaneously if when being insulation course with the organic material, there is the patterning of machine electrode will be not easy to make, and is subject to the restriction of material character; If the mode with printing (printing) is made electrode, the difficulty that contraposition is difficult for then can appear again.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of method of making electronic installation, it utilizes insulating layer patternization and the dry ecthing of arranging in pairs or groups (electric paste etching) mode is made one (organic) thin film transistor (TFT), can reach the purpose that reduces making step and aim at (self-alignment) automatically.
To achieve these goals, the invention provides a kind of method of making electronic installation, its characteristics are, may further comprise the steps: a substrate a) is provided; B) formation one first is rectangular on this substrate; C) insulating layer material is coated on this first rectangular and this substrate, and covered this first rectangular and this substrate fully; D) formation one second is rectangular on this insulating layer material; E) conducting polymer composite is formed on this insulating layer material, and covers fully that this is second rectangular; F), make that this second conducting polymer composite on rectangular is removed fully with this conducting polymer composite of electric paste etching mode etching; And g) this second rectangular on and form the semiconductor layer material on this conducting polymer composite.
The method of above-mentioned making electronic installation, its characteristics are that this substrate is by a kind of substrate selected in silicon wafer substrate, glass substrate, quartz base plate, plastic base and the bendable substrate.
The method of above-mentioned making electronic installation, its characteristics be, this insulating layer material is by selected a kind of in inorganic material, macromolecular material and other high dielectric constant material.
The method of above-mentioned making electronic installation, its characteristics are that this high dielectric constant material has the specific inductive capacity greater than 3.
The method of above-mentioned making electronic installation, its characteristics be, in this step d), uses in the gold-tinted pattern-makingization of the gold-tinted pattern-makingization of nano-imprint lithography art, forward exposure and exposure dorsad selected a kind of method to form that this is second rectangular.
The method of above-mentioned making electronic installation, its characteristics are that in this step g), selected a kind of method forms this semiconductor layer material in use evaporation, wire mark, ink jet printing and the contact printing.
The method of above-mentioned making electronic installation, its characteristics be, this is first rectangular selected a kind of made for being blended together by common metal, conducting polymer composite and organic and inorganic in the conductive material.
The method of above-mentioned making electronic installation, its characteristics are that this conducting polymer composite is that organic and inorganic blendes together conductive material.
Effect of the present invention is to utilize insulating layer patternization and the dry ecthing of arranging in pairs or groups (electric paste etching) mode to make one (organic) thin film transistor (TFT), can reach to reduce fabrication steps and self-aligning purpose.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Figure 1A to Fig. 1 C is the schematic flow sheet of the thin-film transistor structure method for making of prior art;
Fig. 2 to Fig. 7 makes the schematic flow sheet of the method for electronic installation for the present invention;
Fig. 8 A is for using the synoptic diagram of nano-imprint lithography art with insulating layer patternization in the present invention;
Fig. 8 B is the gold-tinted pattern-making technology of the using forward exposure in the present invention synoptic diagram with insulating layer patternization;
Fig. 8 C is the gold-tinted pattern-making technology of using the exposure of another forward in the present invention synoptic diagram with insulating layer patternization; And
Fig. 8 D is for using the synoptic diagram of the gold-tinted pattern-making technology of exposure dorsad with insulating layer patternization in the present invention.
Wherein, Reference numeral:
The 1-thin film transistor (TFT), the 10-substrate
The 12-gate electrode, 14-first dielectric layer
16-backfill dielectric layer, the 16a-patterning covers the backfill dielectric layer
The 16b-patterning covers the backfill dielectric layer, 18-electricity slurry
20-patterning the 3rd dielectric layer, the 22-patterning is semiconductor layer initiatively
24a-patterning ohmic contact layer, 24b-patterning ohmic contact layer
The 26a-patterned conductive layer, the 26b-patterned conductive layer
The 31-substrate, 32-first is rectangular
The 33-insulating layer material, 331-second is rectangular
The 34-conducting polymer composite, the 34a-conducting polymer composite
The 34b-conducting polymer composite, 35-semiconductor layer material
The 40-mould, the positive photoresistance pattern of 41-, 411-light source
42-bears photoresistance pattern, 421-light source
The 431-light source, 44-electricity slurry
Embodiment
Fig. 2 to Fig. 7 makes the schematic flow sheet of the method for electronic installation for the present invention.Wherein, Fig. 2 is the making that gate mainly is described, Fig. 3 mainly illustrates the coating of insulation course, and Fig. 4 mainly illustrates the patterning of insulation course, and Fig. 5 mainly illustrates the formation of electrode, and Fig. 6 mainly illustrates etched program, and Fig. 7 mainly illustrates the making of active layers.
Please refer to Fig. 2, one substrate 31 at first is provided, on this substrate 31, form one first rectangular 32 then, this first rectangular 32 usefulness as gate, and make with general conventional semiconductor manufacturing process, for example: gold-tinted pattern-makingization, cover shady shielding (shadow mask) formation, ink jet printing (ink-jet printing), wire mark (screen printing) or contact printing (contact printing) etc.
Then as Fig. 3, with an insulating layer material 33 coat this first rectangular 32 and this substrate 31 on, and cover fully this first rectangular 32 and this substrate 31; Wherein this coating method can be rotary coating (spincoating) or rotational slide coating existing coating processes such as (spin-slide coating).
As Fig. 4, form one second rectangularly 331 again on this insulating layer material 33, wherein this second rectangular 331 can use the gold-tinted pattern-making technology (please refer to Fig. 8 B) of nano-imprint lithography art (please refer to Fig. 8 A), forward exposure or the gold-tinted pattern-making technology (please refer to Fig. 8 C) of exposure dorsad to make; Certainly, above-mentioned process technique is only for embodiment but not be used to limit the scope of the invention.
As Fig. 5, a conducting polymer composite 34 is coated on this insulating layer material 33, and covered fully that this is second rectangular 331, wherein this coating method can be known coating processes such as rotary coating or rotational slide coating.
Then as Fig. 6, make electricity consumption slurry 44 come this conducting polymer composite 34 of etching, removed fully until this conducting polymer composite 34 on second rectangular 331, and this remaining conducting polymer composite 34a in second rectangular 331 both sides and conducting polymer composite 34b promptly can be used as electrode (source/drain).In this step, if avoid electricity slurry 44 over etchings, then can formerly form at these second rectangular 331 o'clock and be made into and have thicker thickness, even so when etching is excessive, the also unlikely electrical characteristics that influence final products.
Finally, as Fig. 7, at this formation semiconductor layer material 35 on second rectangular 331 and on this conducting polymer composite 34a and the conducting polymer composite 34b; Wherein this generation type can be evaporation (thermalevaporation), wire mark, ink jet printing or contact printing.And these final products are a thin film transistor (TFT) 1.
Fig. 8 A is for using the synoptic diagram of nano-imprint lithography art with insulating layer patternization in the present invention.Wherein on this insulating layer material 33, impress by a mould 40, can form this second rectangular 331.
Fig. 8 B is the gold-tinted pattern-making technology of the using forward exposure in the present invention synoptic diagram with insulating layer patternization.Wherein by behind a light source 411 exposure one positive photoresistance pattern 41, can on this insulating layer material 33, form this second rectangular 331.
Fig. 8 C is the gold-tinted pattern-making technology of using the exposure of another forward in the present invention synoptic diagram with insulating layer patternization.Wherein by behind a light source 421 exposure one negative photoresistance pattern 42, can on this insulating layer material 33, form this second rectangular 331.
Fig. 8 D is for using the synoptic diagram of the gold-tinted pattern-making technology of exposure dorsad with insulating layer patternization in the present invention.Wherein can use exposure method dorsad during for transparent material when this substrate 31, in the method because this first rectangular 32 is light tight, therefore this first rectangular 32 itself promptly can be used as positive photoresistance, therefore after shining dorsad by a light source 431, can on this insulating layer material 33, form this second rectangular 331.
In the present invention, this substrate can be silicon wafer substrate, glass substrate, quartz base plate, plastic base or bendable substrate.This first rectangularly uses common metal, conducting polymer composite or organic and inorganic to blend together conductive material to be made; This insulating layer material can be inorganic material, macromolecular material or other high dielectric constant material (K is greater than 3).This conducting polymer composite can be organic and inorganic and blendes together conductive material.This semiconductor layer material can be the organic semiconductor layer material.Certainly, the above-mentioned material composition only is used for embodiment but not is used to limit range of application of the present invention; As long as under the exercisable prerequisite of this electronic installation, the present invention makes the method for electronic installation can use any existing (organic) thin-film-transistor material.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of claim of the present invention.
Claims (8)
1, a kind of method of making electronic installation is characterized in that, may further comprise the steps:
A) provide a substrate;
B) formation one first is rectangular on this substrate;
C) insulating layer material is coated on this first rectangular and this substrate, and covered this first rectangular and this substrate fully;
D) formation one second is rectangular on this insulating layer material;
E) conducting polymer composite is formed on this insulating layer material, and covers fully that this is second rectangular;
F), make that this second conducting polymer composite on rectangular is removed fully with this conducting polymer composite of electric paste etching mode etching; And
G) this second rectangular on and form the semiconductor layer material on this conducting polymer composite.
2, the method for making electronic installation according to claim 1 is characterized in that, this substrate is by a kind of substrate selected in silicon wafer substrate, glass substrate, quartz base plate, plastic base and the bendable substrate.
3, the method for making electronic installation according to claim 1 is characterized in that, this insulating layer material is by selected a kind of in inorganic material, macromolecular material and other high dielectric constant material.
4, the method for making electronic installation according to claim 1 is characterized in that, this high dielectric constant material has the specific inductive capacity greater than 3.
5, the method for making electronic installation according to claim 1, it is characterized in that, in this step d), use in the gold-tinted pattern-makingization of the gold-tinted pattern-makingization of nano-imprint lithography art, forward exposure and exposure dorsad selected a kind of method to form that this is second rectangular.
6, the method for making electronic installation according to claim 1 is characterized in that, in this step g), selected a kind of method forms this semiconductor layer material in use evaporation, wire mark, ink jet printing and the contact printing.
7, the method for making electronic installation according to claim 1 is characterized in that, this is first rectangular selected a kind of made for being blended together by common metal, conducting polymer composite and organic and inorganic in the conductive material.
8, the method for making electronic installation according to claim 1 is characterized in that, this conducting polymer composite is that organic and inorganic blendes together conductive material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100802901A CN100362413C (en) | 2004-09-29 | 2004-09-29 | Method for making electronic apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100802901A CN100362413C (en) | 2004-09-29 | 2004-09-29 | Method for making electronic apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1755466A true CN1755466A (en) | 2006-04-05 |
| CN100362413C CN100362413C (en) | 2008-01-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100802901A Expired - Fee Related CN100362413C (en) | 2004-09-29 | 2004-09-29 | Method for making electronic apparatus |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800707A (en) * | 2011-05-25 | 2012-11-28 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4663038B2 (en) * | 1997-05-28 | 2011-03-30 | 三菱電機株式会社 | Contact hole formation method |
| JP3968954B2 (en) * | 2000-05-29 | 2007-08-29 | セイコーエプソン株式会社 | Substrate device manufacturing method and electro-optical device manufacturing method |
| JP4667682B2 (en) * | 2001-10-16 | 2011-04-13 | ソニー株式会社 | Manufacturing method of semiconductor device, manufacturing method of liquid crystal display device, and manufacturing method of electroluminescence display device |
| US6900856B2 (en) * | 2002-12-04 | 2005-05-31 | Lg. Philips Lcd Ltd. | Liquid crystal display device and manufacturing method thereof |
| JP3991883B2 (en) * | 2003-02-20 | 2007-10-17 | 日本電気株式会社 | Method for manufacturing thin film transistor substrate |
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2004
- 2004-09-29 CN CNB2004100802901A patent/CN100362413C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800707A (en) * | 2011-05-25 | 2012-11-28 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
| CN102800707B (en) * | 2011-05-25 | 2017-03-01 | 瑞萨电子株式会社 | Semiconductor device and its manufacture method |
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| Publication number | Publication date |
|---|---|
| CN100362413C (en) | 2008-01-16 |
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Granted publication date: 20080116 Termination date: 20170929 |