CN1734670A - Data exchange circuit and method for synchronous DRAM - Google Patents
Data exchange circuit and method for synchronous DRAM Download PDFInfo
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- CN1734670A CN1734670A CN 200410055166 CN200410055166A CN1734670A CN 1734670 A CN1734670 A CN 1734670A CN 200410055166 CN200410055166 CN 200410055166 CN 200410055166 A CN200410055166 A CN 200410055166A CN 1734670 A CN1734670 A CN 1734670A
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Abstract
The invention discloses a SDRAM data communicative circuit and method, which is characterized by the following: the SDRAM data communicative circuit contains several circuits which couples to several SDRAM data joint-feet, wherein the quantity of the data circuit is less than the quantity of SDRAM data joint-feet. The circuit receives or outputs first part of the data from down-present or up-present mask joint-foot, which reaches the other joint-foot, then receives or outputs second part of the data.
Description
Technical field
The invention relates to a kind of Synchronous Dynamic Random Access Memory (Synchronous DynamicRandom Access Memory, hereinafter to be referred as SDRAM) exchanges data circuit and method, and particularly (storer is a memory body relevant for a kind of Synchronous Dynamic Random Access Memory that is applied to the optical media reading device, below all be called storer) data (data are data, below all be called data) switched circuit and method.
Background technology
Seeing also shown in Figure 1ly, is the architecture block diagram of the exchanges data circuit of a kind of existing known SDRAM.As shown in FIG., the exchanges data circuit 100 of existing known SDRAM is to have several control lines 110, for example/CS ,/RAS ,/CAS ,/WE ... Deng, be used for allowing exchanges data circuit 100 transmit controlling signal to SDRAM 102.In addition, existing known exchanges data circuit 100 also has address wire 120 and data line 130, wherein address wire 120 is to be used for allowing exchanges data circuit 100 transfer address signal address to SDRAM 102, and data line 130 then is to allow exchanges data circuit 100 transmit data to SDRAM 102.The data line 130 of existing known exchanges data circuit 100 is the corresponding respectively data pin that couples SDRAM 102 (Q1～Qn).In general, the data line 130 of existing known exchanges data circuit 100 is that the data pin that is coupled to SDRAM 102 (on the Q1～Qn), and the number of data line 130, the just width of the data bus of exchanges data circuit one to one correspondingly.
Present technical, the size of SDRAM comprised * 1, * 2, * 4, * 8, * 16 and * 32.Yet it is, especially obvious in the market of low capacity electronic product (as video and audio CD disc (VCD) playing device) because market supply and demand situation difference often is subject to some set width and selects.Particle with 16Mb is an example, and at present the most general should be the packing of 1M * 16, and that is to say to provide * 16 data-bus width, but for the low capacity electronic product, is subject to the packing of product integral body sometimes and becomes difficult to achieve.
This shows that the exchanges data circuit of above-mentioned existing Synchronous Dynamic Random Access Memory obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.The problem that exists for the exchanges data circuit that solves Synchronous Dynamic Random Access Memory, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that the exchanges data circuit of above-mentioned existing Synchronous Dynamic Random Access Memory exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, exchanges data circuit and method in the hope of the Synchronous Dynamic Random Access Memory of founding a kind of new structure, can improve the exchanges data circuit of general existing Synchronous Dynamic Random Access Memory, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to, overcome the defective of the exchanges data circuit existence of existing Synchronous Dynamic Random Access Memory, and a kind of exchanges data circuit of new Synchronous Dynamic Random Access Memory (SDRAM) is provided, technical matters to be solved is to make it can transmit more large-capacity data with lower data-bus width.
A further object of the present invention provides the method for interchanging data of a kind of Synchronous Dynamic Random Access Memory (SDRAM), and technical matters to be solved is to make its electronic product that goes for low capacity, thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.The exchanges data circuit of a kind of Synchronous Dynamic Random Access Memory (SDRAM) that proposes according to the present invention, wherein this SDRAM has most data pins, in order to receive or to export data, and this SDRAM also has predetermined shade (UDQM) pin and predetermined shade (LDQM) pin on one once, this exchanges data circuit comprises: a data input circuit, be to couple those data pins by most data line correspondences, and the number of those data lines is the numbers less than those data pins, this data input circuit is in the one-period of a default time pulse signal, receive the first of these data from the part of those data pins, and in the following one-period of this default time pulse signal, receive the second portion of these data from another part of those data pins; One data output circuit, couple those data pins by those data line correspondences, this data output circuit is in the one-period of this default time pulse signal, the first that exports these data is wherein a part of to those data pins, and in the following one-period of this default time pulse signal, export the second portion of these data another part to those data pins; An and shade signal generating circuit, be to couple predetermined shade pin and the predetermined shade pin of this time on this, and, come activation should go up tentation data switched circuit shade pin and the predetermined shade pin of this time the two one of them according to the first or the second portion of these these data of data output circuit output/input.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The exchanges data circuit of aforesaid Synchronous Dynamic Random Access Memory, the first of wherein said data, be the low address part of these data and high address part the two one of them, and the second portion of these data, then be these data low address partly and high address partly the two another.
The exchanges data circuit of aforesaid Synchronous Dynamic Random Access Memory, wherein said data input circuit comprises: one the one D type flip-flop, in order to the first of these data of receiving this exchanges data circuit of input, and according to the first that should default time pulse signal exports these data; And one the 2nd D type flip-flop, be the second portion that receives the output of a D type flip-flop respectively and import these data of this exchanges data circuit, and according to the first that should default time pulse signal makes up these data and second portion to reduce these data.
The exchanges data circuit of aforesaid Synchronous Dynamic Random Access Memory, wherein said data output circuit comprises: one the 3rd D type flip-flop, in order to receiving the second portion of these data that this exchanges data circuit will export, and according to the second portion of should default time pulse signal exporting these data; One selector switch is to receive the output of the 3rd D type flip-flop and the first of these data that this exchanges data circuit will be exported respectively, and decides the output first of these data and second portion the two one of them according to a counting signal; And one the 4th D type flip-flop, be the output that receives this selector switch, in order to according to the first that should default time pulse signal exports these data and second portion the two one of them.
The exchanges data circuit of aforesaid Synchronous Dynamic Random Access Memory, wherein said data output circuit more comprises a counter, in order to produce a counting signal, make the first of these data of this selector switch decision output and second portion the two one of them to this selector switch.
The exchanges data circuit of aforesaid Synchronous Dynamic Random Access Memory, wherein said shade signal generating circuit comprises a multiplexer, be to receive predetermined shade (DQM) signal, and according to a sign state decide output should predetermined shade signal to going up predetermined shade pin and the predetermined shade pin of this time the two one of them.
The exchanges data circuit of aforesaid Synchronous Dynamic Random Access Memory, it is to be applied to a video and audio CD disc (VCD) playing device.
The exchanges data circuit of aforesaid Synchronous Dynamic Random Access Memory, it is to be applied to numerical digit video signal laser disc (DVD) playing device.
The object of the invention to solve the technical problems also adopts following technical scheme to realize.The method for interchanging data of a kind of Synchronous Dynamic Random Access Memory (SDRAM) that proposes according to the present invention, be applicable to this SDRAM in the optical storage media reading device, wherein this SDRAM has most data pins, couple mutually with the data bus in this optical storage media reading device, and the width of this data bus is the number less than those data pins, and this SDRAM has more predetermined shade (UDQM) pin and predetermined shade (LDQM) pin on one once, this method for interchanging data may further comprise the steps: when exporting these data to this SDRAM, activation should be gone up predetermined shade pin and the predetermined shade pin of this time the two one of them, and it is wherein a part of to those data pins to export the first of these data; Activation should be gone up predetermined shade pin and the predetermined shade pin of this time the two another, and the second portion of exporting these data is to those pin another part; When receiving these data,, receive the second portion of these data again from those data pin another part earlier from the wherein a part of first that receives these data of those data pins by this SDRAM; And make up the first of these data and second portion with this reduction of data.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method for interchanging data of aforesaid Synchronous Dynamic Random Access Memory, the first of wherein said data be the high bit part of these data and low bit part the two wherein one, and the second portion of these data is the high bit part of these data and low bit partly the two another.
The method for interchanging data of aforesaid Synchronous Dynamic Random Access Memory, it more comprises provides a default time pulse signal.
The method for interchanging data of aforesaid Synchronous Dynamic Random Access Memory is wherein exported these data to the step of this SDRAM and is more comprised the following steps: in the time will exporting these data to this SDRAM, and the cycle of the next default time pulse signal of definition is first cycle; In first cycle activation should on predetermined shade pin and the predetermined shade pin of this time the two one of them, and the first that exports these data; The second portion of these data of bolt-lock in first cycle; And in second period activation should on predetermined shade pin and the predetermined shade pin of this time the two another, and export the second portion of these data.
The method for interchanging data of aforesaid Synchronous Dynamic Random Access Memory is wherein comprised the following steps: in the time will receiving these data by this SDRAM by the step that this SDRAM receives these data, and the cycle of the next default time pulse signal of definition is first cycle; In first cycle activation should on predetermined shade pin and the predetermined shade pin of this time the two one of them, and receive the first of these data; In second period activation should on predetermined shade pin and the predetermined shade pin of this time the two another, and receive the second portion of these data; And make up the first of these data and second portion to reduce these data.
The method for interchanging data of aforesaid Synchronous Dynamic Random Access Memory, wherein said optical storage media reading device comprise a video and audio CD disc (VCD) playing device.
The method for interchanging data of aforesaid Synchronous Dynamic Random Access Memory, wherein said optical storage media reading device comprise numerical digit video signal laser disc (DVD) playing device.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, in order to reach aforementioned goal of the invention, major technique of the present invention thes contents are as follows:
The present invention proposes the exchanges data circuit of a kind of Synchronous Dynamic Random Access Memory (SDRAM), and wherein SDRAM has many data pins, is to be used for receiving or output data.In addition, SDRAM also has predetermined shade (UDQM) pin and predetermined shade (LDQM) pin on one once, and exchanges data circuit of the present invention comprises data input circuit and data output circuit, wherein data input circuit is the data pin that is coupled to SDRAM by several data line correspondences, and the number of these data lines, less than the number of the data pin of SDRAM.Data input circuit is in one of them cycle of a default time pulse signal, receive the first of data from the data pin of a part of SDRAM wherein, in the next cycle of default time pulse signal, receive the second portion of data from the data pin of another part SDRAM then.In addition, data output circuit also is coupled to the data pin of SDRAM by the data line correspondence.Similarly, data output circuit is in one of them cycle of default time pulse signal, the first of output data is the data pin of a part of SDRAM extremely wherein, and in the next cycle of default time pulse signal, the second portion of output data is to the data pin of another part SDRAM then.In addition, the present invention has more a shade signal generating circuit, be to couple predetermined shade pin of going up of SDRAM and following predetermined shade pin, it comes predetermined shade pin or following predetermined shade pin in the activation according to the first or the second portion of exchanges data circuit output/input data of the present invention.
In general, the first of data is the low address part of data and high address partly the two one of them.And the second portion of data then is the low address part of data and high address partly the two another.
In one embodiment of the invention, data input circuit comprises a D type flip-flop (Flip-flop) and the 2nd D type flip-flop.Wherein, a D type flip-flop is used for receiving the first of the data that input to the exchanges data circuit, and comes first's to the two D type flip-flops of output data according to default time pulse signal.The 2nd D type flip-flop then receives the output of a D type flip-flop respectively and inputs to the second portion of the data of exchanges data circuit, and comes the first of data splitting and second portion with restoring data according to default time pulse signal.
In addition, data output circuit comprises the 3rd D type flip-flop, the 4th D type flip-flop and selector switch.The 3rd D type flip-flop is used for receiving the second portion of exchanges data circuit with the data of output, and comes the second portion of output data to selector switch according to default time pulse signal.And selector switch receives the output of the 3rd D type flip-flop and the exchanges data circuit first with the data of output respectively, and decides the first or second portion to the four D type flip-flops of output data according to a counting signal.The 4th D type flip-flop then receives the output of selector switch, in order to come output data first or second portion to SDRAM according to default time pulse signal.
From another viewpoint, the present invention also provides the method for interchanging data of a kind of Synchronous Dynamic Random Access Memory (SDRAM), is useful in the SDRAM in the optical storage media reading device.Wherein, SDRAM has several data pins, and the data bus in itself and the optical storage media reading device couples each other, and the width of data bus is the number less than the data pin of SDRAM.In addition, SDRAM has more predetermined shade pin and following predetermined shade pin, and the step of method for interchanging data of the present invention is as described below.When output data during to SDRAM, activation (Enable) go up predetermined shade pin and down predetermined shade pin the two one of, and the first of output data is to the data pin of the SDRAM of a part wherein.Then, predetermined shade pin and predetermined shade pin the two another down in the activation, and the second portion of output data is to the data pin of the SDRAM of another part.And when receiving data by SDRAM, receive the first of data earlier from the data pin of wherein a part of SDRAM, receive the second portion of data again from the data pin of the SDRAM of another part, the first of data splitting and second portion are with reduction of data then.
Under preferable situation, method for interchanging data of the present invention more comprises provides a default time pulse signal earlier.
And in one embodiment of the invention, output data is as described below to the step of SDRAM.When wanting output data to SDRAM, then the cycle of the next default time pulse signal of definition is first cycle.During first cycle, predetermined shade pin and following the two one of them first of predetermined shade pin in the activation with output data, and bolt-lock is lived the second portion of data.Then, during second period, predetermined shade pin and predetermined shade pin the two another down in the activation are with the second portion of output data.
In addition, then as described below by the step of SDRAM reception data.In the time will receiving data by SDRAM, the cycle of the next default time pulse signal of definition is first cycle.During first cycle, predetermined shade pin and predetermined shade pin the two one of them down in the activation, and receive the first of data.Then during second period, predetermined shade pin and predetermined shade pin the two another down in the activation, and receive the second portion of data.At last, then the first of data splitting and second portion with restoring data.
In sum, exchanges data circuit of the present invention has comprised data output circuit and data input circuit, data can be divided into first and second portion transmits, and method for interchanging data of the present invention is first and second portion at two adjacent cycle swap datas.Therefore, the present invention can be transmitted bigger data with less highway width, make the present invention go for the electronic product of low capacity, for example the optical storage media reading device.
Via as can be known above-mentioned, the invention relates to a kind of exchanges data circuit of Synchronous Dynamic Random Access Memory, have plurality of data lines, be on several data pins that are coupled on the SDRAM.Wherein, the number of the data line that the present invention is included is the number less than the data pin on the SDRAM.When the present invention to receive/during output data, following predetermined shade pin on can first activation SDRAM and last predetermined shade pin the two one of them, and the first of reception/output data.And then predetermined shade pin and last predetermined shade pin the two another under the activation, and the second portion of reception/output data.Therefore, the present invention can use narrower highway width to receive/export bigger data.
By technique scheme, the exchanges data circuit and the method for Synchronous Dynamic Random Access Memory of the present invention have following advantage at least:
1, the present invention utilizes the following predetermined shade pin on the control SDRAM or goes up predetermined shade pin, transmit and data are divided into two parts, so the present invention can use narrower highway width to transmit bigger data to SDRAM.
2 and also because the present invention can use narrower highway width, therefore go on the electronic product of low capacity.
In sum, the exchanges data circuit of Synchronous Dynamic Random Access Memory of the present invention can transmit more large-capacity data with lower data-bus width.The method for interchanging data of Synchronous Dynamic Random Access Memory of the present invention is applicable to the electronic product of low capacity.It has above-mentioned many advantages and practical value, and in like product, do not see have similar structural design and method to publish or use and really genus innovation, no matter it all has bigger improvement on product structure, method or function, have large improvement technically, and produced handy and practical effect, and the exchanges data circuit of more existing Synchronous Dynamic Random Access Memory has the multinomial effect of enhancement, thereby being suitable for practicality more, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by going out preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is a kind of architecture block diagram that has the exchanges data circuit of known SDRAM now.
Fig. 2 is the transmission circuit architecture block diagram according to a kind of SDRAM of a preferred embodiment of the present invention.
Fig. 3 is the method for interchanging data process flow diagram according to a kind of SDRAM of a preferred embodiment of the present invention.
Fig. 4 A is the block scheme according to a kind of data input circuit of a preferred embodiment of the present invention.
Fig. 4 B is the method flow diagram according to a kind of data input of a preferred embodiment of the present invention.
Fig. 4 C is the signal sequential chart of the data input circuit of Fig. 4 A.
Fig. 5 A is a kind of data output circuit block scheme according to a preferred embodiment of the present invention.
Fig. 5 B is the method flow diagram according to a kind of data output of a preferred embodiment of the present invention.
Fig. 5 C is the signal sequential chart of the data output circuit of Fig. 5 A.
Fig. 6 is a kind of shade signal generating circuit block scheme according to a preferred embodiment of the present invention.
100,200: exchanges data circuit 102,220:SDRAM
110: control line 120: address wire (address lines)
130,208: data line (data line) 202: data input circuit
204: data output circuit 206: the shade signal generating circuit
403: the two D types of 401: the one D type flip-flops flip-flop
501: the three D type flip-flops 503: selector switch
505: the four D type flip-flops 507: counter
601: multiplexer 603: sign (flag) working storage
The method for interchanging data process step of S301, S303, S305, S307, S309:SDRAM
S401, S403, S405, S407: the method flow step of data input
S501, S503, S505, S507: the method flow step of data output
/ CS ,/RAS ,/CAS ,/WE: controlling signal
Addres s: address (address) pin CK: default time pulse signal
Q0～Qn: data pin DQM: shade signal
LDQM: following predetermined shade pin UDQM: upward predetermined shade pin
DQ[7:0]: data bus (data bus)
DQ_DLY[7:0]: the output of a D type flip-flop
DIN[15:0]: the output of the 2nd D type flip-flop
DOUT[15:0], DOUT[15:8], DOUT[7:0]: local bus (local bus-bar)
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, exchanges data circuit and its embodiment of method, structure, method, step, feature and the effect thereof of the Synchronous Dynamic Random Access Memory that foundation the present invention is proposed, describe in detail as after.
Seeing also shown in Figure 2ly, is the transmission circuit architecture block diagram according to a kind of SDRAM of a preferred embodiment of the present invention.As shown in the figure, exchanges data circuit 200 provided by the present invention can be applied in the optical storage media reading device (as VCD, DVD playing device), is to be utilized to intercourse data with SDRAM220.In exchanges data circuit 200, data input circuit 202, data output circuit 204 and shade signal generating circuit 206 have been comprised.Wherein, data input circuit 202 and data output circuit 204 are data pin (corresponding separately from each other the coupling of Q0～Qn) by data line 208 and SDRAM 220, and the number of data line 208, the width of data bus just is the data pin (number of Q0～Qn) less than SDRAM220.In addition, SDRAM 220 also has upward predetermined shade pin UDQM and following predetermined shade pin LDQM, is to couple shade signal generating circuit 206 jointly.
Seeing also shown in Figure 3ly, is the method for interchanging data process flow diagram according to a kind of SDRAM of a preferred embodiment of the present invention.As shown in the figure, at first as described in the step S301, judgment data switched circuit 200 is to receive data by SDRAM 220, or wants output data to SDRAM 220.(" reception ") that just step S301 is indicated in the time will receiving data by SDRAM220, then data input circuit 202 is as described in the step S303, earlier (receive the first of data as Q0～Qm), and then (receive the second portion of data as Qm+1～Qn) from the data pin of another part from the data pin of a part of SDRAM wherein.Then, exchanges data circuit 200 can be as described in the step S305, and the first of data splitting and second portion are with restoring data.Relatively, (" output ") that just step S301 is indicated when transmission circuit 200 is wanted output data to SDRAM 220, then shade signal generating circuit 206 can be as described in the step S307, send the shade signal and come in the activation predetermined shade pin UDQM and predetermined shade pin LDQM the two one of them down, and the first of output data to the data pin of a part wherein (as Q0～Qm).Shade signal generating circuit 206 can carry out step S309 then, send the shade signal and come in the activation predetermined shade pin UDQM and predetermined shade pin LDQM the two another down, and the second portion of output data to the data pin of another part (as Qm+1～Qn).
In the present embodiment, the first of data can be the high address part of data and low address part the two one of them, the second portion of data then be data high address partly and low address partly the two another.
Seeing also shown in Fig. 4 A, is the block scheme according to a kind of data input circuit of a preferred embodiment of the present invention.As shown in the figure, the highway width of supposing the data input circuit among Fig. 4 A is 8, and the number of the data pin of SDRAM is 16.In the present embodiment, data input circuit has a D type flip-flop 401 and the 2nd D type flip-flop 403.Wherein, the input of a D type flip-flop 401 is to couple data bus DQ[7:0], the 2nd D type flip-flop 403 then receives the output DQ_DLY[7:0 of a D type flip-flop 401] and data bus DQ[7:0].
See also shown in Fig. 4 B and Fig. 4 C, Fig. 4 B is that Fig. 4 C is the signal sequential chart of the data input circuit of Fig. 4 A according to the method flow diagram of a kind of data input of a preferred embodiment of the present invention.As shown in the figure, when the period T 0 of the data input circuit among Fig. 4 A at default time pulse signal CK, begin to receive SDRAM and transmit the data of coming, then as described in the step S401, definition is next, and to preset time pulse signal period T 1 be first cycle.Then as described in the step S403, in first period T 1, activation SDRAM goes up predetermined shade pin UDQM and predetermined shade pin LDQM the two one of them down, and a D type flip-flop 401 is from data bus DQ[7:0] receive the D0 of first of data, then its bolt-lock is lived.Then as described in the step S405, during second period, predetermined shade pin UDQM and predetermined shade pin LDQM the two one of them down in the activation, at this moment, the one D type flip-flop 401 can be from its output DQ_DLY[7:0] send the D0 to the of the first two D type flip-flops 403 of data, almost simultaneously, the second portion D1 of data can be from data bus DQ[7:0], via the output DQ_DLY[7:0 of a D type flip-flop 401] deliver to the 2nd D type flip-flop 403.In the present embodiment, then the 2nd D type flip-flop 403 can be in second period T2, and as described in step S407, the D0 of first of data splitting and second portion D1 be with reduction of data, and from its output terminal DIN[15:0] the output raw data.
Seeing also shown in Fig. 5 A, is a kind of data output circuit block scheme according to a preferred embodiment of the present invention.As shown in the figure, suppose to have in the exchanges data circuit of the present invention highway width and be 16 local bus DOUT[15:0], be to be used for transmitting the data that will export SDRAM to.In the present embodiment, the input of the 3rd D type flip-flop 501 is coupled to local bus DOUT[15:0] a part of DOUT[15:8], it exports DOUT_DLY[15:8] then be coupled to the input of selector switch 503.Another input of selector switch 503 then couples local bus DOUT[15:0] another part DOUT[7:0], and the output terminal DOUT_TMP[7:0 of selector switch 503], then be coupled to the 4th D type flip-flop 505, and the output terminal of the 4th D type flip-flop 505 is to be coupled on the data pin of SDRAM by the data bus that several data lines are formed.Suppose that the number of data line is 8, the highway width that is to say data output circuit is 8.In addition, selector switch 503 selecting sides are counting signals that count pick up device 507 is produced, and it uses the output terminal DOUT_TMP[7:0 that decides selector switch 503] be coupled to and import DOUT[15:8] or DOUT[7:0].
See also shown in Fig. 5 B and Fig. 5 C, wherein, Fig. 5 B is that Fig. 5 C is the signal sequential chart of the data output circuit of Fig. 5 A according to the method flow diagram of a kind of data output of a preferred embodiment of the present invention.As shown in the figure, supposing has data from local bus DOUT[15:0 when the period T 0 of default time pulse signal CK] input, desire to deliver to SDRAM, then as described in the step S501, the next default time pulse signal period T 1 of definition is first cycle.At this moment, the D0 of first of data can be from local bus DOUT[15:0] a part of DOUT[7:0] directly deliver to selector switch 503, and counter 507 can output be counted signal, makes selector switch 503 in period T 0 D0 of first of data directly be delivered to the 4th D type flip-flop 505 bolt-locks.Almost simultaneously, the second portion D1 of data can be from local bus DOUT[15:0 in period T 0] another part DOUT[15:8] deliver to the 3rd D type flip-flop 501, and got up by bolt-lock.Meeting then of the present invention is as described in the step S503, in first period T 1, can activation SDRAM go up predetermined shade pin UDQM and predetermined shade pin LDQM the two one of them down, and the 4th D type flip-flop 505 can be with the first of data via data bus DQ[7:0], export the part in the data pin of SDRAM to.Almost at the same time, the 3rd D type flip-flop 501 can export the second portion D1 of data to selector switch 503, and counter 507 can output be counted signal, make selector switch 503 that the second portion D1 of data is delivered to the 4th D type flip-flop 505, and, the second portion D1 bolt-lock of data is got up as as described in the step S505.At last, as described in step S507, in second period T2, can activation on predetermined shade pin UDQM and predetermined shade pin LDQM the two another down, and the 4th D type flip-flop 505 can export the second portion D1 of data to the another part in the data pin of SDRAM.
Seeing also shown in Figure 6ly, is a kind of shade signal generating circuit block scheme according to a preferred embodiment of the present invention.As shown in the figure, in the present embodiment, provide a kind of shade signal generating circuit, it has comprised multiplexer 601.Multiplexer 601 is to receive shade signal DQM, according to the sign state that for example indicates that working storage 603 is stored, decides shade signal DQM is delivered to the following predetermined shade pin LDQM of SDRAM or goes up predetermined shade pin UDQM then.
In sum, the present invention utilizes the following predetermined shade pin on the control SDRAM or goes up predetermined shade pin, transmit and data are divided into two parts, so the present invention can use narrower highway width to transmit bigger data to SDRAM.And, therefore go on the electronic product of low capacity also because the present invention can use narrower highway width.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (15)
1, the exchanges data circuit of a kind of Synchronous Dynamic Random Access Memory (SDRAM), it is characterized in that wherein this SDRAM has most data pins, in order to receive or to export data, and this SDRAM also has predetermined shade (UDQM) pin and predetermined shade (LDQM) pin on one once, and this exchanges data circuit comprises:
One data input circuit, be to couple those data pins by most data line correspondences, and the number of those data lines is the numbers less than those data pins, this data input circuit is in the one-period of a default time pulse signal, receive the first of these data from the part of those data pins, and in the following one-period of this default time pulse signal, receive the second portion of these data from another part of those data pins;
One data output circuit, be to couple those data pins by those data line correspondences, this data output circuit is in the one-period of this default time pulse signal, the first that exports these data is wherein a part of to those data pins, and in the following one-period of this default time pulse signal, export the second portion of these data another part to those data pins; And
One shade signal generating circuit, couple predetermined shade pin and the predetermined shade pin of this time on this, and, come activation should go up tentation data switched circuit shade pin and the predetermined shade pin of this time the two one of them according to the first or the second portion of these these data of data output circuit output/input.
2, the exchanges data circuit of Synchronous Dynamic Random Access Memory according to claim 1, the first that it is characterized in that wherein said data, be the low address part of these data and high address partly the two one of them, and the second portion of these data then is the low address part of these data and high address partly the two another.
3, the exchanges data circuit of Synchronous Dynamic Random Access Memory according to claim 1 is characterized in that wherein said data input circuit comprises:
One the one D type flip-flop, in order to the first of these data of receiving this exchanges data circuit of input, and according to the first that should default time pulse signal exports these data; And
One the 2nd D type flip-flop is the second portion that receives the output of a D type flip-flop respectively and import these data of this exchanges data circuit, and according to the first that should default time pulse signal makes up these data and second portion to reduce these data.
4, the exchanges data circuit of Synchronous Dynamic Random Access Memory according to claim 1 is characterized in that wherein said data output circuit comprises:
One the 3rd D type flip-flop, in order to receiving the second portion of these data that this exchanges data circuit will export, and according to the second portion of should default time pulse signal exporting these data;
One selector switch is to receive the output of the 3rd D type flip-flop and the first of these data that this exchanges data circuit will be exported respectively, and decides the output first of these data and second portion the two one of them according to a counting signal; And
One the 4th D type flip-flop is the output that receives this selector switch, in order to according to the first that should default time pulse signal exports these data and second portion the two one of them.
5, the exchanges data circuit of Synchronous Dynamic Random Access Memory according to claim 4, it is characterized in that wherein said data output circuit more comprises a counter, in order to produce a counting signal, make the first of these data of this selector switch decision output and second portion the two one of them to this selector switch.
6, the exchanges data circuit of Synchronous Dynamic Random Access Memory according to claim 1, it is characterized in that wherein said shade signal generating circuit comprises a multiplexer, be to receive predetermined shade (DQM) signal, and according to a sign state decide output should predetermined shade signal to going up predetermined shade pin and the predetermined shade pin of this time the two one of them.
7, the exchanges data circuit of Synchronous Dynamic Random Access Memory according to claim 1 is characterized in that it is to be applied to a video and audio CD disc (VCD) playing device.
8, the exchanges data circuit of Synchronous Dynamic Random Access Memory according to claim 1 is characterized in that it is to be applied to numerical digit video signal laser disc (DVD) playing device.
9, the method for interchanging data of a kind of Synchronous Dynamic Random Access Memory (SDRAM), be applicable to this SDRAM in the optical storage media reading device, wherein this SDRAM has most data pins, couple mutually with the data bus in this optical storage media reading device, and the width of this data bus is the number less than those data pins, and this SDRAM has more predetermined shade (UDQM) pin and predetermined shade (LDQM) pin on one once, it is characterized in that this method for interchanging data may further comprise the steps:
When these data of output during to this SDRAM, activation should be gone up predetermined shade pin and the predetermined shade pin of this time the two one of them, and it is wherein a part of to those data pins to export the first of these data;
Activation should be gone up predetermined shade pin and the predetermined shade pin of this time the two another, and the second portion of exporting these data is to those pin another part;
When receiving these data,, receive the second portion of these data again from those data pin another part earlier from the wherein a part of first that receives these data of those data pins by this SDRAM; And
Make up the first of these data and second portion with this reduction of data.
10, the method for interchanging data of Synchronous Dynamic Random Access Memory according to claim 9 (SDRAM), the first that it is characterized in that wherein said data be the high bit part of these data and low bit part the two wherein one, and the second portion of these data is the high bit part of these data and low bit partly the two another.
11, the method for interchanging data of Synchronous Dynamic Random Access Memory according to claim 9 (SDRAM), it is characterized in that it more comprises provides a default time pulse signal.
12, the method for interchanging data of Synchronous Dynamic Random Access Memory according to claim 11 (SDRAM) is characterized in that wherein exporting these data to the step of this SDRAM and more comprises the following steps:
In the time will exporting these data to this SDRAM, the cycle of the next default time pulse signal of definition is first cycle;
In first cycle activation should on predetermined shade pin and the predetermined shade pin of this time the two one of them, and the first that exports these data;
The second portion of these data of bolt-lock in first cycle; And
In second period activation should on predetermined shade pin and the predetermined shade pin of this time the two another, and export the second portion of these data.
13, the method for interchanging data of Synchronous Dynamic Random Access Memory according to claim 11 (SDRAM) is characterized in that wherein the step that is received these data by this SDRAM comprises the following steps:
In the time will receiving these data by this SDRAM, the cycle of the next default time pulse signal of definition is first cycle;
In first cycle activation should on predetermined shade pin and the predetermined shade pin of this time the two one of them, and receive the first of these data;
In second period activation should on predetermined shade pin and the predetermined shade pin of this time the two another, and receive the second portion of these data; And
Make up the first of these data and second portion to reduce these data.
14, the method for interchanging data of Synchronous Dynamic Random Access Memory according to claim 9 (SDRAM) is characterized in that wherein said optical storage media reading device comprises a video and audio CD disc (VCD) playing device.
15, the method for interchanging data of Synchronous Dynamic Random Access Memory according to claim 9 (SDRAM) is characterized in that wherein said optical storage media reading device comprises numerical digit video signal laser disc (DVD) playing device.
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| CN108628778A (en) * | 2017-03-23 | 2018-10-09 | 发那科株式会社 | More storage row SDRAM control methods and sdram controller |
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| KR100364127B1 (en) * | 1997-12-29 | 2003-04-11 | 주식회사 하이닉스반도체 | Chip-set |
| JP2002288037A (en) * | 2001-03-27 | 2002-10-04 | Sony Corp | Memory control device and method |
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| US10474393B2 (en) | 2017-03-23 | 2019-11-12 | Fanuc Corporation | Multi-rank SDRAM control method and SDRAM controller |
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