CN1731574A - Circuit rewiring method and circuit structure - Google Patents
Circuit rewiring method and circuit structure Download PDFInfo
- Publication number
- CN1731574A CN1731574A CN 200510084372 CN200510084372A CN1731574A CN 1731574 A CN1731574 A CN 1731574A CN 200510084372 CN200510084372 CN 200510084372 CN 200510084372 A CN200510084372 A CN 200510084372A CN 1731574 A CN1731574 A CN 1731574A
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- conductive plate
- circuit
- integrated circuit
- conductive
- reroutes
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims description 28
- 230000004888 barrier function Effects 0.000 claims description 25
- 238000012360 testing method Methods 0.000 claims description 19
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 8
- 150000002894 organic compounds Chemical class 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000000523 sample Substances 0.000 description 17
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 230000000875 corresponding effect Effects 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 244000291564 Allium cepa Species 0.000 description 1
- 235000002732 Allium cepa var. cepa Nutrition 0.000 description 1
- 244000247747 Coptis groenlandica Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 240000001439 Opuntia Species 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 210000002683 foot Anatomy 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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Abstract
The invention discloses a circuit structure and a method for rearranging outer lines of integrated circuits. The inventive method comprises the steps of: placing a plurality of first conductive plates on base materials of the integrated circuit to form an insulating layer; then placing a plurality of second conductive plates on the insulating layer, each second conductive plate taking the first conductive plated with electric connection as center and moving a same vector. Exploiting the vector moving settings of the second conductive plates, the inventive circuit structure has the advantage of saving cost and material management.
Description
Technical field
The present invention relates to a kind of method that reroutes and circuit structure of integrated circuit, particularly a kind of second conductive plate of on integrated circuit all test boards being used to be to wait mode of vector, be arranged at its method that reroutes and the circuit structure of a side of corresponding first conductive plate.
Background technology
Probe (Probe Card) is before integrated circuit (IC) does not encapsulate as yet, in order to naked crystalline substance is done the function test to filter out the equipment of defective products, the non-defective unit that screens after the test, the encapsulation engineering after just can carrying out again with probe (Probe).Therefore, during integrated circuit is manufactured, the test of relevant QC, be one can't the abridged program.The yield that the use of probe can make finished product is promoted to more than 90% by original 70%, and the semiconductor factory that 20% yield contribution degree is all haggled over every penny 1% yield difference influences very huge.
Wafer sort is to utilize tester table and probe to come each crystal grain on the test wafer, is produced according to design specification with electrical characteristic and the usefulness of guaranteeing crystal grain.Tester table also can pass through special design in addition, its detection head loaded onto with gold thread make carefully probe as hair, contact with weld pad (Pad) on the chip by probe,, and then reach the purpose of test products so that directly to the chip input signal or detect output valve.
Because integrated circuit is when making, go up the circuit of manufacturing at chip (Wafer), often be the preferred circuit of same size, for example: may make thousands of or up to ten thousand identical operational amplifier or other preferred circuits on the same chip, but after being cut, these amplifiers or preferred circuit become many crystal grain (Die), then can be further with these crystal grain with after lead frame combines, the go forward side by side packaging operation of line correlation, make become on the market common packaged integrated circuit.
The circuit structure vertical view of known its external circuit of integrated circuit as shown in Figure 1.Wherein this external circuit comprises one first conductive plate 21, one the 3rd conductive plate 23 and an electric conductor 33; except packaged standard items; the user of general many integrated circuits usually can require the manufacturer of integrated circuit; pin with integrated circuit; manufacture the specification that meets this client, with circuit design or the layout that makes things convenient for this client.Go up the preferred circuit of manufacturing this moment at chip (Wafer), just must be when manufacturing with the external circuit of this integrated circuit, by the circuit rerouting technology that winds the line again, this external circuit is rearranged, so when crystal grain with after lead frame combines, the integrated circuit that encapsulation is finished, its pin specification just can meet requirement of client.
Known recoil line technology, because the only simple electrical property of its pin of integrated circuit after the encapsulation of considering meets client's specification, problem as for relevant product test in the processing procedure does not take in, therefore each integrated circuit is once through after recoiling line again, just must make a probe more again, so not only increased the cost of dependence test, simultaneously with regard to design, the buying of material, check and accept, use and manage with regard to the equal angles, the cost that is increased also is difficult to estimate virtually.
Summary of the invention
The present invention proposes for the following problem that solves known integrated circuit: when carrying out external circuit when recoiling line, must additionally make one again and meet the probe of test board spacing behind this recoil line, thereby increase cost and handling of goods and materials burden thereof.
The object of the invention provides a kind of circuit method that reroutes, carry out again arrangement in order to external circuit with an integrated circuit, may further comprise the steps: several first conductive plates are set on the base material of this integrated circuit, and each this first conductive plate is electrically connected with this integrated circuit; Form an insulating barrier, and be covered on this integrated circuit and this first conductive plate; Several second conductive plates are set on this insulating barrier, each second conductive plate is electrically connected one first conductive plate, and each this two conductive plate is the center with first conductive plate that is electrically connected, and moves the position of an identical vector and is provided with; And several the 3rd conductive plates are set on this insulating barrier, and each the 3rd conductive plate is electrically connected with this second conductive plate by one second conductor.
Another object of the present invention provides a kind of circuit structure that reroutes, in order to the external circuit of an integrated circuit is rearranged, comprise: several first conductive plates be arranged at respectively on the base material of this integrated circuit, and each first conductive plate are electrically connected with this integrated circuit; One insulating barrier is covered on this integrated circuit and this first conductive plate; Several second conductive plates are arranged on this insulating barrier, and each this second conductive plate is electrically connected one first conductive plate, and each second conductive plate is the center with first conductive plate that is electrically connected, and move the position of an identical vector and are provided with; And several the 3rd conductive plates, be arranged on this insulating barrier, and each the 3rd conductive plate is electrically connected with this second conductive plate by one second conductor.
By the setting that vector such as second conductive plate moves, make the position of all second conductive plate settings of the present invention all be positioned at a side of its pairing its equidirectional of first conductive plate and same distance.Therefore when desire uses second conductive plate that circuit is tested, can continue to use the probe of original test first conductive plate.So not only can avoid making extra probe, and back segment production fixture or materials and parts, for example therefore lead frame, substrate etc. also can be shared, and can also reach the effect of saving cost and handling of goods and materials in addition.
By enforcement of the present invention, can realize following effect at least:
One, by enforcement of the present invention, can continue to use the probe of original test first conductive plate, avoid making extra probe.
Two, by enforcement of the present invention, back segment production fixture or materials and parts are shared, help volume production and buying.
Three,, can reduce the cost of equipment and handling of goods and materials, and can avoid the similar probe of external form to be misapplied, and cause the problem on the processing procedure by enforcement of the present invention.
The present invention is described in detail below in conjunction with accompanying drawing.
Description of drawings
Fig. 1 is the circuit structure vertical view of known its external circuit of integrated circuit;
Fig. 2 is the external circuit of a kind of integrated circuit of the present invention method embodiment flow chart that reroutes;
Fig. 3 A is the circuit structure embodiment vertical view that reroutes of a kind of integrated circuit of the present invention;
Fig. 3 B is the three-dimensional partial enlarged drawing of Fig. 3 A;
Fig. 3 C is the partial enlarged drawing of overlooking of Fig. 3 A;
Fig. 3 D is the cutaway view of A-A hatching among Fig. 3 B;
Fig. 4 is the embodiment vertical view of the present invention when having nemaline first conductor;
Fig. 5 be the present invention have the one side shape first conductor time the embodiment vertical view;
Fig. 6 is the embodiment vertical view after the present invention omits first conductor.
Description of reference numerals: step S1 is provided with several first conductive plates; Step S2 forms an insulating barrier; Step S3 is provided with several second conductive plates, and each second conductive plate is the center with first conductive plate of its electric connection, move an identical vector and be provided with; Step S4 is provided with several the 3rd conductive plates, and electrically connects by one second conductor and second conductive plate; 10 base materials; 21 first conductive plates; 22 second conductive plates; 23 the 3rd conductive plates; 31 first conductors; 32 second conductors; 33 electrical conductors; 4 insulating barriers.
Embodiment
As shown in Figure 2 be the external circuit of a kind of integrated circuit of the present invention method embodiment flow chart that reroutes, this method embodiment carries out again arrangement with the external circuit of an integrated circuit, it comprises the following steps: to be provided with several first conductive plates on the base material of this integrated circuit, and each this first conductive plate is electrically connected (step S1) with this integrated circuit; Form an insulating barrier, be covered on this integrated circuit and this first conductive plate (step S2); Several second conductive plates are set on this insulating barrier, each this second conductive plate is electrically connected this first conductive plate, and each this second conductive plate is the center with this first conductive plate of its electric connection, moves the position of an identical vector and (step S3) is set; And several the 3rd conductive plates are set on this insulating barrier, and each the 3rd conductive plate, be electrically connected (step S4) by one second conductor with this second conductive plate.
The circuit structure embodiment vertical view that reroutes of a kind of integrated circuit of the present invention as shown in Figure 3A.In above-mentioned circuit reroutes the method and the circuit structure embodiment that reroutes, base material 10 is a chip, and this integrated circuit and external circuit thereof all are made on this base material 10, after integrated circuit and external circuit thereof complete, again with this base material 10 according to made circuit unit, be cut into many crystal grain, and then combine, and carry out follow-up packaging operation with lead frame.
First conductive plate 21 is formed on this base material 10, and each this first conductive plate 21 is electrically connected with this integrated circuit, and it can do the test of phase I by 21 pairs of made integrated circuits of this first conductive plate.
Insulating barrier 4 is covered on this integrated circuit and this first conductive plate 21, this insulating barrier 4 can be the insulating barrier 4 of silicon monoxide (SiOx) or a silicon nitride (SiNx) or an organic compound (Organic material), again this organic compound system poly-green onion imines (Polyimide) for example.
Second conductive plate 22 is arranged on this insulating barrier 4, and each second conductive plate 22 is electrically connected one first conductive plate 21 when being provided with, and each second conductive plate 22 is the center with first conductive plate 21 of its electrical connection, moves the position of an identical vector and is provided with.Second conductive plate 22 is tested usefulness in order to the integrated circuit second stage to be provided, so it is the good test board of a conductivity.General second conductive plate 22 can be in plane inequality with first conductive plate 21 by the support of insulating barrier 4, so that the design of circuit rerouting has more elasticity and staggered space is arranged.During test, can carry out the input and the output of signal to second conductive plate 22, the quality examination that whether flaw is arranged and be correlated with testing circuit by probe.
The 3rd conductive plate 23 can be arranged on this insulating barrier 4, and each the 3rd conductive plate 23, is electrically connected with one second conductive plate 22 by one second conductor 32.The 3rd conductive plate 23 is that this integrated circuit is connected the contact of (for example routing connection) with external module.
The three-dimensional partial enlarged drawing of Fig. 3 A shown in Fig. 3 B.Fig. 3 A shown in Fig. 3 C overlooks partial enlarged drawing.The cutaway view of A-A hatching among Fig. 3 B shown in Fig. 3 D.Fig. 3 B, Fig. 3 C and Fig. 3 D, in order to represent that first conductive plate 21 and second conductive plate 22 are benchmark with its central point, the relation of angle and distance between the two.When second conductive plate 22 of present embodiment is provided with, first conductive plate 21 and second conductive plate 22 are arranged in the same rectangular coordinate system, this rectangular coordinate system is a known rectangular coordinate system with X-axis, Y-axis, Z axle for example.This rectangular coordinate system comprises one at conplane X-axis line and Y-axis line and perpendicular to the Z axle on this plane again.Wherein the X-axis on Y-axis line right side be on the occasion of, and the X-axis in Y-axis line left side is a negative value, and the Y-axis of X-axis line top be on the occasion of, and the X-axis below the Y-axis line is a negative value, again the Z axle be positioned at this X, the formed plane of Y top person on the occasion of, and the below person who is positioned at this plane is negative value.The part of relevant angle calculation, the X-axis line on Y-axis line right side is the angle zero degree, just first angle initial point of starting at counterclockwise to divide, can be divided into the formed plane area of this X, Y 360 degree.With regard to the Z axle, it is the angle zero degree with the formed plane of this X, Y, and just second spends the initial point of starting at, and counterclockwise to divide, also can be divided into 360 degree perpendicular to X, Y institute plane area.And the position that this X-axis line, Y-axis line and z axis intersect or be called this origin of coordinates, the just position of each first conductive plate, 21 its central point of present embodiment.
When each second conductive plate 22 is provided with, only corresponding single first conductive plate 21, and what is called moves the relation that an identical vector is meant each second conductive plate 22 and 21 relative positions of its pairing first conductive plate, is the first identical angle A and second angle B and identical distance C.For example: first angle A central point of each second conductive plate, 22 displacement coordinate initial point (first conductive plate 21)) is that 45 degree, second angle B are that 15 degree and the distance C of displacement coordinate initial point (first conductive plate 21) are 2 millimeters (mm).The spacing that each second conductive plate like this is 22 reaches the relation of position toward each other, can and the spacing of 21 of each first conductive plates and the relation of position is in full accord toward each other, thereby can continue to use the probe of original test die pad, and avoid making extra probe.
If 21 of the present invention's second conductive plate 22 first conductive plates corresponding with it, its position relation is not represented with angle A, B and distance C, but with for example: the spacing of each second conductive plate, 22 equal displacement coordinate initial point is that X-axis+2 millimeter (mm), Y-axis+3 millimeter (mm) and Z axle+1 millimeter modes such as (mm) are when being represented, because only be the mode difference that the position is represented, will impartial effectiveness take place with the identical vector that moves of present embodiment.
For whole circuit can be interconnected, so present embodiment is provided with several first conductors 31 again, is electrically connected one second conductive plate 22 and pairing one first conductive plates 21 thereof by each bar first conductor 31.Several second conductors 32 are set again again,, electrically connect one second conductive plate 22 and pairing several lead foots thereof by each bar second conductor 32.
Embodiment vertical view when the present invention as shown in Figure 4 has nemaline first conductor.Fig. 5 be the present invention have the one side shape first conductor time the embodiment vertical view.The present invention as shown in Figure 6 omits the embodiment vertical view behind first conductor.First conductor 31 is when the position of first conductive plate 21 and the design of second conductive plate 22 is kept off, in order to being electrically connected first conductive plate 21 and second conductive plate 22, this first conductor 31 except that as can shape for face, can also be the shape of a line.But when the position of first conductive plate 21 and the design of second conductive plate 22 quite near the time, also first conductor 31 can be omitted, directly the area of first conductive plate 21 or second conductive plate 22 is strengthened and first conductive plate 21 directly is electrically connected with second conductive plate 22.
The above only is preferred embodiment of the present invention, when not limiting the scope of the invention with this.Therefore, all equalizations of doing according to claim of the present invention change and modify, and will not lose main idea of the present invention place, also without departing from the spirit or scope of the invention, all should be considered as further enforcement of the present invention.
Claims (12)
1. circuit method that reroutes is characterized in that, may further comprise the steps:
Several first conductive plates are set on the base material of this integrated circuit, and each first conductive plate is electrically connected with this integrated circuit;
Form an insulating barrier, and be covered on this integrated circuit and this first conductive plate;
Several second conductive plates are set on this insulating barrier, each this second conductive plate is electrically connected this first conductive plate, and each this second conductive plate is the center with first conductive plate of its electrical connection, moves the position of an identical vector and is provided with; And
Several the 3rd conductive plates are set on this insulating barrier, and each the 3rd conductive plate is electrically connected with this second conductive plate by one second conductor.
2. the method that reroutes as claimed in claim 1 is characterized in that, this identical vector is identical angle and equal distance.
3. the method that reroutes as claimed in claim 1, it comprises that further one is provided with the step of several first conductors, it is electrically connected one first conductor between each second conductive plate and pairing first conductive plate thereof.
4. the method that reroutes as claimed in claim 1 is characterised in that, second conductive plate is the conductive plate of a test usefulness.
5. the method that reroutes as claimed in claim 1 is characterised in that, the 3rd conductive plate is used so that this integrated circuit is electrically connected with other external circuit.
6. the circuit structure that reroutes is characterized in that, comprising:
Several first conductive plates are arranged on the base material of this integrated circuit, and each first conductive plate is electrically connected with this integrated circuit;
One insulating barrier is covered on this integrated circuit and this first conductive plate;
Several second conductive plates are arranged on this insulating barrier, and each this second conductive plate is electrically connected one first conductive plate, and each second conductive plate is the center with first conductive plate that is electrically connected, and move the position of an identical vector and are provided with; And
Several the 3rd conductive plates are arranged on this insulating barrier, and each the 3rd conductive plate is electrically connected with this second conductive plate by one second conductor.
7. the circuit structure that reroutes as claimed in claim 6 is characterised in that, this insulating barrier is the insulating barrier of silicon monoxide (SiOx) or a silicon nitride (SiNx) or an organic compound.
8. the circuit structure that reroutes as claimed in claim 7 is characterised in that, this organic compound is a polyimides.
9. the circuit structure that reroutes as claimed in claim 6 is characterised in that, this identical vector is identical angle and equal distance.
10. the circuit structure that reroutes as claimed in claim 6 is characterised in that, further comprises several first conductors, and each first conductor is electrically connected one second conductive plate and one first conductive plate.
11. the circuit structure that reroutes as claimed in claim 6 is characterised in that, second conductive plate is the test board of a test usefulness.
12. the circuit structure that reroutes as claimed in claim 6 is characterised in that, the 3rd conductive plate is used to make integrated circuit to be electrically connected with other external circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100843728A CN100346467C (en) | 2005-07-19 | 2005-07-19 | Circuit rewiring method and circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100843728A CN100346467C (en) | 2005-07-19 | 2005-07-19 | Circuit rewiring method and circuit structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1731574A true CN1731574A (en) | 2006-02-08 |
| CN100346467C CN100346467C (en) | 2007-10-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100843728A Active CN100346467C (en) | 2005-07-19 | 2005-07-19 | Circuit rewiring method and circuit structure |
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| Country | Link |
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| CN (1) | CN100346467C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104600043A (en) * | 2013-10-30 | 2015-05-06 | 瑞萨电子株式会社 | Semiconductor Device and Method for Manufacturing Semiconductor Device |
| CN109524377A (en) * | 2018-11-19 | 2019-03-26 | 武汉新芯集成电路制造有限公司 | A kind of rewiring structure of chip |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05160215A (en) * | 1991-12-09 | 1993-06-25 | Toshiba Corp | Evaluation tool for semiconductor device |
| JPH06140484A (en) * | 1992-10-28 | 1994-05-20 | Nippon Telegr & Teleph Corp <Ntt> | Probe card |
| JP2539763B2 (en) * | 1994-06-23 | 1996-10-02 | 株式会社リコー | Semiconductor device mounting method |
| JPH0855879A (en) * | 1994-08-16 | 1996-02-27 | Nec Corp | Tape for tab and manufacture of semiconductor device using tape for tab |
| JP2581017B2 (en) * | 1994-09-30 | 1997-02-12 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JPH09330934A (en) * | 1996-06-12 | 1997-12-22 | Toshiba Corp | Semiconductor device and its manufacture |
| JP4794808B2 (en) * | 2001-04-04 | 2011-10-19 | 富士通セミコンダクター株式会社 | Contactor device for semiconductor device and test method of semiconductor device |
| JP4559733B2 (en) * | 2002-01-25 | 2010-10-13 | 株式会社アドバンテスト | Probe card and probe card manufacturing method |
-
2005
- 2005-07-19 CN CNB2005100843728A patent/CN100346467C/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104600043A (en) * | 2013-10-30 | 2015-05-06 | 瑞萨电子株式会社 | Semiconductor Device and Method for Manufacturing Semiconductor Device |
| EP2876679A3 (en) * | 2013-10-30 | 2015-08-12 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing the same |
| CN109524377A (en) * | 2018-11-19 | 2019-03-26 | 武汉新芯集成电路制造有限公司 | A kind of rewiring structure of chip |
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| Publication number | Publication date |
|---|---|
| CN100346467C (en) | 2007-10-31 |
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