CN1728626A - Method and device for detecting error code in wireless digital communication system - Google Patents
Method and device for detecting error code in wireless digital communication system Download PDFInfo
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Abstract
The method includes steps: generating pseudo random sequence in use for testing data; test initialization including initializing counter for error code and looping back channels needed to test in system; sending out test series in use for pseudo random sequence to pass through loop backed channels needed to test, and sustaining for certain time; acceptance test sequence in use for receiving original pseudo random test sequence, and receiving result of test sequence from loop back channel, and sustaining for certain time; sequence of comparison test in use for comparing bit by bit continuously between received result of test sequence and original pseudo random test sequence; result statistics of error code calculated from relevant error code rate based on value of counter for error code after testing is completed. Features are: neat algorithm, simple structure of equipment, capable of testing channels in large scale (thousands), using only little system resource in time of test.
Description
Technical field
The invention belongs to radio digital communication system, be specifically related to the bit error detection method and the device of radio digital communication system.
Background technology
Error detection is a kind of very general test and the means of orientation problem in digital communication system, and especially in radio digital communication, the error code in order to determine to be produced in the communication process must carry out Error detection.Do not have the error code testing function in the present radio digital communication system, when needing the test error code, use the bit error analyzing instrument that its error performance is measured usually.Though bit error analyzing instrument feature richness,, cost an arm and a leg, be difficult for adaptive with some system interface, need add outer secondary growth encourage line drive circuit usually in addition.
The patent No. is 99812651.9 Chinese patent " being transmitter, receiver and the method that a plurality of subscriber channels produce the PN sequences in telecommunication system ", based on time slot, use the PN sequencer, status register, transmitter and receiver carries out Error detection to a plurality of subscriber channels.In detecting, it all the time a plurality of status registers to be set, when i bar Channel Detection begins, in the PN sequence, the state information of this moment deposits i status register in, when i bar Channel Detection finishes, obtain in the PN sequence state information of this moment,, can reflect the error code state of i bar channel by the comparative analysis of content in software algorithm and i the status register.Like this, PN sequence just can be used to the Error detection of a plurality of subscriber channels.But there are the following problems for it:
1. such method only is applicable to the detection of (tens channels) on a small scale, and when the channel number increased, the complexity of software algorithm increased greatly, and is also different to the status register initial value of different channels, to such an extent as to can't in time draw analysis result.
2. many status registers will consume a lot of system resources, and in radio digital communication system, and system resource is very valuable often, when in the face of large volumes of channels (thousands of), often can't provide enough system resource.Therefore this method is unsuitable for wireless communication system.
Summary of the invention
The technical problem to be solved in the present invention be to provide a kind of be applicable to wireless communication system bit error detection method and device, this method algorithm is succinct, and this apparatus structure is simple, can the channel of extensive (thousands of) be detected, and when detecting, only take system resource seldom.
In order to reach goal of the invention of the present invention, the invention discloses a kind of bit error detection method of radio digital communication system, comprise the steps:
(1) produces pseudo random sequence, as test data;
(2) test initialization comprises required detection channel in the tested wireless communication system of initialization error code counter and loopback;
(3) send cycle tests, be used for the required detection channel of pseudo random sequence by loop backed, and certain time;
(4) acceptance test sequence, be used to receive original pseudorandom cycle tests and on the loop back channel the reception result cycle tests, and continue and time of step (3) equal length;
(5) compare test sequence, the comparison that cycle tests as a result that is used for will receiving continuously and original pseudorandom cycle tests pursue bit;
(6) error code result statistics, the value of the error code counter after being used for finishing according to the testing time calculates the corresponding error rate.
Described pseudo random sequence is the m sequence.
The progression of described m sequence is 15.
Also comprise in the step (3) and judge whether error code counter overflows.
Step (5) is described pursues relatively comprising of bit:
If original cycle tests is with the cycle tests bit is identical as a result, then continue relatively next bit;
If original cycle tests and the cycle tests bit is inequality as a result, then error code counter adds 1, and continues relatively next bit.
If error code counter overflows, error code counter is got the maximum that its data type can reach and is calculated the error rate.
The invention also discloses a kind of device for detecting code error of radio digital communication system, comprise pseudo random sequence generation module, initiator block, receiving terminal module and loop back channel and error code counter, wherein,
Pseudo random sequence generation module is used to produce pseudo random sequence, as test data;
Initiator block is used to send cycle tests, with the required detection channel of pseudo random sequence by loop backed;
The receiving terminal module is used to receive original cycle tests and cycle tests as a result;
Loop back channel is used for original cycle tests and the transmission of cycle tests as a result;
Comparison module, the comparison that cycle tests as a result that is used for will receiving continuously and original cycle tests pursue bit;
Error code counter is used for the error code in the testing time is counted.
Implement method provided by the invention, compare with Error Detector and existing error-code testing method, has following advantage: adopt modular institutional framework, can carry out integrated with existing wireless communication system easily, provide the error code testing function as a functional module, and no longer need be in maintenance work the bit error analyzing instrument of configuration rates costliness in addition; Different bits by cycle tests between counting sending module and the receiver module calculate the error rate, and algorithm is very succinct; Only used an error code counter in this method, the system resource that takies wireless communication system is few, even in to multi channel test, also only need use this error code counter to get final product repeatedly, can not need extra system resource because of the expansion of test scale.
Description of drawings
Fig. 1 is the schematic diagram of linear feedback shift register;
Fig. 2 is a wireless communication system error code testing device functional block diagram;
Fig. 3 is a wireless communication system error-code testing method flow chart.
Embodiment
Below in conjunction with accompanying drawing the present invention is done and to be described in further detail:
Fig. 1 shows the principle of the linear feedback shift register that produces the m sequence, the pseudo random number of m sequence is a kind of pseudorandom definite sequence, it is a kind of pseudo random sequence of present extensive use, the m sequence is the longest a kind of binary sequence of cycle by the shift register generation of band linear feedback, aspect Error detection, it can be used as a kind of good random sources.
Table 1 shows linear feedback shift register progression sequence table (videing infra), has listed the proper polynomial of long output sequence that the linear feedback shift register of different progression (being different numbers) can produce.Its projectional technique is not given unnecessary details herein.Consider the cycle and the length of m sequence, selected the m sequence of progression r=15 among the present invention.
Fig. 2 shows m sequence generation module, the functional relationship between initiator block and the receiving terminal module.Among the figure, pseudo random sequence generation module 31 is used to produce pseudo random sequence, as test data; Initiator block 32 is used to send cycle tests, and the required detection channel of pseudo random sequence by loop backed sent; Receiving terminal module 34 obtains the identical original m sequence that sends with initiator block from m sequence generation module, and receives the cycle tests as a result that initiator block sends over from loop back channel; Loop back channel 33 is used for original cycle tests and the transmission of cycle tests as a result; Comparison module 36, the comparison that cycle tests as a result that is used for will receiving continuously and original cycle tests pursue bit; Error code counter 35 is used for the error code in the testing time is counted.
Table 1
| R (progression) | The longest output sequence | R (progression) | The |
| 2 | X2+X+1 | 12 | X12+X6+X4+X+1 |
| 3 | X3+X+1 | 13 | X13+X4+X3+X+1 |
| 4 | X4+X+1 | 14 | X14+X10+X6+X+1 |
| 5 | X5+X2+1 | 15 | X15+X+1 |
| 6 | X6+X+1 | 16 | X16+X12+X3+X+1 |
| 7 | X7+X3+1 | 17 | X17+X3+1 |
| 8 | X8+X4+X3+X2+1 | 18 | X18+X7+1 |
| 9 | X9+X4+1 | 19 | X19+X5+X2+X+1 |
| 10 | X10+X3+1 | 20 | X20+X3+1 |
| 11 | X11+X2+1 |
Fig. 3 shows wireless communication system error-code testing method flow chart, wherein in this exemplary method m sequence generation module to finish form be 2
15The generation of-1 cycle tests, a generation form is 2
15-1 cycle tests.Concrete steps are as follows:
Step S41: structure pseudo random sequence generation module;
One of radio digital communication system very important prerequisite be: original source signal is a general and separate random digit sequence such as 0,1.Therefore, reflect the performance of system as far as possible truly, adopt pseudo random sequence (m sequence) as test data for making test result.The m sequence is a kind of linear feedback shift register sequence, and its principle as shown in Figure 1.The output of every grade of shift register is fed coefficient Ci weighting (Ci can get 1 or 0), feeds back to the first order again through the nodulo-2 addition computing.Make a that is input as of the first order
k, according to the value difference of feedback factor, circuit can produce various Serial No.s with different qualities.For certain number of shift register stages r, there are some special Ci values, make the cycle of output sequence reach the longest, be 2
r-1.Such sequence is called as longest linear feedback shift register sequence, i.e. m sequence.
Step S42: test initialization;
Test initialization comprises required detection channel in initialization error code counter and the tested wireless communication system of loopback.The initialization error code counter is to make error code counter (EC) zero clearing, and initiator block is finished the clear operation of error code counter before the test beginning.Required detection channel is the necessary condition that test is carried out in the tested wireless communication system of loopback.
Step S43: judge whether error code counter overflows,, change step S51, otherwise change step S44 if overflow;
Step S44: send cycle tests; Initiator block is called the interface that m sequence generation module provides, and obtains the original m sequence that error code testing is used, and produces original m sequential test data.
Step S45: initiator block sends to the m sequence channel of loop backed.
Step S44 and step S45 continue certain testing time, and the testing time can be selected by the user, generally get 2 hours, 12 hours, 24 hours, wait the integer time in 48 hours.
Step S46: acceptance test sequence;
In the testing time, the receiving terminal module obtains the identical original m sequence that sends with initiator block from m sequence generation module, and receiving the cycle tests as a result that initiator block sends over from loop back channel, this process continues the testing time with step S44 and step S45 equal length.
Step S47, S48, S49: compare test sequence;
With original m sequence and the cycle tests comparison of pursuing bit as a result, relatively the time, continuing relatively next bit by bit if the two is identical, if the two difference then make error code counter (EC) add 1 earlier to continue relatively next bit again.
Step S50: relatively finishing judges whether to arrive the testing time, carries out step S52 as time is up, and not arriving as the time changes step S43.
Step S51: call the interface that m sequence generation module provides, notice m sequence generation module stops the generation of original m sequence, stops error code testing then.
Step S52: EOT, carry out error code result statistics.
Obtain error code counter (EC) value after the testing time finishes, value according to this error code counter (EC), calculate the corresponding error rate, following formula is adopted in the calculating of the error rate: the error rate=error code counter value/(the tested channel speed * testing time), tested channel speed unit be " bps ", testing time unit is second.
In the testing time section, not zero clearing of error code counter.
In test process, if the error code on the test channel is too many, cause error code counter to overflow, initiator block stops error code testing, and error code counter is got the maximum that its data type can reach when then calculating the error rate.
Foregoing only is an optimum implementation of the present invention, and it is not to be used for limiting the specific embodiment of the present invention, and all modification and changes of carrying out according to the main inventive concept of this method all should belong to the desired protection range of claims of the present invention.
Claims (8)
1. the bit error detection method of a radio digital communication system is characterized in that, comprises the steps:
(1) produces pseudo random sequence, as test data;
(2) test initialization comprises required detection channel in the tested wireless communication system of initialization error code counter and loopback;
(3) send cycle tests, be used for the required detection channel of pseudo random sequence by loop backed, and certain time;
(4) acceptance test sequence, be used to receive original pseudorandom cycle tests and on the loop back channel the reception result cycle tests, and continue and time of step (3) equal length;
(5) compare test sequence, the comparison that cycle tests as a result that is used for will receiving continuously and original pseudorandom cycle tests pursue bit;
(6) error code result statistics, the value of the error code counter after being used for finishing according to the testing time calculates the corresponding error rate.
2. the bit error detection method of radio digital communication system as claimed in claim 1 is characterized in that, described pseudo random sequence is the m sequence.
3. the bit error detection method of radio digital communication system as claimed in claim 2 is characterized in that, the progression of described m sequence is 15.
4. the bit error detection method of radio digital communication system as claimed in claim 1 is characterized in that, also comprises in the described step (3) judging whether error code counter overflows.
5. the bit error detection method of radio digital communication system as claimed in claim 1 is characterized in that, described step (5) relatively comprises by bit:
If original cycle tests is with the cycle tests bit is identical as a result, then continue relatively next bit;
If original cycle tests and the cycle tests bit is inequality as a result, then error code counter adds 1, and continues relatively next bit.
6. the bit error detection method of radio digital communication system as claimed in claim 1, it is characterized in that, following formula is adopted in the calculating of the error rate: the error rate=error code counter value/(the tested channel speed * testing time), tested channel speed unit be " bps ", testing time unit is second.
7. the bit error detection method of radio digital communication system as claimed in claim 1 is characterized in that, if error code counter overflows, error code counter is got the maximum that its data type can reach and calculated the error rate.
8. the device for detecting code error of a radio digital communication system is characterized in that, comprises pseudo random sequence generation module, initiator block, receiving terminal module and loop back channel and error code counter, wherein,
Pseudo random sequence generation module is used to produce pseudo random sequence, as test data;
Initiator block is used to send cycle tests, with the required detection channel of pseudo random sequence by loop backed;
The receiving terminal module is used to receive original cycle tests and cycle tests as a result;
Loop back channel is used for original cycle tests and the transmission of cycle tests as a result;
Comparison module, the comparison that cycle tests as a result that is used for will receiving continuously and original cycle tests pursue bit;
Error code counter is used for the error code in the testing time is counted.
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| CN100461655C (en) * | 2007-04-28 | 2009-02-11 | 北京交通大学 | System and method for testing channel transmission performance with the practical channel and computer simulation |
| CN101771525A (en) * | 2010-01-01 | 2010-07-07 | 江苏华丽网络工程有限公司 | High-speed digital communication line error code detection device and method |
| CN102752098A (en) * | 2012-07-11 | 2012-10-24 | 烽火通信科技股份有限公司 | Error code measuring method based on pseudo-random code sequence synchronization for communication system |
| CN102970077A (en) * | 2012-12-13 | 2013-03-13 | 上海市共进通信技术有限公司 | Error rate testing device and method for circuit board integrated optical component system |
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